8XC196KC/8XC196KC20
COMMERCIAL/EXPRESS CHMOS
MICROCONTROLLER
87C196KCÐ16 Kbytes of On-Chip OTPROM
83C196KCÐ16 Kbytes ROM
80C196KCÐROMless
Y
16 and 20 MHz Available
Y
488 Byte Register RAM
Y
Register-to-Register Architecture
Y
28 Interrupt Sources/16 Vectors
Y
Peripheral Transaction Server
Y
1.4 ms 16 x 16 Multiply (20 MHz)
Y
2.4 ms 32/16 Divide (20 MHz)
Y
Powerdown and Idle Modes
Y
Five 8-Bit I/O Ports
Y
16-Bit Watchdog Timer
Y
Extended Temperature Available
The 80C196KC 16-bit microcontroller is a high performance member of the MCSÉ96 microcontroller family.
The 80C196KC is an enhanced 80C196KB device with 488 bytes RAM, 16 and 20 MHz operation and an
optional 16 Kbytes of ROM/OTPROM. Intel’s CHMOS III process provides a high performance processor
along with low power consumption.
Y
Dynamically Configurable 8-Bit or
16-Bit Buswidth
Y
Full Duplex Serial Port
Y
High Speed I/O Subsystem
Y
16-Bit Timer
Y
16-Bit Up/Down Counter with Capture
Y
3 Pulse-Width-Modulated Outputs
Y
Four 16-Bit Software Timers
Y
8- or 10-Bit A/D Converter with
Sample/Hold
Y
HOLD/HLDA Bus Protocol
Y
OTPROM One-Time Programmable
Version
The 87C196KC is an 80C196KC with 16 Kbytes on-chip OTPROM. The 83C196KC is an 80C196KC with 16
Kbytes factory programmed ROM. In this document, the 80C196KC will refer to all products unless otherwise
stated.
Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an A/D conversion. Events can be based on the timer or up/down counter.
With the commercial (standard) temperature option, operational characteristics are guaranteed over the temperature range of 0
teristics are guaranteed over the temperature range of
Ctoa70§C. With the extended (Express) temperature range option, operational charac-
§
b
40§Ctoa85§C. Unless otherwise noted, the specifi-
cations are the same for both options.
See the Packaging information for extended temperature designators.
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
November 1994COPYRIGHT©INTEL CORPORATION, 1995 Order Number: 270942-005
8XC196KC/8XC196KC20
270942– 1
Figure 1. 8XC196KC Block Diagram
IOC3 (0CH HWIN1 READ/WRITE)
NOTE:
*RSVÐReserved bits must be
2
270942– 45
e
0
Figure 2. 8XC196KC New SFR Bit (CLKOUT Disable)
8XC196KC/8XC196KC20
PROCESS INFORMATION
This device is manufactured on PX29.5 or PX29.9, a
CHMOS III process. Additional process and reliability information is available in Intel’s
Quality and Reliability Handbook,
210997.
EXAMPLE: N87C196KC is 68-Lead PLCC OTPROM,
16 MHz.
For complete package dimensional data, refer to the
Intel Packaging Handbook (Order Number 240800).
NOTE:
1. EPROMs are available as One Time Programmable
(OTPROM) only.
Figure 3. The 8XC196KC Family Nomenclature
Table 1. Thermal Characteristics
Package
Type
i
ja
PLCC 35§C/W 13§C/W
QFP 55§C/W 16§C/W
SQFP TBD TBD
All thermal impedance data is approximate for static air
conditions at 1W of power dissipation. Values will change
depending on operation conditions and application. See
Packaging Handbook
the Intel
description of Intel’s thermal impedance test methodology.
(order number 240800) for a
Components
Order Number
270942– 43
i
jc
Table 2. 8XC196KC Memory Map
Description Address
External Memory or I/O 0FFFFH
06000H
Internal ROM/OTPROM or External 5FFFH
Memory (Determined by EA
)
2080H
Reserved. Must contain FFH. 207FH
(Note 5)
205EH
PTS Vectors 205DH
2040H
Upper Interrupt Vectors 203FH
2030H
ROM/OTPROM Security Key 202FH
2020H
Reserved. Must contain FFH. 201FH
(Note 5)
201AH
Reserved. Must Contain 20H 2019H
(Note 5)
CCB 2018H
Reserved. Must contain FFH. 2017H
(Note 5)
2014H
Lower Interrupt Vectors 2013H
2000H
Port 3 and Port 4 1FFFH
1FFEH
External Memory 1FFDH
0200H
488 Bytes Register RAM (Note 1) 01FFH
0018H
CPU SFR’s (Notes 1, 3, 4) 0017H
0000H
NOTES:
1. Code executed in locations 0000H to 01FFH will be
forced external.
2. Reserved memory locations must contain 0FFH unless
noted.
3. Reserved SFR bit locations must contain 0.
4. Refer to 8XC196KC User’s manual for SFR descriptions.
5. WARNING: Reserved memory locations must not be
written or read. The contents and/or function of these locations may change with future revisions of the device.
Therefore, a program that relies on one or more of these
locations may not function properly.
3
8XC196KC/8XC196KC20
270942– 2
Figure 4. 68-Lead PLCC Package
4
8XC196KC/8XC196KC20
Figure 5. S8XC196KC 80-Pin QFP Package
270942– 40
5
8XC196KC/8XC196KC20
270942– 44
Figure 6. 80-Pin SQFP Package
6
8XC196KC/8XC196KC20
PIN DESCRIPTIONS
Symbol Name and Function
V
CC
V
SS
V
REF
ANGND Reference ground for the A/D converter. Must be held at nominally the same potential as
V
PP
XTAL1 Input of the oscillator inverter and of the internal clock generator.
XTAL2 Output of the oscillator inverter.
CLKOUT Output of the internal clock generator. The frequency of CLKOUT is (/2 the oscillator
RESET Reset input and open drain output.
BUSWIDTH Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus
NMI A positive transition causes a vector through 203EH.
INST Output high during an external memory read indicates the read is an instruction fetch. INST
EA Input for memory select (External Access). EA equal high causes memory accesses to
ALE/ADV Address Latch Enable or Address Valid output, as selected by CCR. Both pin options
RD Read signal output to external memory. RD is activated only during external memory reads.
WR/WRL Write and Write Low output to external memory, as selected by the CCR. WR will go low for
BHE/WRH Bus High Enable or Write High output to external memory, as selected by the CCR. BHE will
READY Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory,
HSI Inputs to High Speed Input Unit. Four HSI pins are available: HSI.0, HSI.1, HSI.2 and HSI.3.
HSO Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2,
Port 0 8-bit high impedance input-only port. These pins can be used as digital inputs and/or as
Port 1 8-bit quasi-bidirectional I/O port.
Port 2 8-bit multi-functional port. All of its pins are shared with other functions in the 80C196KC.
Main supply voltage (5V).
Digital circuit ground (0V). There are multiple VSSpins, all of which must be connected.
Reference voltage for the A/D converter (5V). V
portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D
is also the supply voltage to the analog
REF
and Port 0 to function.
V
.
SS
Timing pin for the return from powerdown circuit. This pin also supplies the programming
voltage on the EPROM device.
frequency.
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH isa0an
8-bit cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus.
is valid throughout the bus cycle. INST is activated only during external memory accesses
and output low for a data fetch.
locations 2000H through 5FFFH to be directed to on-chip ROM/EPROM. EA
equal to low
causes accesses to those locations to be directed to off-chip memory. Also used to enter
programming mode.
provide a signal to demultiplex the address from the address/data bus. When the pin is
, it goes inactive high at the end of the bus cycle. ALE/ADV is activated only during
ADV
external memory accesses.
every external write, while WRL
being written. WR
/WRL is activated only during external memory writes.
go low for external writes to the high byte of the data bus. WRH
writes where an odd byte is being written. BHE
will go low only for external writes where an even byte is
will go low for external
/WRH is activated only during external
memory writes.
or for bus sharing. When the external memory is not being used, READY has no effect.
Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.
HSI.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.
analog inputs to the on-chip A/D converter.
Pins 2.6 and 2.7 are quasi-bidirectional.
7
8XC196KC/8XC196KC20
PIN DESCRIPTIONS (Continued)
Symbol Name and Function
Ports 3 and 4 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
HOLD Bus Hold input requesting control of the bus.
HLDA Bus Hold acknowledge output indicating release of the bus.
BREQ Bus Request output activated when the bus controller has a pending external memory
PMODE Determines the EPROM programming mode.
PACT A low signal in Auto Programming mode indicates that programming is in process. A high
CPVER Cummulative Program Output Verification. Pin is high if all locations have programmed
PALE A falling edge in Slave Programming Mode and Auto Configuration Byte Programming Mode
PROG A falling edge in Slave Programming Mode indicates that ports 3 and 4 contain valid
PVER A high signal in Slave Programmig Mode and Auto Configuration Byte Programming Mode
AINC Auto Increment. Active low input signal indicates that the auto increment mode is enabled.
multiplexed address/data bus which has strong internal pullups.
cycle.
signal indicates programming is complete.
correctly since entering a programming mode.
indicates that ports 3 and 4 contain valid programming address/command information
(input to slave).
programming data (input to slave).
indicates the byte programmed correctly.
Auto Increment will allow reading or writing of sequential EPROM locations without address
transactions across the PBUS for each read or write.
8
8XC196KC/8XC196KC20
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature
Under Bias ААААААААААААААААА
Storage Temperature ААААААААААb65§Ctoa150§C
Voltage On Any Pin to V
SS
Voltage from EA or
to VSSor ANGNDААААААААААААААААa13.00V
V
PP
Power Dissipation ААААААААААААААААААААААА1.5W
NOTE:
1. This includes V
2. Power dissipation is based on package heat transfer limitations, not device power consumption.
and EA on ROM or CPU only devices.
PP
b
55§Ctoa125§C
ААААААb0.5V toa7.0V
(1)
(2)
NOTICE: This is a production data sheet. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
*
WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
OPERATING CONDITIONS
Symbol Description Min Max Units
T
A
T
A
V
CC
V
REF
ANGND Analog Ground Voltage V
F
OSC
F
OSC
NOTE:
1. ANGND and V
Ambient Temperature Under Bias Commercial Temp. 0
Ambient Temperature Under Bias Extended Temp.
Digital Supply Voltage 4.50 5.50 V
Analog Supply Voltage 4.00 5.50 V
Oscillator Frequency (8XC196KC) 8 16 MHz
Oscillator Frequency (8XC196KC20) 8 20 MHz
should be nominally at the same potential.
SS
b
SS
40
b
0.4 V
a
a
SS
70
85
a
0.4 V
C
§
C
§
(1)
DC CHARACTERISTICS (Over Specified Operating Conditions)
Symbol Description Min Typ Max Units Test Conditions
V
V
V
V
V
V
V
V
IL
IH
IH1
IH2
HYS
OL
OL1
OH
Input Low Voltage
Input High Voltage (Note 1) 0.2 V
Input High Voltage on XTAL 1 0.7 V
Input High Voltage on RESET 2.2 V
Hysteresis on RESET 300 mV V
Output Low Voltage 0.3 V I
Output Low Voltage
in RESET on P2.5 (Note 2)
Output High Voltage V
(Standard Outputs) V
b
0.5 0.8 V
a
1.0 V
CC
CC
a
CC
a
V
CC
a
CC
0.45 V I
1.5 V I
0.8 V
b
0.3 V I
CC
b
0.7 V I
CC
b
V
1.5 V I
CC
0.5 V
0.5 V
0.5 V
I
OL
OL
OL
OL
OH
OH
OH
CC
e
e
200 mA
e
2.8 mA
e
7mA
ea
eb
eb
eb
5.0V
0.4 mA
200 mA
3.2 mA
7mA
9
8XC196KC/8XC196KC20
DC CHARACTERISTICS (Over Specified Operating Conditions) (Continued)
Symbol Description Min Typ Max Units Test Conditions
V
I
OH1
Output High Voltage V
OH1
(Quasi-bidirectional Outputs) V
Logical 1 Output Current in Reset.
on P2.0. Do not exceed this
b
0.3 V I
CC
b
0.7 V I
CC
b
1.5 V I
V
CC
b
0.8 mA V
or device may enter test modes.
I
IL2
Logical 0 Input Current in Reset TBD mA V
on P2.0. Maximum current that
must be sunk by external
device to ensure test mode entry.
I
IH1
Logical 1 Input Current.
Maximum current that external
a
200 mAV
device must source to initiate NMI.
I
LI
I
LI1
I
TL
I
IL
I
IL1
I
CC
I
CC
I
IDLE
I
IDLE
I
PD
I
REF
R
C
NOTES:
1. All pins except RESET and XTAL1.
2. Violating these specifications in Reset may cause the part to enter test modes.
3. Commercial specifications apply to express parts except where noted.
4. QBD (Quasi-bidirectional) pins include Port 1, P2.6 and P2.7.
5. Standard Outputs include AD0 – 15, RD
TXD/P2.0 and RXD (in serial mode 0). The V
6. Standard Inputs include HSI pins, READY, BUSWIDTH, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3 and T2RST/P2.4.
7. Maximum current per pin must be externally limited to the following values if V
below V
8. Maximum current per bus pin (data and control) during normal operation is
9. During normal (non-transient) conditions the following total current limits apply:
Input Leakage Current (Std. Inputs)
Input Leakage Current (Port 0)
1 to 0 Transition Current (QBD Pins)
Logical 0 Input Current (QBD Pins)
Ports 3 and 4 in Reset
Active Mode Current in Reset 65 75 mA XTAL1e16 MHz
(8XC196KC)
Active Mode Current in Reset 80 92 mA XTAL1e20 MHz
(8XC196KC20)
Idle Mode Current (8XC196KC) 17 25 mA XTAL1e16 MHz
Idle Mode Current (8XC196KC20) 21 30 mA XTAL1e20 MHz
Powerdown Mode Current 8 15 mAV
A/D Converter Reference Current 2 5 mA V
Reset Pullup Resistor 6K 65K X V
RST
Pin Capacitance (Any Pin to VSS)10pF
S
,WR, ALE, BHE, INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Ports 3 and 4,
specification is not valid for RESET. Ports 3 and 4 are open-drain outputs.
OH
b
0.7V:
CC
on Output pins: 10 mA
I
OL
on quasi-bidirectional pins: self limiting
I
OH
on Standard Output pins: 10 mA
I
OH
Port 1, P2.6 I
HSO, P2.0, RXD, RESET
P2.5, P2.7, WR
AD0–AD15 I
, ALE, INST – CLKOUT IOL:13mA IOH:13mA
RD
, BHE IOL:13mA IOH:11mA
:29mA IOHis self limiting
OL
IOL:29mA IOH:26mA
:52mA IOH:52mA
OL
g
10 mA0kV
g
3 mA0kV
b
650 mAV
b
70 mAV
b
70 mAV
OL
g
3.2 mA.
eb
IH
IN
IN
IN
IN
IN
CC
CC
CC
CC
CC
CC
CC
eb
eb
e
V
e
0.45V
e
V
IN
IN
e
2.0V
e
0.45V
e
0.45V
e
V
e
V
e
V
e
V
e
V
e
V
e
5.5V, V
10 mA
30 mA
60 mA
CC
CC
k
V
k
V
PP
PP
PP
PP
PP
PP
b
e
e
e
e
e
e
e
CC
REF
1.5V
2.4V
b
V
REF
V
REF
V
REF
V
REF
V
REF
V
REF
IN
0.3V
e
OH
OH
OH
V
V
V
V
is held above 0.45V or VOHis held
e
e
e
e
e
e
4.0V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
10
8XC196KC/8XC196KC20
ICCMaxe4.13cFrequencya9mA
Type3.50cFrequencya9mA
I
CC
Maxe1.25cFrequencya5mA
I
IDLE
Type0.88cFrequencya3mA
I
IDLE
NOTE:
Frequencies below 8 MHz are shown for reference only; no testing is performed.
Figure 7. ICCand I
vs Frequency
IDLE
270942– 17
AC CHARACTERISTICS
For use over specified operating conditions.
Test Conditions: Capacitive load on all pinse100 pF, Rise and fall timese10 ns, F
The system must meet these specifications to work with the 80C196KC:
Symbol Description Min Max Units Notes
T
AVYV
T
YLYH
T
CLYX
T
LLYX
T
AVGV
T
CLGX
T
AVDV
T
RLDV
T
CLDV
T
RHDZ
T
RXDX
NOTES:
1. If max is exceeded, additional wait states will occur.
2. If wait states are used, add 2 T
Address Valid to READY Setup 2 T
Non READY Time No upper limit ns
READY Hold after CLKOUT Low 0 T
READY Hold after ALE Low T
Address Valid to Buswidth Setup 2 T
Buswidth Hold after CLKOUT Low 0 ns
Address Valid to Input Data Valid 3 T
RD Active to Input Data Valid T
CLKOUT Low to Input Data Valid T
End of RD to Input Data Float T
Data Hold after RD Inactive 0 ns
* N, where Nenumber of wait states.
OSC
OSC
b
15 2 T
b
68 ns
OSC
b
30 ns (Note 1)
OSC
b
40 ns (Note 1)
OSC
b
68 ns
OSC
b
55 ns (Note 2)
OSC
b
22 ns (Note 2)
OSC
b
45 ns
OSC
OSC
OSC
ns
e
16 MHz
11
8XC196KC/8XC196KC20
AC CHARACTERISTICS (Continued)
For user over specified operating conditions.
Test Conditions: Capacitive load on all pins
e
100 pF, Rise and fall timese10 ns, F
The 80C196KC will meet these specifications:
Symbol Description Min Max Units Notes
F
XTAL
F
XTAL
T
OSC
T
OSC
T
XHCH
T
CLCL
T
CHCL
T
CLLH
T
LLCH
T
LHLH
T
LHLL
T
AVLL
T
LLAX
T
LLRL
T
RLCL
T
RLRH
T
RHLH
T
RLAZ
T
LLWL
T
CLWL
T
QVWH
T
CHWH
T
WLWH
T
WHQX
T
WHLH
T
WHBX
T
WHAX
T
RHBX
T
RHAX
NOTES:
1. Testing performed at 8 MHz. However, the device is static by design and will typically operate below 1 Hz.
2. Assuming back-to-back bus cycles.
3. 8-Bit bus only.
4. If wait states are used, add 2 T
Frequency on XTAL1 (8XC196KC) 8 16 MHz (Note 1)
Frequency on XTAL1 (8XC196KC20) 8 20 MHz (Note 1)
I/F
I/F
XTAL1 High to CLKOUT High or Low
CLKOUT Cycle Time 2 T
CLKOUT High Period T
CLKOUT Falling Edge to ALE Rising
ALE Falling Edge to CLKOUT Rising
ALE Cycle Time 4 T
ALE High Period T
Address Setup to ALE Falling Edge T
Address Hold after ALE Falling Edge T
ALE Falling Edge to RD Falling Edge T
RD Low to CLKOUT Falling Edge
RD Low Period T
RD Rising Edge to ALE Rising Edge T
RD Low to Address Float
ALE Falling Edge to WR Falling Edge T
CLKOUT Low to WR Falling Edge 0
Data Stable to WR Rising Edge T
CLKOUT High to WR Rising Edge
WR Low Period T
Data Hold after WR Rising Edge T
WR Rising Edge to ALE Rising Edge T
BHE, INST after WR Rising Edge T
AD8–15 HOLD after WR Rising T
BHE, INST after RD Rising Edge T
AD8–15 HOLD after RD Rising T
(8XC196KC) 62.5 125 ns
XTAL
(8XC196KC20) 50 125 ns
XTAL
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
* N, where Nenumber of wait states.
OSC
a
20
b
10 T
b
5
b
20
OSC
b
10 T
b
15
b
35 ns
b
30 ns
a
4
b
5 ns (Note 4)
OSC
OSC
b
10 ns
b
23 (Note 4)
b
5
b
20 ns (Note 4)
b
25 ns
b
10 T
b
10 ns
b
30 ns (Note 3)
b
10 ns
b
25 ns (Note 3)
OSC
T
OSC
OSC
OSC
OSC
a
110 ns
a
a
15 ns
a
15 ns
a
a
30 ns
a
a
5ns
a
25 ns
a
15 ns
a
15 ns
10 ns
25 ns (Note 2)
15 ns (Note 2)
e
16 MHz
OSC
ns
ns (Note 4)
12
System Bus Timings
8XC196KC/8XC196KC20
270942– 18
13
8XC196KC/8XC196KC20
READY Timings (One Wait State)
Buswidth Timings
14
270942– 20
270942– 35
8XC196KC/8XC196KC20
HOLD/HLDA Timings
Symbol Description Min Max Units Notes
T
HVCH
T
CLHAL
T
CLBRL
T
HALAZ
T
HALBZ
T
CLHAH
T
CLBRH
T
HAHAX
T
HAHBV
T
CLLH
NOTE:
1. To guarantee recognition at next clock.
HOLD Setup
CLKOUT Low to HLDA Low
CLKOUT Low to BREQ Low
HLDA Low to Address Float
HLDA Low to BHE, INST, RD,WRWeakly Driven
CLKOUT Low to HLDA High
CLKOUT Low to BREQ High
HLDA High to Address No Longer Float
HLDA High to BHE, INST, RD,WRValid
CLKOUT Low to ALE High
DC SPECIFICATIONS IN HOLD
Description Min Max Units
Weak Pullups on ADV, RD, 50K 250K V
,WRL, BHE
WR
Weak Pulldowns on 10K 50K V
ALE, INST
a
55 ns (Note 1)
b
b
b
b
b
b
b
a
15
15
15
15
15 ns
a
15 ns
a
15 ns
a
20 ns
a
15 ns
a
15 ns
15 ns
a
10
5
15 ns
a
15 ns
e
5.5V, V
CC
e
5.5V, V
CC
e
0.45V
IN
e
2.4
IN
15
8XC196KC/8XC196KC20
270942– 36
Maximum Hold Latency
Bus Cycle Type
Internal Execution 1.5 States
16-Bit External Execution 2.5 States
8-Bit External Execution 4.5 States
EXTERNAL CLOCK DRIVE (8XC196KC)
Symbol Parameter Min Max Units
16
1/T
T
XLXL
T
XHXX
T
XLXX
T
XLXH
T
XHXL
XLXL
Oscillator Frequency 8 16.0 MHz
Oscillator Period 62.5 125 ns
High Time 20 ns
Low Time 20 ns
Rise Time 10 ns
Fall Time 10 ns
8XC196KC/8XC196KC20
EXTERNAL CLOCK DRIVE (8XC196KC20)
Symbol Parameter Min Max Units
1/T
XLXL
T
XLXL
T
XHXX
T
XLXX
T
XLXH
T
XHXL
EXTERNAL CLOCK DRIVE WAVEFORMS
Oscillator Frequency 8 20.0 MHz
Oscillator Period 50 125 ns
High Time 17 ns
Low Time 17 ns
Rise Time 8 ns
Fall Time 8 ns
270942– 21
EXTERNAL CRYSTAL CONNECTIONS
270942– 41
NOTE:
Keep oscillator components close to chip and use
short, direct traces to XTAL1, XTAL2 and V
using crystals, C1
resonators, consult manufacturer for recommended circuitry.
e
C2&20 pF. When using ceramic
. When
SS
AC TESTING INPUT, OUTPUT WAVEFORMS
AC Testing inputs are driven at 2.4V for a Logic ‘‘1’’ and 0.45V for
a Logic ‘‘0’’ Timing measurements are made at 2.0V for a Logic
‘‘1’’ and 0.8V for a Logic ‘‘0’’.
270942– 22
EXTERNAL CLOCK CONNECTIONS
270942– 42
NOTE:
*Required if TTL driver used.
Not needed if CMOS driver is used.
FLOAT WAVEFORMS
OH/VOL
270942– 23
Level occurs;
For Timing Purposes a Port Pin is no Longer Floating when a
150 mV change from Load Voltage Occurs and Begins to Float
when a 150 mV change from the Loaded V
e
g
I
OL/IOH
15 mA.
17
8XC196KC/8XC196KC20
EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by ‘‘T’’ for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.
Conditions:
HÐ High
LÐ Low
VÐ Valid
XÐ No Longer Valid
ZÐ Floating
Signals:
AÐ Address
BÐ BHE
CÐ CLKOUT
DÐ DATA
GÐ Buswidth
HÐ HOLD
LÐ ALE/ADV
BRÐ BREQ
RÐ RD
WÐ WR/WRH/WRL
XÐ XTAL1
YÐ READY
QÐ Data Out
HAÐ HLDA
AC CHARACTERISTICSÐSERIAL PORTÐSHIFT REGISTER MODE
SERIAL PORT TIMINGÐSHIFT REGISTER MODE (MODE 0)
Symbol Parameter Min Max Units
T
XLXL
T
XLXH
T
XLXL
T
XLXH
T
QVXH
T
XHQX
T
XHQV
T
DVXH
T
XHDX
T
XHQZ
Serial Port Clock Period (BRRt8002H) 6 T
Serial Port Clock Falling Edge 4 T
to Rising Edge (BRR
t
8002H)
Serial Port Clock Period (BRRe8001H) 4 T
Serial Port Clock Falling Edge 2 T
to Rising Edge (BRR
e
8001H)
Output Data Setup to Clock Rising Edge 2 T
Output Data Hold after Clock Rising Edge 2 T
Next Output Data Valid after Clock Rising Edge 2 T
Input Data Setup to Clock Rising Edge T
OSC
b
50 4 T
OSC
OSC
b
50 2 T
OSC
b
50 ns
OSC
b
50 ns
OSC
a
50 ns
OSC
OSC
OSC
OSC
a
50 ns
a
50 ns
a
50 ns
Input Data Hold after Clock Rising Edge 0 ns
Last Clock Rising to Output Float 1 T
OSC
ns
ns
ns
WAVEFORMÐSERIAL PORTÐSHIFT REGISTER MODE
SERIAL PORT WAVEFORMÐSHIFT REGISTER MODE (MODE 0)
18
270942– 24
8XC196KC/8XC196KC20
A to D CHARACTERISTICS
The A/D converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of V
10-BIT MODE A/D OPERATING CONDITIONS
Symbol Description Min Max Units
a
T
A
T
A
V
CC
V
REF
T
SAM
T
CONV
F
OSC
F
OSC
NOTE:
ANGND and V
1. The value of ADÐTIME is selected to meet these specifications.
Ambient Temperature Commercial Temp. 0
Ambient Temperature Extended Temp.
Digital Supply Voltage 4.50 5.50 V
Analog Supply Voltage 4.00 5.50 V
Sample Time 1.0 ms
Conversion Time 10 20 ms
Oscillator Frequency (8XC196KC) 8.0 16.0 MHz
Oscillator Frequency (8XC196KC20) 8.0 20.0 MHz
should nominally be at the same potential, 0.00V.
SS
b
40
70
a
85
§
§
10-BIT MODE A/D CHARACTERISTICS (Over Specified Operating Conditions)
Parameter Typical
Resolution 1024 1024 Levels
Absolute Error 0
Full Scale Error 0.25g0.5 LSBs
Zero Offset Error 0.25g0.5 LSBs
Non-Linearity 1.0g2.0 0
Differential Non-Linearity Error
Channel-to-Channel Matching
Repeatability
Temperature Coefficients:
Offset 0.009 LSB/
Full Scale 0.009 LSB/§C
Differential Non-Linearity 0.009 LSB/
Off Isolation
Feedthrough
VCCPower Supply Rejection
Input Series Resistance 750 1.2K X 4
Voltage on Analog Input Pin ANGNDb0.5 V
DC Input Leakage 0
Sampling Capacitor 3 pF
(1)
Minimum Maximum Units* Notes
10 10 Bits
g
3 LSBs
g
3 LSBs
l
b
1
g
0.1 0
g
0.25 LSBs
b
60 dB 1, 2
b
60 dB 1
b
60 dB 1
a
2 LSBs
g
1 LSBs
a
0.5 V 5, 6
REF
g
3.0 mA
C
§
C
§
.
REF
C
C
(1)
(1)
NOTES:
*An ‘‘LSB’’ as used here has a value of approxiimately 5 mV. (See Embedded Microcontrollers and Processors Handbook
for A/D glossary of terms).
1. These values are expected for most parts at 25
2. DC to 100 KHz.
3. Multiplexer Break-Before-Make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
5. These values may be exceeded if the pin current is limited to
6. Applying voltages beyond these specifications will degrade the accuracy of all channels being converted.
7. All conversions performed with processor in IDLE mode.
C but are not tested or guaranteed.
§
g
2 mA.
19
8XC196KC/8XC196KC20
8-BIT MODE A/D OPERATING CONDITIONS
Symbol Description Min Max Units
T
A
T
A
V
CC
V
REF
T
SAM
T
CONV
F
OSC
F
OSC
NOTE:
ANGND and V
1. The value of ADÐTIME is selected to meet these specifications.
Ambient Temperature Commercial Temp. 0
Ambient Temperature Extended Temp.
Digital Supply Voltage 4.50 5.50 V
Analog Supply Voltage 4.00 5.50 V
Sample Time 1.0 ms
Conversion Time 7 20 ms
Oscillator Frequency (8XC196KC) 8.0 16.0 MHz
Oscillator Frequency (8XC196KC20) 8.0 20.0 MHz
should nominally be at the same potential, 0.00V.
SS
b
40
a
70
a
85
C
§
C
§
(1)
(1)
8-BIT MODE A/D CHARACTERISTICS (Over Specified Operating Conditions)
Parameter Typical Minimum Maximum Units* Notes
Resolution 256 256 Levels
Absolute Error 0
Full Scale Error
Zero Offset Error
g
0.5 LSBs
g
0.5 LSBs
Non-Linearity 0
Differential Non-Linearity Error
Channel-to-Channel Matching
Repeatability
g
0.25 LSBs
Temperature Coefficients:
Offset 0.003 LSB/§C
Full Scale 0.003 LSB/
Differential Non-Linearity 0.003 LSB/
Off Isolation
Feedthrough
VCCPower Supply Rejection
b
60 dB 2
b
60 dB 2
Input Series Resistance 750 1.2K Xs4
Voltage on Analog Input Pin V
DC Input Leakage 0
Sampling Capacitor 3 pF
8 8 Bits
g
1 LSBs
g
1 LSBs
l
b
1
b
60 dB 2, 3
b
0.5 V
SS
a
1 LSBs
g
1 LSBs
a
0.5 V 5, 6
REF
g
3.0 mA
C
§
C
§
NOTES:
*An ‘‘LSB’’ as used here has a value of approximately 20 mV. (See Embedded Microcontrollers and Processors Handbook
for A/D glossary of terms).
1. These values are expected for most parts at 25
2. DC to 100 KHz.
3. Multiplexer Break-Before-Make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
5. These values may be exceeded if pin current is limited to
6. Applying voltages beyond these specifications will degrade the accuracy of all channels being converted.
7. All conversions performed with processor in IDLE mode.
C but are not tested or guaranteed.
§
g
2 mA.
20
8XC196KC/8XC196KC20
EPROM SPECIFICATIONS
OPERATING CONDITIONS DURING PROGRAMMING
Symbol Description Min Max Units
T
V
V
V
V
F
A
CC
REF
PP
EA
OSC
Ambient Temperature During Programming 20 30 C
Supply Voltage During Programming 4.5 5.5 V
Reference Supply Voltage During Programming 4.5 5.5 V
Programming Voltage 12.25 12.75 V
EA Pin Voltage 12.25 12.75 V
(1)
(1)
(2)
(2)
Oscillator Frequency During Auto and Slave 6.0 8.0 MHz
Mode Programming
F
OSC
Oscillator Frequency During 6.0 16.0 MHz
Run-Time Programming (8XC196KC)
F
OSC
Oscillator Frequency During 6.0 20.0 MHz
Run-Time Programming (8XC196KC20)
NOTES:
and V
1. V
CC
and VEAmust never exceed the maximum specification, or the device may be damaged.
2. V
PP
and ANGND should nominally be at the same potential (0V).
3. V
SS
4. Load capacitance during Auto and Slave Mode programming
should nominally be at the same voltage during programming.
REF
e
150 pF.
AC EPROM PROGRAMMING CHARACTERISTICS
Symbol Description Min Max Units
T
SHLL
T
LLLH
T
AVLL
T
LLAX
T
PLDV
T
PHDX
T
DVPL
T
PLDX
(1)
T
PLPH
T
PHLL
T
LHPL
T
PHPL
T
PHIL
T
ILIH
T
ILVH
T
ILPL
T
PHVL
NOTE:
1. This specification is for the Word Dump Mode. For programming pulses, use the Modified Quick Pulse Algorithm. See
user’s manual for further information.
Reset High to First PALE Low 1100 T
PALE Pulse Width 50 T
Address Setup Time 0 T
Address Hold Time 100 T
PROG Low to Word Dump Valid 50 T
Word Dump Data Hold 50 T
Data Setup Time 0 T
Data Hold Time 400 T
PROG Pulse Width 50 T
High to Next PALE Low 220 T
PROG
PALE High to PROG Low 220 T
PROG High to Next PROG Low 220 T
PROG High to AINC Low 0 T
AINC Pulse Width 240 T
PVER Hold after AINC Low 50 T
AINC Low to PROG Low 170 T
PROG High to PVER Valid 220 T
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
21
8XC196KC/8XC196KC20
DC EPROM PROGRAMMING CHARACTERISTICS
Symbol Description Min Max Units
I
PP
NOTE:
Do not apply V
damaged.
VPPSupply Current (When Programming) 100 mA
until VCCis stable and within specifications and the oscillator/clock has stabilized or the device may be
PP
EPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
NOTE:
P3.0 must be high (‘‘1’’)
SLAVE PROGRAMMING MODE IN WORD DUMP WITH AUTO INCREMENT
NOTE:
P3.0 must be low (‘‘0’’)
22
270942– 27
270942– 28
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM
WITH REPEATED PROG PULSE AND AUTO INCREMENT
8XC196KC/8XC196KC20
270942– 29
8XC196KB TO 8XC196KC DESIGN
CONSIDERATIONS
1. Memory Map. The 8XC196KC has 512 bytes of
RAM/SFRs and an optional 16K of
ROM/OTPROM. The extra 256 bytes of RAM will
reside in locations 100H – 1FFH and the extra 8K
of ROM/OTPROM will reside in locations
4000H–5FFFH. These locations are external
memory on the 8XC196KB.
2. The CDE pin on the KB has become a V
the KC to support 16/20 MHz operation.
3. EPROM programming. The 8XC196KC has a different programming algorithm to support 16K of
on-board memory. When performing Run-Time
Programming, use the section of code in the
8XC196KC User’s Guide.
SS
pin on
4. ONCE Mode Entry. The ONCE mode is entered
on the 8XC196KC by driving the TXD pin low on
the rising edge of RESET. The TXD pin is held
high by a pullup that is specified by I
Pullup must not be overridden or the 8XC196KC
will enter the ONCE mode.
5. During the bus HOLD state, the 8XC196KC
weakly holds RD
their inactive states. The 8XC196KB only holds
ALE in its inactive state.
6. A RESET pulse from the 8XC196KC is 16 states
rather than 4 states as on the 8XC196KB (i.e., a
watchdog timer overflow). This provides a longer
RESET pulse for other devices in the system.
,WR, ALE, BHE and INST in
OH1
. This
8XC196KC ERRATA
1. Missed EXTINT on P0.7.
The 80C196KC20 could possibly miss an
EXTINT on P0.7. See techbit MC0893.
2. HSIÐMODE divide-by-eight.
See Faxback
3. IPD hump.
See FaxbackÝ2311.
Ý
2192.
23
8XC196KC/8XC196KC20
DATA SHEET REVISION HISTORY
This data sheet is valid for devices with a ‘‘H’’, ‘‘L’’ or ‘‘M’’ at the end of the topside tracking number. The
topside tracking number consists of nine characters and is the second line on the top side of the device. Data
sheets are changed as new device information becomes available. Verify with your local Intel sales office that
you have the latest version before finalizing a design or ordering devices.
The following are differences between the 270942-004 and 270942-005 datasheets:
1. Removed ‘‘Word Addressable Only’’ from Port 3 and 4 in Table 2.
2. Renamed PVAL to CPVER.
3. Removed T
4. Added HSIÐMODE divide-by-eight and IPD hump to 8XC196KC errata.
The following are important differences between the 270942-002 and 270942-004 data sheets:
1. NMI during PTS, QBD port glitch and Divide HOLD/READY erratas were fixed and have been removed
from the data sheet. The HSI errata is also removed as this is now considered normal operation.
2. Combined 16 and 20 MHz data sheets. Data sheet 270924-001 (20 MHz) is now obsolete.
3. Added 80-lead SQFP package pinout.
4. Added documentation for CLKOUT disable bit.
5. i
for QFP package was changed to 55§C/W from 42§C/W.
JA
6. iJCfor QFP package was changed to 16§C/W from TBD§C/W.
7. T
8. T
9. I
10. I
11. I
12. I
13. V
(MIN) in 10-bit mode was changed to 1.0 ms from 3.0 ms.
SAM
(MIN) in 8-bit mode was changed to 1.0 ms from 2.0 ms.
SAM
specification for port 2.0 was renamed I
IL1
(MAX) is changed to TBD fromb6 mA.
IL2
(MAX) is changed toa200 mA froma100 mA.
IH1
test condition changes to V
IH1
is changed to 300 mV from 150 mV.
HYS
14. ICC(TYP) at 16 MHz is changed to 65 mA from 50 mA.
15. ICC(MAX) at 16 MHz is changed to 75 mA from 70 mA.
16. I
(TYP) at 20 MHz is changed to 80 mA from 60 mA.
CC
17. ICC(MAX) at 20 MHz is changed to 92 mA from 86 mA.
18. I
19. I
20. I
21. I
(TYP) at 16 MHz is changed to 17 mA from 15 mA.
IDLE
(MAX) at 16 MHz is changed to 25 mA from 30 mA.
IDLE
(TYP) at 20 MHz is changed to 21 mA from 15 mA.
IDLE
(MAX) at 20 MHz is changed to 30 mA from 35 mA.
IDLE
22. IPD(TYP) at 16 MHz is changed to 8 mA from 15 mA.
23. IPD(MAX) at 16 MHz is changed to 15 mA from TBD.
24. IPD(TYP) at 20 MHz is changed to 8 mA from 18 mA.
25. IPD(MAX) at 20 MHz is changed to 15 mA from TBD.
26. T
27. T
28. T
29. T
30. T
31. T
(MAX) is changed to T
CLDV
(MIN) is changed to T
LLAX
(MIN) is changed tob5 ns fromb10 ns.
CHWH
(MIN) is changed to T
RHAX
(MAX) is changed toa15 ns froma10 ns.
HALAZ
(MAX) is changed toa20 ns froma15 ns.
HALBZ
LLYV
and T
from the waveform diagrams.
LLGV
IL2
e
2.4V from V
IN
b
45 ns from T
OSC
b
35 ns from T
OSC
b
25 ns from T
OSC
.
e
5.5V.
IN
b
50 ns.
OSC
b
40 ns.
OSC
b
30 ns.
OSC
24
8XC196KC/8XC196KC20
32. T
33. The T
(MAX) is now specified ata15 ns, was formerly unspecified.
HAHBV
and T
LLYV
systems designs.
specifications were removed. These specifications are not required in high-speed
LLGV
34. Added EXTINT, P0.7 errata to Errata section.
The following are the important differences between the -001 and -002 versions of data sheet 270942.
1. Express and Commercial devices are combined into one data sheet. The Express only data sheet
270794-001 is obsolete.
2. Removed KB/KC feature set differences, pin definition table, and SFR locations and bitmaps.
3. Added programming pin function to package drawings and pin descriptions.
4. Changed absolute maximum temperature under bias from 0
5. Replaced V
6. Added I
IH1
specification with I
OH2
OH1
and I
specifications.
IL1
specification for NMI pulldown resistors.
Ctoa70§Ctob55§Ctoa125§C.
§
7. Added maximum hold latency table.
8. Added external oscillator and external clock circuit drawings.
9. Changed Clock Drive T
10. Fixed Serial Port T
XLXH
and T
XHXX
specification.
Min spec to 20 ns.
XLXX
11. Added 8- and 10-bit mode A/D operating conditions tables.
12. Specified operating range for sample and convert times.
13. Added specification for voltage on analog input pin.
14. Put operating conditions for EPR OM programming into tabular format.
25
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