INTEL 82546GB User Manual
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82546GB Dual Port Gigabit Ethernet
Controller
Networking Silicon
Datasheet
Product Features
■ PCI/PCI-X
—PCI-X Revision 1.0a support for
frequencies up to 133 MHz
—Multi-function PCI device
—PCI Revision 2.3 su pport for 3 2-bit wide
or 64-bit wide interface at 33 MHz and
66 MHz
■ MAC
—IEEE 802.3x compliant flow control
support with software controllable pause
times and threshold values
—Programmable host memory receive
buffers (256 Bytes to 16 Kbytes) and
cache line size (16 Bytes to 256 Bytes)
—Wide, optimized internal data path
architecture (128 bits)
—Dual 64 Kbytes configurable Transmit
and Receive FIFO buffers
—Optimized descriptor fetching and write-
back mechanisms
■ PHY
—Integrated PHY for 10/100/1000 Mbps
full and half duplex operation
—IEEE 802.3ab Auto-Negotiation support
—IEEE 802.3ab PHY compliance and
compatibility
—PHY ability to automatically detect
polarity and cable lengths and MDI
versus MDI-X cable at all speeds
■ Host Offloading
—Transmit and receive IP, TCP and UDP
checksum off-loading capabilities
—Transmit TCP segmentation
—IEEE 802.1q VLAN support with
VLAN tag insertion, stripping and
packet filtering for up to 4096 VLAN
tags
—Advanced packet filtering
■ Manageability
—Manageability features on both ports:
SMB port, ASF 1.0, ACPI, Wake on
LAN, and PXE
—Compliance with PCI Power
Management 1.1 and ACPI 2.0 register
set compliant
■ T wo complete gigabit Ethernet connections
in a single device
■ Eight activity and link indication outputs
that directly drive LEDs
■ Lead-free
a
364-pin Ba ll Grid Array (BGA).
Devices that are lead-free are marked with
a circled “e1” and have the product code:
NHxxxxxx.
a. This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at <1000 ppm.
The Material Declaration Data Sheet, which includes lead impurity levels and the concentration of other Restriction on Hazardous Substances (RoHS)-banned materials, is available at:
ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks
In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the de-
vice. For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales representative.
Revision 1.7
October 2005
Revision History
Revision Date Description
1.7 Oct 2005
1.6 June 2005
1.5 April 2005
1.4 Sept 2004
1.3 Dec 2003 Added an I/O Characteristics table in Section 4.3, “DC Characteristics.”
1.2 Nov 2003
1.1 Sept 2003 Declassified document from confidential status.
1.0 July 2003 Initial release.
Corrected the nominal impedance values for the I/O cells from 50 KΩ to a
nominal impedance value of 120 KΩ, with a minimum of 90 KΩ and a
maximum of 190 KΩ.
Corrected typing error of “q” to “θ” in Section 6.3, “Thermal Specifications,” on
page 38.
• Changed interrupt signals INTA# and INTB# symbol types from TS (tristate) to OD (open drain).
• Added a more detailed AUX_PWR pin description.
• Added tristate and XOR non-JTAG test modes description.
• Added lead-free product and ordering information.
• Added major product features to cover page.
• Added text stating that the TTL inputs on the Ethernet controller are not 5V
tolerant.
• Updated thermal specifications.
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty , relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 82546GB Gigabit Ethernet controller may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order .
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © 2005, Intel Corporation.
®
Intel
is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.
*Third-party brands and names are the property of their respective owners.
ii Datasheet
Networking Silicon — 82546GB
Contents
1.0 Introduction.........................................................................................................................1
1.1 Document Scope...................................................................................................2
1.2 Reference Documents . ....... ...... .......................................................... ....... ...... ......2
1.3 Product Codes.......................................................................................................3
2.0 Additional 82546GB Features............................................................................................5
2.1 PCI ........................................................................................................................5
2.2 MAC ......................................................................................................................5
2.3 PHY.......................................................................................................................5
2.4 Host Offloading...... ...... ....... ...... ....... ...... ...... ....... ...... .............................................6
2.5 Manageability ........................................................................................................6
2.6 Device ...................................................................................................................7
2.7 Technology............................................................................................................7
3.0 Signal Descriptions.............................................................................................................8
3.1 Signal Type Definitions..........................................................................................8
3.2 PCI Bus Interface ..................................................................................................8
3.2.1 PCI Address, Data and Control Signals ...................................................9
3.2.2 Arbitration Signals ..................................................................................10
3.2.3 Interrupt Signals .....................................................................................10
3.2.4 System Signals.......................................................................................11
3.2.5 Error Reporting Signals..........................................................................11
3.2.6 Power Management Signals ..................................................................11
3.2.7 Impedance Compensation Signals.........................................................12
3.2.8 SMB Signals...........................................................................................12
3.3 EEPROM Interface Signals.................................................................................12
3.4 Flash Interface Signals........................................................................................13
3.5 Miscellaneous Signals.........................................................................................13
3.5.1 LED Signals............................................................................................13
3.5.2 Software Definable Signals....................................................................13
3.6 PHY Signals ................ ....... ...... ....... ...... ...... ....... .................................................14
3.6.1 Crystal Signals .......................................................................................14
3.6.2 PHY Analog Signals.................................... ....... ...... ....... .......................14
3.7 Serializer / Deserializer Signals...........................................................................15
3.8 JTAG Test Interface Signals ...............................................................................16
3.9 Power Supply Connections .................................................................................16
3.9.1 Power Support Signals...........................................................................16
3.9.2 Digital Supplies.......................................................................................16
3.9.3 Analog Supplies ................. .......................................................... ...... ....1 6
3.9.4 Ground and No Connects.......................................................................17
4.0 Test Port Functionality......................................................................................................18
4.1 XOR Testing........................................................................................................18
4.1.1 XOR Tree Control and Operation...........................................................18
4.1.2 Pins Tested ............................................................................................19
4.2 Tristate Mode ......................................................................................................20
4.2.1 Tristate Mode Control and Operation.....................................................20
Datasheet iii
82546GB — Networking Silicon
4.2.2 Tristate Mode Using JTAG (TAP)...........................................................20
5.0 Voltage, Temperature, and Timing Specifications ...........................................................21
5.1 Targeted Absolute Maximum Ratings.................................................................21
5.2 Recommended Operating Conditions.................................................................21
5.3 DC Specifications................................................................................................22
5.4 AC Characteristics ..............................................................................................25
5.5 Serial Interface Specifica tio ns............ ...... ...... ....... ...... ........................................26
5.6 Timing Specifications ............................... ...... .....................................................27
5.6.1 PCI/PCI-X Bus Interface ........................................................................27
5.6.1.1 PCI/PCI-X Bus Interface Clock..................................................27
5.6.1.2 PCI/PCI-X Bus Interface Timing................................................28
5.6.2 Link Interface Timing..............................................................................30
5.6.2.1 Link Interface Rise and Fall Time..............................................30
5.6.2.2 Link Interface Transmit Timing..................................................31
5.6.2.3 Link Interface Receive Timing..... ...... ........................................32
5.6.3 Flash Interface .......................................................................................33
5.6.4 EEPROM Interface ... ...... .......................................................... ....... ...... .34
6.0 Package and Pinout Information......................................................................................35
6.1 Device Identification ...........................................................................................35
6.2 Package Information ...........................................................................................36
6.3 Thermal Specifications........................................................................................38
6.4 Ball Mapping Diagram.........................................................................................39
6.5 Pinout Information...............................................................................................40
Figures
Tables
1 Gigabit Ethernet Controller Block Diagram ...........................................................2
2 XOR Tree Concept..............................................................................................18
3 AC Test Loads for General Output Pins..............................................................26
4 PCI/PCI-X Clock Timing......................................................................................27
5 PCI Bus Interface Output Timing Measurement .................................................29
6 PCI Bus Interface Input Timing Measurement Conditions..................................29
7 TVAL (max) Rising Edge Test Load....................................................................29
8 TVAL (max) Falling Edge Test Load...................................................................30
9 Link Interface Rise/Fall Timing............................................................................31
10 Transmit Interface Timing ..... ...... ....... ...... ...... ....... ...... ....... ...... ....... ...... ....... ...... .31
11 Receive Interface Timing ....................................................................................32
12 Flash Read Timing..............................................................................................33
13 Flash Write Timing ..............................................................................................33
14 82546GB Device Identification Markings ............................................................35
15 82546GB 364-Lead BGA Ball Pad Dimensions..................................................36
16 82546GB Mechanical Spec ifi catio ns.................................. ...... ....... ...... ....... ...... .37
1 Tested Pins Included in XOR Tree......................................................................19
2 Absolute Maximum Ratings ................................................................................21
3 Recommended Operating Conditions.................................................................21
4 DC Characteristics ..............................................................................................22
5 Power Supply Characteristics.............................................................................22
iv Datasheet
Networking Silicon — 82546GB
6 I/O Characteristics...............................................................................................24
7 AC Characteristics: 3.3 V Interfacing ..................................................................25
8 25 MHz Clock Input Requirements......................................................................25
9 Link Interface Clock Requirements .....................................................................25
10 EEPROM Interface Clock Requirements ............................................................26
11 AC Test Loads for General Output Pins..............................................................26
12 Driver Characteristics..........................................................................................26
13 Receiver Characteristics .....................................................................................27
14 PCI/PCI-X Bus Interface Clock Parameters........................................................27
15 PCI/PCI-X Bus Interface Timing Parameters......................................................28
13 PCI Bus Interface Timing Measurement Conditions ...........................................28
16 Rise and Fall Times.............................................................................................30
17 Transmit Interface Timing....................................................................................31
18 Receive Interface Timing.....................................................................................32
19 Flash Read Operation Timing .............................................................................33
20 Flash Write Operation Timing..............................................................................34
21 Link Interface Clock Requirements .....................................................................34
22 Link Interface Clock Requirements .....................................................................34
23 Thermal Characteristics ......................................................................................38
24 PCI Address, Data, and Control Signals.............................................................40
25 PCI Arbitration Signals........................................................................................40
26 Interrupt Signals ..................................................................................................41
27 System Signals....................................................................................................41
28 Error Reporting Signals.......................................................................................41
29 Power Management Signals ...............................................................................41
30 Impedance Compensation Signals......................................................................41
31 SMB Signals........................................................................................................41
32 EEPROM Interface Signals.................................................................................41
33 Flash Interface Signals........................................................................................42
34 LED Signals.........................................................................................................42
35 Software Definable Signals.................................................................................42
36 Crystal Signals ....................................................................................................42
37 PHY Signals ................ ....... ...... ....... .......................................................... ...... ....4 2
38 Serializer / Deserializer Signals...........................................................................43
39 JTAG Test Interface Signals ...............................................................................43
40 Power Support Signals........................................................................................43
41 Digital Power Signals ..........................................................................................44
42 Analog Power Signals . ....... .......................................................... ...... ....... ...... ....44
43 Grounds and No Connect Signals.......................................................................45
44 Reserved Signals ................................................................................................46
Datasheet v
82546GB — Networking Silicon
Note: This page is intentionally left blank.
vi Datasheet
1.0 Introduction
The Intel® 82546GB Dual Port Gigabit Ethernet Controller is a single, compact component with
two full integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY)
functions. The Intel
area and can be used for desktop and workstation PC network designs as well as backplane
applications with critical space constraints.
The Intel
®
82546GB integrates Intel’s fourth generation gigabit MAC and PHY to provide a
standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T
applications (802.3, 802.3u, and 802.3ab). The controller is capable of transmitting and receiving
two channels of data at rat es o f 1000 Mbps, 10 0 Mbps , or 1 0 Mbps. In addi tion, it provi des a 64- bit
wide direct Peripheral Component Interconnect (PCI) 2.3 and PCI-X 1.0a compliant interface
capable of operating at frequencies up to 133 MHz. The 82546GB also delivers a dual port PCI-X
solution without added bridge lat ency.
The Intel
®
82546GB on-board System Management Bus (SMB) port enables network
manageability implementations required by information technology personnel for remote con trol
and alerting through the LAN. Using the SMB, management packets can be routed to or from a
management processor. The SMB port enables industry standards, such as Intelligent Platform
Management Interface (IPMI) and Alert Standard Format (ASF), to be implemented using the
82546GB. In addition, on chip ASF 1.0 circuitry provides alerting and remote control capabilities
with standardized interfaces.
®
82546GB enables dual port Gi gabit Eth ernet i mplement ations in a ver y small
Networking Silicon — 82546GB
The 82546GB Dual Port Gigabit Ethernet Controller architecture is designed to deliver high
performance and PCI/PCI-X bus efficiency. Wide internal data paths eliminate performance
bottlenecks by efficiently handling large address and data words. Combining a parallel and pipelined logic architecture optimized for Gigabit Ethernet and independent transmit and receive
queues, the 82546GB controller efficiently handles packets with minimum latency. The 82546GB
controller includes advanced interrupt handling features to limit PCI bus traf fic and a PCI interface
that maximizes the use of bursts for efficient bus usage. The 82546GB is able to cache up to 64
packet descriptors in a single burst for efficient PCI bandwidth use. A large 64 Kbyte on-chip
packet buffer maintains superior performance as available PCI bandwidth changes. By using
hardware acceleration, the controller is able to offload tasks, such as checksum calculations and
TCP segmentation, from the host processor.
Datasheet 1
82546GB — Networking Silicon
PCI (64 bit,33/66MHz); PCI
S/W Defined
Pins MDI
Interface A
Design For Test
Interface
LED's
EEPROM
Interface
e
SM Bus
Interface
PHY
MDIO
MII
PHY
MDIO
MII S/W Defined
Pins LED's
External
TBI Interface
MDI Interface B
The 82546GBis packaged in a 21 mm x 21 mm 364-ball grid array and footprint compatible with
the Intel
Controller.
Figure 1. Gigabit Ethernet Controller Block Diagram
®
82544GC Gigabit Ethernet Controller and 82546EB Dual Port Gigabit Ethernet
1000Base-T PHY Interfaces
10/100/1000
GMII/
Device Funct. #0
MAC/Controller
(LAN A)
10/100/1000
GMII/
Device Funct. #1
MAC/Controlle r
(LAN B)
Flash Interfac
1.1 Document Scope
This document contains datasheet specifications for the 82546GB Dual Port Gigabit Ethernet
Controller, which includes sign al des cri pti on s, DC and AC parameters, packaging d at a, an d p in ou t
information.
1.2 Refe r ence Documents
It is assumed that the designer is acquainted with high-speed design and board layout techniques.
Document that may provide additional information are:
• PCI Local Bus Specification, Revision 2.3, PCI Special Interest Group.
• PCI-X Specification, Revision 1.0a, PCI Special Interest Group.
• PCI Bus Power Management Interface Specification, Rev. 1.1, PCI Special Interest Group.
• IEEE Standard 802.3, 1996 Edition, Institute of Electrical and Electronics Engineers (IEEE).
• IEEE Standard 802.3u, 1995 Edition, Institute of Electrical and Electronics Engineers (IEEE).
• IEEE Standard 802.3x, 1997 Edition, Institute of Electrical and Electronics Engineers (IEEE).
• IEEE Standard 802.3z, 1998 Edition, Institute of Electrical and Electronics Engineers (IEEE).
-X (133MHz)
2 Datasheet
• IEEE Standard 802.3ab, 1999 Edition, Institute of Electrical and Electronics Engineers
(IEEE).
®
• Intel
Ethernet Controllers Timing Device Selection Guide, AP-419. Intel Corporation.
1.3 Product Codes
The product ordering code for the 82546GB is: FW82546GB.
The lead-free product ordering code for the 82546GB is: NH82546GB.
Networking Silicon — 82546GB
Datasheet 3
82546GB — Networking Silicon
Note: This page intentionally left blank.
4 Datasheet
2.0 Additional 82546GB Features
2.1 PCI
Feature Benefits
Algorithms that optimally use advanced PCI, MWI,
MRM, and MRL commands as well as PCI-X MRD,
MRB, and MWB commands
2.2 MAC
Features Benefits
Low-latency transmit and receive queues
Caches up to 64 packet descriptors in a single burst • Efficient use of PCI bandwidth
Descriptor ring management hardware for transmit
and receive
Mechanism available for reducing interrupts
generated by transmit and receive operations
Support for transmission and reception of packets up
to 16 Kbytes
• Efficient bus operations
• Network packets handled without waiting or buffer
overflow.
• Simple software programming model
• Maximizes system performance and throughput
• Enables jumbo frames
Networking Silicon — 82546GB
2.3 PHY
Feature Benefits
State-of-the-art DSP architecture implements digital
adaptive equalization, echo cancellation, and crosstalk cancellation
Datasheet 5
• Robust performance in noisy environments
• Tolerance of common electrical signal
impairments
82546GB — Networking Silicon
2.4 Host Offloading
Features Benefits
Descriptor ring management hardware for transmit
and receive
16-Kbyte jumbo frame support
Interrupt coalescing (multiple packets per interrupt)
2.5 Manageability
Features Benefits
On-board SMB port
Preboot eXecution Environment (PXE) Flash
interface support (32-bit and 64-bit)
Compliance with PCI Power Management 1.1 and
ACPI 2.0 register set compliant including:
• D0 and D3 power states
• Network Device Class Power Management
Specification 1.1
• PCI Specification 2.3
SNMP and RMON statistic counters
SDG 3.0, WfM 2.0, and PC2001 compliance
Wake on LAN support
IPMI MAC Address Read capability
2
IPMI I
C Addressing capability • Enables device addressing over the I2C bus
• Optimized fetching and write-back mechanisms for
efficient system memory and PCI bandwidth
usage
• High throughput for large data transfers on
networks supporting jumbo frames
• Increased throughput by reducing interrupts
generated by transmit and receive operations
• Enables IPMI and ASF implementations
• Allows packets routing to and from either LAN port
and a server management processor
• Local Flash interface for PXE image
• PCI power management capability requirements
for PC and embedded applications
• Easy system monitoring with industry standard
consoles
• Remote network management capabilities through
DMI 2.0 and SNMP software
• Packet recognition and wake-up for NIC and LOM
applications without software configuration
• Allows MAC address read to be read by remote
users through IMPI
6 Datasheet
2.6 Device
Internal PLL for clock generation (use either a 25 MHz
crystal or a 25 MHz oscillator)
JTAG (IEEE 1149.1) Test Access Port built in silicon • Simplified testing using boundary scan
On-chip power control circuitry
Eight software definable pins
Supports little endian byte ordering for both 32 and 64
bit systems and big endian byte ordering for 64 bit
systems
Provides loopback capabilities • Validates silicon integrity
Single-pin LAN disable function
VLAN Management Filtering • Allows VLAN-based management packet filtering
Full 2/3 Wire Downshift capability
PICMIG 3.1 Compliant SERDES Interface
Networking Silicon — 82546GB
Features Benefits
• Lower component count and system cost
• Reduced number of on-board power supply
regulators
• Simplified power supply design
• Additional flexibility for LEDs or other low speed
I/O devices
• Portable across application architectures
• Allows LAN port enabling and disabling through
BIOS control (OS not required) for both ports
• Allows silicon to downshift speed to two or three
wire install and still achieve valid link
• Enables interface connections with PICMIG 3.1
compliant devices
2.7 Technology
364-pin Ball Grid Array (BGA) package
Footprint compatible with the 82544GC/EI and
82545GM/EM single port gigabit Ethernet controllers
Implemented in 0.15µ CMOS process
3.3 V PCI signaling with an average power dissipation
of 3.5 W
Operating temperature: 0° C to 55° C (with or without
thermal management, maximum); 0° C to 70° C (with
increased thermal management, maximum)
Features Benefits
• 21 mm x 21 mm component makes LOM designs
easier
• Single port or dual port implementation on the
same board with minor option changes.
• Offers lowest geometry to minimize power and
size while maintaining Intel quality reliability
standards
• Lower power requirements
• Extended temperature attainable with thermal
management device for more demanding systems
requiring a wider temperature range.
Datasheet 7
82546GB — Networking Silicon
3.0 Signal Descriptions
Note: The targeted signal names are subject to change without notice. Verify with your local Intel sales
office that you have the latest information before finalizing a design.
3.1 Signal Type Definitions
The signals of the 82546GB controller are electrically defined as follows:
Name Definition
I Input. Standard input only digital signal.
O Output. S t andard output only digital signal.
TS Tri-state. Bi-directional three-state digital input/output signal.
Sustained Tri-state. Sustained digital three-state signal driven by one agent at a time.
STS
OD
A Analog. PHY analog data signal.
P Power. Power connection, voltage reference, or other reference connection.
R Reserved.
An agent driving the STS pin low must actively drive it high for at least one clock before letting it
float. The next agent of the signal cannot drive the pin earlier than one clock after it has been
released by the previous agent.
Open Drain. Wired-OR with other agents.
The signaling agent asserts the OD signal, but the signal is returned to the inactive state by a
weak pull-up resistor. The pull-up resistor may require two or three clock periods to fully restore
the signal to the de-asserted state.
Note: The TTL inputs on the Ethernet controller are not 5V tolerant. If these inputs are connected to 5V,
then damage to the Ethernet controller is likely to occur. TTL inputs include the JTAG interface
pins, the FLASH interface pins, the EEPROM interface pins, the LED pins, the software definable
pins, and the LAN_PWR_GOOD pin.
3.2 PCI Bus Interface
When the Reset signal (RST#) is asserted, the 82546GB will not drive any PCI outpu t or bidirectional pins except the Power Management Event signal (PME#).
8 Datasheet
3.2.1 PCI Address, Data and Control Signals
Symbol Type Name and Function
Address and Data. Address and data signals are multiplexed on the same PCI pins. A
bus transaction includes an address phase followed by one or more data phases.
The address phase is the clock cycle when the Frame signal (FRAME#) is asserted
low. During the address phase AD[63:0] contain a physical address (64 bits). For I/O,
this is a byte address, and for configuration and memory, a DWORD address. The
AD[63:0] TS
CBE[7:0]# TS
PAR TS
PAR64 TS
FRAME# STS
IRDY# STS
TRDY# STS
82546GB device uses little endian byte ordering.
During data phases, AD[7:0] contain the least significant byte (LSB) and AD[63:56]
contain the most significant byte (MSB).
The 82546GBcontroller may optionally be connected to a 32-bit PCI bus. On the 32-bit
bus, AD[63:32] and other signals corresponding to the high order byte lanes do not
participate in the bus cycle.
Bus Command and Byte Enables. Bus command and byte enable signals are
multiplexed on the same PCI pins. During the address phase of a transaction,
CBE[7:0]# define the bus command. In the data phase, CBE[7:0]# are used as byte
enables. The byte enables are valid for the entire data phase and determine which byte
lanes contain meaningful data.
CBE0# applies to byte 0 (LSB) and CBE7# applies to byte 7 (MSB).
Parity. The Parity signal is issued to implement even parity across AD[31:0] and
CBE[3:0]#. PAR is stable and valid one clock after the address phase. During data
phases, PAR is stable and valid one clock after either IRDY# is asserted on a write
transaction or TRDY# is asserted after a read transaction. Once PAR is valid, it remains
valid until one clock after the completion of the current data phase.
When the 82546GB controller is a bus master, it drives P AR for address and write data
phases, and as a slave device, drives PAR for read data phases.
Parity 64. The Parity 64 signal is issued to implement even parity across AD[63:32] and
CBE[7:4]#. PAR64 is stable and valid one clock after the address phase. During data
phases, PAR64 is stable and valid one clock after either IRDY# is asserted on a write
transaction or TRDY# is asserted after a read transaction. Once PAR64 is valid, it
remains valid until one clock after the completion of the current data phase.
When the 82546GB controller is a bus master, it drives PA R64 for address and write
data phases, and as a slave device, drives PAR64 for read data phases.
Cycle Frame.
beginning and length of an access and indicate the beginning of a bus transaction.
While FRAME# is asserted, data transfers continue. FRAME# is de-asserted when the
transaction is in the final data phas
Initiator Ready. Initiator Ready indicates the ability of the 82546GB controller (as bus
master device) to complete the current data phase of the transaction. IRDY# is used in
conjunction with the Target Ready signal (TRDY#). The data phase is completed on any
clock when both IRDY# and TRDY# are asserted.
During the write cycle, IRDY# indicates that valid data is present on AD[63:0]. For a
read cycle, it indicates the master is ready to accept data. Wait cycles are inserted until
both IRDY# and TRDY# are asserted together. The 82546GB controller drives IRDY#
when acting as a master and samples it when acting as a slave.
Target Ready. The Target Ready signal indicates the ability of the 82546GB controller
(as a selected device) to complete the current data phase of the transaction. TRDY# is
used in conjunction with the Initiator Ready signal (IRDY#). A data phase is completed
on any clock when both TRDY# and IRDY# are sampled asserted.
During a read cycle, TRDY# indicates that valid data is present on AD[63:0]. For a write
cycle, it indicates the target is ready to accept data. Wait cycles are inserted until both
IRDY# and TRDY# are asserted together. The 82546GB device drives TRDY# when
acting as a slave and samples it when acting as a master.
The Frame signal is driven by the 82546GB device to indicate the
e.
Networking Silicon — 82546GB
Datasheet 9
82546GB — Networking Silicon
Symbol Type Name and Function
Stop. The Stop signal indicates the current target is requesting the master to stop the
STOP# STS
IDSEL# I
DEVSEL# STS
VIO P
current transaction. As a slave, the 82546GB controller drives STOP# to request the
bus master to stop the transaction. As a master, the 82546GB controller receives
STOP# from the slave to stop the current transaction.
Initialization Dev ic e Se lect. The Initialization Device Select signal is used by the
82546GB as a chip select signal during configuration read and write transactions.
Device Select. When the Device Select signal is actively driven by the 82546GB, it
signals notifies the bus master that it has decoded its address as the target of the
current access. As an input, DEVSEL# indicates whether any device on the bus has
been selected.
VIO. The VIO signal is a voltage reference for the PCI interface (3.3 V or 5 V PCI
signaling environment). It is used as the clamping voltage.
Note: An external resistor is required between the voltage reference and the VIO pin.
The target resistor value is 100 KΩ
3.2.2 Arbitration Signals
Symbol Type Name and Function
REQ64# TS
ACK64# TS
REQ# TS
GNT# I
LOCK# I
Request Transfer. The Request Transfer signal is generated by the current initiator
indicating its desire to perform a 64-bit transfer. REQ64# has the same timing as the
Frame signal.
Acknowledge Transfer. The Acknowledge Transfer signal is generated by the currently
addressed target in response to the REQ64# assertion by the initiator. ACK64# has the
same timing as the Device Select signal.
Request Bus. The Request Bus signal is used to request control of the bus from the
arbiter. This signal is point-to-point.
Grant Bus. The Grant Bus signal notifies the 82546GB that bus access has been
granted. This is a point-to-point signal.
Lock Bus. The Lock Bus signal is asserted by an initiator to require sole access to a
target memory device during two or more separate transfers. The 82546GB device
does not implement bus locking.
3.2.3 Interrupt Signals
Symbol Type Name and Function
INTA# OD
INTB# OD
Interrupt A. Interrupt A is used to request an interrupt by port 1 of the 82546GB. It is
an active low, level-triggered interrupt signal.
Interrupt B. Interrupt B is used to request an interrupt by port 2 of the 82546GB. It is
an active low, level-triggered interrupt signal.
10 Datasheet
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