The ATMEM4, ATMEM8 and ATMEM16 all run at 100 ns. The boards support no other speeds.
5. TYPE
The ATMEM4 and ATMEM8 support only 1 Mbit X 1 DRAMs. The ATMEM16 supports 1 Mbit X 1 and 4 Mbit X 1 DRAMs. The boards support no other size DRAMs.
6. MEMORY BOARD MAKEUP
Like the baseboard memory, each 32-bit extended memory board uses nine individual DRAMs to form one byte. The nine bits correspond to eight memory bits and one
parity bit. To form a 32-bit word, the memory boards use four bytes (36 total DRAMs; 32 memory bits and 4 parity bits).
* NOTE: Like the baseboard memory, the extended memory boards do not support ECC.
7. EXPANDED MEMORY
The Model 303 can use extended memory to emulate expanded memory. The Model 303 does not support expanded memory functionality via hardware, but instead Intel
suggests using a software emulation package. CTRL386, 386MAXX and QEMM are all high quality expanded memory emulation packages available on the software
market.
Cache Features
1. SIZE
Like the Model 302, the Model 303 uses a 64 KB cache to provide zero wait state performance.
2. IMPLEMENTATION
The system does not use the Intel 82385 cache controller, choosing instead to implement the cache with discrete logic. Using discrete logic instead of the 82385 does not
imply slower performance or an inferior cache design. Both caches perform equally well and there are no significant performance discrepancies. The direct mapped with
posted write through cache design is an Intel386 MicroComputer standard which provides an impressive 90 percent hit ratio with 100 percent cache coherency.
3. COMPONENT SPEED
The cache uses three 15 ns Tag SRAMs to locate addresses within the cache. Eight 25 ns 16 Kbit X 4 data SRAMs provide 16 KB of data addresses and make up the 64 KB
data cache.
4. WAIT STATES
Locating data within the cache produces zero wait state performance. However, during a cache miss, slower main memory must be accessed. Depending on the speed and
type of the DRAMs installed, as well as the memory address location, a cache miss will result in various numbers of wait states. The absolute worst case scenario results in
a maximum of eight wait states. Keep in mind that a wait state at 33 MHz is just 30 ns. Competitors' cache designs are not immune to the realities of memory design and
wait states of high speed processors. All computers running at 33 MHz will have cache miss wait state performance not significantly different than the Model 303.
5. SNOOPING
The cache algorithm implements a snooping feature to ensure cache coherency when the CPU is put into a hold state. When a bus master device puts the CPU into a hold
state, the Model 303's main memory may be accessed or modified. When the bus master releases control, the snooping feature checks the data cache with main memory
data to ensure cache coherency. This feature allows intelligent PC/AT add-in boards performing DMA to modify main memory without destroying the integrity of the cache.
Central Processing Unit(CPU) Features
1. SPEED
The Model 303 uses an official 32-bit 33 MHz 386 MicroProcessor. Some competitors may run a 25 MHz 386 CPU at 33 MHz, raising the serious question of reliability
and longevity. Intel's MicroComponents Group does not sanction 25 MHz 386 CPUs running faster than 25 MHz. The Model 303 does not require a heat sink.
2. ADDRESS PIPELINING
The Model 303 does not use the address pipelining capabilities of the 386 MicroProcessor. Extensive study of the 386 CPU pipelining feature determined that for the CPU
sections of the Model 302 and Model 303, pipelining did not provide any additional wait state reductions.
3. MATH COPROCESSOR
The Model 303 supports both the Intel 387 coprocessor and the Weitek 3167 and the 3167BRD coprocessor products. All the coprocessors run synchronously with the 386
CPU at 33 MHz.
Battery and Real Time Clock Features
Like the Model 302, the Model 303 uses the Dallas Semiconductor 1287 CMOS Real Time clock. The real time clock contains 64 bytes of RAM locations, 14 bytes used
for clock and control registers and 50 bytes of general purpose RAM. A self-contained lithium battery provides ten years of data integrity in the absence of power. The
1287 is directly pin-compatible with the MC146818A clock chip used on the original IBM PC/AT. Therefore, using the 1287 introduces no incompatibilities with the IBM
PC/AT standard and only enhances the Model 303 by increasing the real time clock reliability and functionality.
I/O Ports Features
1. SERIAL PORTS
The Model 303 supports two DB9 RS232 serial ports configured as COM1 and COM2. In addition, COM2 may be configured as a 25-pin serial connector. Both ports may
be enabled or disabled via easily accessible jumper locations on the system board. Using two Intel 82510 serial drivers, the Model 303 supports baud rates of 300, 1200,
2400, 9600, 19,200 and 38,400. In accordance with the RS232 standard, Intel discourages the use of cables longer than 50 feet in length connected to the serial ports.
2. PARALLEL PORT
The Model 303 provides one Centronix parallel port configurable as either LPT1 or LPT2. The port may be enabled or disabled for LPT1 or LPT2 via easily accessible
jumper locations on the system board. The parallel port may also be configured to use the leading or trailing edge of the printer acknowledge signal.
3. MOUSE PORT
Integrated onto the system board, the Model 303 provides a PS/2 style mouse connector supporting full mouse functionality. The mouse circuitry implemented via the
keyboard controller is completely PS/2 compatible. Per IBM specifications, the mouse port uses interrupt 12. No jumper exists on the baseboard to disable the mouse port.
However, since the mouse port is driven by an open collector circuit, other devices can use IRQ 12 when the user disconnects the mouse.
4. KEYBOARD CONNECTOR
The Model 303 supports a wide variety of 84 and 101 key AT compatible keyboards. The microcomputer does not support XT or PCjr style keyboards.
5. SPEAKER PORT
The Model 303 provides a programmable speaker. The speaker provides error beep code information and may be programmed via port 61H per the IBM PC/AT
specification.