INFINEON TDA5251 F1 User Manual

Preliminary Specification, Version 1.0, 2003-02-18

TDA5251 F1 ASK/FSK 315MHz Wireless

Transceiver

Wireless Components

Never stop thinking.

Edition 2003-02-18 Published by Infineon Technologies AG,

St.-Martin-Strasse 53, D-81541 München, German y

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Preliminary Specification, Version 1.0, 2003-02-18

TDA5251 F1 ASK/FSK 315MHz Wireless

Transceiver

Wireless Components

Never stop thinking.

Preliminary Specification Confidential Revision History: 2003-02-18 TDA5251 F1

Previous Version: Page Subjects (major changes since last revision)

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ASK/FSK 315MHz Wireless Transceiver TDA5251 F1

Product Info

General Description

The IC is a low power consumption single chip FSK/ASK Transceiver for half duplex low datarate communication in the 315MHz band. The IC offers a very high level of in tegr ation an d needs only a few external components. It contains a highly efficient power amplifier, a low noise amplifier (LNA) with AGC, a double balanced mixer, a complex direct conversion stage, I/ Q limiters with RSSI generation, an FSK demodulator, a fully integrated VCO and PLL synthesizer, a tuneable crystal oscillator, an onboard data filter, a data comparator (slicer), positive and negative peak detectors, a data rate detection circuit and a 2/3-wire bu s interface. Ad ditionally th ere is a power down feature to save battery power.

Version 1.0

Features

– Low supp ly c u rre nt (Is = 9mA typ. receive, I

= 13mA typ. transmit mode) – Supply voltage range 2.1 - 5.5V – Power down mode with very low supply

current consumption – FSK and ASK modulation and demodulation

capability – Fully integrated VCO and PLL

synthesizer and loop filter on-chip with on

chip crystal oscillator tuning

Application

– Low Bitrate Communication

Systems – Keyless Entry Systems – Remote Control Systems –Alarm Systems – Telemetry Systems

–I

C/3-wire µController Interface

– On-chip low pass channel select filter and

data filter with tuneable bandwidth

– Data slicer with self-adjusting threshold and

2 peak detectors

– FSK sensitivity <-109dBm, ASK sensitivity <

–109dBm – Transmit power up to +13dBm – Self-polling logic with ultra fast data rate

detection

– Electronic Metering – Home Automation Systems

Type Ordering Code Package

TDA5251 F1 P-TSSOP-38-1

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Table of Contents

page

1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4 Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.4.1 Power Amplifier (PA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.4.2 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.4.3 Downconverter 1st Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.4.4 Downconverter 2nd I/Q Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.4.5 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.4.6 I/Q Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.4.7 I/Q Limiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4.8 FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4.9 Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.4.10 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.4.11 Peak Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.4.12 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.4.13 Bandgap Reference Circuitry and Powerdown . . . . . . . . . . . . . 22

2.4.14 Timing and Data Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.4.15 Bus Interface and Register Definition . . . . . . . . . . . . . . . . . . . . 23

2.4.16 Wakeup Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.4.17 Data Valid Detection, Data Pin . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.4.18 Sequence Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.4.19 Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.4.20 RSSI and Supply Voltage Measurement . . . . . . . . . . . . . . . . . . 35

3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.1 LNA and PA Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.1.1 RX/TX Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.1.2 Switch in RX-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.1.3 Switch in TX-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.1.4 Power-Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.2 Crystal Osc illa tor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

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3.2.1 Synthesizer Frequency setting . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.2.2 Transmit/Receive ASK/FSK Frequency Assignment . . . . . . . . . 50

3.2.3 Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.2.4 Calculation of the external capacitors . . . . . . . . . . . . . . . . . . . . 54

3.2.5 FSK-switch modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.2.6 Finetuning and FSK modulation relevant registers . . . . . . . . . . 55

3.2.7 Chip and System Tolerances . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.3 IQ-Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.4 Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.5 Limiter and RSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.6 Data Slicer - Slicing Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.6.1 RC Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.6.2 Peak Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.6.3 Peak Detector - Analog output signal . . . . . . . . . . . . . . . . . . . . 64

3.6.4 Peak Detector – Power Down Mode . . . . . . . . . . . . . . . . . . . . . 64

3.7 Data Valid Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.7.1 Frequency Window for Data Rate Detection . . . . . . . . . . . . . . . 67

3.7.2 RSSI threshold voltage - RF input power . . . . . . . . . . . . . . . . . 68

3.8 Calculation of ON_TIME and OFF_TIME . . . . . . . . . . . . . . . . . . . 68

3.9 Example for Self Polling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.10 Sensitivity Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

3.10.1 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

3.10.2 BER performance depending on Supply Voltage . . . . . . . . . . . 72

3.11 Default Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

4 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.1.4 Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

4.2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4.3 Test Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

4.4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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Product Description

1 Product Description

1.1 Overview

The IC is a low power consumption single chip FSK/ASK Transceiver for the frequency band 315MHz. The IC combines a very high level of integration and minimum external part count. The device contains a low nois e amplifier (LNA), a d ouble balanced mixe r, a fully integrated VC O, a PLL synthesizer, a crystal oscillator with FSK modulator, a limiter with RSSI generator, an FSK demodulator, a dat a filter, a data comp ara tor (slicer), a posi tive an d a negative data peak detector, a highly efficient power amplifier and a complex digital timing and control unit with I microcontroller interface. Additionally there is a power down feature to save battery power.

The transmit section uses direct ASK modulation by switching the power amplifier, and crystal oscillator detuning for FSK modulation. The necessary detuning load capacitors are external. The capacitors for fine tuning are integrated. The receive section is using a novel single-conversion/ direct-conversion scheme that is combining the advantages of both receive topologies. The IF is contained on the chip, no RF channel filters are necessary as the channel filter is also on the chip.

The self-polling logi c can be used to le t the device operate autonomously as a master for a dec oding microcontroller.

C/3-wire

1.2 Features

– Low supply current (Is = 9 mA typ. receive, Is = 13mA typ. transmit mode, both at 3 V supply

voltage, 25°C) – Supply voltage range 2.1 V to 5.5 V – Operating temperatur e range -40°C to +85°C – Power down mode with very low supply current consumption – FSK and ASK modulation and demodulation capability without external circuitry changes, FM

demodulation capability – Fully integrated VCO and PLL synthesizer and loop filter on-chip with on-chip crystal oscillator

tuning, therefore no additional external components necessary – Differential receive signal path completely on-chip, therefore no external filters are necessary – On-chip low pass channel select and data filter with tuneable bandwith – Data slicer with self-adjusting threshold and 2 peak detectors – Self-polling logic with adjustable duty cycle and ultrafast data rate detection and timer mode

providing periodical interrupt – FSK and ASK sensitivity < -109 dBm – Adjustable LNA gain – Digital RSSI and Battery Voltage Readout – Provides Clock Out Pin for external microcontroller – Transmit power up to +13 dBm in 50W load at 5V supply voltage

–I

C/3-wire microcontroller interface, working at max. 400kbit/s

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1.3 Application

– Low Bitrate Communication Systems – Keyless Entry Systems – Remote Control Systems –Alarm Systems – Telemetry Systems – Electronic Metering – Home Automation Systems

1.4 Package Outlines

Product Description

P-TSSOP-38-1.EPS

Figure 1-1 P-TSSOP-38-1 package outlines

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2 Functional Description

2.1 Pin Configuration

VCC

BUSMODE

____

ASKFSK

RxTx

LNI

LNIx

GND1

GNDPA

VCC1

PDN

PDP

SLC

VDD

BUSDATA

BUSCLK

VSS

XOUT

Functional Description

CI1

CI1x

CQ1

CQ1x

CI2

CI2x

CQ2

CQ2x

GND

RSSI

DATA ___ PWDDD

CLKDIV ______ RESET ___ EN

XGND

XSWA

XIN

XSWF

5251F1_pin_conf.wmf

Figure 2-1 Pin Configuration

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2.2 Pin Definitions and Functions

Table 2-1 Pin Definition and Function

Pin No.

Symbol Equivalent I/O-Schematic Function

VCC Analog su pply (antiparallel diode s

1 11

BUSMODE Bus mode selection (I²C/ 3 wire bus

350

Functional Description

between VCC, VCC1, VDD)

mode selection)

LF Loop filter and VCO control volt age

200

ASKFSK ASK/FSK- mode switch input

350

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Functional Description

5 RXTX RX/TX-mode switch input/output

LNI RF input to differential Low Noise

350

Amplifier (LNA))

5k 5k

PWDN

LNIX see Pin 6 Complementary RF i np u t to

1.1V 7

180180

PWDN

differential LNA

GND1 Ground return for LNA and Power

Amplifier (PA) dirver stage

9 10

GNDPA see Pin 8 Ground return for PA output stage PA PA output stage

GndPA

VCC1 see Pin 1 Supply for LNA and PA

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Functional Description

12 PDN Output of the negative peak

detector

PWDN

350

50k

PDP Output of the positive peakdetector

50k

350

PWDN

SLC Slicer level for the data slicer

1.2uA

350

50k

50k 50k

50k

15 16

1.2uA

50k 50k

VDD see Pin 1 Digital supply BUSDATA Bus data in/output

15k

350

BUSCLK Bus clock input

350

VSS see Pin 8 Ground for digital section

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Functional Description

19 XOUT Crystal oscillator output, can also

be used as external reference frequency input.

Vcc

Vcc-860mV

150

XSWF FSK modulation switch

125fF ..... 4pF

250fF ..... 8pF

XIN see Pin 20

22 XSWA ASK modulation/FSK center

frequency switch

23 24

XGND

see Pin 22

Crystal oscillator ground return

EN 3-wire bus enable input

350

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Functional Description

25 RESET Reset of the entire system (to

default values), active low

110k

350

10p

350

CLKDIV Clock output

PWDDD Power Down input (active high),

data detect output (active low)

30k

350

DATA TX Data input, RX data ou tput (RX

powerdown: pin 28 @ GND)

350

RSSI RSSI outp ut

350

37k

16p

S&H

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Functional Description

30 GND see Pin 8 Analog ground 31

CQ2x Pin for external Capacitor

Q-channel, stage 2

Stage1:Vcc-630mV

Stage2: Vcc-560mV

32 33 34 35 36 37 38

CQ2 II Q-channel, stage 2 CI2x II I-channel, stage 2 CI2 II I-channel, stage 2 CQ1x II Q-channel, stage 1 CQ1 II Q-channel, stage 1 CI1x II I-channel, stage 1 CI1 II I-channel, stage 1

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2.3 Functional Block Diagram

ASKFSK

PDP

100k

ASK/FSK

100k

Det

+Peak

BUSMODE __

BUSCLK

BUSDATA

RXTX

Data (RX/TX)

CLKDIV

PWDDD

282627

LOGIC

17 24 2

SLC

WAKEUP

INTERFACE

CONTROLLER

SLICER

Data

FILTER

ASK

FSK

Functional Description

PDN

100k

Det

-Peak

RESET

VCC

6-bit

SAR-ADC

RSSI

(digital)

(analog)

(LNA/PA)

FSK DATA

Bandgap

Reference

CLK

VssGnd1

Gnd

XSWA XGND

22 23

XSWF

VDD

VCC

VCC1

XIN

QUADRI

CORRELATOR

CQ2x

CQ2

CI2x

CI2

CQ1x

35 36

CQ1 CI1x CI1

(digital)

(analog)

(LNA/PA)

LIMITER

Filter

Channel

MIXER

= 105MHz

LNI

= 315MHz

ANT

37 38

LIMITER

Filter

Channel

MIXER

FILTER

LNA MIXER

single ended to

differenti al conv.

Gain

high/low

LNIx

RSSI

0°

f = 105MHz

90°

ASK/FSK

TX/RX

ASK DATA

PHASE

:6/8

TX/RX

LOOP

ANT

CRYSTAL Osc, FSKMod, Finetuni ng

= 13,125MHz

XOUT

DET.

Charge P.

FILTER

VCO

= 315MHz

= 420MHz

GndPA

TDA5251F1_blockdiagram_aktuell.wmf

Figure 2-2 Main Block Diagram

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Functional Description

2.4 Functional Block Description

2.4.1 Power Amplifier (PA)

The power amplifier is operating in C-mode. It can be used in either high or low power mode. In high-power mode the transmit power is approximately +13dBm into 50 Ohm at 5V and +6dBm at

2.1V supply voltage. In low power mode the transmit power is approximately +12dBm at 5V and 34dBm at 2.1V supply voltage using the same matching network. The transmit power is controlled by the D0-bit of the CONFIG register (subaddress 00H) as shown in the following Table 2-2. The default output power mode is high power mode.

Table 2-2 Sub Address 00H: CONFIG

Bit

In case of ASK modulation the power amplifier is turned fully on and off by the transmit baseband data, i.e. 100% On-Off-Keying.

Function Description Default

PA_PWR 0= low TX Power, 1= high TX Power 1

2.4.2 Low Noise Amplifier (LNA)

The LNA is an on- chip cascode amplifi er wit h a voltage gain of 15 to 2 0dB and symmetrical i npu ts. It is possible to reduce the gain to 0 dB via logic.

Table 2-3 Sub Address 00H: CONFIG

Bit

Function Description Default

LNA_GAIN 0= low Gain, 1= high Gain 1

2.4.3 Downconverter 1st Mixer

The Double Balanced 1st Mixer converts the input frequency (RF) in the range of 31 5M Hz dow n to the intermediate frequency (IF) at approximately 105MHz. The local oscillator frequency is generated by the PLL synthesizer that is fully implemented on-chip as described in Section 2.4.5. This local oscillator operates at approximately 420MHz in receive mode providing the above mentioned IF frequency of 105MHz. The mixer is followed by a low pass filter with a corner frequency of approximately 175MHz in order to prevent RF and LO signals from appearing in the 105MHz IF signal.

2.4.4 Downconverter 2nd I/Q Mixers

The Low pass filter is followed by 2 mixers (inphase I and quadrature Q) that convert the 105MHz IF signal down to zero-IF. These two mi xer s are driv en by a sig nal that is generate d by di viding the local oscillator signal by 4, thus equalling the IF frequency.

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Functional Description

2.4.5 PLL Synthesizer

The Phase Locked Loop synthesizer consists of two VCOs (i.e. transmit and receive VCO), a divider by 4, an asynchronous divider chain with selectable overall division ratio, a phase detector with charge pump and a lo op filter and is fully implem en ted on-chip. The VCOs are includ ing spiral inductors and varactor diodes. The center frequency of the transmit VCO is 630MHz, the center frequency of the receive VCO is 840MHz.

Generally in receive mode the relationship between local oscillator frequency f frequency fRF and the IF freq uency fIF and thus the frequency that is applied to the I/Q Mixers is given in the following formula:

osc

f 4 f 4/3

IFRF

[2 – 1]

The VCO signal is applied to a divider by 2 and afterwards by 4 which is producing approximately 105MHz signals in quad rature. The overa ll divisio n ratio of the div ider chai n following the divider by 2 and 4 is 6 in transmit mode and 8 in receive mode as the nominal crystal oscillator frequency is

13.125MHz. The division ratio is controlled by the RxTx

pin (pin 5) and the D10 bit in the CONFIG

, the receive RF

osc

2.4.6 I/Q Filters

The I/Q IF to zero-IF mixers are followed by baseband 6th order low pass filters that are used for RF-channel filtering.

INTERNAL BUS

iq_filter.wmf

Figure 2-3 One I/Q Filter stage

The bandwidth of the filters is controlled by the values set in the filter-register. It can be adjusted between 50 and 350kHz in 50kHz steps via the bits D1 to D3 of the LPF register (subaddress 03H).

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Functional Description

2.4.7 I/Q Limiters

The I/Q Limiters are DC coupled multistage amplifiers with offset-compensating feedback circuit and an overall gain of approximately 80dB each in the frequency range of 100Hz up to 350kHz. Receive Signal Streng th Indicator (RSSI) gene rators are included in both limiters which produ ce DC voltages that are directly proportional to the input signal level in the respective channels. The resulting I- and Q-channel RSSI-signals are summed to the nominal RSSI signal.

2.4.8 FSK Demodulator

The output differential si gnals of the I/Q limiters are fed to a quadrature corr elator circuit that is used to demodulate frequency shift keyed (FSK) signals. The demodulator gain is 2.4mV/kHz, the maximum frequency deviation is ±300kHz as shown in Figure 2-4 below.

The demodulated signa l is ap plie d to the ASK/FSK mode switch whic h is co nne cted to the input of the data filte r. The swit ch ca n be c ontrol led by the ASKFSK CONFIG register.

The modulation index m must be larger than 2 for correct demodulation of the signal.

1,6

pin (pin 4) and via the D11 bit in the

1,5

1,4

1,3

1,2

1,1

U /V

0,9

0,8

0,7

0,6

0,5

-350 -300 -250 -200 -150 -100 -50 0 50 100 150 200 250 300 350

f /kHz

Figure 2-4 Quadricorrelator Demodulation Characteristic

Qaudricorrelator.wmf

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Functional Description

2.4.9 Data Filter

The 2-pole data filter has a Sallen-Key arc hitecture and is impl emented fully on-chip. T he bandwidth can be adjusted betw een ap proxim ately 5 kHz an d 102k Hz via the bits D4 to D7 of the LPF register as shown in Table 3-10.

ASK / FSK

OTA

INTER NAL BU S

data_filter.wmf

Figure 2-5 Data Filter architecture

2.4.10 Data Slicer

The data slic er is a fast comparat or with a bandwidth of 100kHz. The self-a djusting thres hold is generated by a RC-network (LPF) or by use of one or both peak detectors depending on the baseband coding scheme as de scr ibed in Section 3.6. This can be controlled by the D15 bit of the

CONFIG register as shown in the following table.

Table 2-4 Sub Address 00H: CONFIG

Bit

D15

Function Description Default

SLICER 0= Lowpass Filter, 1= Peak Detector 0

2.4.11 Peak Detectors

Two separate Peak Detectors are available. They are generating DC voltages in a fast-attack and slow-release manner that are proportional to the positive and negative peak voltages appearing in the data signal. These voltages may be used to generate a threshold voltage for non-Manchester encoded signals, for example. The time-constant of the fast-attack/slow-release action is determined by the RC network with external capacitor.

2.4.12 Crystal Oscillator

The reference oscillator is an NIC oscillator type (Negative Impedance Converter) with a crystal operating in serial resonan ce. The no minal opera ting frequenc y of 13.125MH z and the freque ncies for FSK modulation ca n be adjus ted via 3 external c apacitors . Via micr ocontrolle r and bus interface the chip-internal capacitors can be used for finetuning of the nominal and the FSK modulation frequencies. This finetuning of the crystal oscillator allows to eliminate frequency errors due to crystal or component tolerances.

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Functional Description

2.4.13 Bandgap Reference Circuitry and Powerdown

A Bandgap Reference Circ uit provides a temperature s tab le 1.2V reference voltage for the d evice. A power down mode is available to switch off all subcircuits that are controlled by the bidirectional Powerdown&DataDetect PwdDD

pin (pin 27) as shown in the following table. Power down mode can either be ac tivated b y pin 27 or b it D1 4 in Re gister 00 . In p ower do wn mode a lso p in 28 (D ATA) is affected (see Section 2.4.17).

Table 2-5 PwdDD Pin Operating States

PwdDD

VDD

Ground/VSS

Operating State

Powerdown Mode

Device On

2.4.14 Timing and Data Control Unit

The timing and data control unit contains a wake-up logic unit, an I2C/3-wire microcontroller interface, a “data valid” detection unit and a set of configuration registers as shown in the subsequent figure.

REGISTERS

RF - BLOCK

RSSI

RX DATA

FSK DATA

ASK DATA

BLOCK ENABLE

ASK / FSK

RX / TX

INTERNAL BUS

6 Bit ADC

BusData

BusCLK

I2C / 3Wire

INTERFACE

DATA VALID

DETECTOR

AMPLITUDE

threshold TH 3

FREQUENCY

window

TH1<T

<TH2

GATE

DATA

ENABLE

CONTROL

LOGIC

POWER ON

SEQUENCER

BusMode

13.125 MHz XTAL-Osz

WAKEUP

LOGIC

RC-Osz.

VALID

32kHz

CLKDiv

PwdDD

Data

AskFsk

RxTx

Reset

logic.wmf

Figure 2-6 Timing and Data Control Unit

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Functional Description

The I2C / 3-wire Bus Interface gives an external microcontroller full control over important system parameters at any time.

It is possible to set the device in three different modes: Slave Mode, Self Polling Mode and Timer Mode. This is done by a state machine which is implemented in the WAKEUP LOGIC unit. A detailed description is given in Section 2.4.16.

The DATA VALID DETECTOR contains a frequency window counter and an RSSI threshold comparator. The window counter uses the incoming data signal from the data slicer as the gating signal and the crystal oscillator frequency as the timebase to determine the actual datarate. The result is compared with the expected datarate. The threshold comparator compares the actual RSSI level with the expected RSSI level.

If both conditions are true the PwdDD

pin is set to LOW in self polling mode as you can see in Section 2 .4.16. This signal can be used as an interrupt for an external µP. Because the PwdDD pin is bidirectional and open drain driven by an internal pull-up resistor it is possible to apply an external LOW thus enabling the device.

2.4.15 Bus Interface and Register Definition

The TDA5251 supports the I2C bus protocol (2 wire) and a 3-wire bus protocol. Operation is selectable by the BusMode pin (pin 2) as shown in the following table. All bus pins (BusData, BusCLK, EN where the output is open drain driven by an internal 15kW pull up resistor.

, BusMode) have a Schmitt-triggered input stage. The BusData pin is bidirectional

Table 2-6 Bus Interface Format

Function

C Mode Low High= inactive,

3-wire Mode

BusMode EN BusCLK BusData

High

BusData

BusCLK

BusMode

Figure 2-7 Bus Interface

Low= active

I2C / 3-wire

INTERFACE

FRONTEND

1 1 1 0 0 0 0 0

CHIP ADDRESS

Clock input Data in/out

INTERNAL BUS

i2c_3w_bus.wmf

Note: The Interface is able to access the internal registers at any time, even in POWER DOWN mode. There is no internal clock necessary for Interface operation.

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Functional Description

I2C Bus Mode

In this mode the BusMode pin (pin 2) = LOW and the EN pin (pin 24) = LOW.

Data Transition: Data transition on the pin BusData c an only occur whe n BusCLK is LOW . BusData tran sitions while

BusCLK is HIGH will be interpreted as start or stop condition.

Start Condition (STA): A start condition is defined b y a HIGH to LOW transition of the BusData lin e while BusCLK is HIG H.

This start condition must precede any command and initiate a data transfer onto the bus.

Stop Condition (STO): A stop condition is defined by a LOW to HIGH transit ion of the BusData line whi le BusCLK is HIGH.

This condition termi nates the com munication be tween the devices an d forces t he bus inte rface into the initial state.

Acknowledge (ACK): Indicates a successfu l data tra nsf er. The transmitte r wil l releas e the bu s aft er send ing 8 bit o f data.

During the 9th clock cycle th e receive r will set th e SDA line to LOW lev el to indic ate it has rec eived the 8 bits of data correctly.

Data Transfer Write Mode: To start the communi cation, the b us master must initiate a st art condition (ST A), followed by the 8bit

chip address. The chip address for the TDA5251 is fixed as „1110000“ (MSB at first). The last bit (LSB=A0) of the chip address byte defines the type of operation to be performed:

A0=0, a write operation is selected and A0=1 a read operation is selected. After this comparison the TD A52 51 w ill ge ner ate an ACK and awaits the desired s ub ad dress byte

(00H...0FH) and data bytes. At the end of the data transition the master has to generate the stop condition (STO).

Data Transfer Read Mode: To start the communication in the read mode, the bus master must initiate a start condition (STA),

followed by the 8 bit chip address (write: A0=0), followed by the sub address to read (80H, 81H), followed by the chip address (read: A0=1). After that procedure the data of the selected register (80H, 81H) is read out. During this time the data line h as to be kept in HIGH state an d the chip sends out the data. At the end of data transition the master has to generate the stop condition (STO).

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Functional Description

Bus Data Format in I2C Mode

Table 2-7 Chip address Organization

MSB

1 1 1 0 0 0 0 0 Chip Address Write 1 1 1 0 0 0 0 1 Chip Address Read

Table 2-8 I2C Bus Write Mode 8 Bit

MSB CHIP ADDRESS

(WRITE)

STA 1 1 1 0 0 0 0 0 ACK S7 S6 S5 S4 S3 S2 S1 S0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK STO

LSB MSB SUB ADDRESS (WRITE)

00H...08H, 0DH, 0EH, 0FH

Table 2-9 I2C Bus Write Mode 16 Bit

MSB CHIP ADDRESS (WRITE) LSB MSB SUB ADDRESS (WRITE)

STA 1 1 1 0 0 0 0 0 ACK S7 S6 S5 S4 S3 S2 S1 S0 ACK D15 ... D8 ACK D7 D6 ... D0 ACK STO

00H...08H, 0DH, 0EH, 0FH

Table 2-10 I2C Bus Read Mode

MSB CHIP ADDRESS (WRITE) LSB MSB SUB ADDRESS (R EAD)

STA 1 1 1 0 0 0 0 0 ACK S7 S6 S5 S4 S3 S2 S1 S0 ACK STA 1 1 1 0 0 0 0 1 ACK

80H, 81H

Table 2-10 I2C Bus Read Mode (continued)

MSB DATA OUT FROM SUB ADDRESS LSB

R7 R6 R5 R4 R3 R2 R1 R0 ACK* STO

* mandatory HIGH

LSB Function

LSB MSB DATA IN LSB

LSB MSB CHIP ADDRESS (READ) LSB

3-wire Bus Mode

In this mode pin 2 (BusMode)= HIGH and Pin 16 (BusData) is in the data input/output pin. Pin 24

) is used to activate t he bus inte rface to all ow the tran sfer of dat a to / from t he device. When pin

(EN 24 (EN

Data Transition: Data transition on pin 16 (Bus Da ta) can only occur if the clock BusCLK is LOW. To perform a data

transfer the interface has to be enabled. Th is is done by settin g the EN is done via BusData, BusCLK and EN

Data Transfer Write Mode: To start the communication the EN

data bytes have to follow. The subaddress (00H...0FH) determines which of the data bytes are transmitted. At the end of data transition the EN

Data transfer Read Mode: To start the communication in the r ead mode, the EN

address to read (80H, 81H). Afterwards the device is ready to read out data. At the end of data transition EN

) is inactive (HIGH), data transfer is inhibited.

line to LOW. A serial transfer

. The bit stream needs no chip address.

line has to be set to LOW. The desired sub address byte and

must be HIGH.

line has to be set to LOW follo wed by the sub

must be HIGH.

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Bus Data Format 3-wire Bus Mode

Table 2-11 3-wire Bus Write Mode

MSB

SUB ADDRESS (WRITE)

LSB MSB DATA IN X...0 (X=7 or 15) LSB

00H...08H, 0DH, 0EH,0FH

S7 S6 S5 S4 S3 S2 S1 S0 DX ... D5 D4 D3 D2 D1 D0

Table 2-12 3-wire Bus Read Mode

MSB

SUB ADDRESS (READ)

80H, 81H

LSB MSB DATA OUT FROM

SUB ADDRESS

S7 S6 S5 S4 S3 S2 S1 S0 R7 R6 R5 R4 R3 R2 R1 R0

Sub Addresses Overview

LSB

ADC

RSSI [8 Bit]

CONTROL

CONFIG [16 Bit] STATUS [8 Bit] CLK_DIV [8 Bit] BLOCK_PD [16Bit]

ON_TIME [16 Bi t] OFF_TIME [16 Bit] COUNT_TH1 [16Bit] COUNT_TH2 [16Bit] RSSI_TH3 [8 Bit]

Figure 2-8 Sub Addresses Overview

I2C - SPI

INTERFACE

WAKEUP

FILTER

LPF [8 Bit]

XTAL

XTAL_TUNE [16Bit] FSK [16Bit] XTAL_CONFIG [8 Bit]

register_overview.wmf

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Subaddress Organization

Table 2-13 Sub Addresses of Data Registers Write

MSB LSB HEX Function Description Bit Length

0 0 000 0 000h CONFIG Gener al de f inition of status bits 16 0 0 000 0 101h FSK Values for FSK-shift 16

0 0

0 0 000 1 002h XTAL_TUNING Nominal frequency 16 0 0 000 1 103h LPF I/Q and data filter cut off fr equencies 8

0 0

0 0 001 0 004h ON_TIME ON time of wakeup counter 16 0 0 001 0 105h OFF_TIME OFF time of wakeup counter 16

0 0

0 0 001 1 006h COUNT_TH1 Lower threshold of window counter 16 0 0 001 1 107h COUNT_TH2 Higher threshold of window counter 16

0 0

0 0 010 0 008h RSSI_TH3 Threshold for RSSI signal 8 0 0 011 0 10Dh CLK_DIV Configuration and Ratio of clock divider 8

0 0

0 0 011 1 00Eh XTAL_CONFIG XTAL configuration 8 0 0 011 1 10Fh BLOCK_PD Building Blocks Power Down 16

Table 2-14 Sub Addresses of Data Registers Read

MSB LSB HEX Function Description Bit Length

0 0 000 0 0 80h STATUS Results of comparison: ADC & WINDOW 8

0 0 000 0 1 81h ADC ADC data out 8

Data Byte Specification

Table 2-15 Sub Address 00H: CONFIG

Bit Function Description Default

D15 D14 D13 D12 D11 D10

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Note D3: Function is only activ e in selfpollin g and timer mode. When D3 is set to LOW the RX path is not enabled if PwdDD of the RX building blocks.

SLICER 0= Lowpass, 1= Peak Detecto r 0 ALL_PD 0= normal operation, 1= all Power dow n 0

TESTMODE 0= normal operation, 1=Test mode 0

CONTROL 0= RX/TX and ASK/FSK external controlled, 1= Register controlled 0

ASK_NFSK 0= FSK, 1=ASK 0

RX_NTX 0= TX, 1=RX 1 CLK_EN 0= CLK off during power down, 1= always CLK on, ever in PD 0

RX_DATA_INV 0= no Data inversion, 1= Data invers i on 0

D_OUT 0= Data out if valid, 1= always Data out 1

ADC_MODE 0= one shot, 1= continuous 1

F_COUNT_MODE 0= one shot, 1= continuous 1

LNA_GAIN 0= low gain, 1= high gain 1

EN_RX 0= disable receiver, 1= enable receiver (in self polling and timer mode) * 1 MODE_2 0= slave mode, 1= timer mode 0 MODE_1 0= slave or timer mode, 1= self polling mode 0 PA_PWR 0= low TX Power, 1= high TX Power 1

pin is set to LOW. A delayed setting of D3 results in a delayed power ON

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