INFINEON TDA5251 F1 User Manual

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Preliminary Specification, Version 1.0, 2003-02-18

TDA5251 F1 ASK/FSK 315MHz Wireless

Transceiver

Wireless Components

Never stop thinking.

Edition 2003-02-18 Published by Infineon Technologies AG,

St.-Martin-Strasse 53, D-81541 München, German y

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Preliminary Specification, Version 1.0, 2003-02-18

TDA5251 F1 ASK/FSK 315MHz Wireless

Transceiver

Wireless Components

Never stop thinking.

Preliminary Specification Confidential Revision History: 2003-02-18 TDA5251 F1

Previous Version: Page Subjects (major changes since last revision)

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ASK/FSK 315MHz Wireless Transceiver TDA5251 F1

Product Info

General Description

The IC is a low power consumption single chip FSK/ASK Transceiver for half duplex low datarate communication in the 315MHz band. The IC offers a very high level of in tegr ation an d needs only a few external components. It contains a highly efficient power amplifier, a low noise amplifier (LNA) with AGC, a double balanced mixer, a complex direct conversion stage, I/ Q limiters with RSSI generation, an FSK demodulator, a fully integrated VCO and PLL synthesizer, a tuneable crystal oscillator, an onboard data filter, a data comparator (slicer), positive and negative peak detectors, a data rate detection circuit and a 2/3-wire bu s interface. Ad ditionally th ere is a power down feature to save battery power.

Version 1.0

Features

– Low supp ly c u rre nt (Is = 9mA typ. receive, I

= 13mA typ. transmit mode) – Supply voltage range 2.1 - 5.5V – Power down mode with very low supply

current consumption – FSK and ASK modulation and demodulation

capability – Fully integrated VCO and PLL

synthesizer and loop filter on-chip with on

chip crystal oscillator tuning

Application

– Low Bitrate Communication

Systems – Keyless Entry Systems – Remote Control Systems –Alarm Systems – Telemetry Systems

–I

C/3-wire µController Interface

– On-chip low pass channel select filter and

data filter with tuneable bandwidth

– Data slicer with self-adjusting threshold and

2 peak detectors

– FSK sensitivity <-109dBm, ASK sensitivity <

–109dBm – Transmit power up to +13dBm – Self-polling logic with ultra fast data rate

detection

– Electronic Metering – Home Automation Systems

Type Ordering Code Package

TDA5251 F1 P-TSSOP-38-1

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Table of Contents

page

1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4 Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.4.1 Power Amplifier (PA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.4.2 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.4.3 Downconverter 1st Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.4.4 Downconverter 2nd I/Q Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.4.5 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.4.6 I/Q Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.4.7 I/Q Limiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4.8 FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4.9 Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.4.10 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.4.11 Peak Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.4.12 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.4.13 Bandgap Reference Circuitry and Powerdown . . . . . . . . . . . . . 22

2.4.14 Timing and Data Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.4.15 Bus Interface and Register Definition . . . . . . . . . . . . . . . . . . . . 23

2.4.16 Wakeup Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.4.17 Data Valid Detection, Data Pin . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.4.18 Sequence Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.4.19 Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.4.20 RSSI and Supply Voltage Measurement . . . . . . . . . . . . . . . . . . 35

3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.1 LNA and PA Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.1.1 RX/TX Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.1.2 Switch in RX-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.1.3 Switch in TX-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.1.4 Power-Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.2 Crystal Osc illa tor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

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3.2.1 Synthesizer Frequency setting . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.2.2 Transmit/Receive ASK/FSK Frequency Assignment . . . . . . . . . 50

3.2.3 Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.2.4 Calculation of the external capacitors . . . . . . . . . . . . . . . . . . . . 54

3.2.5 FSK-switch modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.2.6 Finetuning and FSK modulation relevant registers . . . . . . . . . . 55

3.2.7 Chip and System Tolerances . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.3 IQ-Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.4 Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.5 Limiter and RSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.6 Data Slicer - Slicing Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.6.1 RC Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.6.2 Peak Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.6.3 Peak Detector - Analog output signal . . . . . . . . . . . . . . . . . . . . 64

3.6.4 Peak Detector – Power Down Mode . . . . . . . . . . . . . . . . . . . . . 64

3.7 Data Valid Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.7.1 Frequency Window for Data Rate Detection . . . . . . . . . . . . . . . 67

3.7.2 RSSI threshold voltage - RF input power . . . . . . . . . . . . . . . . . 68

3.8 Calculation of ON_TIME and OFF_TIME . . . . . . . . . . . . . . . . . . . 68

3.9 Example for Self Polling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.10 Sensitivity Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

3.10.1 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

3.10.2 BER performance depending on Supply Voltage . . . . . . . . . . . 72

3.11 Default Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

4 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.1.4 Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

4.2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4.3 Test Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

4.4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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Product Description

1 Product Description

1.1 Overview

The IC is a low power consumption single chip FSK/ASK Transceiver for the frequency band 315MHz. The IC combines a very high level of integration and minimum external part count. The device contains a low nois e amplifier (LNA), a d ouble balanced mixe r, a fully integrated VC O, a PLL synthesizer, a crystal oscillator with FSK modulator, a limiter with RSSI generator, an FSK demodulator, a dat a filter, a data comp ara tor (slicer), a posi tive an d a negative data peak detector, a highly efficient power amplifier and a complex digital timing and control unit with I microcontroller interface. Additionally there is a power down feature to save battery power.

The transmit section uses direct ASK modulation by switching the power amplifier, and crystal oscillator detuning for FSK modulation. The necessary detuning load capacitors are external. The capacitors for fine tuning are integrated. The receive section is using a novel single-conversion/ direct-conversion scheme that is combining the advantages of both receive topologies. The IF is contained on the chip, no RF channel filters are necessary as the channel filter is also on the chip.

The self-polling logi c can be used to le t the device operate autonomously as a master for a dec oding microcontroller.

C/3-wire

1.2 Features

– Low supply current (Is = 9 mA typ. receive, Is = 13mA typ. transmit mode, both at 3 V supply

voltage, 25°C) – Supply voltage range 2.1 V to 5.5 V – Operating temperatur e range -40°C to +85°C – Power down mode with very low supply current consumption – FSK and ASK modulation and demodulation capability without external circuitry changes, FM

demodulation capability – Fully integrated VCO and PLL synthesizer and loop filter on-chip with on-chip crystal oscillator

tuning, therefore no additional external components necessary – Differential receive signal path completely on-chip, therefore no external filters are necessary – On-chip low pass channel select and data filter with tuneable bandwith – Data slicer with self-adjusting threshold and 2 peak detectors – Self-polling logic with adjustable duty cycle and ultrafast data rate detection and timer mode

providing periodical interrupt – FSK and ASK sensitivity < -109 dBm – Adjustable LNA gain – Digital RSSI and Battery Voltage Readout – Provides Clock Out Pin for external microcontroller – Transmit power up to +13 dBm in 50W load at 5V supply voltage

–I

C/3-wire microcontroller interface, working at max. 400kbit/s

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1.3 Application

– Low Bitrate Communication Systems – Keyless Entry Systems – Remote Control Systems –Alarm Systems – Telemetry Systems – Electronic Metering – Home Automation Systems

1.4 Package Outlines

Product Description

P-TSSOP-38-1.EPS

Figure 1-1 P-TSSOP-38-1 package outlines

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2 Functional Description

2.1 Pin Configuration

VCC

BUSMODE

____

ASKFSK

RxTx

LNI

LNIx

GND1

GNDPA

VCC1

PDN

PDP

SLC

VDD

BUSDATA

BUSCLK

VSS

XOUT

Functional Description

CI1

CI1x

CQ1

CQ1x

CI2

CI2x

CQ2

CQ2x

GND

RSSI

DATA ___ PWDDD

CLKDIV ______ RESET ___ EN

XGND

XSWA

XIN

XSWF

5251F1_pin_conf.wmf

Figure 2-1 Pin Configuration

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2.2 Pin Definitions and Functions

Table 2-1 Pin Definition and Function

Pin No.

Symbol Equivalent I/O-Schematic Function

VCC Analog su pply (antiparallel diode s

1 11

BUSMODE Bus mode selection (I²C/ 3 wire bus

350

Functional Description

between VCC, VCC1, VDD)

mode selection)

LF Loop filter and VCO control volt age

200

ASKFSK ASK/FSK- mode switch input

350

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Functional Description

5 RXTX RX/TX-mode switch input/output

LNI RF input to differential Low Noise

350

Amplifier (LNA))

5k 5k

PWDN

LNIX see Pin 6 Complementary RF i np u t to

1.1V 7

180180

PWDN

differential LNA

GND1 Ground return for LNA and Power

Amplifier (PA) dirver stage

9 10

GNDPA see Pin 8 Ground return for PA output stage PA PA output stage

GndPA

VCC1 see Pin 1 Supply for LNA and PA

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Functional Description

12 PDN Output of the negative peak

detector

PWDN

350

50k

PDP Output of the positive peakdetector

50k

350

PWDN

SLC Slicer level for the data slicer

1.2uA

350

50k

50k 50k

50k

15 16

1.2uA

50k 50k

VDD see Pin 1 Digital supply BUSDATA Bus data in/output

15k

350

BUSCLK Bus clock input

350

VSS see Pin 8 Ground for digital section

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Functional Description

19 XOUT Crystal oscillator output, can also

be used as external reference frequency input.

Vcc

Vcc-860mV

150

XSWF FSK modulation switch

125fF ..... 4pF

250fF ..... 8pF

XIN see Pin 20

22 XSWA ASK modulation/FSK center

frequency switch

23 24

XGND

see Pin 22

Crystal oscillator ground return

EN 3-wire bus enable input

350

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Functional Description

25 RESET Reset of the entire system (to

default values), active low

110k

350

10p

350

CLKDIV Clock output

PWDDD Power Down input (active high),

data detect output (active low)

30k

350

DATA TX Data input, RX data ou tput (RX

powerdown: pin 28 @ GND)

350

RSSI RSSI outp ut

350

37k

16p

S&H

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Functional Description

30 GND see Pin 8 Analog ground 31

CQ2x Pin for external Capacitor

Q-channel, stage 2

Stage1:Vcc-630mV

Stage2: Vcc-560mV

32 33 34 35 36 37 38

CQ2 II Q-channel, stage 2 CI2x II I-channel, stage 2 CI2 II I-channel, stage 2 CQ1x II Q-channel, stage 1 CQ1 II Q-channel, stage 1 CI1x II I-channel, stage 1 CI1 II I-channel, stage 1

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2.3 Functional Block Diagram

ASKFSK

PDP

100k

ASK/FSK

100k

Det

+Peak

BUSMODE __

BUSCLK

BUSDATA

RXTX

Data (RX/TX)

CLKDIV

PWDDD

282627

LOGIC

17 24 2

SLC

WAKEUP

INTERFACE

CONTROLLER

SLICER

Data

FILTER

ASK

FSK

Functional Description

PDN

100k

Det

-Peak

RESET

VCC

6-bit

SAR-ADC

RSSI

(digital)

(analog)

(LNA/PA)

FSK DATA

Bandgap

Reference

CLK

VssGnd1

Gnd

XSWA XGND

22 23

XSWF

VDD

VCC

VCC1

XIN

QUADRI

CORRELATOR

CQ2x

CQ2

CI2x

CI2

CQ1x

35 36

CQ1 CI1x CI1

(digital)

(analog)

(LNA/PA)

LIMITER

Filter

Channel

MIXER

= 105MHz

LNI

= 315MHz

ANT

37 38

LIMITER

Filter

Channel

MIXER

FILTER

LNA MIXER

single ended to

differenti al conv.

Gain

high/low

LNIx

RSSI

0°

f = 105MHz

90°

ASK/FSK

TX/RX

ASK DATA

PHASE

:6/8

TX/RX

LOOP

ANT

CRYSTAL Osc, FSKMod, Finetuni ng

= 13,125MHz

XOUT

DET.

Charge P.

FILTER

VCO

= 315MHz

= 420MHz

GndPA

TDA5251F1_blockdiagram_aktuell.wmf

Figure 2-2 Main Block Diagram

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Functional Description

2.4 Functional Block Description

2.4.1 Power Amplifier (PA)

The power amplifier is operating in C-mode. It can be used in either high or low power mode. In high-power mode the transmit power is approximately +13dBm into 50 Ohm at 5V and +6dBm at

2.1V supply voltage. In low power mode the transmit power is approximately +12dBm at 5V and 34dBm at 2.1V supply voltage using the same matching network. The transmit power is controlled by the D0-bit of the CONFIG register (subaddress 00H) as shown in the following Table 2-2. The default output power mode is high power mode.

Table 2-2 Sub Address 00H: CONFIG

Bit

In case of ASK modulation the power amplifier is turned fully on and off by the transmit baseband data, i.e. 100% On-Off-Keying.

Function Description Default

PA_PWR 0= low TX Power, 1= high TX Power 1

2.4.2 Low Noise Amplifier (LNA)

The LNA is an on- chip cascode amplifi er wit h a voltage gain of 15 to 2 0dB and symmetrical i npu ts. It is possible to reduce the gain to 0 dB via logic.

Table 2-3 Sub Address 00H: CONFIG

Bit

Function Description Default

LNA_GAIN 0= low Gain, 1= high Gain 1

2.4.3 Downconverter 1st Mixer

The Double Balanced 1st Mixer converts the input frequency (RF) in the range of 31 5M Hz dow n to the intermediate frequency (IF) at approximately 105MHz. The local oscillator frequency is generated by the PLL synthesizer that is fully implemented on-chip as described in Section 2.4.5. This local oscillator operates at approximately 420MHz in receive mode providing the above mentioned IF frequency of 105MHz. The mixer is followed by a low pass filter with a corner frequency of approximately 175MHz in order to prevent RF and LO signals from appearing in the 105MHz IF signal.

2.4.4 Downconverter 2nd I/Q Mixers

The Low pass filter is followed by 2 mixers (inphase I and quadrature Q) that convert the 105MHz IF signal down to zero-IF. These two mi xer s are driv en by a sig nal that is generate d by di viding the local oscillator signal by 4, thus equalling the IF frequency.

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Functional Description

2.4.5 PLL Synthesizer

The Phase Locked Loop synthesizer consists of two VCOs (i.e. transmit and receive VCO), a divider by 4, an asynchronous divider chain with selectable overall division ratio, a phase detector with charge pump and a lo op filter and is fully implem en ted on-chip. The VCOs are includ ing spiral inductors and varactor diodes. The center frequency of the transmit VCO is 630MHz, the center frequency of the receive VCO is 840MHz.

Generally in receive mode the relationship between local oscillator frequency f frequency fRF and the IF freq uency fIF and thus the frequency that is applied to the I/Q Mixers is given in the following formula:

osc

f 4 f 4/3

IFRF

[2 – 1]

The VCO signal is applied to a divider by 2 and afterwards by 4 which is producing approximately 105MHz signals in quad rature. The overa ll divisio n ratio of the div ider chai n following the divider by 2 and 4 is 6 in transmit mode and 8 in receive mode as the nominal crystal oscillator frequency is

13.125MHz. The division ratio is controlled by the RxTx

pin (pin 5) and the D10 bit in the CONFIG

, the receive RF

osc

2.4.6 I/Q Filters

The I/Q IF to zero-IF mixers are followed by baseband 6th order low pass filters that are used for RF-channel filtering.

INTERNAL BUS

iq_filter.wmf

Figure 2-3 One I/Q Filter stage

The bandwidth of the filters is controlled by the values set in the filter-register. It can be adjusted between 50 and 350kHz in 50kHz steps via the bits D1 to D3 of the LPF register (subaddress 03H).

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Functional Description

2.4.7 I/Q Limiters

The I/Q Limiters are DC coupled multistage amplifiers with offset-compensating feedback circuit and an overall gain of approximately 80dB each in the frequency range of 100Hz up to 350kHz. Receive Signal Streng th Indicator (RSSI) gene rators are included in both limiters which produ ce DC voltages that are directly proportional to the input signal level in the respective channels. The resulting I- and Q-channel RSSI-signals are summed to the nominal RSSI signal.

2.4.8 FSK Demodulator

The output differential si gnals of the I/Q limiters are fed to a quadrature corr elator circuit that is used to demodulate frequency shift keyed (FSK) signals. The demodulator gain is 2.4mV/kHz, the maximum frequency deviation is ±300kHz as shown in Figure 2-4 below.

The demodulated signa l is ap plie d to the ASK/FSK mode switch whic h is co nne cted to the input of the data filte r. The swit ch ca n be c ontrol led by the ASKFSK CONFIG register.

The modulation index m must be larger than 2 for correct demodulation of the signal.

1,6

pin (pin 4) and via the D11 bit in the

1,5

1,4

1,3

1,2

1,1

U /V

0,9

0,8

0,7

0,6

0,5

-350 -300 -250 -200 -150 -100 -50 0 50 100 150 200 250 300 350

f /kHz

Figure 2-4 Quadricorrelator Demodulation Characteristic

Qaudricorrelator.wmf

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Functional Description

2.4.9 Data Filter

The 2-pole data filter has a Sallen-Key arc hitecture and is impl emented fully on-chip. T he bandwidth can be adjusted betw een ap proxim ately 5 kHz an d 102k Hz via the bits D4 to D7 of the LPF register as shown in Table 3-10.

ASK / FSK

OTA

INTER NAL BU S

data_filter.wmf

Figure 2-5 Data Filter architecture

2.4.10 Data Slicer

The data slic er is a fast comparat or with a bandwidth of 100kHz. The self-a djusting thres hold is generated by a RC-network (LPF) or by use of one or both peak detectors depending on the baseband coding scheme as de scr ibed in Section 3.6. This can be controlled by the D15 bit of the

CONFIG register as shown in the following table.

Table 2-4 Sub Address 00H: CONFIG

Bit

D15

Function Description Default

SLICER 0= Lowpass Filter, 1= Peak Detector 0

2.4.11 Peak Detectors

Two separate Peak Detectors are available. They are generating DC voltages in a fast-attack and slow-release manner that are proportional to the positive and negative peak voltages appearing in the data signal. These voltages may be used to generate a threshold voltage for non-Manchester encoded signals, for example. The time-constant of the fast-attack/slow-release action is determined by the RC network with external capacitor.

2.4.12 Crystal Oscillator

The reference oscillator is an NIC oscillator type (Negative Impedance Converter) with a crystal operating in serial resonan ce. The no minal opera ting frequenc y of 13.125MH z and the freque ncies for FSK modulation ca n be adjus ted via 3 external c apacitors . Via micr ocontrolle r and bus interface the chip-internal capacitors can be used for finetuning of the nominal and the FSK modulation frequencies. This finetuning of the crystal oscillator allows to eliminate frequency errors due to crystal or component tolerances.

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Functional Description

2.4.13 Bandgap Reference Circuitry and Powerdown

A Bandgap Reference Circ uit provides a temperature s tab le 1.2V reference voltage for the d evice. A power down mode is available to switch off all subcircuits that are controlled by the bidirectional Powerdown&DataDetect PwdDD

pin (pin 27) as shown in the following table. Power down mode can either be ac tivated b y pin 27 or b it D1 4 in Re gister 00 . In p ower do wn mode a lso p in 28 (D ATA) is affected (see Section 2.4.17).

Table 2-5 PwdDD Pin Operating States

PwdDD

VDD

Ground/VSS

Operating State

Powerdown Mode

Device On

2.4.14 Timing and Data Control Unit

The timing and data control unit contains a wake-up logic unit, an I2C/3-wire microcontroller interface, a “data valid” detection unit and a set of configuration registers as shown in the subsequent figure.

REGISTERS

RF - BLOCK

RSSI

RX DATA

FSK DATA

ASK DATA

BLOCK ENABLE

ASK / FSK

RX / TX

INTERNAL BUS

6 Bit ADC

BusData

BusCLK

I2C / 3Wire

INTERFACE

DATA VALID

DETECTOR

AMPLITUDE

threshold TH 3

FREQUENCY

window

TH1<T

<TH2

GATE

DATA

ENABLE

CONTROL

LOGIC

POWER ON

SEQUENCER

BusMode

13.125 MHz XTAL-Osz

WAKEUP

LOGIC

RC-Osz.

VALID

32kHz

CLKDiv

PwdDD

Data

AskFsk

RxTx

Reset

logic.wmf

Figure 2-6 Timing and Data Control Unit

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Functional Description

The I2C / 3-wire Bus Interface gives an external microcontroller full control over important system parameters at any time.

It is possible to set the device in three different modes: Slave Mode, Self Polling Mode and Timer Mode. This is done by a state machine which is implemented in the WAKEUP LOGIC unit. A detailed description is given in Section 2.4.16.

The DATA VALID DETECTOR contains a frequency window counter and an RSSI threshold comparator. The window counter uses the incoming data signal from the data slicer as the gating signal and the crystal oscillator frequency as the timebase to determine the actual datarate. The result is compared with the expected datarate. The threshold comparator compares the actual RSSI level with the expected RSSI level.

If both conditions are true the PwdDD

pin is set to LOW in self polling mode as you can see in Section 2 .4.16. This signal can be used as an interrupt for an external µP. Because the PwdDD pin is bidirectional and open drain driven by an internal pull-up resistor it is possible to apply an external LOW thus enabling the device.

2.4.15 Bus Interface and Register Definition

The TDA5251 supports the I2C bus protocol (2 wire) and a 3-wire bus protocol. Operation is selectable by the BusMode pin (pin 2) as shown in the following table. All bus pins (BusData, BusCLK, EN where the output is open drain driven by an internal 15kW pull up resistor.

, BusMode) have a Schmitt-triggered input stage. The BusData pin is bidirectional

Table 2-6 Bus Interface Format

Function

C Mode Low High= inactive,

3-wire Mode

BusMode EN BusCLK BusData

High

BusData

BusCLK

BusMode

Figure 2-7 Bus Interface

Low= active

I2C / 3-wire

INTERFACE

FRONTEND

1 1 1 0 0 0 0 0

CHIP ADDRESS

Clock input Data in/out

INTERNAL BUS

i2c_3w_bus.wmf

Note: The Interface is able to access the internal registers at any time, even in POWER DOWN mode. There is no internal clock necessary for Interface operation.

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Functional Description

I2C Bus Mode

In this mode the BusMode pin (pin 2) = LOW and the EN pin (pin 24) = LOW.

Data Transition: Data transition on the pin BusData c an only occur whe n BusCLK is LOW . BusData tran sitions while

BusCLK is HIGH will be interpreted as start or stop condition.

Start Condition (STA): A start condition is defined b y a HIGH to LOW transition of the BusData lin e while BusCLK is HIG H.

This start condition must precede any command and initiate a data transfer onto the bus.

Stop Condition (STO): A stop condition is defined by a LOW to HIGH transit ion of the BusData line whi le BusCLK is HIGH.

This condition termi nates the com munication be tween the devices an d forces t he bus inte rface into the initial state.

Acknowledge (ACK): Indicates a successfu l data tra nsf er. The transmitte r wil l releas e the bu s aft er send ing 8 bit o f data.

During the 9th clock cycle th e receive r will set th e SDA line to LOW lev el to indic ate it has rec eived the 8 bits of data correctly.

Data Transfer Write Mode: To start the communi cation, the b us master must initiate a st art condition (ST A), followed by the 8bit

chip address. The chip address for the TDA5251 is fixed as „1110000“ (MSB at first). The last bit (LSB=A0) of the chip address byte defines the type of operation to be performed:

A0=0, a write operation is selected and A0=1 a read operation is selected. After this comparison the TD A52 51 w ill ge ner ate an ACK and awaits the desired s ub ad dress byte

(00H...0FH) and data bytes. At the end of the data transition the master has to generate the stop condition (STO).

Data Transfer Read Mode: To start the communication in the read mode, the bus master must initiate a start condition (STA),

followed by the 8 bit chip address (write: A0=0), followed by the sub address to read (80H, 81H), followed by the chip address (read: A0=1). After that procedure the data of the selected register (80H, 81H) is read out. During this time the data line h as to be kept in HIGH state an d the chip sends out the data. At the end of data transition the master has to generate the stop condition (STO).

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Functional Description

Bus Data Format in I2C Mode

Table 2-7 Chip address Organization

MSB

1 1 1 0 0 0 0 0 Chip Address Write 1 1 1 0 0 0 0 1 Chip Address Read

Table 2-8 I2C Bus Write Mode 8 Bit

MSB CHIP ADDRESS

(WRITE)

STA 1 1 1 0 0 0 0 0 ACK S7 S6 S5 S4 S3 S2 S1 S0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK STO

LSB MSB SUB ADDRESS (WRITE)

00H...08H, 0DH, 0EH, 0FH

Table 2-9 I2C Bus Write Mode 16 Bit

MSB CHIP ADDRESS (WRITE) LSB MSB SUB ADDRESS (WRITE)

STA 1 1 1 0 0 0 0 0 ACK S7 S6 S5 S4 S3 S2 S1 S0 ACK D15 ... D8 ACK D7 D6 ... D0 ACK STO

00H...08H, 0DH, 0EH, 0FH

Table 2-10 I2C Bus Read Mode

MSB CHIP ADDRESS (WRITE) LSB MSB SUB ADDRESS (R EAD)

STA 1 1 1 0 0 0 0 0 ACK S7 S6 S5 S4 S3 S2 S1 S0 ACK STA 1 1 1 0 0 0 0 1 ACK

80H, 81H

Table 2-10 I2C Bus Read Mode (continued)

MSB DATA OUT FROM SUB ADDRESS LSB

R7 R6 R5 R4 R3 R2 R1 R0 ACK* STO

* mandatory HIGH

LSB Function

LSB MSB DATA IN LSB

LSB MSB CHIP ADDRESS (READ) LSB

3-wire Bus Mode

In this mode pin 2 (BusMode)= HIGH and Pin 16 (BusData) is in the data input/output pin. Pin 24

) is used to activate t he bus inte rface to all ow the tran sfer of dat a to / from t he device. When pin

(EN 24 (EN

Data Transition: Data transition on pin 16 (Bus Da ta) can only occur if the clock BusCLK is LOW. To perform a data

transfer the interface has to be enabled. Th is is done by settin g the EN is done via BusData, BusCLK and EN

Data Transfer Write Mode: To start the communication the EN

data bytes have to follow. The subaddress (00H...0FH) determines which of the data bytes are transmitted. At the end of data transition the EN

Data transfer Read Mode: To start the communication in the r ead mode, the EN

address to read (80H, 81H). Afterwards the device is ready to read out data. At the end of data transition EN

) is inactive (HIGH), data transfer is inhibited.

line to LOW. A serial transfer

. The bit stream needs no chip address.

line has to be set to LOW. The desired sub address byte and

must be HIGH.

line has to be set to LOW follo wed by the sub

must be HIGH.

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Functional Description

Bus Data Format 3-wire Bus Mode

Table 2-11 3-wire Bus Write Mode

MSB

SUB ADDRESS (WRITE)

LSB MSB DATA IN X...0 (X=7 or 15) LSB

00H...08H, 0DH, 0EH,0FH

S7 S6 S5 S4 S3 S2 S1 S0 DX ... D5 D4 D3 D2 D1 D0

Table 2-12 3-wire Bus Read Mode

MSB

SUB ADDRESS (READ)

80H, 81H

LSB MSB DATA OUT FROM

SUB ADDRESS

S7 S6 S5 S4 S3 S2 S1 S0 R7 R6 R5 R4 R3 R2 R1 R0

Sub Addresses Overview

LSB

ADC

RSSI [8 Bit]

CONTROL

CONFIG [16 Bit] STATUS [8 Bit] CLK_DIV [8 Bit] BLOCK_PD [16Bit]

ON_TIME [16 Bi t] OFF_TIME [16 Bit] COUNT_TH1 [16Bit] COUNT_TH2 [16Bit] RSSI_TH3 [8 Bit]

Figure 2-8 Sub Addresses Overview

I2C - SPI

INTERFACE

WAKEUP

FILTER

LPF [8 Bit]

XTAL

XTAL_TUNE [16Bit] FSK [16Bit] XTAL_CONFIG [8 Bit]

register_overview.wmf

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Functional Description

Subaddress Organization

Table 2-13 Sub Addresses of Data Registers Write

MSB LSB HEX Function Description Bit Length

0 0 000 0 000h CONFIG Gener al de f inition of status bits 16 0 0 000 0 101h FSK Values for FSK-shift 16

0 0

0 0 000 1 002h XTAL_TUNING Nominal frequency 16 0 0 000 1 103h LPF I/Q and data filter cut off fr equencies 8

0 0

0 0 001 0 004h ON_TIME ON time of wakeup counter 16 0 0 001 0 105h OFF_TIME OFF time of wakeup counter 16

0 0

0 0 001 1 006h COUNT_TH1 Lower threshold of window counter 16 0 0 001 1 107h COUNT_TH2 Higher threshold of window counter 16

0 0

0 0 010 0 008h RSSI_TH3 Threshold for RSSI signal 8 0 0 011 0 10Dh CLK_DIV Configuration and Ratio of clock divider 8

0 0

0 0 011 1 00Eh XTAL_CONFIG XTAL configuration 8 0 0 011 1 10Fh BLOCK_PD Building Blocks Power Down 16

Table 2-14 Sub Addresses of Data Registers Read

MSB LSB HEX Function Description Bit Length

0 0 000 0 0 80h STATUS Results of comparison: ADC & WINDOW 8

0 0 000 0 1 81h ADC ADC data out 8

Data Byte Specification

Table 2-15 Sub Address 00H: CONFIG

Bit Function Description Default

D15 D14 D13 D12 D11 D10

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Note D3: Function is only activ e in selfpollin g and timer mode. When D3 is set to LOW the RX path is not enabled if PwdDD of the RX building blocks.

SLICER 0= Lowpass, 1= Peak Detecto r 0 ALL_PD 0= normal operation, 1= all Power dow n 0

TESTMODE 0= normal operation, 1=Test mode 0

CONTROL 0= RX/TX and ASK/FSK external controlled, 1= Register controlled 0

ASK_NFSK 0= FSK, 1=ASK 0

RX_NTX 0= TX, 1=RX 1 CLK_EN 0= CLK off during power down, 1= always CLK on, ever in PD 0

RX_DATA_INV 0= no Data inversion, 1= Data invers i on 0

D_OUT 0= Data out if valid, 1= always Data out 1

ADC_MODE 0= one shot, 1= continuous 1

F_COUNT_MODE 0= one shot, 1= continuous 1

LNA_GAIN 0= low gain, 1= high gain 1

EN_RX 0= disable receiver, 1= enable receiver (in self polling and timer mode) * 1 MODE_2 0= slave mode, 1= timer mode 0 MODE_1 0= slave or timer mode, 1= self polling mode 0 PA_PWR 0= low TX Power, 1= high TX Power 1

pin is set to LOW. A delayed setting of D3 results in a delayed power ON

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Table 2-16 Sub Address 01H: FSK

Bit Function Value Description Default

D15 not used 0 D14 not used 0 D13 FSK+5 8pF Setting for D12 FSK+4 4pF 0 D11 FSK+3 2pF 1 D10 FSK+2 1pF 0

D9 FSK+1 500fF 1 D8 FSK+0 250fF 0 D7 not used 0

D6 not used 0 D5 FSK-5 4pF Setting for D4 FSK-4 2pF 0 D3 FSK-3 1pF 1 D2 FSK-2 500fF 1 D1 FSK-1 250fF 0 D0 FSK-0 125fF 0

Table 2-18 Sub Address 03H: LPF

Bit Function Description Default

D7 D6 D5 D4 D3 D2 D1 D0

Datafilter_3 Datafilter_2 0 Datafilter_1 0 Datafilter_0 1 IQ_Filter_ 2 3dB cutoff IQ_Filter_ 1 0 IQ_Filter_ 0 0

not used 0

positive

frequency

shift: +FSK or

ASK-RX

negative frequency shift: -FSK

3dB cutoff

frequency of

data filter

frequency of

IQ-filter

Functional Description

Table 2-17 Sub Address 02H: XTAL_TUNING

Bit Function Value Description Default

D15 not used 0

D14 not used 0 D13 not used 0 D12 not used 0 D11 not used 0 D10 not used 0

D9 not used 0 D8 not used 0 D7 not used 0

D6 not used 0 D5 Nominal_Frequ_5 8pF Setting for D4 Nominal_Frequ_4 4pF 1 D3 Nominal_Frequ_3 2pF 0 D2 Nominal_Frequ_2 1pF 0 D1 Nominal_Frequ_1 500fF 1 D0 Nominal_Frequ_0 250fF 0

Table 2-19 Sub Addresses 04H / 05H: ON/OFF_TIME

Bit

D15 D14 D13 D12 D11 D10

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Function Default ON_TIME Default

ON_15 / OFF_15 1 1 ON_14 / OFF_14 1 1 ON_13 / OFF_13 1 1 ON_12 / OFF_12 1 1 ON_11 / OFF_11 1 0 ON_10 / OFF_10 1 0

ON_9 / OFF_9 1 1 ON_8 / OFF_8 0 1 ON_7 / OFF_7 1 1 ON_6 / OFF_6 1 0 ON_5 / OFF_5 0 0 ON_4 / OFF_4 0 0 ON_3 / OFF_3 0 0 ON_2 / OFF_2 0 0 ON_1 / OFF_1 0 0 ON_0 / OFF_0 0 0

nominal

frequency

ASK-TX FSK-RX

OFF_TIME

Table 2-20 Sub Address 06H: COUNT_TH1

Bit

D15 D14 D13 D12 D11 D10

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Function Default

not used 0 not used 0 not used 0 not used 0

TH1_11 0 TH1_10 0

TH1_9 0 TH1_8 0 TH1_7 0 TH1_6 0 TH1_5 0 TH1_4 0 TH1_3 0 TH1_2 0 TH1_1 0 TH1_0 0

Table 2-21 Sub Address 07H: COUNT_TH2

Bit

D15 not used 0

D14

D13

D12

D11

D10

Function Default

not used 0

TH2_11 0

TH2_10 0

TH2_9 0

TH2_8 0

TH2_7 0

TH2_6 0

TH2_5 0

TH2_4 0

TH2_3 0

TH2_2 0

TH2_1 0

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able 2-22 Sub Address 08H: RSSI_TH3

Bit Function Description Default

D7 D6 D5 D4 D3 D2 D1 D0

not used 1 SELECT 0= VCC, 1= RSSI 1

TH3_5 1 TH3_4 1 TH3_3 1 TH3_2 1 TH3_1 1 TH3_0 1

Table 2-24 Sub Address 0EH: XTAL_CONFIG

Bit Function Description Default

D7 D6 D5 D4 D3 D2 FSK-Ramp 0 D1 FSK-Ramp 1 D0 Bipolar_FET

Functional Description

Table 2-23 Sub Address 0DH: CLK_DIV

Bit Function Default

D7 D6 D5 D4 D3 D2 D1 D0

not used 0 not used 0 not used 0 not used 0 not used 0

only in bipolar mode 0

0= FET, 1=Bipolar 1

not used 0

not used 0 DIVMODE_1 0 DIVMODE_0 0

CLKDIV_3 1 CLKDIV_2 0 CLKDIV_1 0 CLKDIV_0 0

Table 2-25 Sub Address 0FH: BLOCK_PD

Bit Function Description Default

D15 D14 D13 D12 D11 D10

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

able 2-26 Sub Address 80H: STATUS

Bit Function Description

COMP_LOW 1 if data rate < TH1

D7 D6 COMP_IN 1 if TH1 < data rate < TH2 D5 COMP_HIGH 1 if TH2 < data rate

COMP_0,5*LOW 1 if data rate < 0,5*TH1

D4 D3 COMP_0,5*IN 1 if 0,5*TH1 < data rate < 0,5*TH2 D2

COMP_0,5*HIGH 1 if 0,5*TH2 < data rate D1 RSSI=TH3 1 if RSSI value is equal TH3 D0

RSSI>TH3 1 if RSSI value is greater than TH3

REF_PD 1= power down Band Gap Reference 1

RC_PD 1= power down RC Oscillator 1

WINDOW_PD 1= power down Window Counter 1

ADC_PD 1= power down ADC 1 PEAK_DET_PD 1= power down Peak Detectors 1 DATA_SLIC_PD 1= power down Data Slicer 1

DATA_FIL_PD 1= power down Data Filter 1

QUAD_PD 1= power down Quadri Correlator 1

LIM_PD 1= power down Limiter 1

I/Q_FIL_PD 1= power down I/Q Filters 1

MIX2_PD 1= power down I/Q Mixer 1 MIX1_PD 1= power down 1st Mixer 1

LNA_PD 1= power down LNA 1

PA_PD 1= power down Power Amplifier 1

PLL_PD 1= power down PLL 1

XTAL_PD 1= power down XTAL Oscillator 1

Table 2-27 Sub Address 81H: ADC

Bit Function Description

PD_ADC ADC power down feedback Bit

SELECT SELECT feedback Bit

D6 D5 D4 D3 D2 D1 D0

RSSI_5 RSSI value Bit5 RSSI_4 RSSI value Bit4 RSSI_3 RSSI value Bit3 RSSI_2 RSSI value Bit2 RSSI_1 RSSI value Bit1 RSSI_0 RSSI value Bit0

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2.4.16 Wakeup Logic

SLAVE MODE

(default)

MODE_1 = 0 MODE_2 = 0

SELF POLLING

MODE

MODE_1 = 1 MODE_2 = X

Figure 2-9 Wakeup Logic States

Table 2-28 MODE settings: CONFIG register

MODE_1

0 0 1

MODE_2 Mode

0 SLAVE MODE 1 TIMER MODE X SELF POLLING MODE

TIMER MODE

MODE_1 = 0 MODE_2 = 1

Functional Description

3_modes.wmf

SLAVE MODE: The receive and transmit operation is fully controlled by an external control device via the respective RxTx

After RESET or 1

, AskFsk, PwdDD, and Data pins. The wakeup logic is inactive in this cas e.

Power-up the chip is in SLAV E MODE. By settin g MODE_1 and MO DE_2 in the

CONFIG register the mode may be changed.

SELF POLLING MODE: The chip turns itself on periodically to receive using a built-in 32kHz RC oscillator. The timing of this i s determined by the ON_TIME and OFF_TIME registers, the duty cycle can be set between 0 and 100% in 31.2 5µs increments. T he data detect log ic is enabled a nd a 15µs LOW impulse is provided at PwdDD

Action

PwdDD pin in

SELF POLLING MODE

pin (Pin 27), if the received data is valid.

ON_TIME ON_TIME

RX ON: valid Data

min. 2.6ms

15µs

OFF_TIME

RX ON: invalid Data

timing_selfpllmode.wmf

Figure 2-10 Timing for Self Polling Mode (ADC & Data Detect in one shot mode)

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Functional Description

Note: The time delay between start of ON time and the 15µs LOW impulse is 2.6ms + 3 period of

data rate.

If ADC & Data Detect Logic are in continuous mode the 15µs LOW impulse is applied at PwdDD after each data valid decision. In self polling mode if D9=0 (Register 00h) and when PwdDD

pin level is HIGH the CLK output is

on during ON time and off during OFF time. If D9=1, the CLK output is always on.

TIMER MODE: Only the internal Timer (determined by the ON_TIME and OFF_TIME registers) is active to support an external logic with periodical Interrupts. After ON_TIME + OFF_TIME a 15µs LOW impulse is appli ed at the PwdDD

ON_TIME ON_TIME

Action Register 04H

PwdDD pin in

TIMER MODE

15µs 15µs

pin (Pin 27).

OFF_TIME

timing_timermode.wmf

Figure 2-11 Timing for Timer Mode

2.4.17 Data Valid Detection, Data Pin

Data signals generate a typical spectrum and this can be used to determine if valid data is on air.

Amplitude

RSSI

Figure 2-12 Frequency and RSSI Window

The “data valid” criterio n is generated from the result of RSSI-TH3 comparison and t TH1 and TH2 result as s hown below . In c ase of M ancheste r coding the 0, 5*TH1 and 0,5*TH2 gives improved performance.

The use of permanent data valid recognition makes it absolutely necessary to set the RSSI-ADC and the Window counter into continuous mode (Register 00H, Bit D5 = D6 = 1).

Frequency & RSSI Window

DATA on air

no DATA on air

Frequency

data_rate_detect.wmf

between

GATE

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0,5*TH1 T

TH1 T

0,5*TH2

GATE

RSSI TH3

TH2

DATA VALID

Functional Description

data_valid.wmf

Figure 2-13 Data Valid Circuit

D_OUT and RX_DATA_INV from the CONFIG register determine the output of data at Pin 28.

RxTx

int and TX_ON are internally generated signals.

In RX and power down mode Data pin (Pin 28) is tied to GND.

RxTxint

RX_DATA_INV

RX DATA

DATA VALID

D_OUT

Data

TX DATA

TX ON

data_switch.wmf

Figure 2-14 Data Input/Output Circuit

2.4.18 Sequence Timer

The sequence time r has to control all th e e nable signals of the a nalog components insi de the chip. The time base is the 32 kHz RC oscillator.

After the first POWER ON or RE SET a 73 0kHz cl ock i s availa ble at the cl ock output pin . This clo ck output can be used by an external mP to se t the system into the desired state an d outputs valid d ata after 500 µs (see Figure 2-15 and Figure 2-16, t

CLKSU

There are two possibilities to start the device after a reset or first power on:

- PWDDD

until the device is activated (PWDDD t

SYSSU

pin is LOW: Normal operation timing is performed after t pin is HIGH (device in power down mode): A clock is offered at the clock output pin

pin is pulled to LOW). After the first activation the time

is required until normal operation timing is performed (see Figure 2-16 ).

This could be used to extend the clock generation without device programming or activation.

)

SYSSU

(see Figure 2-15).

Note: It is required to activate the device for the duration of t

after first power on or a reset.

SYSSU

Only if this is done the normal operation timing is performed.

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Functional Description

With default settings the clock generating units are disabled during PD, therefore no clock is available at the clock output pin. It is possible to offer a clock signal at the clock output pin every time (also during PD) if the CLK_EN Bit in the CONFIG register is set to HIGH.

RESET

POWER O N

or 1

PWDDD = low

STATUS

XTAL EN

TX activ or RX activ

CLOCK FOR EXTERNAL µP

TX activ

RX activ TX acti v RX activ

DC OFFSET COMPENSATION

PEAK DETECTOR EN

DATADETECTION EN

POWER AMP EN

CLKSU

0.5ms

SYSSU

8ms

1.1ms

TXSU

if RX

if TX

RXSU

2.2ms

DDSU

2.6ms

CLKSU

0.5ms

TXSU

1.1ms

CLKSU

0.5ms

TXSU

1.1ms

RXSU

2.2ms

DDSU

2.6ms

Sequenzer_Timing_pupstart.wmf

RXSU

2.2ms

DDSU

2.6ms

Figure 2-15 1

start or reset in active mode

Note: The time values are typical values

RESET

POWER ON

or 1

PWDDD = high

STATU S

XTAL EN

DC OFFSET COMPENSATION

PEAK DETECTOR EN

DATADETECTION EN

POWE R AMP EN

CLKSU

0.5ms

CLOCK FOR EXTERNAL µP

Figure 2-16 1st start or reset in PD mode

PWDDD = low

TX activ or RX activ

SYSSU

8ms

TXSU

1.1ms

if RX

if TX

PD TX activ RX activ

CLKSU

0.5ms

RXSU

2.2ms

DDSU

2.6ms

TXSU

1.1ms

RXSU

2.2ms

DDSU

2.6ms

Sequenzer_Timing_pdstart.wmf

* State is either „I“ or „O“ depending on time of setting into powerdown

Note: The time values are typical values

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Version 1.0

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This means that the device needs t When activating TX it requires t

TXSU

setup time to start the data detection after RX is acti vated.

DDSU

setup time to enable the power amplifier.

Functional Description

For timing information refer to Table 4-3.

For test purposes a TE STMODE is provided by the Sequencer as w ell. In this mode the BL OCK_PD register be set to various va lues. This will overrid e the Sequencer timi ng. Depending on t he settings in Config Register 00H the corres ponding bui lding bl ocks are ena bled, as sh own in the su bsequent figure.

CLK_EN

RC- OSC.

XTAL FREQU.

SELECT

ENABLE / DISABLE

BUILDING BLOCKS

sequencer_raw.wmf

RESET

32 kHz

RX ON

TX ON

ASK/FSK

INTERNAL BUS

TIMING

BLOCK_PD

DECODE

SWITCH

ALL_PD

TESTMOD E

Figure 2-17 Sequencer‘s capability

2.4.19 Clock Divider

It supports an external logic with a programmable Clock at pin 26 (CLKDIV).

INTERNAL BUS

13 MHz

4 BIT

COUNTER

WINDOW COUNT COMPLETE

DIVIDE

32 kHz

BY 2

Figure 2-18 Clock Divider

The Output Selection and Divider Ratio can be set in the CLK_DIV register.

DIVMODE_0

DIVMODE_1

CLKDiv

SWITCH

clk_div.wmf

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Table 2-29 CLK_DIV Output Selecti on

D5 D4

0 0 1 1

Note: Data are valid 500 µs after the crystal oscillator is enabled (see Figure 2-15 and Figure 2- 16, t

CLKSU

Table 2-30 CLK_DIV Setting

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

D2 D1 D0 Total Divider Ratio Output Frequenc y [MHz]

0 0 0 2 6.6 0 0 1 4 3.3 0 1 0 6 2.2 0 1 1 8 1.6 1 0 0 10 1.3 1 0 1 12 1.1 1 1 0 14 0.94 1 1 1 16 0.82 0 0 0 18 0.730 (default) 0 0 1 20 0.66 0 1 0 22 0.6 0 1 1 24 0.,55 1 0 0 26 0.5 1 0 1 28 0.47 1 1 0 30 0.44 1 1 1 32 0.41

0 Output from Divider (default) 1 13.125MHz 0 32kHz 1 Window Count Complete

Output

Functional Description

Note: As long as default settings are used, there is no clock available at the clock output during

Power Down. It is possible to enable the clock during Power Down by setting CLK_EN (Bit D9) in the Config Register (00H) to HIGH.

2.4.20 RSSI and Supply Voltage Measuremen t

The input of the 6Bit-ADC can be switched betw een two different sources: the RSS I voltage (default setting) or a resistor network dividing the V cc voltage by 5.

Table 2-31 Source for 6Bit-ADC Selection (Register 08H)

SELECT

0 1

Preliminary Specification 35 2003-02-18

Input for 6Bit-ADC

Vcc / 5

RSSI (default)

TDA5251 F1

Version 1.0

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To prevent wrong inte rpretation of the ADC inform ation (read from Registe r 81H: ADC) y ou can use the ADC- Power Down feedback Bit (D7) and the SELECT feedback Bit (D6) which correspond to the actual measurement.

Note: As shown in Section 2.4.18 there is a setup time of 2.6ms after RX activating. Thus the measurement of RSSI voltage does only make sense after this setup time.

Functional Description

Preliminary Specification 36 2003-02-18

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3Application

3.1 LNA and PA Matching

3.1.1 RX/TX Switch

Application

RX/TX_Switch.wmf

Figure 3-1 RX/TX Switch

The RX/TX-switch combines the PA-output and the LNA-input into a single 50 Ohm SMAconnector. Two pin-dio des are u sed as sw itching elemen ts. If no cur ren t flows thr ough a pi n diode, it works as a high impeda nce for R F with very lo w capa citance . If the p in-di ode is forward biased , it provides a low impedance path for RF. (some W)

3.1.2 Switch in RX-Mode

The RX/TX-switch is set to the receive mode by either applying a high level or an open to the RX/ TX-jumper on the evalboard or by leaving it open. Then both pin-diodes are not biased and therefore have a high impedance.

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Figure 3-2 RX-Mode

The RF-signal is able to run f rom the RF-inp ut-SMA-conn ector t o the LN A-input-pin LNI via C1, C2, C7, L3 and C9. R1 does not affect the ma tching cir cuit due to its high res istance. The oth er input of the differ entia l LNA LN IX ca n alwa ys be A C-gro unded using a lar ge capa cito r with out any loss of performance. In this case the differential LNA can be used as a single ended LNA, which is easier to match. The S11 of the LNA at pin LNI on the evalboard is 0.97 / -17° (equals a resistor of

3.3kOhm in parallel to a capac itor of 1.5pF) for both high an d low -gain-m ode of the LNA. (pin LN IX AC-grounded) This im pedanc e has to be ma tched to 50 Ohm w ith the parts C9, L 3, C7 and C2. C1 is a DC-decoupling-capacitor. On the evalboard the most important matching components are (shunt) L3 and (series)C7, C2. The capacitors is mainly a DC-decoupling-capacitor and may be used for some fine tuning of the matching circuit. A good CAE tool (featuring smith-chart) may be used for the calculatio n of the v alues o f the com ponen ts. Howeve r, the fin al valu es of the matchi ng components always have to be found on the board because of the parasitics of the board, which highly influence the matching circuit at RF.

Application

RX_Mode.wmf

Preliminary Specification 38 2003-02-18

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Version 1.0

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Measured Magnitude of S11 of evalboard:

Application

S11_measured_315.pcx.

Figure 3-3 S11 measured

Above you can see the measured S11 of the evalboard. The –3dB-points are at 288MHz and 344MHz. So the 3dB-bandwidth is:

[3 – 1]

fB 56288344 =-=-=

The loaded Q of the resonant circuit is:

center

315

MHz

===

MHzMHzMHz

[3 – 2]

6,5

The unloaded Q of the resonant circuit is equal to the Q of the inductor due to its losses.

Q 315@27»=

INDUCTOR

MHz

[3 – 3]

An approximation of the losses of the input matching network can be made with the formula:

LOSS 2

ê ê

--=

é ê ê

6,5

1log*201log*20 =

--=

[3 – 4]

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Application

The noise figure of the LNA-input-matching network is equal to its losses. The input matching network is always a compromis e of sensitivit y and selectivi ty. The load ed Q should not get too high because of 2 reasons:

more losses in the matching network and hence less sensitivity tolerances of components af fect matching too muc h. This will cause probl ems in a tuning-free ma ss

production of the app lica tion. A good CAE-tool w ill help to see the effec ts of component tolerances on the input matching more accurate by tweaking each value.

A very high selectivity can be rea ched by usi ng SAW-fi lters at the expens e of higher c ost and low er sensitivity which will be reduced by the losses of the SAW-Filter of approx. 4dB.

Image-suppression:

Due to the quite high 1

-IF of the frontend, the image frequency is quite far away. The image

frequency of the receiver is at:

f 525105*2315*2 =+=+=

IMAGE

SIGNAL

MHzMHz

[3 – 5]

The image suppression on the evalboard is about 12dB.

LO-leakage:

The LO of the 1st Mixer is at:

f 420

RECEIVE

* ===

*315

MHzMHz

[3 – 6]

The LO-leakage of the evalboard on the RF-input is about –102dBm.

3.1.3 Switch in TX-Mode

The evalboard can be set into the TX-Mode by grounding the RX/TX-jumper on the evalboard or programming the TDA5251 to operate in the TX-Mode. If the IC is programmed to operate in the TX-Mode, the RX/TX-p in will act as an open drain output at a log ical LOW. Then a DC-current can flow from VCC to GND via L1, L2, D1, R1 and D2.

DIODEPINFORWARD

[3 – 7]

DIODEPIN

Now both pin-diodes are biased with a current of approx. 0.3mA@3V and have a very low impedance for RF.

Preliminary Specification 40 2003-02-18

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Figure 3-4 TX_Mode

Application

TX_Mode.wmf

R1 does not influence the matching because of its very high resistance. Due to the large capacitance of C1, C6 and C5 the circuit can be further simplified for RF:

TX_Mode_simplified.wmf

Figure 3-5 TX_Mode_simplified

The LNA-matching is RF-grounded now, so no power is lost in the LNA-input. The PA-matching consists of C2, C3 L2, C4 and L1.

When designing the matching of the PA, C2 must not be changed anymore because its value is already fixed by the LNA-input-ma tch ing.

Preliminary Specification 41 2003-02-18

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Application

3.1.4 Power-Amplifier

The power amplifier operates in a high efficient class C mode. This mode is characterized by a pulsed operation of the power amplifier transistor at a current flow angle of q<<p. A frequency selective network at th e amplifier outp ut passes the funda mental frequen cy component of the pulse spectrum of the collector current to the load. The load and its resonance transformation to the collector of the power amplifier can be generalized by the equ ivalent circui t of Figur e 3 -6. The tank circuit L//C//RL in parallel to the output impedance of the transistor should be in resonance at the operating frequency of the tran smitter.

Equivalent_power_wmf.

Figure 3-6 Equivalent power amplifier tank circuit

The optimum load at the collector of the power amplifier for “critical” operation under idealized conditions at resonance is:

R =

22P

[3 – 8]

A typical value of RLC for an RF output power of Po= 13mW is:

013.02

= 350

[3 – 9]

Critical” operation i s characterized by the RF peak voltage swing at th e collector of the PA tran sistor to just reach the supply voltage V

. The high efficiency under “critical” operating conditions can be

explained by the low power loss at the transistor. During the conducting phase of the transistor there is no or only a very small collector voltage present, thus minimizing the power loss of the transistor (i current flow angles of q<<p parasitics will reduce the “critical” R

. In practice the RF-saturation voltage of the PA transistor and other

). This is particularly true for low

C*uCE

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Application

The output po wer Po will be reduced when operating in an “overcritical” mode at a RL > RLC. As shown in Figure 3-7, however, power efficiency E (and bandwidth) will increase by some degree when operating at higher RL. The collector efficiency E is defined as

E0=

The diagram of Figure 3-7 has b een mea sur ed directly at the PA-outpu t at V

[3 – 10]

=3V. A power loss in

the matching circuit of about 3dB will decrease the output power. As shown in the diagram, 250 Ohm is the optimum impedance for operation at 3V. For an approximation of R

OPT

and P

OUT

other supply voltages those 2 formulas can be used:

[3 – 11]

OPT

VR ~

and

RP ~

OPTOUT

[3 – 12]

Power_E_vs_RL_315.wmf

Figure 3-7 Output power Po (mW) and collector efficiency E vs. load resistor RL.

The DC collector current Ic of the power amplifier and the RF output power Po vary with the load resistor RL. This is typical for overcritical operation of class C amplifiers. The collector current will show a characteristic dip at the resonance frequency for this type of “overcritical” operation. The depth of this dip will increase with higher values of RL.

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As Figur e 3-8 sh ows, detuning beyond the band width of the match ing circui t results in a significa nt increase of collector c urrent of the power ampli fier and in some loss of out put pow er. This diagram shows the data for the circuit of the test board at the frequency of 315MHz. The effective load resistor of this circuit is RL= 250Ohm, which is the optimum im pedance for operation at 3V. Thi s will lead to a dip of the collector current of approx. 20%.

Application

pout_vs_frequ_315.wmf

Figure 3-8 Power output and collector current vs. frequency

C4, L2 and C3||C2 are the main matching components which are used to transform the 50 Ohm load at the SMA-RF-connector to a higher impedance at the PA-output (250Ohm@3V). L1 can be used for finetuning of the resonance frequency but should not be too low in order to keep its loss low.

The transformed impedance of 250Ohm+j0 at the PA-output-pin can be verified with a network analyzer using this measurement procedure:

1. Calibrate your network analyzer.

2. Connect a short, low-l oss 50 Ohm cable to you r networ k analyzer with an open end on one si de. Semirigid cable works best.

3. Use the „Port Extension“ feature of your network analyzer to shift the reference plane of your network analyzer to the open end of the cable.

4. Connect the center-c onducto r of the cable to the sol der pad of the pin „PA“ of the IC . The shield has to be grounded. Very short connections must be used. Do not remove the IC or any part of the matching-components!

5. Screw a 50Ohm-dummy-load on the RF-I/O-SMA-connector

6. The TDA5251 has to be in ASK-TX-Mode, Data-Input=LOW.

7. Be sure that your network analyzer is AC-coupled and turn on the power supply of the IC.

8. Measure the S-parameter

Preliminary Specification 44 2003-02-18

TDA5251 F1

Version 1.0

Confidential

Application

Sparam_measured_315.pcx

Figure 3-9 Sparam_measured_100M

Above you can see the measurement of the evalboard with a span of 100MHz. The evalboard has been optimized for 3V. The load is about 250+j0 at 315MHz.

A tuning-free realization requires a careful design of the components within the matching network. A simple linear CAE-tool will help to see the influence of tolerances of matching components.

Suppression of spurious harmonics may require some additional filtering within the antenna matching circuit. Both can be seen in Figure 3-10 and Figure 3-11 The total spectrum of the evalboard can be summarized as:

Carrier fc +9dBm fc-13.125MHz -74dBm fc+13.125MHz -74dBm

harmonic -38dBm

harmonic -40dBm

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Figure 3-10 Transmit Spectrum 3GHz

Application

spectrum_tx_3GMhz.pcx

spektrum_tx_3MHz.pcx

Figure 3-11 Transmit Spectrum 300MHz

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Application

3.2 Crystal Oscillator

The equivalent schematic of the crystal with its parameters specified by the crystal manufacturer can be taken from the subsequent figure.

Here also the load capacitan ce of the crystal CL, which the crystal wants to see in order to os cillate at the desired frequency, can be seen.

Crystal.wmf

Figure 3-12 Crystal

-R

: motional inductance of the crystal

: motional capa citance of the crystal

: shunt capacitance of the crystal

Therefore the Resonant Frequency fs of the crystal is defined as:

[3 – 13]

The Series Load Resonant Frequency fS‘ of the crystal is defined as:

[3 – 14]

regarding Figure 3-12

fs’ is the nominal frequency of the crystal with a specified load when tested by the crystal manufacturer.

Pulling Sensitivity of the crystal is defined as the magnitude of the relative change in frequency relating to the variation of the load capacitor.

Preliminary Specification 47 2003-02-18

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()

[3 – 15]

Application

Choosing CL as large as possible res ults in a small pullin g sensitivity. O n the other hand a small C keeps the influence o f the se rial inductance and the tolerances associated to it sm all ( see formula

[3-17]).

Start-up Time

Start

ext

[3 – 16]

where: -R: is the negative impedance of the oscillator

see Figure 3-13

: is the sum of all external resistances (e.g. R1 or any

ext

other resistance that may be present in the circuit, see Figure 3-12

The proportionality of L1 and C1 of the crystal is defined by formula [3-13]. For a crystal with a small C1 the start -up time will also be slower. Typically the lower the value of the crystal frequency, the lower the C1.

A short conclusion regarding crystal and crystal oscillator dependencies is shown in the following table:

Table 3-1 Crystal and crystal oscilator dependency

Result

Independent variable

C1 > C0 >

frequency of quartz >

OSC

CL >

Relative Tolerance Maximum Deviation t

>> >> <

<<-

>>> > <<

>> > -

><-

Start-up

The crystal oscillator in the TDA5251 is a NIC (negative impedance converter) oscillator type. The input impedance of this o scillator is a negative impedanc e in series to an induc tance. The refore the load capacitance of the crystal C capacitance C

as shown in formula [3-17].

(specified by the crystal supplier) is transformed to the

Preliminary Specification 48 2003-02-18

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-R

Figure 3-13 Crystal Oscillator

=«

OSC

: crystal load capacitance for nominal frequency

w: angular frequency L

: inductivity of the crystal oscillator - typ: 2.2mH with pad of board

OSC

TDA 5250

ww +

OSC

f, C

Application

QOSZ_NIC.wmf

[3 – 17]

2.1µH without pad

With the aid of this formula it becomes obvious that the higher the serial capacitance CV is, the higher is the influence of L

OSC

The tolerance of the inter nal oscillat or inductivity i s much higher, so the inductivity is th e dominating value for the tolerance.

FSK modulation and tuning are achieved by a variation of C

In case of small frequency deviations (up to +/- 1000 ppm), the desired load capacitances for FSK modulation are frequency depending and can be calculated with the formula below.

CLC

L ±

------------------------------------------------------------------------------------------= 1

----------

××

Nf×

æö

---------- 1

×±

ç÷

Nf×

èø

---------------------------------+

ç÷ èø

2C0CL+()×

---------------------------------+

[3 – 18]

: crystal load capacitance for nominal frequency : shunt capacitance of the crystal : motional capacitance of the crystal

2C0CL+()×

æö

f: crystal oscillator frequency N: division ratio of the PLL Df: peak frequency deviation

Preliminary Specification 49 2003-02-18

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Application

With CL+ and CL- the necessary Cv+ for FSK HIGH and Cv- for FSK LOW can be calculated. Alternatively, an extern al AC coupled (10nF in se ries to 1k

W) signal can be app lied at pin 19 (Xout).

The drive level should be approximately 100mVpp.

3.2.1 Synthesizer Frequency setting

Generating ASK and FSK modulation 3 setable frequencies are necessary.

3.2.1.1 Possible cry s tal oscillator frequencies

The resulting possible crystal oscillator frequencies are shown in the following Figure 3-14

RX: FSK ASK TX: FSK- ASK FSK+

Deviation Deviation

Nominal

Frequency

free_reg.wmf

Figure 3-14 possible crystal oscillator frequencies

In ASK receive mode the crystal osc illator is set to frequency f offset to receive the ASK signal at f

To set the 3 different frequencies 3 different C

*N (N: division ratio of the PLL).

are necessary. Via internal switches 3 external

capacitors can be combined to generate the necessary C

to realize the necessary freq uency

in case of ASK- or FSK-modulation.

Internal banks of switchable capacitors allow the finetuning of these frequencies.

3.2.2 Transmit/Receive ASK/FSK Frequency Assignment

Depending on whether the device operates in transmit or receive mode or whether it operates in ASK or FSK the following cases can be distinguished:

3.2.2.1 FSK-mode

In transmit mode the two frequencies representing logical HIGH and LOW data states have to be adjusted depending on the intended frequency deviation and separately according to the following formulas:

COSC HI

= (fRF + f

) / 24 f

DEV

COSC LOW

= (fRF - f

DEV

) / 24

[3 – 19]

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Application

e.g.

COSC HI

COSC LOW

= (315E6 + 30E3) / 24= 13.12625MHz

= (315E6 - 30E3) / 24= 13.12375MHz

with a frequency deviation of 30kHz. Figure 3-15 shows the configuration of the switches and the capacitors to achieve the 2 desired

frequencies. Gray parts of the schematics indicate inactive parts. For FSK modulation the ASKswitch is always open.

For FSK LOW the FSK- switch is closed a nd C

and C

are bypassed. The e ffective Cv- is given

tune2

by:

For finetuning C

CCC +=

11 tunevV

can be varied over a range of 8 pF in steps of 125fF. The switche s of this C-

tune1

[3 – 20]

bank are controlled by the bits D0 to D5 in the FSK register (subaddress 01H, see Table 3-6).

For FSK HIGH the FSK-switch is open. So the effective C

is given by:

Cv1C

The C-bank C

+()C

-------------------------------------------------------------------------------------- -= C

tune2

tune1

v1Ctune1

can be varied over a range of 16 pF in ste ps of 250fF for finetu ning of the F SK

+()×

v2Ctune2

[3 – 21]

HIGH frequency. The switches of this C-bank are controlled by the bits D8 to D13 in the FSK register (subaddress 01H, see Table 3-6).

XOUT 19

f, C

XIN 21

XSWF 20

XSWA 22

XGND 23

ASK-

switch

-RL

tune1

tune2

FSK-

switch

f, C

XOUT 19

XIN 21

XSWF 20

XSWA 22

XGND 23

ASK-

switch

-RL

tune1

tune2

FSK-

switch

FSK LOW

FSK HIGH

QOSC_FSK.wmf

Figure 3-15 FSK modulation

Preliminary Specification 51 2003-02-18

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Application

In receive mode the crystal oscillator frequency is set to yield a direct-to-zero conversion of the receive data. Thus the frequency may be calculated as

= fRF / 24,

COSC

e.g.

= 315E6 / 24= 13.123MHz

COSC

[3 – 22]

which is identical to the ASK transmit case.

-RL

tune1

tune2

FSK-

switch

V2CV3

f, C

XOUT 19

XSWF 20

XSWA 22

XGND 23

XIN 21

ASK-

switch

QOSC_ASK.wmf

Figure 3-16 FSK receive

In this case the ASK-switch is closed. The necessary C

The C-bank C

+()C

tune2

v1Ctune1

------------------------------------------------------------------------------------------------------- -= C

v1Ctune1

can be varied over a range of 16 pF in steps of 250fF for finetuning of the FSK

C+

+()×

tune2

C+

tune2

is given by:

[3 – 23]

receive frequency. In this cas e the switches of the C-bank are cont rolled by the bits D0 to D5 of the XTAL_TUNING register (subaddress 02H, see Table 3-5).

3.2.2.2 ASK-mode:

In transmit mode the crystal oscillator frequency is the same as in the FSK receive case, see Figure 3-16.

In receive mode a receive frequency offset is necessary as the limiters feedback is AC-coupled. This offset is achieved by setting the osc illator fr equ ency to th e FSK HIGH transmi t frequen cy, see Figure 3-15.

Preliminary Specification 52 2003-02-18

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Application

3.2.3 Parasitics

For the correct calculation of the external capacitors the parasitic capacitances of the pins and the switches (C

, C21, C22) have to be taken into account.

XOUT 19

f, C

XIN 21

XSWF 20

XSWA 22

XGND 23

-RL

tune1

tune2

Figure 3-17 parasitics of the switching network

Table 3-2 Typical values of parasitic capacitances

Name

With the given parasitics the actual C

v-Cv1Ctune1C21

+()C

v1Ctune1

------------------------------------------------------------------------------------------------------- C21+= Cv1C

tune1

+()C

v1Ctune1

----------------------------------------------------------------------------------------------------------------------------------------- C21+= C

v1Ctune1

++=

v2C20

FSK-: 2,8 pF / FSK+&ASK: 2.2pF

can be calculated:

+()×

C+

tune2

C+

tune2

C++v3C22C+

+()×

C++v3C22C+

Value

4,6 pF

1 pF

tune2

QOSC_parasitics.wmf

[3 – 24]

[3 – 25][3 – 25]

[3 – 26]

Note: Please keep in mind also to include the Pad parasitics of the circuit board. Preliminary Specification 53 2003-02-18

TDA5251 F1

–=

–

Version 1.0

Confidential

Application

3.2.4 Calculation of the external capacitors

1. Determination of necessary crystal frequency using formula [3-19]. e.g. f

2. Determine corresponding C e.g. C

3. Necessary CV using formula [3-17].

e.g.

1. When the nec es sary Cv for the 3 frequencies ( Cv- for FSK LOW, Cv+ for FSK HIGH and Cvm for

FSK-receive) are known the external capacitors and the internal tuning caps can be calculated using the following formulas:

-FSK:

FSK-

L FSK

= f

COSC LOW

- = C

L ±

tune1

FSKL

,--

applying formula [3-18].

Load

()

+=p

v-C21

OSCFSK

[3 – 27]

()

+FSK:

tune2

---------------------------------------------------------------------- C20–= C

()

FSK_RX:

To compensate frequenc y err ors due to cryst al an d comp onent t oler ance C be varied. To enable this correction, half of the necessary capacitance variation has to be realized with the internal C-banks.

If no finetuning is intended it is recommended to leave XIN (Pin 21) open. So the parasitic capacitance of Pin 21 has no effect.

Note: Please keep in mind also to include the Pad parasitics of the circuit board. In the suitable range for the serial capacitor, either capacitors with a tolerance of 0.1pF or 1% are

available. A spreadsheet, which c an be used to predict the total frequen cy error by s imply ente ring the crys tal

specification, may be obtained from Infineon.

tune2

------------------------------------------------------------------------ -C C

tune1

+()C

tune1

v1Ctune1

tune1

+()C

()×

v+C21

()×

vmC21

–()–

[3 – 28]

–C

C21–()–

–C

–=

, Cv2 and Cv3 have to

[3 – 29]

3.2.5 FSK-switch modes

The FSK-switch can be used either in a bipolar or in a FET mode. The mode of this switch is controlled by bit D0 of the XTAL_CONFIG register (subaddress 0EH).

In the bipolar mode the FSK-sw itch can be controlled by a ramp function. Th is ra mp func tion is set by the bits D1 and D2 of the XTAL_CONFIG register (subadress 0EH). With these modes of the FSK-switch the bandwidth of the FSK spectrum can be influenced.

When working in the FET mode the power consumption can be reduced by about 200 mA.

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The default mode is b ipolar switch with n o ramp fu nction (D0 = 1, D1 = D2 = 0) , which is suit able for all bitrates.

Table 3-3 Sub Address 0EH: XTAL_CONFIG

1 1 1

D1 D2 Switch mode Ra mp time Max. Bitrate

n.a. n.a. FET < 0.2 ms > 32 kBit/s NRZ

00bipolar (default) < 0.2 ms > 32 kBit/s NRZ

10 bipolar 4 ms 32 kBit/s NRZ 01 bipolar 8 ms 16 kBit/s NRZ 11 bipolar 12 ms 12 kBit/s NRZ

Application

3.2.6 Finetuning and FSK modulation relevant registers

Case FSK-RX or ASK-TX (C

Table 3-4 Sub Address 02H: XTAL_TUNING

Bit

D5 D4 Nominal_Frequ_4 4pF 1 D3 Nominal_Frequ_3 2pF 0 D2 Nominal_Frequ_2 1pF 0 D1 Nominal_Frequ_1 500fF 1 D0 Nominal_Frequ_0 250fF 0

Function Value Description Default

Nominal_Frequ_5 8pF Setting for

tune2

nominal

frequency

ASK-TX

FSK-RX

tune2

)

Case FSK-TX or ASK-RX (C

Table 3-5 Sub Address 01H: FSK

Bit

D13 FSK+5 8pF Setting for D12 FSK+4 4pF 0 D11 FSK+3 2pF 1

D10 FSK+2 1pF 0

D9 FSK+1 500fF 1 D8 FSK+0 250fF 0 D5 FSK-5 4pF 0 D4 FSK-4 2pF 0 D3 FSK-3 1pF 1 D2 FSK-2 500fF 1 D1 FSK-1 250fF 0 D0 FSK-0 125fF 0

Function Value Description Default

tune1

and C

tune2

positive

frequency shift: +FSK or ASK-RX

Setting for

negative

frequency

shift: -FSK

tune2

tune1

)

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Default values

In case of using the evaluation board, the crystal with its typical parameters (fp=13.125MHz, C

=6.5fF, C0=1.8pF, CL=20pF) and external capacitors with Cv1=27pF, Cv2=1.0pF, Cv3=15pF

each are used the following default states are set in the device

Table 3-6 Default oscillator settings

Operating state

ASK-TX / FSK-RX

+FSK-TX / ASK-RX

-FSK-TX

Frequency

315.0 MHz +30 kHz

-30 kHz

Application

3.2.7 Chip and System Tolerances

Quartz: fp=13.125MHz; C1=6.5fF; C0=1,8pF; CL=20pF (typical values) Cv1=27pF, Cv2=1.0pF, Cv3=15pF

Table 3-7 Internal Tuning

Part

Frequency set accuracy

Temperature (-40...+85C)

Supply Voltage(2.1...5 .5V )

Total

Frequency tolerance

@ 315MHz

+/- 1.3kHz +/- 4ppm +/- 2.5kHz +/- 8ppm +/- 0.6kHz +/- 2ppm +/- 4.4kHz +/- 14ppm

Rel. tolerance

Table 3-8 Default Setup (without internal tuning & without Pin21 usage)

Part

Internal capacitors (+/- 10%)

Inductivity of the crystal oscillator

Temperature (-40...+85C)

Supply Voltage (2.1...5.5V)

Total

Tolerance values in Table 3-8 are valid, if pin 21 is not connected. Establishing the connection to pin 21 the tolerances increase by +/- 16ppm (internal capacitors), if internal tuning is not used.

Concerning the frequency tolerances of the whole system also crystal tolerances (tuning tolerances, temperature stability, tolerance of CL) have to be considered.

In addition to the chip tolerances also the crystal and external component tolerances have to be considered in the tuning and non-tuning case.

Frequency t olerance

@ 315MHz

+/-2.2kHz +/- 7ppm +/- 2.5kHz +/-8ppm +/- 2.5kHz +/- 8ppm +/- 0.6kHz +/- 2ppm +/- 7.8kHz +/- 25ppm

Rel. tolerance

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In case of internal tuning: The crystal on the evaluation board has a temperature stability of +/20ppm (or +/- 6.3kHz), which must be added to the total tolerances in worst case. It’s possible to choose a crystal compensating the oscillators temperature drift in a certain range and thus the overall temperature tolerances are minimized.

In case of default setup (without internal tuning and without usage of pin 21) the temperature stability and tuning tolerance of the crystal as well as the tolerance of the external capacitors (+/-

0.1pF) have to be added. The crystal on the evaluation board has a temperature stability of +/20ppm (or +/- 6.3kHz) an d a tuning tole rance of + /- 10ppm (or +/- 3.2 kHz) . The exter nal capacito rs add a tolerance of +/- 3.5p pm (or + /- 1.1 kH z). H ere also the overall temperature tolerance s ca n be reduced when applying an appropriate temperature drift of the crystal.

The frequency sta bili ties of both the rece ive r a nd the transmitter a nd the m od ulation bandwidth set the limit for the bandwidth of the IQ filter. To achieve a high receiver sensitivity and efficient suppression of adjacent interference signals, the narrowest possible IQ bandwidth should be realized (see Section 3.3).

Application

3.3 IQ-Filter

The IQ-Filter should be se t to va lue s corresponding to the RF-ba ndw idt h of the received RF signal via the D1 to D3 bits of the LPF register (subaddress 03H).

Table 3-9 3dB cutoff frequencies I/Q Filter

0 0 0 1 350 700 0 0 1 1 1 1

D2 D1 nominal f

(programmable)

0 0 not us ed

1 0 250 500 1 1 200 400 0 0 150 (default) 300 0 1 100 200 1 0 50 100 1 1 not us ed

-3dB

in kHz

resulting effective

channel

bandwidth in kHz

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-10

-2 0

-3 0

-4 0

-5 0

-6 0

-7 0

-8 0 10 10 0 10 0 0 10 00 0

Figure 3-18 I/Q Filter Characteristics

effective channel bandwidth

Application

50kHz

100kHz

150 kH z

200kHz

250kHz

350kHz

f [kHz]

iq_filter_curve.wmf

-f

3dB

IQ Filter

3dB

IQ Filter

iq_char.wmf

Figure 3-19 IQ Filter and frequency characteristics of the receive system

3.4 Data Filter

The Data-Filter should be set to values corresponding to the bandwidth of the transmitted Data signal via the D4 to D7 bits of the LPF register (subaddress 03H).

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Table 3-10 3dB cutoff frequencies Data Filter

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

D6 D5 D4 nominal f

0 0 0 5 0 0 1 7 (default) 0 1 0 9 0 1 1 11 1 0 0 14 1 0 1 18 1 1 0 23 1 1 1 28 0 0 0 32 0 0 1 39 0 1 0 49 0 1 1 55 1 0 0 64 1 0 1 73 1 1 0 86 1 1 1 102

-3dB

Application

in kHz

3.5 Limiter and RSSI

I- Filter

CI1x

CI1

36 35 34

CQ1

CI2

CQ1x

Limiter

CQ2

33 32 31

CI2x

RSSI

CQ2x

Quadr.

Corr.

RSSI29

37k

SUM

Q- Filter

Limiter

Quadr.

Corr.

limiter input.wmf

Figure 3-20 Limiter and Pinning

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Application

The DC offset compensation needs 2.2ms after Power On or Tx/Rx switch . This t ime i s har d wir ed and independent from external capacitors CC on pins 31 to 38. The maximum value for this capacitors is 47nF.

RSSI accuracy settling time = 2.2ms + 5*RC=2.2ms+5*37k*2.2 nF =2 .6m s R - internal resistor; C - external capacitor at Pin 29

Table 3-11 Limiter Bandwidth

[nF]

220 100

f3dB

lower limit

[Hz]

f3dB

upper

limit

Comment

100 IQ Filter setup time not guaranteed 220 - ll - setup time not guaranteed

470 - ll - Eval Board

1000 - ll -

10 2200 - ll -

v [dB]

3dB

IQ Filter

Figure 3-21 Limiter frequency characteristics

3dB

Limiterlower limit

limiter_char.wmf

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1300

1200

1100

1000

900

800

700

600

RSSI /mV

500

400

300

200

100

-120 -1 10 -10 0 -90 -8 0 -70 -60 -50 -40 -3 0 - 20

Figure 3-22 Typ. RSSI Level (Eval Board) @3V

RF / dBm

Application

ADC

high gain

low gain

RSSI.wmf

3.6 Data Slicer - Slicing Level

The data slicer is an analog-to -digital converter. It is necessary to genera te a threshold value for the negative comparator in put (data slicer). The TDA52 51 offers an RC integrator and a peak detector which can be selected via logic. Independent of the choice, the peak detector outputs are always active.

3.6.1 RC Integrator

Table 3-12 Sub Address 00H: CONFIG

Bit

D15 Necessary external component (Pin14): C This integrator generates the mean value of the data filter output. For a stable threshold value, the

cut-off frequency has to be lower than the lo west signal frequency . The cutoff freque ncy results from the internal resistance R=100kW and the external capacitor C

Cut-off frequency:

Function Description Default SET

SLICER 0= LP, 1= Peak Detector 0 0

SLC

on Pin14.

SLC

{}

f <

offcut

10021p

×W×

SLC

fMin

Signal

[3 – 30]

Component calculation: (rule of thumb) T

– longest period of no signal change

100

SLC

[3 – 31]

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DataSlicer

Slicer Thresho ld

+ Peak

Detector

100k

Data

Filter

Figure 3-23 Slicer Level using RC Integrator

Signal

- Peak

Detector

Contr.

Logic

100k

Vcc

DATA

PDP

SLC

PDN

Application

SLC

SLC_RC.wmf

3.6.2 Peak Detectors

Table 3-13 Sub Address 00H: CONFIG

Bit

D15

The TDA5251 has two peak detectors built in, one for positive peaks in the data stream and the other for the negative ones.

Necessary external components: - Pin12: C

Function Description Default SET

SLICER 0= LP, 1= Peak Detector 0 1

- Pin13: C

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DataSlicer

Slicer Threshold

+ Peak

Detector

Data

Filter

Figure 3-24 Slicer Level using Peak Detector

Signal

100k

- Peak

Detector

Contr.

Logic

100k

Vcc

DATA

PDP

SLC

PDN

Vcc

Application

SLC_PkD.wmf

For applications requiring fast attack and slow release from the threshold value it is reasonable to use the peak detectors. T he threshold valu e is generated by a n internal voltage divider. The relea se time is defined by the internal resistance values and the external capacitors.

[3 – 32]

[3 – 33]

Signal

negPkD

Ck ×W= 100

Ck ×W= 100t

pposPkD

nnegPkD

posPkD

Pos. Peak Detector (pin13)

Threshold SLC(pin14)

Neg. Peak Detector (pin12)

PkD_timing.wmf

Figure 3-25 Peak Detector timing

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Application

Component calculation: (rule of thumb)

100

W³k

– longest period of no signal change (LOW signal)

W³k

– longest period of no signal change (HIGH signal)

[3 – 34]

–

3.6.3 Peak Detector - Analog output signa l

The TDA5251 data output ca n be digital (pin 28) or in analog form by using the p eak detector output and changing some settings.

To get an analog data output the slicer must be set to lowpass mode (Reg. 0, D15 = LP = 0) and the peak detector capacitor at pin 12 or 13 has to be changed to a resistor of about 47kOhm.

DataSlicer

Slicer T hreshold

Contr.

Logic

DATA

Data

Filter

Signal

+ Peak

Detector

100k

- Peak

Detector

100k

Vcc

PDP

SLC

PDN

47k

SLC

PkD_analog.wmf

Figure 3-26 Peak Detector as analog Buffer (v=1)

3.6.4 Peak Detector – Power Down Mode

For a safe and fast threshold value generation the peak detector is turned on by the sequencer circuit (see Section 2.4.18) only after the entire receiving path is active.

In the off state the output of the positive peak detector is tied down to GND and the output of the negative peak detector is pulled up to VCC.

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Logic

Power Down Mode

+ Peak

Detector

off

Data

Filter

- Peak

Detector

off

Figure 3-27 Peak detector - power down mode

Application

PDP

100k

SLC

100k

PDN

Vcc

PKD_PWDN.wmff

Signal

Data Signal

Vcc

Power ON Power Down

Neg. Peak Detector (pin12)

Threshold (pin14)

Pos. Peak Detector (pin13)

2,2ms

Power ON

Peak Detector Power ON

PkD_PWDN3.wmf

Figure 3-28 Power down mode

3.7 Data Valid Detection

In order to detect valid data two criteria must be fulfilled. One criteria is the data ra te, which can be s et in register 06h and 07h. The othe r one is the receiv ed

RF power level, which can be set in register 08h in form of the RSSI threshold voltage. Thus for using the data valid detection FSK modulation is recommended.

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Application

Timing for data detection looks like the following. Two settings are possible: „Continuous“ and „Single Shot“, which can be set by D5 and D6 in register 00H.

Data

Sequenzer enables

data detection

Counter Reset

Gate time

Compare with single

TH and latch result

Compare with double

TH and latch result

(Frequency) Window

Count Complete

rese trese t

count count

comp. com p.

comp.

ready*

start of conversion possible start of next conversion

Frequ_Detect_Timing_continuous.wmf

Figure 3-29 Frequency Detection timing in continuous mode Note 1: Chip internal signal „Sequencer enables data detection“ has a LOW to HIGH transition

about 2.6ms after RX is activated (see Figure 2-15). Note 2: The positive ed ge of the „W indow Coun t Comple te“ sig nal la tche s the result of co mparis on

of the analog to digital conve rte d RS SI voltage with TH3 (register 08 H) . A logic combination of this output and the result of the comparison with single/double THx defines the internal signal „data_valid“.

Figure 3-29 shows that the log ic is ready for the next conversion after 3 periods of the d ata signal.

Timing in Single Shot mode can be seen in the subsequent figure:

Data

Sequenzer enables

data detection

Counter Reset

Gate time

Compare with single

TH and latch result

Compare with double

TH and latch result

(Frequency) Window

Count Complete

start of conversion

reset

count

no possible start of next conversion

comp.

rea d y*

because of Single Shot Mode

Frequ_Detect_Timing_singleShot_wmf

Figure 3-30 Frequency Detection timing in Single Shot mode

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Application

3.7.1 Frequency Window for Data Rate Detection

The high time of data is used to measure the frequency of the data signal. For Manchester coding either the data frequency or half of the data frequency have to be detected corresponding to one high time or twice the high time of data signal.

A time period of 3*2*T is necessary to decide about valid or invalid data.

T2*T

DATA

possible GATE 1

possible GATE 2

0010

2*T2

2*T1

window_count_timing.wmf

Figure 3-31 Window Counter timing

Example to calculate the thresholds for a given data rate:

- Data signal manchester coded

- Data Rate: 2kbit//s

- f

= 13,125 MHz

clk

Then the period equals to

T2 ==×

2kbit/s

0,5ms

[3 – 36]

respectively the high time is 0,25ms. We set the thresholds to +-10% and get: T1= 0,225ms and T2= 0,275ms

The thresholds TH1 and TH2 are calculated with following formulas

clk

T1TH1

×=

[3 – 37]

clk

T2TH2

×=

[3 – 38]

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Application

This yields the following results:

TH1~ 738= 001011100010 TH2~ 902= 001110000110

b b

which have to be programmed into the D0 to D11 bits of the COUNT_TH1 and COUNT_TH2 registers (subaddresses 06H and 07H), respectively.

Default v alues (window counter inactive): TH1= 000000000000 TH2= 000000000001

b b

Note: The timing window of +-10% of a given high time T in general does not correspond to a frequency window +-10% of the calculated data frequency.

3.7.2 RSSI threshold voltage - RF input power

The RF input power leve l is corre spond ing to a ce rtai n RSSI v oltage, which ca n be see n in Secti on

3.5. The threshold TH3 of this RSSI voltage can be calculated with the following formula:

TH3

1.2V

voltagethresholdRSSIdesired

)12(6-×=

[3 – 39]

As an example a desired R SSI thre shold volta ge of 500mV result s in TH3~26=01 1010b, which has to be written into D0 to D5 of the RSSI_TH3 register (sub address 08H).

Default value (RSSI detection inactive): TH3=111111

3.8 Calculation of ON_TIME and OFF_TIME

ON= (216-1)-(fRC*tON) OFF=( 2 f

Example: t

-1)-(fRC*t

OFF

)

= Frequency of internal RC Oszillator

= 0,005s, t

= 0,055s, fRC= 32300Hz

OFF

ON= 65535-(32300*0,005) ~ 65373= 1111111101011101 OFF= 65535-(32300*0,055) ~ 63758= 1111100100001110

[3 – 40]

[3 – 41]

The values have to be written into the D0 to D15 bits of the ON_TIME and OFF_TIME registers (subaddresses 04H and 05H).

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Application

Default values: ON= 65215 = 1111111011000000 OFF= 62335 = 1111001110000000

tON ~10ms @ fRC= 32kHz t

~100ms @ fRC= 32kHz

OFF

3.9 Example for Self Polling Mode

The settings for Self Polling Mode depend very much on the timing of the transmitted Signal. To create an example we consider following data structure transmitted in FSK.

4 Frames

Data Data Data Data

50ms 50ms

400ms

t [ms ]

Frame-

details

Sync

Preamble

Syncronisation Preamble

Data

t [ms ]

data_timing011.wmf

Figure 3-32 Example for transmitted Data-structure

According to existing synchronization techniques there are some synchronization bursts in front of the data added (code violation!). A minimum of 4 Frames is transmitted. Data are preferably Manchester encoded to get fastest respond out of the Data Rate Detection.

Target Application:

- received Signal has code violation as described before

- total mean current consumption below 1mA

- data reception within max. 400ms after first transmitted frame

One possible Solution: tON = 15ms, t

= 135ms

OFF

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Application

This gives 15ms ON time of a total period of 150ms which results in max. 0.9mA mean current consumption in Self Polling Mode. The resulting worst case timing is shown in the following figure:

Case A:

Case B:

Case C:

Data Data Data Data

50ms 135m s15m s µP enables Receiver

Data Data Data Data

50ms

Data Data Data Data

50ms

... Receiver enabled

135ms15ms

until Data completed

Interrupt due PwdDD

µP enables Receiver

until Data completed

Interrupt due PwdDD

µP enables Receiver until Da ta c o m plet e d

Interrupt due PwdDD

t [ms ]

data_timing021.wmf

Figure 3-33 3 possible timings

Description: Assumption: the ON time comes right after the first frame (Case A). If OFF time is 135ms the

receiver turns on during Sync-pulses and the PwdDD

- pulse wakes up the µP. If the ON time is in the ce nter of the 50ms gap of tr ans mis sio n (C as e B), the Data Detect Log ic w ill wake up the µP 135ms later. If ON time is over just before Sync-puls es (Cas e C), next ON time is during Data transmission and Data Detect Logic will trigger a PwdDD

- pulse to wake up the µP.

Note: In this example it is recommended to use the Peak Detector for slicer threshold generation, because of its fast attack and slow release characteristic. To overcome the data zero gap of 50ms larger external capacitors than noted in Section 4.4 at pin12 and 13 are recommended. Further information on calculating these components can be taken from Section 3.6.2.

3.10 Sensitivity Measurements

3.10.1 Test Setup

The test setup used for the measurements is shown in the following figure. In case of ASK modulation the Rohde & Sc hwarz SMIQ generat or, which is a vector signal genera tor, is connect ed to the I/Q modulation source AMIQ . This "bas eband signal generator" i s in turn con trolled by th e PC

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Application

based software WinQSIM via a GPIB interface. The AMIQ generator has a pseudo random binary sequence (PRBS) gener ator and a bit error test set built in. T he r esu lting I/Q sig nals are applied to the SMIQ to generate a ASK (OOK) spectrum at the desired RF frequency.

Data is demodulated by the TDA5251 and then sent back to the AMIQ to be compared with the originally sent data. The bit error ra te is calcul ated by the bit error rate equipment in side the AMIQ .

Baseband coding in the form of Manchester is applied to the I signal as can be seen in the subsequent figure.

Personal Computer

Software

WinIQSIM

GPIB /

RS 232

Marker Output Rohde & Schw arz

I/Q M odulation Source

AMIQ

AMIQ BERT

(Bit E rror R a te

T est Set)

Clock

Data

Manchester

Encoder

Rohde & Schw arz Vector Signal Generator SM IQ 0 3

ASK / FSK RF Signal

Manchester

Decoder

DATA out

RFin

DUT

Transceiver Testboard TDA 525x

TestSetup.wmf

Figure 3-34 BER Test Setup

In the following figures the RF power level shown is the average power level. These investigations have been made on an Infineon evaluation board using a data rate of 4 kBit/

s with manchester en codi ng a nd a d ata fil ter bandwidth of 7 kHz. This is the standard configurati on of our evaluation boards. All these measurements have been performed with several evaluation boards, so that production scattering and component tolerances are already included in these results.

Regarding the data filter bandwidth it has to be mentioned that a data rate of 4 kBit/s using manchester encoding results in a data frequency of 2 kHz to 4 kHz depending on the occurring data pattern. The test pattern given by the AMIQ is a pseudo random binary sequency (PRBS9) with a 9 bit shift register. This pattern varies the resulting data frequency up to 4 kHz.

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The best sensitivity performance can be achieved using a data filter bandwidth of 1.25 times the maximum occuring data frequency.

The IQ filter setting is depending on the modulation type. ASK needs an IQ filter of 50kHz, 30kHz deviation at FSK recommend a 50kHz IQ filter.

A very practicable config uration is to set the chip -internal adjustab le IQ filter to the sum of FSK pe ak deviation and maximum datafr equency. Concerni ng these aspects the bandwid th should be chosen small enough. With respect to both, the crystal tolerances and the tolerances of the crystal oscillator circuit of receiver and transmitter as well, a too small IQ filter bandwidth will reduce the sensitivity again. So a compromise has to be made. For further details on chip tolerances see also Section

3.2.7

Application

3.10.2 BER performance depending on Supply Voltage

Due to the wide supply voltage range of this transeiver chip also the sensitivity behaviour over this parameter is documented is the subsequent graph.

BER_VCC.wmf

Figure 3-35 BER supply voltage

Please notice the tiny sensitivity changes of less than 1dB, when variing the supply voltage.

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Application

3.11 Default Se tup

Default setup is hard wired on chip and effective after a reset or return of power supply.

Table 3-14 Default Setup

Parameter

IQ-Filter Bandwidth 150kHz

Data Filter Bandwidth 7kHz

Limiter lower fg 470Hz 47nF

Slicing Level Generation RC 10nF

Nom. Frequency Capacity intern (ASK TX, FSK RX) 4.5pF 315MHz

FSK+ Frequency Capacity intern (FSK+, ASK RX) 2.5pF +30kHz

FSK- Frequency Capacity intern (FSK-) 1.5pF -30kHz

LNA Gain HIGH

Power Amplifier HIGH +10dBm

Value IFX-Board Comment

RSSI accuracy settling time 2.6ms 2.2nF

ADC measurement RSSI

ON-Time 10ms

OFF-Time 100ms

Clock out RX PowerON 0.73MHz

Clock out TX PowerON 0.73MHz

Clock out RX PowerDOWN -

Clock out TX PowerDOWN -

XTAL modulation switch bipolar

XTAL modulation shaping off

RX / TX - Jumper

ASK/FSK - Jumper

PwdDD PWDN Jumper

removed

Operating Mode Slave

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4 Reference

4.1 Electrical Data

4.1.1 Absolute Maximum Ratings

WARNING

The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result.

Table 4-1 Absolute Maximum Ratings

1 Supply Voltage V 2 Junction Temperature T 3 Storage Temperature T 4 Thermal Resistance R 5 ESD integrity, all pins V

Parameter Symbol Limit Values Unit Remarks

s thJA ESD

Reference

min max

-0.3 5.8 V

-40 +125 °C

-40 +150 °C 114 K/W

tbd tbd kV HBM according

to MIL STD

883D, method

3015.7

4.1.2 Operating Range

Within the operational range the IC operates as explained in the circuit description.

Table 4-2 Operating Range

1 Supply voltage V 2 Ambient temperature T 3 Receive frequency f 4 Transmit frequency f

Preliminary Specification 74 2003-02-18

Parameter Symbol Limit Values Unit Test Conditions L Item

min max

2.1 5.5 V

-40 85 °C 312 325 MHz 312 325 MHz

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Reference

4.1.3 AC/DC Characteristics

AC/DC characteristics involve the spread of values guaranteed within the specified voltage and ambient temperature range. Typical characteristics are the median of the production.

Table 4-3 AC/DC Characteristics with TA = 25 °C, V

Parameter Symbol Limit Values Unit Test Conditions L Item

min typ max

RECEIVER Characteristics

Supply current RX FSK I

2 Supply current RX FSK I

3 Supply current RX ASK I 4 Supply current RX ASK I

5 Sensitivity FSK

-3

BER

6 Sensitivity ASK

-3

BER

RX_FSK RX_FSK

RX_ASK RX_ASK

RFsens

9.3 mA 3V, FSK, Default

9.8 mA 5V, FSK, Default

8.8 mA 3V, ASK, Default

9.4 mA 5V, ASK, Default

-109 dBm FSK@30kHz, 4kBit/s

-109 dBm ASK, 4kBit/s Manch.

= 2.1 ... 5.5 V

VCC

Manch. Data, Default

7kHz datafilter, 50kHz

data, Default setup

IQ filter

7kHz datafilter,

50kHz IQ filter

7 Power down current I 8 System setup time (1st

PWDN_RX

SYSSU

power on or reset)

9 Clock Out setup time t

10 Receiver setup time t

11 Data detection setup

CLKSU

RXSU

DDSU

time

12 RSSI stable time t

13 Data Valid time t

14 Input P 15 Input P

, high gain P

1dB

, low gain P

1dB

16 Selectivity V

Data_Valid

1dB_low

BL_1MHz

17 LO leakage P

RSSI

1dB

5 nA 5.5V, all power down

4812 ms

0.5 ms stable CLKDIV output signal

1.54 2.2 2.86 ms DATA out (valid or invalid)

1.82 2.6 3.38 ms Begin of Data detection

1.82 2.6 3.38 ms RFin -100dBm

see chapt er 4.5

3.35 ms 4kBit/s Manch. detected (valid)

-48dBm dBm 3V, Default, high gain X

-32dBm dBm 3V, Default, low gain X 50 dB fRF+/-1MHz, Default,

sens

+3dB

-102 dBm 578,9MHz X

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Table 4-3 AC/DC Characteristics with TA = 25 °C, V

TRANSMITTER Characteristics

Supply current TX, FSK I

4 Output power P 5 Output power P 6 Output power P

7 Supply current TX, FSK I 8

Supply current TX, FSK I

Parameter Symbol Limit Values Unit Test Conditions L Item

min typ max

TX TX TX

out out out

TX TX TX

11.4 mA 2.1V, high power 1

14.1 mA 3V, high power 1

18.7 mA 5V, high power 1

+6 dBm 2.1V, high power X +9 dBm 3V, high power X

+13 dBm 5V, high power X

5,4 mA 2.1V, low power 1

8.7 mA 3V, low power 1

17.8 mA 5V, low power 1

= 2.1 ... 5.5 V

VCC

Reference

10 Output power P 11 Output power P 12 Output power P

13 Power down current I

14 Clock Out setup time t

15 Transmitter setup time t

16 Spurious fRF+/-f

17 Spurious fRF+/-f

clock

XTAL

18 Spurious 2nd harmonic P 19 Spurious 3rd harmonic P

1: without pin di ode current (RX/TX-switch) 130uA@2.1V; 310uA@3V; 720uA@5V

out_low out_low out_low

PWDN_TX

CLKSU

TXSU

clock

1st

2nd

3rd

-34 dBm 2.1V, low power X +2 dBm 3V, low power X

+13 dBm 5V, low power X

5 nA 5.5V, all power down

0.5 ms stable CLKDIV output

signal

0.77 1.1 1.43 ms PWDN-->PON or RX-->TX

-75 dBm 3V, 50Ohm Board, Default (730kHz)

-74 dBm 3V, 50Ohm Board X

-38 dBm 3V, 50Ohm Board X

-40 dBm 3V, 50Ohm Board X

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Table 4-4 AC/DC Characteristics with TA = 25 °C, V

GENERAL Characteristics

2 Power down current

3 Power down cu rrent with

4 Power down cu rrent with

5 32kHz oscillator freq. f

Parameter Symbol Limit Values Unit Test Condition s L Item

min typ max

Power down current

PWDN_32k

9 uA 3V, 32kHz clock on

timer mode (standby)

PWDN_32k

11 uA 5V, 32kHz clock on

timer mode (standby)

PWDN_Xtl

750 uA 3V, CONF IG9=1

XTAL ON

PWDN_Xtl

860 uA 5V, CONF IG9=1

XTAL ON

32kHz

24 32 40 kHz

= 2.1 ... 5.5 V

VCC

Reference

6 XTAL startup time t 7 Load capacitance C

8 Serial resistance of the

crystal

9 Input inductance XOUT L

10 Input inductance XOUT L

11 FSK demodulator gain G

12 RSSI@-120dBm U 13 RSSI@-100dBm U

-120dBm

-100dBm

14 RSSI@-70dBm U 15 RSSI@-50dBm U 16 RSSI Gradient G

17 IQ-Filter bandwidth f 18 Data Filter bandwidth f

3dB_IQ

3dB_LP

XTAL

C0max

Rmax

OSC OSC

FSK

-70dBm

-50dBm RSSI

0.5 ms

IFX Board with Crystal Q1 as

specified in Section 4.4

5 pF X

100 W X

2.2 uH

2.1 uH

with pad on evaluation board

without pad on evaluation

board

2.4 mV/ kHz

0.45 V default setup X

0.5 V default setup X

0.9 V default setup X

1.2 V default setup X

11 mV/

default setup X

115 150 185 kHz Default setup X

5.3 7 8.7 kHz Default setup X

X X

19 Vcc-Vtune RX, Pin3 V 20 Vcc-Vtune TX, Pin3 V

cc-tune,RX

cc-tune,TX

0.5 0.67 1.6 V f

0.5 0.86 1.6 V f

=13.125MHz

Ref

=13.125MHz

Ref

Preliminary Specification 77 2003-02-18

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p m

BusMode = LOW

BUS_MODE = HIGH

Version 1.0

Confidential

4.1.4 Digital Characteristics

I2C Bus Timing

BUF

Bus Data

LOW

HIGH

HD.STA

SU.ENAS DA

HD.DAT

HIGH

BusCLK

ul sed or

andatory low

SU.ENAS DA

Reference

SU.DAT

SU.STA

HD.STA t

SU.S TO

SU.ENA SDA

Figure 4-1 I

3-wire Bus Timing

SDA

US_ENA

Figure 4-2 3-wire Bus Timing

C Bus Timing

WHEN

LOW

SU.STA

HD.DAT

HI GH

SU.DAT

SU.STO

Preliminary Specification 78 2003-02-18

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Table 4-5 Digital Characterist ics with TA = 25 °C, V

1 Data rate TX ASK f

3 4 Data rate RX FSK f

5 Digital Inputs

High-level Input Voltage

6 RXTX Pin 5

TX operation, int. controlled

7 CLKDIV Pin 26

rise

fall

Parameter Symbol Limit Values Unit Test Conditions L Item

min typ max

10 kBaud PRBS9,

10 kBaud PRBS9, Manch. X 10 kBaud PRBS9, Manch.

0.4

Data rate TX FSK f

Data rate RX ASK f

Low-level Input Voltage

TX.ASK

TX.FSK

RX.ASK RX.FSK

Vdd-

0.2

1.15

(0.1*Vdd to 0.9*Vdd)

(0.9*Vdd to 0.1*Vdd)

Output High Voltage

Output Low V oltage

f OH OL

35 30

Vdd-

0.4

= 2.1 ... 5.5 V

Vdd

0.2VV

V V

ns ns

V V

Manch.@+9dBm

@30kHz dev.

@Vdd=3V

Isink=800uA

Isink=3mA @Vdd=3V

load 10pF load 10pF

source

sink

=350uA

=400uA

Reference

X 1

Bus Interface Characteristics

9 Pulse width of spikes which

0 50 ns Vdd=5V X

must be suppressed by the

input filter

10 LOW level output voltage at

BusData 11 SLC clock frequency f 12 Bus free time between STOP

and START condition

13 Hold time (repeated) STAR T

condition.

SLC

BUF

HO.STA

0.4 V 3mA sink current V

=5V

0 400 kHz Vdd=5V X

1.3 µs only I2C mode =5V

0.6 µs After this period, the

first clock pulse is

generated, only I

Preliminary Specification 79 2003-02-18

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Table 4-5 Digital Characterist ics with TA = 25 °C, V

14 LOW pe riod of BusCLK clock t 15 HIGH period of BusCLK

16 Setup time for a repeated

17 Data hold time t 18 Data setup time t 19 Rise, fall time of both

21 Capacitive load for ea ch bus

22 Setup time fo r BusCLK to EN t

23 H-pulsewidth (EN) t

Parameter Symbol Limit Values Unit Test Conditions L Item

min typ max

LOW

HIGH

1.3 µs Vdd=5V X

0.6 µs Vdd=5V X

clock

SU.STA

0.6 µs only I2C mode X

START condition

0 ns Vdd=5V X 100 ns Vdd=5V X 20+

0.1C

300 ns Vdd=5V X 2

BusData and BusCLK

HD.DAT

SU.DAT

, t

signals

Setup time for STOP

SU.STO

0.6 µs only I2C mode

condition

400 pF Vdd=5V X

line

SU.SCLE

WHEN

0.6 µs only 3-wire mode

0.6 µs Vdd=5V X

= 2.1 ... 5.5 V

Vdd

Reference

=5V

1: limited by transmission channel bandwidth and depending on transmit power level; ETSI regulation EN 300 220

fullfilled, see Section 3.1

2: C

= capacitance of one bus line

Preliminary Specification 80 2003-02-18

TDA5251 F1

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Reference

4.2 Test Circuit

The device performanc e parameters marke d with X in Section 4.1.3 were measu red on an Infineon evaluation board (IFX board).

TDA5250_v42.schematic.pdf

Figure 4-3 Schematic of the Evaluation Board

Preliminary Specification 81 2003-02-18

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4.3 Test Board Layout

Gerberfiles for this Testboard are available on request.

Reference

TDA5250_v42_layout.pdf

Figure 4-4 Layout of the Evaluation Board Note 1: The LNA and PA matching network was designed for minimum required space and

maximum performance and thus via holes were deliberately placed into solder pads. In case of reproduction p lea se bear i n mind th at this m ay not be suitable for all au tomatic solderi ng

processes. Note 2: Please keep in mind not to lay out the CLKDIV line directly in the neighborh ood of the crystal

and the associated components. Note 3: The opto part (X4) should be supplied by connecting to X3.

Preliminary Specification 82 2003-02-18

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4.4 Bill of Materials

Table 4-6 Bill of Materials

Reference

R1 R2 R3 R4 R5 R6 R7 R8

R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24

C9 C10 C11 C12 C13

Reference

Value Specification Tolerance

4k7 0603 +/-5%

10 0603 +/-5%

--- 0603 +/-5%

1M 0603 +/-5% 4k7 0603 +/-5% 4k7 0603 +/-5% 4k7 0603 +/-5% 6k8 0603 +/-5% 180 0603 +/-5% 180 0603 +/-5% 270 0603 +/-5% 15k 0603 +/-5% 10k 0603 +/-5% 180 0603 +/-5% 180 0603 +/-5%

1M 0603 +/-5%

1M 0603 +/-5% 560 0603 +/-5%

1k 0603 +/-5% 10 0603 +/-5%

00603 +/-5%

10 0603 +/-5%

180 0603 +/-5%

100pF 0603 +/-5%

3,9pF 0603 +/-0 , 1pF

8.2pF 0603 +/-0 . 1pF 8,2pF 0603 +/-0 , 1pF

1nF 0603 +/-5% 1nF 0603 +/-5%

6,8pF 0603 +/-0,1pF

--- 0603 +/-0,1pF

33pF 0603 +/-1%

100pF 0603 +/-5%

--- 0603 +/-5% 10nF 0603 +/-10% 10nF 0603 +/-10%

Preliminary Specification 83 2003-02-18

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Table 4-6 Bill of Materials

Reference

C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30

L1 L2

L3 IC1 IC2 ILQ74 IC3 SFH6186

Q1 13. 125MHz Telcona: C0=1,8pF C1=6.5fF, CL=20pF

T1 BC847B SOT-23 (Infineon)

D1, D2 BAR63-02W SCD-80 (Infineon)

X1, X2 SMA-socket

X5 SubD 25p.

Reference

Value Specification Tolerance

10nF 0603 +/-10% 27pF 0603 +/-1%

1pF 0603 +/-0,1p F 15pF 0603 +/-1% 10nF 0603 +/-10%

2,2nF 0603 +/-10%

47nF 0603 +/-10% 47nF 0603 +/-10% 47nF 0603 +/-10% 47nF 0603 +/-10%

100nF 0603 +/-10% 100nF 0603 +/-10%

--- 0603 +/-10% 100nF 0603 +/-10% 100nF 0603 +/-10% 100nF 0603 +/-10%

--- 0603 +/-10%

82nH SIMID 0603-C (EPCOS) +/-2% 47nH SIMID 0603-C (EPCOS) +/-2% 56nH SIMID 0603-C (EPCOS) +/-2%

TDA5251 F1 PTSSOP38

1-pol.

Preliminary Specification 84 2003-02-18

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List of Tables

Table 2-1 Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 11

Table 2-2 Sub Address 00H: CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 18

Table 2-3 Sub Address 00H: CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 18

Table 2-4 Sub Address 00H: CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 21

Table 2-5 PwdDD Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 22

Table 2-6 Bus Interface Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 23

Table 2-7 Chip address Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 25

Table 2-8 I2C Bus Write Mode 8 Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 25

Table 2-9 I2C Bus Write Mode 16 Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 25

Table 2-10 I2C Bus Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 25

Table 2-11 3-wire Bus Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 26

Table 2-12 3-wire Bus Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 26

Table 2-13 Sub Addresses of Data Registers Write. . . . . . . . . . . . . . . . . . . . . . page 27

Table 2-14 Sub Addresses of Data Registers Read. . . . . . . . . . . . . . . . . . . . . . page 27

Table 2-15 Sub Address 00H: CONFIG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 27

Table 2-16 Sub Address 01H: FSK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 28

Table 2-17 Sub Address 02H: XTAL_TUNING . . . . . . . . . . . . . . . . . . . . . . . . . . page 28

Table 2-18 Sub Address 03H: LPF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 28

Table 2-19 Sub Addresses 04H / 05H: ON/OFF_TIME . . . . . . . . . . . . . . . . . . . page 28

Table 2-20 Sub Address 06H: COUNT_TH1 . . . . . . . . . . . . . . . . . . . . . . . . . . . page 28

Table 2-21 Sub Address 07H: COUNT_TH2 . . . . . . . . . . . . . . . . . . . . . . . . . . . page 28

Table 2-22 Sub Address 08H: RSSI_TH3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 29

Table 2-23 Sub Address 0DH: CLK_DIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 29

Table 2-24 Sub Address 0EH: XTAL_CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . page 29

Table 2-25 Sub Address 0FH: BLOCK_PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 29

Table 2-26 Sub Address 80H: STATUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 29

Table 2-27 Sub Address 81H: ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 29

Table 2-28 MODE settings: CONFIG register . . . . . . . . . . . . . . . . . . . . . . . . . . page 30

Table 2-29 CLK_DIV Output Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 35

Table 2-30 CLK_DIV Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 35

Table 2-31 Source for 6Bit-ADC Selection (Register 08H). . . . . . . . . . . . . . . . . page 35

Table 3-1 Crystal and crystal oscilator dependency . . . . . . . . . . . . . . . . . . . . . page 48

Table 3-2 Typical values of parasitic capacitances. . . . . . . . . . . . . . . . . . . . . . page 53

Table 3-3 Sub Address 0EH: XTAL_CONFIG. . . . . . . . . . . . . . . . . . . . . . . . . . page 55

Table 3-4 Sub Address 02H: XTAL_TUNING . . . . . . . . . . . . . . . . . . . . . . . . . . page 55

Table 3-5 Sub Address 01H: FSK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 55

Table 3-6 Default oscillator settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 56

Table 3-7 Internal Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 56

Table 3-8 Default Setup (without internal tuning & without Pin21 usage). . . . . page 56

Table 3-9 3dB cutoff frequencies I/Q Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 57

Table 3-10 3dB cutoff frequencies Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . page 59

Table 3-11 Limiter Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 60

Table 3-12 Sub Address 00H: CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 61

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List of Tables

Table 3-13 Sub Address 00H: CONFIG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 62

Table 3-14 Default Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 73

Table 4-1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 74

Table 4-2 Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 74

Table 4-3 AC/DC Characteristics with TA = 25 °C, VVCC = 2.1 ... 5.5 V . . . . . page 75

Table 4-4 AC/DC Characteristics with TA = 25 °C, VVCC = 2.1 ... 5.5 V . . . . . page 77

Table 4-5 Digital Characteristics with TA = 25 °C, VVdd = 2.1 ... 5.5 V . . . . . . page 79

Table 4-6 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 83

Preliminary Specification 86 2003-02-18

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List of Figures

Figure 1-1 P-TSSOP-38-1 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . page 9

Figure 2-1 Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 10

Figure 2-2 Main Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 17

Figure 2-3 One I/Q Filter stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 19

Figure 2-4 Quadricorrelator Demodulation Characteristic . . . . . . . . . . . . . . . . . page 20

Figure 2-5 Data Filter architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 21

Figure 2-6 Timing and Data Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 22

Figure 2-7 Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 23

Figure 2-8 Sub Addresses Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 26

Figure 2-9 Wakeup Logic States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 30

Figure 2-10 Timing for Self Polling Mode (ADC & Data Detect in one shot mode) page 30

Figure 2-11 Timing for Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 31

Figure 2-12 Frequency and RSSI Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 31

Figure 2-13 Data Valid Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 32

Figure 2-14 Data Input/Output Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 32

Figure 2-15 1

Figure 2-16 1st start or reset in PD mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 33

Figure 2-17 Sequencer‘s capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 34

Figure 2-18 Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 34

Figure 3-1 RX/TX Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 37

Figure 3-2 RX-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 38

Figure 3-3 S11 measured. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 39

Figure 3-4 TX_Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 41

Figure 3-5 TX_Mode_simplified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 41

Figure 3-6 Equivalent power amplifier tank circuit . . . . . . . . . . . . . . . . . . . . . . . page 42

Figure 3-7 Output power Po (mW) and collector efficiency E vs. load resisto r RL. page 43

Figure 3-8 Power output and collector current vs. frequency. . . . . . . . . . . . . . . page 44

Figure 3-9 Sparam_measured_100M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 45

Figure 3-10 Transmit Spectrum 3GHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 46

Figure 3-11 Transmit Spectrum 300MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 46

Figure 3-12 Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 47

Figure 3-13 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 49

Figure 3-14 possible crystal oscillator frequencies. . . . . . . . . . . . . . . . . . . . . . . . page 50

Figure 3-15 FSK modulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 51

Figure 3-16 FSK receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 52

Figure 3-17 parasitics of the switching network . . . . . . . . . . . . . . . . . . . . . . . . . . page 53

Figure 3-18 I/Q Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 58

Figure 3-19 IQ Filter and frequency characteristics of the receive system. . . . . . page 58

Figure 3-20 Limiter and Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 59

Figure 3-21 Limiter frequency characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . page 60

Figure 3-22 Typ. RSSI Level (Eval Board) @3V . . . . . . . . . . . . . . . . . . . . . . . . . page 61

Figure 3-23 Slicer Level using RC Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 62

Figure 3-24 Slicer Level using Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . page 63

start or reset in active mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 33

Preliminary Specification 87 2003-02-18

TDA5251 F1

Version 1.0

Confidential

List of Figures

Figure 3-25 Peak Detector timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 63

Figure 3-26 Peak Detector as analog Buffer (v=1). . . . . . . . . . . . . . . . . . . . . . . . page 64

Figure 3-27 Peak detector - power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . page 65

Figure 3-28 Power down mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 65

Figure 3-29 Frequency Detection timing in continuous mode . . . . . . . . . . . . . . . page 66

Figure 3-30 Frequency Detection timing in Single Shot mode . . . . . . . . . . . . . . . page 66

Figure 3-31 Window Counter timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 67

Figure 3-32 Example for transmitted Data-structure. . . . . . . . . . . . . . . . . . . . . . . page 69

Figure 3-33 3 possible timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 70

Figure 3-34 BER Test Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 71

Figure 3-35 BER supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 72

Figure 4-1 I2C Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 78

Figure 4-2 3-wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 78

Figure 4-3 Schematic of the Evaluation Board. . . . . . . . . . . . . . . . . . . . . . . . . . page 81

Figure 4-4 Layout of the Evaluation Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 82

Preliminary Specification 88 2003-02-18

INFINEON TDA5251 F1 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Product Description

2 Functional Description

3Application

4 Reference