INFINEON TDA5250 D2 User Manual

Data Sheet, Version 1.7, 2007-02-26

TDA5250 D2

ASK/FSK 868MHz Wireless
Transceiver

Wireless Components

Never stop thinking.

Edition 2007-02-26

Published by Infineon Technologies AG,
Am Campeon 1-12,
D-85579 Neubiberg, Germany

© Infineon Technologies AG 3/7/07.

All Rights Reserved.

Attention please!

The information herein is given to describe certain components and shall not be considered as warranted
characteristics.

Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest
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list).

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be endangered.

Data Sheet, Version 1.7, 2007-02-26

TDA5250 D2

ASK/FSK 868MHz Wireless
Transceiver

Wireless Components

Never stop thinking.

Data Sheet

Revision History: 2007-02-26 TDA5250 D2

Previous Version: V1.6 as of July 2002

Page Subjects (major changes since last revision)

5 indication of the Ordering Code

5, 10 correction of the Package Name

79 indication of the ESD-integrity values

For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com

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Controller Area Network (CAN): License of Robert Bosch GmbH

ASK/FSK 868MHz Wireless Transceiver
TDA5250 D2

Product Info

General Description

The IC is a low power consumption single chip FSK/ASK
Transceiver for half duplex low datarate communication in the
868-870MHz band. The IC offers a very high level of integration
and needs only a few external components. It contains a highly
efficient power amplifier, a low noise amplifier (LNA) with AGC,
a double balanced mixer, a complex direct conversion stage, I/
Q limiters with RSSI generation, an FSK demodulator, a fully
integrated VCO and PLL synthesizer, a tuneable crystal
oscillator, an onboard data filter, a data comparator (slicer),
positive and negative peak detectors, a data rate detection
circuit and a 2/3-wire bus interface. Additionally there is a power
down feature to save battery power.

Version 1.7

Features

■ Low supply current (I

Is = 12mA typ. transmit mode)

■ Supply voltage range 2.1 - 5.5V

■ Power down mode with very low supply cur-

rent consumption

■ FSK and ASK modulation and demodula-

tion capability

■ Fully integrated VCO and PLL

synthesizer and loop filter on-chip with on
chip crystal oscillator tuning

2

■ I

C/3-wire µController Interface

= 9mA typ. receive,

s

Application

■ Low Bitrate Communication

Systems

■ Keyless Entry Systems

■ Remote Control Systems

■ On-chip low pass channel select filter and

data filter with tuneable bandwidth

■ Data slicer with self-adjusting threshold and

2 peak detectors

■ FSK sensitivity <-109dBm, ASK sensitivity

< –109dBm

■ Transmit power up to +13dBm

■ Datarates up to 64kBit/s Manchester

encoded

■ Self-polling logic with ultra fast data rate

detection

■ Alarm Systems

■ Telemetry Systems

■ Electronic Metering

■ Home Automation Systems

Type Ordering Code Package

TDA5250 D2 SP000012956 <Dev_Package1>

Data Sheet 5 2007-02-26

TDA5250 D2

Version 1.7

Table of Contents

page

1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.4 Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.4.1 Power Amplifier (PA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.4.2 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.4.3 Downconverter 1st Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.4.4 Downconverter 2nd I/Q Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.4.5 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4.6 I/Q Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4.7 I/Q Limiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4.8 FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.4.9 Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.4.10 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.4.11 Peak Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.4.12 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.4.13 Bandgap Reference Circuitry & Powerdown . . . . . . . . . . . . . . . 22

2.4.14 Timing and Data Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.4.15 Bus Interface and Register Definition . . . . . . . . . . . . . . . . . . . . 24

2.4.16 Wakeup Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.4.17 Data Valid Detection, Data Pin . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.4.18 Sequence Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.4.19 Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.4.20 RSSI and Supply Voltage Measurement . . . . . . . . . . . . . . . . . . 37

3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.1 LNA and PA Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.1.1 RX/TX Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switch in

RX-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switch in

Data Sheet 6 2007-02-26

TDA5250 D2

Version 1.7

Table of Contents

page

TX-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.1.4 Power-Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.2.1 Synthesizer Frequency setting . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.2.2 Transmit/Receive ASK/FSK Frequency Assignment . . . . . . . . . 53

3.2.3 Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.2.4 Calculation of the external capacitors . . . . . . . . . . . . . . . . . . . . 57

3.2.5 FSK-switch modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.2.6 Finetuning and FSK modulation relevant registers . . . . . . . . . . 58

3.2.7 Chip and System Tolerances . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.3 IQ-Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.4 Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.5 Limiter and RSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.6 Data Slicer - Slicing Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.6.1 RC Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.6.2 Peak Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.6.3 Peak Detector - Analog output signal . . . . . . . . . . . . . . . . . . . . 67

3.6.4 Peak Detector – Power Down Mode . . . . . . . . . . . . . . . . . . . . . 67

3.7 Data Valid Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.7.1 Frequency Window for Data Rate Detection . . . . . . . . . . . . . . . 70

3.7.2 RSSI threshold voltage - RF input power . . . . . . . . . . . . . . . . . 71

3.8 Calculation of ON_TIME and OFF_TIME . . . . . . . . . . . . . . . . . . . 71

3.9 Example for Self Polling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.10 Sensitivity Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.10.1 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.10.2 Sensitivity depending on the ambient Temperature . . . . . . . . . 75

3.10.3 BER performance depending on Supply Voltage . . . . . . . . . . . 76

3.10.4 Datarates and Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.10.5 Sensitivity at Frequency Offset . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.11 Default Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

4 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4.1.4 Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Data Sheet 7 2007-02-26

TDA5250 D2

Version 1.7

Table of Contents

page

4.2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

4.3 Test Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Data Sheet 8 2007-02-26

TDA5250 D2

Version 1.7

Product Description

1 Product Description

1.1 Overview

The IC is a low power consumption single chip FSK/ASK Transceiver for the frequency band 868­870 MHz. The IC combines a very high level of integration and minimum external part count. The
device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a PLL
synthesizer, a crystal oscillator with FSK modulator, a limiter with RSSI generator, an FSK
demodulator, a data filter, a data comparator (slicer), a positive and a negative data peak detector,
a highly efficient power amplifier and a complex digital timing and control unit with I
microcontroller interface. Additionally there is a power down feature to save battery power.

The transmit section uses direct ASK modulation by switching the power amplifier, and crystal
oscillator detuning for FSK modulation. The necessary detuning load capacitors are external. The
capacitors for fine tuning are integrated. The receive section is using a novel single-conversion/
direct-conversion scheme that is combining the advantages of both receive topologies. The IF is
contained on the chip, no RF channel filters are necessary as the channel filter is also on the chip.

The self-polling logic can be used to let the device operate autonomously as a master for a decoding
microcontroller.

2

C/3-wire

1.2 Features

■ Low supply current (I

voltage, 25°C)

■ Supply voltage range 2.1 V to 5.5 V

■ Operating temperature range -40°C to +85°C

■ Power down mode with very low supply current consumption

■ FSK and ASK modulation and demodulation capability without external circuitry changes, FM

demodulation capability

■ Fully integrated VCO and PLL synthesizer and loop filter on-chip with on-chip crystal oscillator

tuning, therefore no additional external components necessary

■ Differential receive signal path completely on-chip, therefore no external filters are necessary

■ On-chip low pass channel select and data filter with tuneable bandwith

■ Data slicer with self-adjusting threshold and 2 peak detectors

■ Self-polling logic with adjustable duty cycle and ultrafast data rate detection and timer mode

providing periodical interrupt

■ FSK and ASK sensitivity < -109 dBm

■ Adjustable LNA gain

■ Digital RSSI and Battery Voltage Readout

■ Provides Clock Out Pin for external microcontroller

■ Transmit power up to +13 dBm in 50Ω

■ Maximum datarate up to 64 kBaud Manchester encoded

2

■ I

C/3-wire microcontroller interface, working at max. 400kbit/s

■ meets the ETSI EN300 220 regulation and CEPT ERC 7003 recommendation

= 9 mA typ. receive, Is = 12mA typ. transmit mode, both at 3 V supply

s

load at 5V supply voltage

Data Sheet 9 2007-02-26

TDA5250 D2

Version 1.7

1.3 Application

■ Low Bitrate Communication Systems

■ Keyless Entry Systems

■ Remote Control Systems

■ Alarm Systems

■ Telemetry Systems

■ Electronic Metering

■ Home Automation Systems

1.4 Package Outlines

Product Description

PG-TSSOP-38.EPS

Figure 1-1 PG-TSSOP-38 package outlines

Data Sheet 10 2007-02-26

TDA5250 D2

Version 1.7

2 Functional Description

2.1 Pin Configuration

VCC

BUSMODE

LF

____

ASKFSK

__

RxTx

LNI

LNIx

GND1

GNDPA

PA

VCC1

PDN

PDP

SLC

VDD

BUSDATA

BUSCLK

VSS

XOUT

10

11

12

13

14

15

16

17

18

19

1

2

3

4

5

6

7

8

9

TDA5250

Functional Description

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

CI1

CI1x

CQ1

CQ1x

CI2

CI2x

CQ2

CQ2x

GND

RSSI

DATA
___
PWDDD

CLKDIV
______
RESET
___
EN

XGND

XSWA

XIN

XSWF

5250D1_pin_conf.wmf

Figure 2-1 Pin Configuration

Data Sheet 11 2007-02-26

TDA5250 D2

Version 1.7

2.2 Pin Definitions and Functions

Table 2-1 Pin Definition and Function

Pin No.

1

2

Symbol Equivalent I/O-Schematic Function

VCC Analog supply (antiparallel diodes

1 11

BUSMODE Bus mode selection (I²C/3 wire bus

350

2

Functional Description

between VCC, VCC1, VDD)

15

mode selection)

3

4

LF Loop filter and VCO control voltage

3

200

ASKFSK ASK/FSK- mode switch input

4

350

Data Sheet 12 2007-02-26

TDA5250 D2

Version 1.7

Functional Description

5 RXTX RX/TX-mode switch input/output

5

6

LNI RF input to differential Low Noise

350

TX

Amplifier (LNA))

5k 5k

6

PWDN

7

VCC see Pin 6 Analog supply (antiparallel diodes

1.1V
7

180180

PWDN

between VCC, VCC1, VDD

8

BUSMODE Bus mode selection (I²C/3 wire bus

mode selection)

9
10

11

30

8

18

9

GNDPA see Pin 8 Ground return for PA output stage
PA PA output stage

10

10

Ω

9

GndPA

VCC1 see Pin 1 Supply for LNA and PA

Data Sheet 13 2007-02-26

TDA5250 D2

Version 1.7

Functional Description

12 PDN Output of the negative peak

detector

13

14

PWDN

12

350

50k

3k

PDP Output of the positive peakdetector

50k

13

350

3k

PWDN

SLC Slicer level for the data slicer

1.2uA

14

350

50k

50k 50k

50k

50k

50k

15
16

17

1.2uA

50k 50k

VDD see Pin 1 Digital supply
BUSDATA Bus data in/output

15k

16

350

BUSCLK Bus clock input

17

350

18

VSS see Pin 8 Ground for digital section

Data Sheet 14 2007-02-26

TDA5250 D2

Version 1.7

Functional Description

19 XOUT Crystal oscillator output, can also

be used as external reference
frequency input.

4k

Vcc

20

Vcc-860mV

µ

A

150

XSWF FSK modulation switch

125fF ..... 4pF

250fF ..... 8pF

19

21

20

23

21

XIN see Pin 20

22 XSWA ASK modulation/FSK center

frequency switch

22

20

23

23

24

XGND

see Pin 22

Crystal oscillator ground return

EN 3-wire bus enable input

24

350

Data Sheet 15 2007-02-26

TDA5250 D2

Version 1.7

Functional Description

25 RESET Reset of the entire system (to

default values), active low

110k

350

10p

350

26

25

CLKDIV Clock output

26

27

28

29

PWDDD Power Down input (active high),

data detect output (active low)

30k

27

350

DATA TX Data input, RX data output (RX

powerdown: pin 28 @ GND)

28

350

RSSI RSSI output

29

350

37k

16p

S&H

Data Sheet 16 2007-02-26

TDA5250 D2

Version 1.7

Functional Description

30 GND see Pin 8 Analog ground
31

CQ2x Pin for external Capacitor

Q-channel, stage 2

Stage1:Vcc-630mV

Stage2: Vcc-560mV

32
33
34
35
36
37
38

31

CQ2 II Q-channel, stage 2
CI2x II I-channel, stage 2
CI2 II I-channel, stage 2
CQ1x II Q-channel, stage 1
CQ1 II Q-channel, stage 1
CI1x II I-channel, stage 1
CI1 II I-channel, stage 1

Data Sheet 17 2007-02-26

TDA5250 D2

Version 1.7

2.3 Functional Block Diagram

PDP

ASKFSK

13

4

100k

100k

-

ASK/FSK

100k

Det

+Peak

BUSMODE
__
EN

BUSCLK

BUSDATA

RXTX

Data (RX/TX)

CLKDIV

PWDDD

5

282627

LOGIC

17 24 2

16

SLC

14

WAKEUP

INTERFACE

CONTROLLER

SLICER

+

Data

FILTER

ASK

FSK

Functional Description

PDN

12

Det

-Peak

RESET

VCC

25

6-bit

SAR-ADC

Bandgap

Reference

RSSI

29

18

(digital)

(analog)

(LNA/PA)

FSK DATA

CLK

VssGnd1

30

Gnd

8

XSWA XGND

22 23

20

XSWF

QUADRI

CORRELATOR

CQ2x

31
32

CQ2

33

CI2x

34

CI2

CQ1x

35
36

CQ1
CI1x
CI1

(digital)

15

1

(analog)

(LNA/PA)

11

LIMITE R

I

Filter

Channel

MIXER

LP

= 289.433MHz

IF

f

6

LNI

= 868.3MHz

RF

f

ANT

37
38

VDD

VCC

VCC1

single ended to

LIMITE R

Filter

Q

Channel

MIXER

FILTER

LNA MIXER

high/low

7

LNIx

differential conv.

Gain

RSSI

0°

90°

f = 289.433MHz

ASK/FSK

TX/RX

ASK DATA

PHASE

:12/16

TX/RX

:4

10

PA

ANT

CRYSTAL Osc, FSKMod, Finetuning

DET.

LOOP

VCO

PA

21

= 18.0896MHz

Q

f

XOUT

19

Charge P.

39

FILTER

= 868.3MHz

TX

f

LF

= 1157.73MHz

RX

f

GndPA

XIN

TDA5250D1_blockdiagram_aktuell.wmf

Figure 2-2 Main Block Diagram

Data Sheet 18 2007-02-26

TDA5250 D2

Version 1.7

Functional Description

2.4 Functional Block Description

2.4.1 Power Amplifier (PA)

The power amplifier is operating in C-mode. It can be used in either high or low power mode. In
high-power mode the transmit power is approximately +13dBm into 50 Ohm at 5V and +4dBm at

2.1V supply voltage. In low power mode the transmit power is approximately -7dBm at 5V and ­32dBm at 2.1V supply voltage using the same matching network. The transmit power is controlled
by the D0-bit of the CONFIG register (subaddress 00H) as shown in the following Table 2-2. The
default output power mode is high power mode.

Table 2-2 Sub Address 00H: CONFIG

Bit

D0

In case of ASK modulation the power amplifier is turned fully on and off by the transmit baseband
data, i.e. 100% On-Off-Keying.

Function Description Default

PA_PWR 0= low TX Power, 1= high TX Power 1

2.4.2 Low Noise Amplifier (LNA)

The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB and symmetrical inputs.
It is possible to reduce the gain to 0 dB via logic.

Table 2-3 Sub Address 00H: CONFIG

Bit

D4

Function Description Default

LNA_GAIN 0= low Gain, 1= high Gain 1

2.4.3 Downconverter 1st Mixer

The Double Balanced 1st Mixer converts the input frequency (RF) in the range of 868-870 MHz
down to the intermediate frequency (IF) at approximately 290MHz. The local oscillator frequency is
generated by the PLL synthesizer that is fully implemented on-chip as described in Section 2.4.5.
This local oscillator operates at approximately 1157MHz in receive mode providing the above
mentioned IF frequency of 290MHz. The mixer is followed by a low pass filter with a corner
frequency of approximately 350MHz in order to prevent RF and LO signals from appearing in the
290MHz IF signal.

2.4.4 Downconverter 2nd I/Q Mixers

The Low pass filter is followed by 2 mixers (inphase I and quadrature Q) that convert the 289MHz
IF signal down to zero-IF. These two mixers are driven by a signal that is generated by dividing the
local oscillator signal by 4, thus equalling the IF frequency.

Data Sheet 19 2007-02-26

TDA5250 D2

Version 1.7

Functional Description

2.4.5 PLL Synthesizer

The Phase Locked Loop synthesizer consists of two VCOs (i.e. transmit and receive VCO), a
divider by 4, an asynchronous divider chain with selectable overall division ratio, a phase detector
with charge pump and a loop filter and is fully implemented on-chip. The VCOs are including spiral
inductors and varactor diodes. The center frequency of the transmit VCO is 868MHz, the center
frequency of the receive VCO is 1156MHz.

Generally in receive mode the relationship between local oscillator frequency f
frequency fRF and the IF frequency fIF and thus the frequency that is applied to the I/Q Mixers is
given in the following formula:

f

= 4/3 fRF = 4 f

osc

The VCO signal is applied to a divider by 4 which is producing approximately 289MHz signals in
quadrature. The overall division ratio of the divider chain following the divider by 4 is 12 in transmit
mode and 16 in receive mode as the nominal crystal oscillator frequency is 18.083MHz. The
division ratio is controlled by the RxTx

IF

pin (pin 5) and the D10 bit in the CONFIG register.

[2 – 1]

, the receive RF

osc

2.4.6 I/Q Filters

The I/Q IF to zero-IF mixers are followed by baseband 6th order low pass filters that are used for
RF-channel filtering.

OP

INTERNAL BUS

iq_filter.wmf

Figure 2-3 One I/Q Filter stage

The bandwidth of the filters is controlled by the values set in the filter-register. It can be adjusted
between 50 and 350kHz in 50kHz steps via the bits D1 to D3 of the LPF register (subaddress 03H).

2.4.7 I/Q Limiters

The I/Q Limiters are DC coupled multistage amplifiers with offset-compensating feedback circuit
and an overall gain of approximately 80dB each in the frequency range of 100Hz up to 350kHz.
Receive Signal Strength Indicator (RSSI) generators are included in both limiters which produce DC
voltages that are directly proportional to the input signal level in the respective channels. The
resulting I- and Q-channel RSSI-signals are summed to the nominal RSSI signal.

Data Sheet 20 2007-02-26

TDA5250 D2

Version 1.7

Functional Description

2.4.8 FSK Demodulator

The output differential signals of the I/Q limiters are fed to a quadrature correlator circuit that is used
to demodulate frequency shift keyed (FSK) signals. The demodulator gain is 2.4mV/kHz, the
maximum frequency deviation is ±300kHz as shown in Figure 2-4 below.

The demodulated signal is applied to the ASK/FSK mode switch which is connected to the input of
the data filter. The switch can be controlled by the ASKFSK
CONFIG register.

The modulation index m must be significantly larger than 2 and the deviation at least larger than
25kHz for correct demodulation of the signal.

1,6

1,5

1,4

1,3

1,2

pin (pin 4) and via the D11 bit in the

1,1

U /V

1

0,9

0,8

0,7

0,6

0,5

-350 -300 -250 -200 -150 -100 -50 0 50 100 150 200 250 300 350

f /kHz

Qaudricorrelator.wmf

Figure 2-4 Quadricorrelator Demodulation Characteristic

2.4.9 Data Filter

The 2-pole data filter has a Sallen-Key architecture and is implemented fully on-chip. The bandwidth
can be adjusted between approximately 5kHz and 102kHz via the bits D4 to D7 of the LPF register
as shown in Table 3-10.

Data Sheet 21 2007-02-26

TDA5250 D2

Version 1.7

ASK / FSK

OTA

INTER NAL B US

Figure 2-5 Data Filter architecture

Functional Description

data_filter.wmf

2.4.10 Data Slicer

The data slicer is a fast comparator with a bandwidth of 100kHz. The self-adjusting threshold is
generated by a RC-network (LPF) or by use of one or both peak detectors depending on the
baseband coding scheme as described in Section 3.6. This can be controlled by the D15 bit of the

CONFIG register as shown in the following table.

Table 2-4 Sub Address 00H: CONFIG

Bit

D15

Function Description Default

SLICER 0= Lowpass Filter, 1= Peak Detector 0

2.4.11 Peak Detectors

Two separate Peak Detectors are available. They are generating DC voltages in a fast-attack and
slow-release manner that are proportional to the positive and negative peak voltages appearing in
the data signal. These voltages may be used to generate a threshold voltage for non-Manchester
encoded signals, for example. The time-constant of the fast-attack/slow-release action is
determined by the RC network with external capacitor.

2.4.12 Crystal Oscillator

The reference oscillator is an NIC oscillator type (Negative Impedance Converter) with a crystal
operating in serial resonance. The nominal operating frequency of 18.083MHz and the frequencies
for FSK modulation can be adjusted via 3 external capacitors. Via microcontroller and bus interface
the chip-internal capacitors can be used for finetuning of the nominal and the FSK modulation
frequencies. This finetuning of the crystal oscillator allows to eliminate frequency errors due to
crystal or component tolerances.

2.4.13 Bandgap Reference Circuitry & Powerdown

A Bandgap Reference Circuit provides a temperature stable 1.2V reference voltage for the device.
A power down mode is available to switch off all subcircuits that are controlled by the bidirectional
Powerdown&DataDetect PwdDD
can either be activated by pin 27 or bit D14 in register 00h. In powerdown mode also pin 28 (DATA)
is affected (see Section 2.4.17).

pin (pin 27) as shown in the following table. Powerdown mode

Data Sheet 22 2007-02-26

TDA5250 D2

Version 1.7

Functional Description

Table 2-5 PwdDD Pin Operating States

PwdDD

Ground/VSS

Operating State

VDD

Powerdown Mode

Device On

2.4.14 Timing and Data Control Unit

The timing and data control unit contains a wake-up logic unit, an I2C/3-wire microcontroller
interface, a “data valid” detection unit and a set of configuration registers as shown in the
subsequent figure.

BusData

BusCLK

EN

BusMode

I2C / 3Wire

INTERFACE

18 MHz

XTAL-Osz.

INTERNAL BUS

REGISTERS

RF - BLOCK

RSSI

RX DATA

FSK DATA

ASK DATA

BLOCK ENABLE

ASK / FSK

RX / TX

6 Bit

ADC

DATA VALID

DETECTOR

AMPLITUDE

threshold TH3

FREQUENCY

window

TH1<T

GATE

ENABLE

<TH2

DATA

CONTROL

LOGIC

POWER ON

SEQUENCER

VALID

WAKEUP

LOGIC

32kHz

RC-Osz.

CLKDiv

PwdDD

Data

AskFsk

RxTx

Reset

logic.wmf

Figure 2-6 Timing and Data Control Unit

2

The I

C / 3-wire Bus Interface gives an external microcontroller full control over important system

parameters at any time.

It is possible to set the device in three different modes: Slave Mode, Self Polling Mode and Timer
Mode. This is done by a state machine which is implemented in the WAKEUP LOGIC unit. A
detailed description is given in Section 2.4.16.

Data Sheet 23 2007-02-26

TDA5250 D2

Version 1.7

Functional Description

The DATA VALID DETECTOR contains a frequency window counter and an RSSI threshold
comparator. The window counter uses the incoming data signal from the data slicer as the gating
signal and the crystal oscillator frequency as the timebase to determine the actual datarate. The
result is compared with the expected datarate.
The threshold comparator compares the actual RSSI level with the expected RSSI level.

If both conditions are true the PwdDD

pin is set to LOW in self polling mode as you can see in

Section 2.4.16. This signal can be used as an interrupt for an external µP. Because the PwdDD
pin is bidirectional and open drain driven by an internal pull-up resistor it is possible to apply an
external LOW thus enabling the device.

2.4.15 Bus Interface and Register Definition

The TDA5250 supports the I2C bus protocol (2 wire) and a 3-wire bus protocol. Operation is
selectable by the BusMode pin (pin 2) as shown in the following table. All bus pins (BusData,
BusCLK, EN
where the output is open drain driven by an internal 15k

Table 2-6 Bus Interface Format

Function

2

I

3-wire Mode

, BusMode) have a Schmitt-triggered input stage. The BusData pin is bidirectional

Ω pull up resistor.

BusMode EN BusCLK BusData

C Mode Low High= inactive,

High

Low= active

Clock input Data in/out

BusData

16

BusCLK

17

EN

24

BusMode

I2C / 3-wire

INTERFACE

FRONTEND

2

1 1 1 0 0 0 0 0

CHIP ADDRESS

INTERNAL BUS

i2c_3w_bus.wmf

Figure 2-7 Bus Interface

Note: The Interface is able to access the internal registers at any time, even in POWER DOWN

mode. There is no internal clock necessary for Interface operation.

I2C Bus Mode

In this mode the BusMode pin (pin 2) = LOW and the EN pin (pin 24) = LOW.

Data Sheet 24 2007-02-26

TDA5250 D2

Version 1.7

Data Transition:

Data transition on the pin BusData can only occur when BusCLK is LOW. BusData transitions while
BusCLK is HIGH will be interpreted as start or stop condition.

Start Condition (STA):

A start condition is defined by a HIGH to LOW transition of the BusData line while BusCLK is HIGH.
This start condition must precede any command and initiate a data transfer onto the bus.

Stop Condition (STO):

A stop condition is defined by a LOW to HIGH transition of the BusData line while BusCLK is HIGH.
This condition terminates the communication between the devices and forces the bus interface into
the initial state.

Acknowledge (ACK):

Indicates a successful data transfer. The transmitter will release the bus after sending 8 bit of data.
During the 9th clock cycle the receiver will set the SDA line to LOW level to indicate it has received
the 8 bits of data correctly.

Functional Description

Data Transfer Write Mode:

To start the communication, the bus master must initiate a start condition (STA), followed by the 8bit
chip address. The chip address for the TDA5250 is fixed as „1110000“ (MSB at first). The last bit
(LSB=A0) of the chip address byte defines the type of operation to be performed:

A0=0, a write operation is selected and A0=1 a read operation is selected.

After this comparison the TDA5250 will generate an ACK and awaits the desired sub address byte
(00H...0FH) and data bytes. At the end of the data transition the master has to generate the stop
condition (STO).

Data Transfer Read Mode:

To start the communication in the read mode, the bus master must initiate a start condition (STA),
followed by the 8 bit chip address (write: A0=0), followed by the sub address to read (80H, 81H),
followed by the chip address (read: A0=1). After that procedure the data of the selected register
(80H, 81H) is read out. During this time the data line has to be kept in HIGH state and the chip sends
out the data. At the end of data transition the master has to generate the stop condition (STO).

Bus Data Format in I2C Mode

Table 2-7 Chip address Organization

MSB

1 1 1 0 0 0 0 0 Chip Address Write
1 1 1 0 0 0 0 1 Chip Address Read

LSB Function

Data Sheet 25 2007-02-26

TDA5250 D2

Version 1.7

Functional Description

Table 2-8 I2C Bus Write Mode 8 Bit

MSB CHIP ADDRESS

(WRITE)

STA 1 1 1 0 0 0 0 0 ACK S7 S6 S5 S4 S3 S2 S1 S0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK STO

LSB MSB SUB ADDRESS (WRITE)

00H...08H, 0DH, 0EH, 0FH

LSB MSB DATA IN LSB

Table 2-9 I2C Bus Write Mode 16 Bit

MSB CHIP ADDRESS (WRITE) LSB MSB SUB ADDRESS (WRITE)

00H...08H, 0DH, 0EH, 0FH

STA 1 1 1 0 0 0 0 0 ACK S7 S6 S5 S4 S3 S2 S1 S0 ACK D15 ... D8 ACK D7 D6 ... D0 ACK STO

LSB MSB DATA IN LSB

Table 2-10 I2C Bus Read Mode

MSB CHIP ADDRESS (WRITE) LSB MSB SUB ADDRESS (READ)

80H, 81H

STA 1 1 1 0 0 0 0 0 ACK S7 S6 S5 S4 S3 S2 S1 S0 ACK STA 1 1 1 0 0 0 0 1 ACK

LSB MSB CHIP ADDRESS (READ) LSB

Table 2-10 I2C Bus Read Mode (continued)

MSB DATA OUT FROM SUB ADDRESS LSB

R7 R6 R5 R4 R3 R2 R1 R0 ACK* STO

* mandatory HIGH

3-wire Bus Mode

In this mode pin 2 (BusMode)= HIGH and Pin 16 (BusData) is in the data input/output pin. Pin 24
(EN

) is used to activate the bus interface to allow the transfer of data to / from the device. When pin

24 (EN

Data Transition:

Data transition on pin 16 (BusData) can only occur if the clock BusCLK is LOW. To perform a data
transfer the interface has to be enabled. This is done by setting the EN
is done via BusData, BusCLK and EN

Data Transfer Write Mode:

To start the communication the EN
data bytes have to follow. The subaddress (00H...0FH) determines which of the data bytes are
transmitted. At the end of data transition the EN

Data transfer Read Mode:

To start the communication in the read mode, the EN
address to read (80H, 81H). Afterwards the device is ready to read out data. At the end of data
transition EN

) is inactive (HIGH), data transfer is inhibited.

line to LOW. A serial transfer

. The bit stream needs no chip address.

line has to be set to LOW. The desired sub address byte and

must be HIGH.

line has to be set to LOW followed by the sub

must be HIGH.

Data Sheet 26 2007-02-26

TDA5250 D2

Version 1.7

Functional Description

Bus Data Format 3-wire Bus Mode

Table 2-11 3-wire Bus Write Mode

MSB

SUB ADDRESS (WRITE)

LSB MSB DATA IN X...0 (X=7 or 15) LSB

00H...08H, 0DH, 0EH,0FH

S7 S6 S5 S4 S3 S2 S1 S0 DX ... D5 D4 D3 D2 D1 D0

Table 2-12 3-wire Bus Read Mode

MSB

SUB ADDRESS (READ)

80H, 81H

LSB MSB DATA OUT FROM

SUB ADDRESS

S7 S6 S5 S4 S3 S2 S1 S0 R7 R6 R5 R4 R3 R2 R1 R0

Register Definition

Sub Addresses Overview

LSB

ADC

RSSI [8 Bit]

CONTROL

CONFIG [16 Bit]
STATUS [8 Bit]
CLK_DIV [8 Bit]
BLOCK_PD [16Bit]

ON_TIME [16 Bi t]
OFF_TIME [16 Bit]
COUNT_TH1 [16Bit]
COUNT_TH2 [16Bit]
RSSI_TH3 [8 Bit]

Figure 2-8 Sub Addresses Overview

I2C - SPI

INTERFACE

WAKEUP

FILTER

LPF [8 Bit]

XTAL

XTAL_TUNE [16Bit]
FSK [16Bit]
XTAL_CONFIG [8 Bit]

register_overview.wmf

Data Sheet 27 2007-02-26

TDA5250 D2

Version 1.7

Functional Description

Subaddress Organization

Table 2-13 Sub Addresses of Data Registers Write

MSB LSB HEX Function Description Bit Length

0

0 0 000 0 000h CONFIG General definition of status bits 16

0 0 000 0 101h FSK Values for FSK-shift 16

0

0

0 0 000 1 002h XTAL_TUNING Nominal frequency 16

0 0 000 1 103h LPF I/Q and data filter cutoff frequencies 8

0

0

0 0 001 0 004h ON_TIME ON time of wakeup counter 16

0 0 001 0 105h OFF_TIME OFF time of wakeup counter 16

0

0

0 0 001 1 006h COUNT_TH1 Lower threshold of window counter 16

0 0 001 1 107h COUNT_TH2 Higher threshold of window counter 16

0

0

0 0 010 0 008h RSSI_TH3 Threshold for RSSI signal 8

0 0 011 0 10Dh CLK_DIV Configuration and Ratio of clock divider 8

0

0

0 0 011 1 00Eh XTAL_CONFIG XTAL configuration 8

0 0 011 1 10Fh BLOCK_PD Building Blocks Power Down 16

0

Table 2-14 Sub Addresses of Data Registers Read

MSB LSB HEX Function Description Bit Length

1

0 0 000 0 080h STATUS Results of comparison: ADC & WINDOW 8

0 0 000 0 181h ADC ADC data out 8

1

Data Byte Specification

Table 2-15 Sub Address 00H: CONFIG

Bit Function Description Default

D15
D14
D13
D12

D11
D10

D9
D8
D7
D6
D5
D4
D3

D2
D1
D0

SLICER 0= Lowpass, 1= Peak Detector 0
ALL_PD 0= normal operation, 1= all Power down 0

TESTMODE 0= normal operation, 1=Testmode 0

CONTROL 0= RX/TX and ASK/FSK external controlled, 1= Register

controlled

ASK_NFSK 0= FSK, 1=ASK 0

RX_NTX 0= TX, 1=RX 1
CLK_EN 0= CLK off during power down, 1= always CLK on, ever in PD 0

RX_DATA_INV 0= no Data inversion, 1= Data inversion 0

D_OUT 0= Data out if valid, 1= always Data out 1

ADC_MODE 0= one shot, 1= continuous 1

F_COUNT_MODE 0= one shot, 1= continuous 1

LNA_GAIN 0= low gain, 1= high gain 1

EN_RX 0= disable receiver, 1= enable receiver (in self polling and

timer mode) *
MODE_2 0= slave mode, 1= timer mode 0
MODE_1 0= slave or timer mode, 1= self polling mode 0

PA_PWR 0= low TX Power, 1= high TX Power 1

0

1

Note D3: Function is only active in selfpolling and timer mode. When D3 is set to LOW the RX path
is not enabled if PwdDD

pin is set to LOW. A delayed setting of D3 results in a delayed power ON

of the RX building blocks.

Data Sheet 28 2007-02-26

TDA5250 D2

Version 1.7

Functional Description

Subaddress Organization

Table 2-16 Sub Addresses of Data Registers Write

MSB LSB HEX Function Description Bit Length

0

0 0 000 0 000h CONFIG General definition of status bits 16

0 0 000 0 101h FSK Values for FSK-shift 16

0

0

0 0 000 1 002h XTAL_TUNING Nominal frequency 16

0 0 000 1 103h LPF I/Q and data filter cutoff frequencies 8

0

0

0 0 001 0 004h ON_TIME ON time of wakeup counter 16

0 0 001 0 105h OFF_TIME OFF time of wakeup counter 16

0

0

0 0 001 1 006h COUNT_TH1 Lower threshold of window counter 16

0 0 001 1 107h COUNT_TH2 Higher threshold of window counter 16

0

0

0 0 010 0 008h RSSI_TH3 Threshold for RSSI signal 8

0 0 011 0 10Dh CLK_DIV Configuration and Ratio of clock divider 8

0

0

0 0 011 1 00Eh XTAL_CONFIG XTAL configuration 8

0 0 011 1 10Fh BLOCK_PD Building Blocks Power Down 16

0

Table 2-17 Sub Addresses of Data Registers Read

MSB LSB HEX Function Description Bit Length

0 0 000 0 0 80h STATUS Results of comparison: ADC & WINDOW 8

1

0 0 000 0 1 81h ADC ADC data out 8

1

Data Byte Specification

Table 2-18 Sub Address 00H: CONFIG

Bit Function Description Default

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Note D3: Function is only active in selfpolling and timer mode. When D3 is set to LOW the RX path
is not enabled if PwdDD
of the RX building blocks.

SLICER 0= Lowpass, 1= Peak Detector 0

ALL_PD 0= normal operation, 1= all Power down 0

TESTMODE 0= normal operation, 1=Testmode 0

CONTROL 0= RX/TX and ASK/FSK external controlled, 1= Register controlled 0

ASK_NFSK 0= FSK, 1=ASK 0

RX_NTX 0= TX, 1=RX 1

CLK_EN 0= CLK off during power down, 1= always CLK on, ever in PD 0

RX_DATA_INV 0= no Data inversion, 1= Data inversion 0

D_OUT 0= Data out if valid, 1= always Data out 1

ADC_MODE 0= one shot, 1= continuous 1

F_COUNT_MODE 0= one shot, 1= continuous 1

LNA_GAIN 0= low gain, 1= high gain 1

EN_RX 0= disable receiver, 1= enable receiver (in self polling and timer mode) * 1

MODE_2 0= slave mode, 1= timer mode 0

MODE_1 0= slave or timer mode, 1= self polling mode 0

PA_PWR 0= low TX Power, 1= high TX Power 1

pin is set to LOW. A delayed setting of D3 results in a delayed power ON

Data Sheet 29 2007-02-26