INFINEON IPB04N03LA, IPI04N03LA, IPP04N03LA User Manual

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IPB04N03LA

IPI04N03LA, IPP04N03LA

OptiMOS®2 Power-Transistor

Product Summary

Features

• Ideal for high-frequency dc/dc converters

• N-channel

• Logic level

• Excellent gate charge x R

• Very low on-resistance R

product (FOM)

DS(on)

DS(on)

• Superior thermal resistance

• 175 °C operating temperature

• dv /dt rated

Type Package Ordering Code Marking

IPB04N03LA P-TO263-3-2 Q67042-S4181 04N03LA

V

DS

R

DS(on),max

I

D

25 V

(SMD version) 3.9

80 A

P-TO220-3-1P-TO262-3-1P-TO263-3-2

mΩ

IPI04N03LA P-TO262-3-1 Q67042-S4183 04N03LA

IPP04N03LA P-TO220-3-1 Q67042-S4182 04N03LA

Maximum ratings, at T

Parameter Symbol Conditions Unit

Continuous drain current

Pulsed drain current

Avalanche energy, single pulse

Reverse diode dv /dt dv /dt

Gate source voltage

Power dissipation

Operating and storage temperature

=25 °C, unless otherwise specified

j

I

D

TC=25 °C

T

I

D,pulse

E

AS

TC=25 °C

ID=77 A, RGS=25 Ω

I
di /dt =200 A/µs,

T

3)

V

GS

P

tot

T

, T

j

TC=25 °C

stg

1)

=100 °C

C

2)

=80 A, VDS=20 V,

D

=175 °C

j,max

Value

80 A

80

385

290 mJ

6 kV/µs

±20 V

107 W

-55 ... 175 °C

IEC climatic category; DIN IEC 68-1 55/175/56

Rev. 1.3 page 1 2003-12-18

IPB04N03LA

IPI04N03LA, IPP04N03LA

Parameter Symbol Conditions Unit

Values

min. typ. max.

Thermal characteristics

Thermal resistance, junction - case

SMD version, device on PCB

Electrical characteristics, at T

=25 °C, unless otherwise specified

j

R

thJC

R

thJA

minimal footprint - - 62

6 cm

2

cooling area

4)

- - 1.4 K/W

--40

Static characteristics

Drain-source breakdown voltage

Gate threshold voltage

Zero gate voltage drain current

V

(BR)DSSVGS

V

GS(th)

I

DSS

=0 V, ID=1 mA

VDS=VGS, ID=60 µA

VDS=25 V, VGS=0 V,
T

=25 °C

j

25 - - V

1.2 1.6 2

- 0.1 1 µA

V

=25 V, VGS=0 V,

DS

T

=125 °C

j

Gate-source leakage current

Drain-source on-state resistance

I

R

GSS

DS(on)

VGS=20 V, VDS=0 V

VGS=4.5 V, ID=55 A

V

=4.5 V, ID=55 A,

GS

SMD version

V

=10 V, ID=55 A

GS

V

=10 V, ID=55 A,

GS

SMD version

Gate resistance

Transconductance

1)

Current is limited by bondwire; with an R

2)

See figure 3

3)

T

=150 °C and duty cycle D <0.25 for VGS<-5 V

j,max

4)

Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain

connection. PCB is vertical in still air.

R

G

g

thJC

fs

|VDS|>2|ID|R

I

=55 A

D

=1.4 K/W the chip is able to carry 125 A.

DS(on)max

,

- 10 100

- 10 100 nA

- 5.4 6.7

- 5.1 6.4

- 3.5 4.2

- 3.2 3.9

- 1.1 -

43 85 - S

mΩ

Ω

Rev. 1.3 page 2 2003-12-18

IPB04N03LA

y

g

IPI04N03LA, IPP04N03LA

Parameter Symbol Conditions Unit

Values

min. typ. max.

namic characteristics

D

Input capacitance

Output capacitance

Reverse transfer capacitance

Turn-on delay time

Rise time

Turn-off delay time

Fall time

Gate Char

e Characteristics

Gate to source charge

Gate charge at threshold

C

iss

V

=0 V, VDS=15 V,

C

oss

C

rss

t

d(on)

t

r

t

d(off)

t

f

5)

Q

gs

Q

g(th)

GS

f =1 MHz

V

=15 V, VGS=10 V,

DD

I

=20 A, RG=2.7 Ω

D

- 2915 3877 pF

- 1236 1643

- 175 263

-1319ns

- 4.5 7

-3857

- 5.4 8

-1013nC

- 4.6 6.2

Gate to drain charge

Switching charge

Gate charge total

Gate plateau voltage

Gate charge total, sync. FET

Output charge

Reverse Diode

Diode continous forward current

Diode pulse current

Diode forward voltage

Reverse recovery charge

Q

gd

Q

sw

Q

g

V

plateau

Q

g(sync)

Q

oss

I

S

I

S,pulse

V

SD

Q

rr

V

=15 V, ID=40 A,

DD

V

=0 to 5 V

GS

VDS=0.1 V,
V

=0 to 5 V

GS

VDD=15 V, VGS=0 V

TC=25 °C

VGS=0 V, IF=80 A,
T

=25 °C

j

VR=15 V, IF=IS,

di

/dt =400 A/µs

F

-711

-1217

-2432

- 3.3 - V

-2027nC

-2735

- - 80 A

- - 385

- 0.96 1.2 V

- - 15 nC

5)

See figure 16 for gate charge parameter definition

Rev. 1.3 page 3 2003-12-18