IDT RC5000 Technical data

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MULTI-ISSUE
64-BIT MICROPROCESSOR

In tegrat ed De v i ce Technology, I nc.

FEATURES

• Dual issue super-scalar execution core, executing at
high-frequency

- 250 MHz frequency

- Dual issue floating-point ALU operations with other
instruction classes

- Traditional 5-stage pipeline, minim izes load and
branch latencies

- Single cycle repeat rate for most floating point ALU
operations

• High level of performance for a variety of applications

- High-performance 64-bit integer unit achieves 330
dhrystone MIPS (dhrystone 2.1)

- Ultra high-performance floating-point accelerator,
directly implementin g single- and double-precision
operations achieves 500mflops

- Extremely large on-chip primary caches

- On-chip secondary cache controller

• Large, efficient on-chip caches

- 32KB Instruction Cache, 32KB Data Cache

- 2-set associative in each cache

- Virtually indexed and physically tagged to minimize
cache flushes

- Write-back and write-through selectable on a per
page basis

- Critical word first cache miss processing

- Supports back-to-back loads and stores in any com­bination at full pipeline rate

IDT RC5000

• High-performance memory system

- Large primary caches integrated on-chip

- Secondary cac he con trol interface on-chip

- High-frequency 64-bit bus interface runs up to
100MHz

- Aggregate bandwidth of on-chip caches, system
interface of 5GB/s

- High-performance write protocols for graphics and
data communications

• MIPS-IV 64-bit ISA for improved computation

- Compound floating-point operations for 3D graphics
and floating-point DSP

- Conditional move operations

• Compatible with a variety of operating systems

- Windows™ CE

- Numerous MIPS-compatible real-time operating sys­tems

• Uses input system clock, with processor pipeline
clock multiplied by a factor of 2-8

• Large on-chip TLB

• Active power management, including use of WAIT
operation

BLOCK DIAGRAM

Control

Floating Point Register File

Unpacker/Packer

Floating Point

MAdd,Add,Sub, Cvt

Div, SqRt

Data Set A
Store Buffer

Write Buffer

Read Buffer

Data Set B

DBus

SysAD

FPIBus

Floating-point Control

Phase Lock Loop

Data Tag A

DTLB Physical

Address Buffer

Instruction Tag A

ITLB Physical

Instruction Tag B

Tag

Coprocessor 0

System/Memory

Instruction TLB Virtual

AuxTag

Joint TLB

Control

PC Incrementer

Branch Adder

Program Counter

IVA

DV A

Instruction Set A

Instruction Select

Integer Instruction Register
FP Instruction Register

Instruction Set B

IntIBus

Load Aligner

Integer Register File

Integer Control

Integer/Address Adder

Data TLB Virtual

Shifter/Store Aligner

Logic Unit

ABus

Integer Multiply, Divide

The IDT logo is a registered trademark and ORION, R4600, R4640, R4650, R4700, R5000, RV5000, and RISController are trademarks of Integrated Device Technology, Inc. MIPS is a registered
trademark of MIPS Computer Systems, Inc.

COMMERCIAL TEMPERATURE RANGE

 1998 Integrated Device Technology, Inc. 1

June, 1998

IDT RC5000 COMMERCIAL TEMPERATURE RANGE

DESCRIPTION

The RC5000 serves many performance critical
embedded applications, such as high-end internet­working systems, color printers, and graphics terminals.

The RC5000 is optimized for high-performa nce appli ­cations, with special emphasis on s ystem bandwidth and
floating point operations, through integration of high­performance computa t io nal un its a nd a high-performance
memory hierarchy. For this class of applica tion, the result
is a relatively low-cost CPU capable of approximately 330
Dhrystone MIPS.

IDT’s objectives in offering the RC5000 include:

• Offering a high performance upgrade path to existing

embedded customers in the internetworking, office

automation and visualization markets.

• Providing a significant improvement in the floating-

point performance currently available in a moderately

priced MIPS CPU.

• Providing improvements in the memory hierarchy of

desktop systems by using large primary caches and

integrating a secondary cache controller.

• Enabling improvements in performance through the

use of the MIPS-IV ISA.

Instruction Issue Mechanism

The RC5000 recognizes two general classes of
instructions for multi-issue:

• Floating-point ALU

• All others

These instruction classes are pre-decoded by the
RC5000, as they are brough t on-chip. The pre-de coded
information is stored in the instruction cache.

Assuming that there are no pending resource
conflicts, the RC5000 can issue one instr uction per cl ass
per pipeline clock cycle. Note that this broad separation of
classes insures that there are no data dependencies to
restrict multi-issue.

However, long-latency resources in either the floating­point ALU (e.g. DIV or SQRT instru ctions) or instr uctions
in the integer unit (such as multiply) can restrict the issue
of instructions. Note that the R5000 does not perform out­of-order or speculative execution; instead, the pipeline
slips until the required resource becomes available.

There are no alignment restrictions on dual-issue
instruction pairs. The RC5000 fetches two instructions
from the cache per cycl e. Thus, for optimal performance,
compilers should atte mpt to align branch target s to allow
dual-issue on the first target cycle, since the instruction
cache only performs aligned fetches.

Integer Pipeline

The RC5000 is a limited dual-issue machine that
utilizes a traditional 5-stage integer pipeline. This basic
integer pipeline of the RC5000 is illustrated in Figure 1.

The integer instruction execution speed is tabulated
(in number of pipeline clocks) as follows:

Operation Latency Repeat

Load 2 1
Store 2 1
MULT/MUL TU 8 8
DMULT/DMULTU 12 12
DIV/DIVU 36 36
DDIV/DDIVU 68 68
Other Integer ALU 1 1
Branch 2 2
Jump 2 2

The RC5000’s short pipeline keeps the load and
branch latencies very low. The caches contain special
logic that allows any com bination of loads and stores to
execute in back-to-back cycles without requiring pipelin e
slips or stalls. (This p resumes, o f course, that th e opera­tion does not miss in the cache.)

Instruction Set Architecture

The RC5000 implements the MIPS-IV 64-bit ISA,
including CP1 and CP1X functional units (and their
instruction se t).

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IDT RC5000 COMMERCIAL TEMPERATURE RANGE

I

0

1I 2I 1R 2R 1A 2A 1D 2D 1W 2W

I

1

I

2

I

3

I

4

Key to Figure

1I-1R Instruction cache access
2I Instruction virtual to physical address translation
2A-2D Data cache access and load align
1D Data virtual to physical address translation
1D-2D Virtual to physical address translation
2R Register file read
2R Bypass calculation
2R Instruction decode
2R Branch address calculation
1A Issue or slip decision
1A-2A Integer add, logical, shift
1A Data virtual address calculation
2A Store align
1A Branch decision
2W Register file write

1I 2I 1R 2R 1A 2A 1D 2D 1W 2W

1I 2I 1R 2R 1A 2A 1D 2D 1W •••

1I 2I 1R 2R 1A 2A 1D •••

1I 2I 1R 2R 1A •••

one cycle

Figure 1. R5000 Integer Pipeline Stages

RC5000 Computational Units

The RC5000 contains the following computational units:

Integer ALU

. The RC5000 implements a full, single-cycle 64-bit ALU for all integer ALU functions other than
multiply and divide. Bypassing is used to support back-to-back ALU operations at the full pipeline rate, without requiring
stalls for data dependencies.

Integer Multiply/Divide Unit

. This unit is separated from the primary ALU, to allow these longer latency operations
to run in parallel with oth er operations. The pipe line stalls only if an attempt to ac cess the HI or LO r egisters is mad e
before the operation completes.

Floating-point ALU

. This unit is res ponsible for all CP1/CP1X ALU operations other t han DIV/SQRT. The unit is

pipelined to allow a single-cycle repeat rate for single-precision operations

Floating-point DIV/SQRT unit

. This unit is separated from the other floating-point ALU, so that these long latency

operations do not prevent the issue of other floating point operations.

In addition, the RC5000 implements separate logical units to implement loads, stores, and branches.

Electrical Specifications

Operating Frequency

The input clock operates in a frequency range of 33MHz to 100MHz. The pipeline frequency for the RC5000 is 2 to

8 times the input clock (up to the maximum for the speed grade of CPU).

THERMAL CONSIDERATIONS

The RC5000 utilizes special packaging techni ques, to improve the thermal propertie s of high-speed proces sors.
The RC5000 is packaged using cavity down packagin g in a 223-pin PGA package with integral th ermal slug, and a
272-pin BGA package. These packages effectively dissipate the power of the CPU, increasing device reliability.

3

IDT RC5000 COMMERCIAL TEMPERATURE RANGE

The RC5000 utilizes an all-aluminum package with
the die attached to a normal co pper lead frame moun ted
to the aluminum casing. D ue to the hea t-s prea di ng e ffect
of the aluminum, the package allows for an efficient
thermal transfer between the die and the case. The
aluminum offers less internal r esistance from one end of
the package to the other, reducing the temperature
gradient across the package and therefore presenting a
greater area for convection and conduction to the PCB for
a given temperature. Even nominal amounts of airflow will
dramatically reduce the junction temperature of the die,
resulting in cooler operatio n.

The RC5000 is guaranteed in a case temperature
range of 0° to +85° C. The type of package, speed
(power) of the device, and airflow conditions affect the
equivalent ambient temperature co nditions that will meet
this specification.

The equivalent allowable ambient temperature, T

A

can be calculated using the thermal resistance from case
to ambient (

) of the given package. The following

∅

CA

equation relates ambient and case temperatures:

A

= T

C

- P *

∅

CA

T

where P is the maximum power consumpt ion at hot
temperature, calculated by using the maximum I
fication for the device. Typical values for

∅

CC

at various

CA

speci-

airflows are shown in Table 1.

CA

∅

DATA SHEET REVISION HISTORY

Changes to version dated January 1996:

Pin Description section:

- Corrected pin list for Clock/Control, Initialization,
and Secondary Cache interfac es.

Advance Pin-Out section:

- Changed pins AA19 and AA21 from Vcc to Vss.

Changes to version dated March 1997:

- Upgraded data sheet status from “Preliminary” to
Final.

- Added section on thermal considerations

- Added section on absolute maximum ratings

Changes to version dated June 1997:

- Revised Power Consumption and System Interface
Parameters

,

Changes to version dated September 1997:

- Added user notation on Boot Mode Bits 20 and 33
for 200 MHz frequency

Changes to version dated June 1998:

- Added 250 MHz; changed naming conventions

Airflow (ft/min) 0 200 400 600 800 1000

PGA 167532.52
BGA 146432.52

Table 1. Thermal Resistance (∅CA) at Various Airflows

Note:

The RC5000 implements advanced power
management to substantially reduce the average power
dissipation of the device. This operation is described in

IDT79RV5000 RISC Microprocessor Reference

the

Manual.

4

IDT RC5000 COMMERCIAL TEMPERATURE RANGE

LOGIC SYMBOL

System Interface

Clock Interface

SysAD(63:0)
SysADC(7:0)
SysCmd(8:0)
SysCmdP
ValidIn*
ValidOut*
ExtRqst*
Release*
RdRdy*
WrRdy*

SysClock
VccP
VssP

Vcc
Vss

34

64

34

2

8
9

ScWord (1:0)
ScTCE*
ScTDE*
ScTOE*
ScCLR*
ScDCE*
ScDOE*
ScCWE*

16

ScLine (15:0)

Secondary Cache Interface

ScMATCH

ScVALID

RC5000

Logic

Symbol

6

Int (5:0)*
NMI*

BigEndian

ModeClock
ModeIN

VccOk
ColdReset*
Reset*

Interface

Interrupt

Interface

Initialization

Figure 1. RC5000 Logic Symbol

JTDI
JTDO
JTMS
JTCK

JTAG

Interface

5