Integrated Device Technology Inc IDT70T633S012BFI, IDT70T633S012DD, IDT70T633S012DDI, IDT70T633S015BC, IDT70T633S015BF Datasheet

...
©2003 Integrated Device Technology, Inc.
1
NOVEMBER 2003
DSC-5670/3
Functional Block Diagram
◆◆
◆◆
Full hardware support of semaphore signaling between ports on-chip
◆◆
◆◆
On-chip port arbitration logic
◆◆
◆◆
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus matching compatibility
◆◆
◆◆
Sleep Mode Inputs on both ports
◆◆
◆◆
Supports JTAG features compliant to IEEE 1149.1 in BGA-208 and BGA-256 packages
◆◆
◆◆
Single 2.5V (±100mV) power supply for core
◆◆
◆◆
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV) power supply for I/Os and control signals on each port
◆◆
◆◆
Available in a 256-ball Ball Grid Array, 144-pin Thin Quad Flatpack and 208-ball fine pitch Ball Grid Array
◆◆
◆◆
Industrial temperature range (–40°C to +85°C) is available for selected speeds
Features
◆◆
◆◆
True Dual-Port memory cells which allow simultaneous access of the same memory location
◆◆
◆◆
High-speed access
– Commercial: 8/10/12/15ns (max.) – Industrial: 10/12ns (max.)
◆◆
◆◆
RapidWrite Mode simplifies high-speed consecutive write cycles
◆◆
◆◆
Dual chip enables allow for depth expansion without external logic
◆◆
◆◆
IDT70T633/1 easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device
◆◆
◆◆
M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave
◆◆
◆◆
Busy and Interrupt Flags
HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE
PRELIMINARY
IDT70T633/1S
1. Address A18x is a NC for IDT70T631.
2. BUSY is an input as a Slave (M/S=V
IL) and an output when it is a Master (M/S=VIH).
3 BUSY and INT are non-tri-state totem-pole outputs (push-pull).
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the
sleep mode pins themselves (ZZx) are not affected during sleep mode.
CE
0R
R/
W
R
CE
1R
LB
R
UB
R
512/256K x 18
MEMORY
ARRAY
Address Decoder
A
18R
(1)
A
0R
Address Decoder
CE
0L
R/
W
L
CE
1L
LB
L
UB
L
Dout0-8_L Dout9-17_L
Dout0-8_R
Dout9-17_R
B E 0 L
B E 1 L
B E 1 R
B E 0 R
I/O0L-I/O
17L
I/O0R-I/O
17R
Din_L
ADDR_L
Din_R
ADDR_R
OE
R
OE
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/S
R/W
L
OE
L
R/W
R
OE
R
CE
0L
CE
1L
CE
0R
CE
1R
5670 drw 01
A
18L
(1)
A
0L
ZZ
CONTROL
LOGIC
ZZ
L
(4)
ZZ
R
(4)
JTAG
TCK
TRST
TMS
TDI
TDO
INT
L
(3)
SEM
L
BUSY
L
(2,3)
BUSY
R
(2,3)
SEM
R
INT
R
(3)
NOTES:
IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
2
Description
The IDT70T633/1 is a high-speed 512/256K x 18 Asynchronous Dual-Port Static RAM. The IDT70T633/1 is designed to be used as a stand-alone 9216/4608K-bit Dual-Port RAM or as a combination MAS­TER/SLAVE Dual-Port RAM for 36-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic.
This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.
The IDT70T651/9 has a RapidWrite Mode which allows the designer
to perform back-to-back write operations without pulsing the R/W input each cycle. This is especially significant at the 8 and 10ns cycle times of the IDT70T651/9, easing design considerations at these high perfor­mance levels.
The 70T633/1 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controlled by the OPT pins. The power supply for the core of the device (V
DD) remains at 2.5V.
3
IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Pin Configuration
(1,2,3)
NOTES:
1. All V
DD pins must be connected to 2.5V power supply.
2. All V
DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to V
SS (0V).
3. All V
SS pins must be connected to ground supply.
4. A
18X is a NC for IDT70T631.
5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
6. This package code is used to reference the package diagram.
70T633/1BC
BC-256
(5,6)
256-Pin BGA
Top View
E16
I/O
7R
D16
I/O
8R
C16
I/O
8L
B16
NC
A16
NC
A15
NC
B15
NC
C15
NC
D15
NC
E15
I/O
7L
E14
NC
D14
NC
D13
V
DD
C12
A
6L
C14
OPT
L
B14
NC
A14
A
0L
A12
A
5L
B12
A
4L
C11
BUSY
L
D12
V
DDQR
D11
V
DDQR
C10
SEM
L
B11
NC
A11
INT
L
D8
V
DDQR
C8
NC
A9
CE
1L
D9
C9
LB
L
B9
CE
0L
D10
V
DDQL
C7
A
7L
B8
UB
L
A8
NC
B13
A
1L
A13
A
2L
A10
OE
L
D7
V
DDQR
B7
A
9L
A7
A
8L
B6
A
12L
C6
A
10L
D6
V
DDQL
A5
A
14L
B5
A
15L
C5
A
13L
D5
V
DDQL
A4
B4
A
18L
(4)
C4
A
16L
D4
V
DD
A3
NC
B3
TDO
C3
V
SS
D3
NC
D2
I/O
9R
C2
I/O
9L
B2
NC
A2
TDI
A1
NC
B1
NC
C1
NC
D1
NC
E1
I/O
10R
E2
I/O
10L
E3
NCE4V
DDQL
F1
I/O
11L
F2
NCF3I/O
11R
F4
V
DDQL
G1
NC
G2
NC
G3
I/O
12L
G4
V
DDQR
H1
NCH2I/O
12R
H3
NCH4V
DDQR
J1
I/O
13L
J2
I/O
14R
J3
I/O
13R
J4
V
DDQL
K1
NC
K2
NC
K3
I/O
14L
K4
V
DDQL
L1
I/O
15L
L2
NC
L3
I/O
15R
L4
V
DDQR
M1
I/O
16R
M2
I/O
16L
M3
NCM4V
DDQR
N1
NCN2I/O
17R
N3
NC
N4
V
DD
P1
NCP2I/O
17L
P3
TMSP4A
16R
R1
NCR2NCR3TRSTR4A
18R
(4)
T1
NC
T2
TCKT3NC
T4
A
17R
P5
A
13R
R5
A
15R
P12
A
6R
P8
NCP9LB
R
R8
UB
R
T8
NC
P10
SEM
R
T11
INT
R
P11
BUSY
R
R12
A
4R
T12
A
5R
P13
A
3R
P7
A
7R
R13
A
1R
T13
A
2R
R6
A
12R
T5
A
14R
T14
A
0R
R14
OPT
R
P14
NC
P15
NC
R15
NC
T15NCT16
NC
R16
NC
P16
I/O
0L
N16
NC
N15
I/O
0R
N14
NC
M16
NC
M15
I/O
1L
M14
I/O
1R
L16
I/O
2R
L15
NC
L14
I/O
2L
K16
I/O
3L
K15
NC
K14
NC
J16
I/O
4L
J15
I/O
3R
J14
I/O
4R
H16
I/O
5R
H15
NC
H14
NC
G16
NC
G15
NC
G14
I/O
5L
F16
I/O
6L
F14
I/O
6R
F15
NC
R9
CE
0R
R11
M/S
T6
A
11R
T9
CE
1R
A6
A
11L
B10
R/W
L
C13
A
3L
P6
A
10R
R10
R/W
R
R7
A
9R
T10
OE
R
T7
A
8R
,
E5
V
DD
E6
V
DD
E7
V
SS
E8
V
SS
E9
V
SS
E10
V
SS
E11
V
DD
E12
V
DD
E13
V
DDQR
F5
V
DD
F6
NC
F8
V
SS
F9
V
SS
F10
V
SS
F12
V
DD
F13
V
DDQR
G5
V
SS
G6
V
SS
G7
V
SS
G8
V
SS
G9
V
SS
G10
V
SS
G11
V
SS
G12
V
SS
G13
V
DDQL
H5
V
SS
H6
V
SS
H7
V
SS
H8
V
SS
H9
V
SS
H10
V
SS
H11
V
SS
H12
V
SS
H13
V
DDQL
J5
ZZ
R
J6
V
SS
J7
V
SS
J8
V
SS
J9
V
SS
J10
V
SS
J11
V
SS
J12
ZZ
L
J13
V
DDQR
K5
V
SS
K6
V
SS
K7
V
SS
K8
V
SS
L5
V
DD
L6
NC
L7
V
SS
L8
V
SS
M5
V
DD
M6
V
DD
M7
V
SS
M8
V
SS
N5 N6
V
DDQR
N7
V
DDQL
N8
V
DDQL
K9
V
SS
K10
V
SS
K11
V
SS
K12
V
SS
L9
V
SS
L10
V
SS
L11
V
SS
L12
V
DD
M9
V
SS
M10
V
SS
M11
V
DD
M12
V
DD
N9
V
DDQR
N10
V
DDQR
N11
V
DDQL
N12
V
DDQL
K13
V
DDQR
L13
V
DDQL
M13
V
DDQL
N13
V
DD
F7
V
SS
F11
V
SS
5670 drw 02c
,
03/13/03
A
17L
V
DDQL
V
DDQR
IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
4
NOTES:
1. All V
DD pins must be connected to 2.5V power supply.
2. All V
DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to V
SS (0V).
3. All V
SS pins must be connected to ground.
4. A
18X is a NC for IDT70T631.
5. Package body is approximately 20mm x 20mm x 1.4mm.
6. This package code is used to reference the package diagram.
7. 8ns Commercial and 10ns Industrial speed grades are not available in the DD-144 package.
8. This text does not indicate orientation of the actual part-marking.
9. Due to the restricted number of pins, JTAG is not supported in the DD-144 package.
V
SS
V
DDQR
V
SS
I/O
9L
I/O
9R
I/O
10L
I/O
10R
I/O
11L
I/O
11R
V
DDQL
V
SS
I/O
12L
I/O
12R
V
DDQR
ZZ
R
V
DD
V
DD
V
SS
V
SS
V
DDQL
V
SS
I/O
13R
I/O
13L
I/O
14R
I/O
14L
V
DDQR
V
SS
I/O
15R
I/O
15L
I/O
16R
I/O
16L
I/O
17R
I/O
17L
V
SS
V
DDQL
NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
3
7
3
8
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
5
1
5
2
5
3
5
4
5
5
5
6
5
7
5
8
5
9
6
0
6
1
6
2
6
3
6
4
6
5
6
6
6
7
6
8
6
9
7
0
7
1
7
2
108 107 106 105 104 103 102 101 100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
1
4
4
1
4
3
1
4
2
1
4
1
1
4
0
1
3
9
1
3
8
1
3
7
1
3
6
1
3
5
1
3
4
1
3
3
1
3
2
1
3
1
1
3
0
1
2
9
1
2
8
1
2
7
1
2
6
1
2
5
1
2
4
1
2
3
1
2
2
1
2
1
1
2
0
1
1
9
1
1
8
1
1
7
1
1
6
1
1
5
1
1
4
1
1
3
1
1
2
1
1
1
1
1
0
1
0
9
V
D
D
N
C
N
C
A
1
8
R
(
4
)
A
1
7
R
A
1
6
R
A
1
5
R
A
1
4
R
A
1
3
R
A
1
2
R
A
1
1
R
A
1
0
R
A
9
R
A
8
R
A
7
R
U
B
R
L
B
R
C
E
1
R
C
E
0
R
V
D
D
V
S
S
S
E
M
R
O
E
R
R
/
W
R
B
U
S
Y
R
I
N
T
R
M
/
S
A
6
R
A
5
R
A
4
R
A
3
R
A
2
R
A
1
R
A
0
R
V
D
D
V
S
S
OPT
L
V
DDQR
V
SS
I/O
8L
I/O
8R
I/O
7L
I/O
7R
I/O
6L
I/O
6R
V
SS
V
DDQL
I/O
5L
I/O
5R
V
SS
V
DDQR
V
DD
V
DD
V
SS
V
SS
ZZ
L
V
DDQL
I/O
4R
I/O
4L
I/O
3R
I/O
3L
V
SS
V
DDQR
I/O
2R
I/O
2L
I/O
1R
I/O
1L
I/O
0R
I/O
0L
V
SS
V
DDQL
OPT
R
V
D
D
N
C
N
C
A
1
8
L
(
4
)
A
1
7
L
A
1
6
L
A
1
5
L
A
1
4
L
A
1
3
L
A
1
2
L
A
1
1
L
A
1
0
L
A
9
L
A
8
L
A
7
L
U
B
L
L
B
L
C
E
1
L
C
E
0
L
V
D
D
V
S
S
S
E
M
L
O
E
L
R
/
W
L
B
U
S
Y
L
I
N
T
L
N
C
A
6
L
A
5
L
A
4
L
A
3
L
A
2
L
A
1
L
A
0
L
V
D
D
V
S
S
70T633/1DD
DD-144
(5,6,7)
144-Pin TQFP
Top View
(8)
5670 drw 02a
,
03/13/03
Pin Configurations
(1,2,3,8)
(con't.)
5
IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3)
(con't.)
NOTES:
1. All V
DD pins must be connected to 2.5V power supply.
2. All V
DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to V
SS (0V).
3. All V
SS pins must be connected to ground.
4. A
18X is a NC for IDT70T631.
5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
1716
15
1412 13
10
9876543
21
11
A B C D E F G H J K L M N P R T U
I/O
9L
NC V
SS
A
4L
INT
L
SEM
L
NCA
8L
A
12L
A
16L
V
SS
NC
OPT
L
A
0L
NC V
SS
NC
NC
A
1L
A
5L
BUSY
L
V
SS
CE
0L
CE
1L
NC
A
9L
A
13L
A
17L
I/O
8L
V
DDQR
V
SS
V
DDQL
I/O
9R
V
DDQR
V
DD
A
2L
A
6
L
R/
W
L
V
SS
UB
L
A
10L
A
14L
A
18L
(4)
NC
I/O
8R
V
DD
I/O
11L
V
SS
I/O
10L
NC V
DD
A
3L
NC
OE
L
NC
I/O
11R
V
DDQR
I/O
10R
V
DDQL
NC
NC
V
SS
NC
V
SS
I/O
12L
NC
V
DD
NC V
DDQR
I/O
12R
V
DDQL
V
DD
VSSZZ
R
NC I/O
14LVDDQR
V
DDQL
NC
I/O
15RVSS
I/O
7R
V
DDQL
I/O
7L
A
15LA11LA7L
LB
L
I/O
6L
NC
V
SS
NC
V
SS
I/O
6R
NC
NC V
DDQL
I/O
5L
NC
V
DD
NC
V
SS
I/O
5R
ZZ
L
V
DDQR
I/O
3R
V
DDQL
I/O
4R
V
SS
I/O
4L
V
SS
I/O
3L
NC
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
I/O
1R
NC
V
SS
NC I/O
15L
A
16RA12RA8R
NC
V
DD
SEM
R
INT
R
V
DDQR
NC I/O
1L
NC
V
SS
NC I/O
17R
A
17R
A
13RA9R
NC
CE
0R
CE
1R
V
DD
V
SS
BUSY
R
V
SS
V
DD
V
SS
V
DDQL
I/O0RV
DDQR
NC I/O
17LVDDQL
NC
A
18R
(4)
A
14RA10R
UB
R
V
SS
NC
NCV
SS
I/O
2R
NC
V
SS
NC
V
DD
A
15R
A
11RA7R
LB
R
OE
R
M/
S
R/
W
R
V
DDQL
I/O
2L
OPTRNC I/O
0L
70T633/1BF
BF-208
(5,6)
208-Ball BGA
Top View
(7)
5670 drw 02b
I/O
13L
I/O
14RVSS
I/O
13R
V
SS
I/O
16R
I/O
16LVDDQR
NC
A B C D E F G H J K L M N P R T U
V
SS
NC
NC
V
DDQR
V
SS
V
DD
V
SS
NC
V
DD
V
DD
TDO
TDI
TCK
TMS
TRST
V
SS
03/12/03
IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
6
Pin Names
Left Port Right Port Names
CE
0L
,
CE
1L
CE
0R
,
CE
1R
Chip Enables (Input)
R/W
L
R/W
R
Read/ Write E nable (Input)
OE
L
OE
R
Outp ut Enable (Input)
A
0L
- A
18L
(1)
A0R - A
18R
(1)
Address (Input)
I/O
0L
- I/O
17L
I/O0R - I/O
17R
Data Inp ut/Outp ut
SEM
L
SEM
R
Semapho re Enable (Input)
INT
L
INT
R
Interrup t Flag (Outp ut)
BUSY
L
BUSY
R
Busy Flag (Output)
UB
L
UB
R
Upper Byte Select (Input)
LB
L
LB
R
Lower Byte Select (Input)
V
DDQL
V
DDQR
Power (I/O Bus ) (3.3V o r 2.5V )
(2)
(Input)
OPT
L
OPT
R
Optio n fo r sele c ting V
DDQX
(2,3 )
(Input)
ZZ
L
ZZ
R
Sleep Mode Pin
(4)
(Input)
M/S Master or Slave Select (Input)
(5)
V
DD
Power (2.5V)
(2)
(Input)
V
SS
Ground (0V) (Input)
TDI Test Data Input
TDO Test Data Outp ut
TCK Te st Logic Cloc k (10MHz) (Input)
TMS Test Mode Select (Input)
TRST
Reset (Initialize TAP Controlle r) (Input)
5670 tbl 01
NOTES:
1. Address A
18x is a NC for IDT70T631.
2. V
DD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on I/O
X.
3. OPT
X selects the operating voltage levels for the I/Os and controls on that port.
If OPT
X is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V
levels and V
DDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that
port's I/Os and controls will operate at 2.5V levels and V
DDQX must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V.
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are not affected during sleep mode. It is recommended that boundry scan not be operated during sleep mode.
5. BUSY is an input as a Slave (M/S=V
IL) and an output when it is a Master
(M/S=V
IH).
7
IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
NOTE:
1. "H" = V
IH, "L" = VIL, "X" = Don't Care.
Truth Table I—Read/Write and Enable Control
(1)
OE SEM CE
0
CE
1
UB LB
R/W ZZ
Upper Byte
I/O
9-17
Lower Byte
I/O
0-8
MODE
X H H X X X X L H ig h-Z Hig h-Z De s e lec te d–Po wer Do wn
X H X L X X X L High -Z High-Z De sele c te d –P o we r Do wn
X H L H H H X L High-Z High-Z Both Bytes Deselected
XHLHHLLLHigh-Z D
IN
Write to Lower Byte
XHLHLHLL D
IN
High-Z Write to Uppe r Byte
XHLHLLLL D
IN
D
IN
Write to B o th By te s
LHLHHLHLHigh-ZD
OUT
Read Lo we r By te
LHLHLHHL D
OUT
Hig h-Z Re ad Uppe r Byte
LHLHLLHLD
OUT
D
OUT
Read Bo th Byte s
H H L H L L X L High-Z High-Z Outputs Dis abled
XXXXXXXHHigh-ZHigh-ZHigh-Z Sleep Mode
5670 tbl 02
Truth Table II – Semaphore Read/Write Control
(1)
NOTES:
1. There are eight semaphore flags written to I/O
0 and read from all the I/Os (I/O0-I/O17). These eight semaphore flags are addressed by A0-A2.
2. CE = L occurs when CE
0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.
3. Each byte is controlled by the respective UB and LB. To read data UB and/or LB = V
IL.
Inputs
(1)
Outputs
Mode
CE
(2)
R/W
OE UB LB SEM
I/O
1-17
I/O
0
HHLLLLDATA
OUT
DATA
OUT
Read Data in Se maphore Flag
(3)
H
XXL L X DATAINWrite I/O0 into Semaphore Flag
LXXXX L
______ ______
Not Allowed
5670 tbl 03
IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
8
Recommended Operating Temperature and Supply Voltage
(1)
Recommended DC Operating Conditions with V
DDQ at 2.5V
Absolute Maximum Ratings
(1)
NOTES:
1. V
IL (min.) = -1.0V for pulse width less than tRC/2 or 5ns, whichever is less.
2. V
IH (max.) = V DDQ + 1.0V for pulse width less than tRC/2 or 5ns, whichever is
less.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to V
SS (0V), and VDDQX for that port must be
supplied as indicated above.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary; however, the voltage on any Input or I/O pin cannot exceed V
DDQ during power
supply ramp up.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
NOTE:
1. This is the parameter T
A. This is the "instant on" case temperature.
Grade
Ambi ent
Temperature GND V
DD
Commercial 0OC to +7 0OC0V2.5V + 100mV
Industrial -40
O
C to +85OC0V2.5V + 100mV
5670 tbl 0 4
Symbol Rating Commercial
& Industrial
Unit
V
TER M
(VDD)
V
DD
Te r m i n al V o lta g e
with Re spect to GND
-0.5 to 3.6 V
V
TER M
(2)
(V
DDQ
)
V
DDQ
Terminal Voltage
with Re spect to GND
-0.3 to V
DDQ
+ 0.3 V
V
TE RM
(2)
(INPUTS and I/O's)
Inp u t a nd I/O Termin al Voltage with Respect to GND
-0.3 to V
DDQ
+ 0.3 V
T
BIAS
(3)
Temperature Under Bi as
-55 to +125
o
C
T
STG
Storage Temperature
-65 to +150
o
C
T
JN
Junction Te mpe rature +150
o
C
I
OUT
(For V
DDQ =
3.3V) DC Output Current 50 mA
I
OUT
(For V
DDQ =
2.5V) DC Output Current 40 mA
5670 tbl 07
Symbol Parameter Min. Typ. Max. Unit
V
DD
Core Sup ply Vol tage 2.4 2.5 2.6 V
V
DDQ
I/O Supply Voltage
(3)
2.4 2.5 2. 6 V
V
SS
Ground 0 0 0 V
V
IH
Input Hig h Vo ll tag e (Address, Control & Data I/O Inputs)
(3)
1.7
____
V
DDQ
+ 100mV
(2)
V
V
IH
Input Hig h Vo ltag e
_
JTAG
1.7
____
V
DD
+ 100mV
(2)
V
V
IH
Input High Voltage ­ZZ, O PT, M/ S
V
DD
- 0.2V
____
V
DD
+ 100mV
(2)
V
V
IL
Input Low Voltage -0.3
(1)
____
0.7 V
V
IL
Input Lo w Vo ltag e ­ZZ, O PT, M/ S
-0.3
(1)
____
0.2 V
5670 tbl 05
NOTES:
1. These parameters are determined by device characterization, but are not production tested.
2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V.
3. C
OUT also references CI/O.
Capacitance
(1)
(TA = +25°C, F = 1.0MHZ) TQFP ONLY
Symbol Parameter Conditions
(2)
Max. Unit
C
IN
Input Capaci tance VIN = 3dV 8 pF
C
OUT
(3)
Output Capacitance V
OUT
= 3dV 10.5 pF
5670 tbl 08
Recommended DC Operating Conditions with V
DDQ at 3.3V
NOTES:
1. V
IL (min.) = -1.0V for pulse width less than tRC/2 or 5ns, whichever is less.
2. V
IH (max.) = V DDQ + 1.0V for pulse width less than tRC/2 or 5ns, whichever is
less.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to V
DD (2.5V), and VDDQX for that port must be
supplied as indicated above.
Symbol Parameter Min. Typ. Max. Unit
V
DD
Core Supply Voltage 2.4 2.5 2.6 V
V
DDQ
I/O Supply Voltage
(3)
3.15 3.3 3.45 V
V
SS
Ground 0 0 0 V
V
IH
Input Hig h Vol tag e (Address, Control &Data I/ O Inputs)
(3)
2.0
____
V
DDQ
+ 150mV
(2)
V
V
IH
Input Hig h Vol tag e
_
JTAG
1.7
____
V
DD
+ 100mV
(2)
V
V
IH
Input High Vo ltage ­ZZ, O PT, M / S
V
DD
- 0.2V
____
V
DD
+ 100mV
(2)
V
V
IL
Input Low Voltage -0. 3
(1)
____
0.8 V
V
IL
Input Low Voltage ­ZZ, O PT, M / S
-0.3
(1)
____
0.2 V
5670 tbl 06
9
IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range
(VDD = 2.5V ± 100mV)
Symbol Parameter Test Conditions
70T633/1S
UnitMin. Max.
|I
LI
| Input Le ak ag e Curre nt
(1)
V
DDQ
= Max., VIN = 0V to V
DDQ
___
10 µA
|I
LI
| JTAG & ZZ Input Le ak ag e Curre nt
(1,2)
V
DD =
Max., VIN = 0V to V
DD
___
+30 µA
|I
LO
| Outp ut Le akage Current
(1,3)
CE0 = VIH or CE1 = VIL, V
OUT
= 0V to V
DDQ
___
10 µA
V
OL
(3.3V) Output Low Vo ltage
(1)
IOL = +4mA, V
DDQ
= Min.
___
0.4 V
V
OH
(3.3V) Output High Voltage
(1)
IOH = -4mA, V
DDQ
= Min. 2.4
___
V
V
OL
(2.5V) Output Low Vo ltage
(1)
IOL = +2mA, V
DDQ
= Min.
___
0.4 V
V
OH
(2.5V) Output High Voltage
(1)
IOH = -2mA, V
DDQ
= Min. 2.0
___
V
5670 tb l 09
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range
(VDD = 2.5V ± 100mV)
NOTES:
1. At f = f
MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, using "AC TEST CONDITIONS".
2. f = 0 means no address or control lines change. Applies only to input at CMOS level standby.
3. V
DD = 2.5V, TA = 25°C for Typ. values, and are not production tested. IDD DC(f=0) = 100mA (Typ).
4. CE
X = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQX - 0.2V CE
X > VDDQX - 0.2V means CE0X > VDDQX - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
5. I
SB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and /or ZZR = VIH.
6. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.
70T63 3/1S 8
(6)
Com'l Only
70T633/1S10
Com 'l
& Ind
(6)
70T633/1S12
Com'l & Ind
70T6 33/1S 15
Com 'l On ly
Symbol Parameter Test Condition Version Typ.
(4)
Max. Typ.
(4)
Max. Typ.
(4)
Max. Typ.
(4)
Max. Unit
I
DD
Dynamic Op erating Current (Both Ports Active)
CE
L
and CER= VIL,
Outputs Di sab led f = f
MAX
(1)
COM'L S 350 475 300 405 300 355 225 305
mA
IND S
____ ____
300 445 300 395
____ ____
I
SB1
(6)
Standby Current (Both P orts - TTL Lev e l Inputs)
CE
L
= CER = V
IH
f = f
MAX
(1)
COM'L S 115 140 90 120 75 105 60 85
mA
IND S
____ ____
90 145 75 130
____ ____
I
SB2
(6)
Standby Current (One Port - TTL Lev e l Inputs)
CE
"A"
= VIL and CE
"B"
= V
IH
(5)
Active Po rt Outputs Disabled, f = f
MAX
(1)
COM'L S 240 315 200 265 180 230 150 200
mA
IND S
____ ____
200 290 180 255
____ ____
I
SB3
Full Standby Curre nt (Both P orts - CMOS Lev e l Inputs)
Both Ports CEL and
CE
R
> VDD - 0.2V, VIN > VDD - 0.2 V
or V
IN
< 0.2V, f = 0
(2)
COM'LS210210210210
mA
IND S
____ ____
220220
____ ____
I
SB4
(6)
Full Standby Curre nt (One Port - CMOS Lev e l Inputs)
CE
"A"
< 0.2V and CE
"B"
> VDD - 0.2V
(5)
VIN > VDD - 0.2V or VIN < 0.2V, Active Port, Outputs Disabled, f = f
MAX
(1)
COM'L S 240 315 200 265 180 230 150 200
mA
IND S
____ ____
200 290 180 255
____ ____
I
ZZ
Sleep Mode Current (Both P orts - TTL Lev e l Inputs)
ZZ
L = ZZR = VIH
f = f
MAX
(1)
COM'LS210210210210
mA
IND S
____ ____
220220
____ ____
5670 tbl 10
NOTES:
1. V
DDQ is selectable (3.3V/2.5V) via OPT pins. Refer to page 6 for details.
2. Applicable only for TMS, TDI and TRST inputs.
3. Outputs tested in tri-state mode.
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