IDT IDT709289L User Manual

HIGH-SPEED 64K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STA TIC RAM

Features

◆

True Dual-Ported memory cells which allow simultaneous access of the same memory location

◆

High-speed clock to data access

– Commercial: 7.5/9/12ns (max.)

◆

Low-power operation

– IDT709289L

Active: 1.2W (typ.) Standby: 2.5mW (typ.)

◆

Flow-Through or Pipelined output mode on either Port via the FT/PIPE pins

◆

Counter enable and reset features

◆

Dual chip enables allow for depth expansion without additional logic

Functional Block Diagram

R/

W

L

UB

L

IDT709289L

◆

Full synchronous operation on both ports

– 4ns setup to clock and 0ns hold on all control, data, and

address inputs

– Data input, address, and control registers – Fast 7.5ns clock to data out in the Pipelined output mode – Self-timed write allows fast cycle time – 12ns cycle time, 83MHz operation in Pipelined output mode

◆

Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility

◆

TTL- compatible, single 5V (±10%) power supply

◆

Industrial temperature range (–40°C to +85°C) is available for selected speeds

◆

Available in a 100-pin Thin Quad Flatpack (TQFP) package

R/

UB

W

R

CE

/PIPE

FT

I/O8L-I/O

I/O0L-I/O

0L 1L

LB

OE

15L

7L

L L

L

A

CLK

ADS

CNTEN

CNTRST

15L

0L

CE

1 0

0/1

1b 0b

0/1

L L

1a 0a

ba

Counter/

Address

Reg.

I/O

Control

I/O

Control

MEMORY

ARRAY

0a 1a

ab

Counter/

Address

Reg.

0b 1b

1 0

0/1

4842 drw 01

0R 1R

CE

LB

R

OE

/PIPE

FT

I/O8R-I/O

I/O0R-I/O

A

15R

A

0R

R

CLK

ADS

R

CNTEN CNTRST

R

15R

7R

R

JANUARY 2001

1

DSC-4842/3

IDT709289L

.

High-Speed 64K x 16 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Description

The IDT709289 is a high-speed 64K x 16 bit synchronous DualPort RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times.

With an input data register, the IDT709289 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE

0 and CE1, permits

the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 1.2W of power.

Pin Configurations

Index

A

10L

A A

11L

A

12L 13L

A A

14L 15L

A

NC NC

LB

UB

CE

CNTRST

Vcc

W

R/

OE

FT

/PIPE

GND

I/O

15L 14L

I/O I/O

13L 12L

I/O I/O

11L 10L

I/O

9L

L

L 0L 1L

L

8

7

A

1009998979695 949392 9190 8988 8786 8584 838281 8079 7877 76

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

(1,2,3)

L

5

6

A

L

N

L

E

L

2

4

3

A

T

L

N

0

1

C

A

D

S

K

N

D

L

A

C

G

IDT709289PF

PN100-1

(4)

100-Pin TQFP

Top View

(5)

R

N

R

E

R

S

T

K

D A

R

N

L

0

C

A

C

R

3

2

1

A

R

5

4

A

8

7

6

A

75 74

73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

9R

A

10R 11R

A A

12R 13R

A A

14R 15R

A NC NC

R

LB

R

UB

0R

CE

1R

CNTR ST

GND R/

R

W

R

OE FT

/PIPE

GND

15R

I/O I/O

14R

I/O

13R 12R

I/O I/O

11R 10R

I/O

R

c

L

8

9

c V

O

/

I

NOTES:

CC pins must be connected to power supply.

1. All V

2. All GND pins must be connected to ground.

3. Package body is approximately 14mm x 14mm x 1.4mm

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

L

5

4

6

7

O

/

I

L

2

3

O

/

I

L

I

D

0

N

O

/

I

G

6.42

2

R

D

1

0

N

O

/

G

I

R

2

O

/

I

5

3

4

O

/

I

R

c

6

7

8

V

O

/

I

O

/

I

c

R

9

O

/

I

4842 drw 02

C N

IDT709289L High-Speed 64K x 16 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Names

Left Port Right P ort Names

CE

0L, CE1L

W

L

R/

OE

L

0L

- A

A

I/O0L - I/O

L

CLK

UB

L

LB

L

ADS

L

CNTEN

CNTRST

FT

/PIPE

15L

L

CE

0R, CE1R

W

R

R/

OE

R

15R

A0R - A

15L

I/O0R - I/O CLK

UB

LB

ADS

CNTEN

L

CNTRST

FT

CC

V

R

/PIPE

15R

R

Chip Enab le s Read/Write Enable Outp ut Enab l e

Address Data Inp ut/Ou tput Clock Upper Byte Selec t Lo wer B y te Se le c t

Address Strobe Counter Enable Counte r Res e t Flow-Through/Pipeline Power

GND Ground

4842 tbl 01

Truth Table IRead/Write and Enable Control

OE

1

CLK

X X X X X X

L L L

CE

↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑

CE

0

UB LB

H X X X X High-Z High-Z Deselected—P owe r Do wn X L X X X High-Z High-Z Deselected—P o we r Down L H H H X High-Z Hig h-Z Bo th By te s Des e le c ted LHLHLDATAINHigh-Z Write to Upper Byte Only LHHLL High-Z DATAINWrite to Lower Byte Only LHLLLDATAINDATA LHLHHDATA LHHLHHigh-ZDATA LHLLHDATA

Upper Byte

W

R/

I/O

8-15

OUT

Lower B

I/O

Hig h-Z Re ad Upp e r By te Only

DATA

(1,2,3)

yte

0-7

IN

Write to Bo th Bytes

OUT

Read Lower By te Only

OUT

Read Both Bytes

H X L H L L X Hi g h-Z High-Z Outp uts Dis ab le d

NOTES:

1. "H" = V

IH, "L" = VIL, "X" = Don't Care.

2. ADS, CNTEN, CNTRST = X.

3. OE is an asynchronous input signal.

Mode

4842 tbl 02

6.42

3

IDT709289L High-Speed 64K x 16 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Truth Table IIAddress Counter Control

Address

XX0 An X An An Ap Ap

XApAp + 1↑H L

Addr Used CLK

↑ ↑ ↑

ADS CNTEN CNTRST

XX L D

(4)

L

XHD

HH H D

(5)

HD

(1,2,6)

(3)

I/O

(p)

I/O

(p+1)

Mode

Co u nte r Re s e t t o A d d r e ss 0

(0)

External Address Loaded into Counter

(n)

External Address Blocked—Counter Disabled (Ap reused ) Counte r Enab le —Inter na l Ad dre s s Gene ra ti o n

NOTES:

1. "H" = V

2. CE

IH, "L" = VIL, "X" = Don't Care.

0, LB, UB, and OE = VIL; CE1 and R/W = VIH.

3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.

4. ADS is independent of all other signals including CE

5. The address counter advances if CNTEN = V

6. While an external address is being loaded (ADS = V

0, CE1, UB and LB.

IL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.

IL), R/W = VIH is recommended to ensure data is not written arbitrarily.

4842 tbl 03

Recommended Operating Temperature and Supply Voltage

Grade Ambient

Temperature

Commercial 0OC to +7 0OC0V5.0V + 10%

O

Industrial -40

C to +8 5OC0V 5.0V + 10%

NOTES:

1. Industrial temperature: for other speeds, packages and powers contact your sales office.

2. This is the parameter T

A. This is the "instant on" case temperature.

Absolute Maximum Ratings

Symbol Rating Commercial

(2)

V

TERM

T

BIAS

T

STG

I

OUT

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

TERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns

2. V maximum, and is limited to

Terminal Voltage with Respect to GND

Temperature Und e r B i as

Storage Temperature

DC Ou tp ut Current

< 20mA for the period of VTERM > Vcc + 10%.

GND Vcc

(2)

(1)

& Industrial

-0.5 to +7.0 V

-55 to + 125

-65 to + 150

50 mA

(1)

4842 tbl 04

Unit

o

C

o

C

4842 tbl 06

Recommended DC Operating Conditions

Symbol Parameter Min. Typ. Max. Unit

CC

V

Sup p ly Vo ltag e 4.5 5.0 5. 5 V

GND Ground 0 0 0 V

IH

V

Inp u t Hi g h Vo l ta g e 2. 2

IL

V

Input Lo w Voltag e -0.5

____

(2)

____

NOTES:

TERM must not exceed Vcc + 10%.

1. V

IL > -1.5V for pulse width less than 10ns.

2. V

Capacitance

(1)

(TA = +25°C, f = 1.0MHz)

Symbol Parameter Conditions

C

Inpu t Cap ac itan c e VIN = 3dV 9 pF

IN

(3)

C

NOTES:

1. These parameters are determined by device characterization, but are not

2. 3dV references the interpolated capacitance when the input and output switch from

3. C

Outp ut Cap ac i tanc e V

OUT

production tested. 0V to 3V or from 3V to 0V.

OUT also references CI/O.

(2)

= 3dV 10 pF

OUT

(1)

6.0

V

0.8 V

4842 tbl 05

Max. Unit

4842 tbl 07

6.42

4

IDT709289L High-Speed 64K x 16 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating Temperature Supply Voltage Range

Symbol Parameter Test Conditions

|ILI| Input Leakage Current

LO

|I

| Output Leakage Current

OL

V V

Output Low Voltage IOL = +4mA

OH

Output High Voltag e IOH = -4mA 2.4

NOTE:

1. At Vcc

< 2.0V input leakages are undefined.

(1)

VCC = 5. 5V, VIN = 0V to V

CE

(VCC = 5.0V ± 10%)

0

= VIH or CE1 = VIL, V

CC

OUT

= 0V to V

709289L

___

CC

___

5µA 5µA

0.4 V

___

DC Electrical Characteristics Over the Operating

(3,6)

Temperature and Supply Voltage Range

Symbol Param eter Test Condition Version Typ.

I

Dynami c O pe rating

I

SB1

CC

Current (Bo th Ports Activ e )

Standby Current (Bo th Ports - TTL

and

CE

L

Outputs Disabled

f = f

MAX

=

CE

L

f = f

MAX

CE

= V

CE

R

(1)

= V

R

(1)

IL

IH

Le ve l Inp uts )

I

Standby Current

SB2

(One P ort - TTL Le ve l Inp uts )

I

Full Standby Current

SB3

(Bo th Ports CM OS L e v e l Inp u ts )

I

Full Standby Current

SB4

(One P ort CM OS L e v e l Inp u ts )

= VIL and

CE

"A"

(3)

= V

CE

"B"

Active Port Outputs

Disabled, f=f

IH

(1)

MAX

Both Ports CER and

> VCC - 0.2V

CE

L

V

> VCC - 0.2V o r

IN

V

< 0.2V , f = 0

IN

< 0.2V and

CE

"A"

> VCC - 0.2V

CE

"B"

(2)

VIN > VCC - 0.2V o r

< 0. 2V, A c tive P o rt

V

IN

(5)

Outputs Disabled , f = f

NOTES:

1. At f = f

MAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of

GND to 3V.

2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. I

X = VIL means CE0X = VIL and CE1X = VIH

5. CE

CC DC(f=0) = 150mA (Typ).

CEX = VIH means CE0X = VIH or CE1X = VIL CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V

X > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V

CE

"X" represents "L" for left port or "R" for right port.

6. Industrial temperature: for other speeds, packages and powers contact your sales office.

COM'L L 275 465 250 400 230 355 IND L COM'L L 95 150 80 135 70 110 IND L COM'L L 200 295 175 275 150 240 IND L

COM'LL0.530.530.53 IND L

COM'L L 190 290 170 270 140 225 IND L

(1)

MAX

(VCC = 5V ± 10%)

709289L7

Com'l Only

(4)

Max. Typ.

____ ____ ____ ____ ____ ____

709289L9

Com'l Only

(4)

Max. Typ.

709289L12

Com'l Only

(4)

Max.

UnitMin. Max.

V

4842 t bl 08

Unit

mA

4842 t bl 09

6.42

5

IDT IDT709289L User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual