Integrated Device Technology Inc. IDT54FCT623T, IDT54FCT623AT, IDT54FCT623CT, IDT74FCT623T, IDT74FCT623AT User Manual
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Integrated Device Technology, Inc.
LOW POWER 2V CMOS SRAM
1 MEG (64K x 16-BIT)
ADVANCE
INFORMATION
IDT71T016
FEATURES:
• 64K x 16 Organization
• Wide Operating Voltage Range: 1.8 to 2.7V
• Speed Grades: 150ns, 200ns
• Low Operating Power: 20mA (max)
• Low Standby Power: 5µA (max)
• Low-Voltage Data Retention: 1.5V (min)
• Available in a 44-pin TSOP package
FUNCTIONAL BLOCK DIAGRAM
OE
Output
Enable
Buffer
DESCRIPTION:
The IDT71T016 is a 1,048,576-bit very low-power Static
RAM organized as 64K x 16. It is fabricated using IDT’s highreliability CMOS technology. This state-of-the-art technology,
combined with innovative circuit design techniques, provides
a cost-effective solution for low-power memory needs. It uses
a 6-transistor memory cell.
Operation is from a single extended-range 2.5V supply.
This extended supply range makes the device ideally suited
for unregulated battery-powered applications. Fully static
asynchronous circuitry is used, requiring no clocks or refresh
for operation.
The IDT71T016 is packaged in a JEDEC standard 44-pin
TSOP Type II.
A0 - A15
CS
WE
BHE
BLE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Address
Buffers
Chip
Enable
Buffer
Write
Enable
Buffer
Byte
Enable
Buffers
Row / Column
Decoders
64K x 16
Memory
Array
I/O 15
8
Sense
16
Amps
and
Write
Drivers
8
High
Byte
I/O
Buffer
Low
Byte
I/O
Buffer
8
I/O 8
I/O 7
8
I/O 0
3777 drw 01
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES MAY 1997
1997 Integrated Device Technology, Inc. DSC-3777/1
1
IDT71T016
LOW POWER 2V CMOS STATIC RAM 1 MEG (64K x 16-BIT) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
DD
1
2
3
4
5
6
7
8
9
10
11
SS
12
13
14
15
16
17
18
19
20
21
22
SO44-2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O 15
I/O 14
I/O 13
I/O 12
SS
V
V
DD
I/O 11
I/O 10
I/O 9
I/O 8
NC
A8
A9
A10
A11
NC
3777 drw 02
CAPACITANCE
(TA = +25°C, f = 1.0MHz)
Symbol Parameter
IN Input Capacitance VIN = 1dV 6 pF
C
I/O I/O Capacitance VOUT = 1dV 7 pF
C
NOTE: 3777 tbl 06
1. This parameter is guaranteed by device characterization, but not prod-
uction tested.
(1)
Conditions Max. Unit
A4
A3
A2
A1
A0
CS
I/O 0
I/O 1
I/O 2
I/O 3
V
V
I/O 4
I/O 5
I/O 6
I/O 7
WE
A15
A14
A13
A12
NC
TSOP
TOP VIEW
PIN DESCRIPTIONS
A0 – A15 Address Inputs Input
TRUTH TABLE
CS
CS
OE
OE
(1)
WE
WE
BLE
BLE
BHE
BHE
CS
WE
OE
BHE
BLE
I/O
0 - I/O15 Data Input/Output I/O
V
DD Power Pwr
V
SS Ground Gnd
I/O0-I/O7 I/O8-I/O15 Function
Chip Select Input
Write Enable Input
Output Enable Input
High Byte Enable Input
Low Byte Enable Input
3777 tbl 01
H X X X X High-Z High-Z Deselected - Standby
L L H L H DATA
L L H H L High-Z DATA
L L H L L DATA
L X L L L DATA
L X L L H DATA
L X L H L High-Z DATA
OUT High-Z Low Byte Read
OUT High Byte Read
OUT DATAOUT Word Read
IN DATAIN Word Write
IN High-Z Low Byte Write
IN High Byte Write
L H H X X High-Z High-Z Outputs Disabled
L X X H H High-Z High-Z Outputs Disabled
NOTE: 3777 tbl 02
1.H = VIH, L = VIL, X = Don't care.
2
IDT71T016
LOW POWER 2V CMOS STATIC RAM 1 MEG (64K x 16-BIT) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Rating Com’l. and Ind'l. Unit
(2)
TERM
V
VTERM
Terminal Voltage with –0.5 to +3.6 V
Respect to V
(3)
Terminal Voltage with –0.5 to VDD + 0.5 V
Respect to V
SS
SS
TBIAS Temperature Under Bias –55 to +125 °C
STG Storage Temperature –55 to +125 °C
T
T Power Dissipation 1.0 W
P
OUT DC Output Current 20 mA
I
NOTES: 3777 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
DD terminals only.
3. Input, Output,and I/O terminals; 3.6V maximum.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade Temperature VSS VDD
Commercial 0°C to +70°C 0V 1.8V to 2.7V
Industrial -40°C to +85°C 0V 1.8V to 2.7V
3777 tbl 04
RECOMMENDED DC OPERATING
CONDITIONS
Symbol Parameter Min. Max. Unit
VDD Supply Voltage 1.8 2.7 V
VSS Ground 0 0 V
VIH Input High Voltage VDD x 0.7 VDD + 0.3
V
IL Input Low Voltage –0.3
NOTE: 3777 tbl 05
1. VIH (max.) = VDD + 1.5V for pulse width less than 5ns, once per cycle.
IL (min.) = –1.5V for pulse width less than 5ns, once per cycle.
1. V
(2)
VDD x 0.3 V
(1)
V
DC ELECTRICAL CHARACTERISTICS
VDD = 1.8V to 2.7V, Commercial and Industrial Temperature Ranges
Symbol Parameter Test Conditions Min. Max. Unit
LI| Input Leakage Current VDD = Max., VIN = VSS to VDD —1µA
|I
LO| Output Leakage Current VDD = Max.,
|I
OH Output High Voltage VDD = 1.8 to 2.7V IOH = –0.3mA VDD - 0.2 — V
V
DD = 2.3V IOH = –2.0mA 1.7 —
V
OL Output Low Voltage VDD = 1.8 to 2.7V IOL = 0.3mA — 0.2 V
V
DD = 2.3V IOL = 2mA — 0.4
V
DC ELECTRICAL CHARACTERISTICS
VDD = 1.8 to 2.7V, VLC = 0.2V, VHC = VDD–0.2V, Commercial and Industrial Temperature Ranges
Symbol Parameter Test Conditions Typ.
I
CC2 Dynamic Operating Current
CC Static Operating Current
I
ISB1 Standby Supply Current
NOTES: 3771 tbl 08
1. All values are maximum guaranteed values.
2. Input low and high voltage levels are 0.2V and V
3. f
MAX = 1/tRC (all address inputs are cycling at fMAX).
4. f = 0 means no address input lines are changing
5. Typical conditions are V
DD = 2.0V and specified temperature.
CS
= VLC, Outputs Open, -70 ns — 20 mA
V
DD = 2.7V, f = fMAX
CS
= VLC, Outputs Open, — 8 mA
WE
= V
HC, VDD = 2.7V, f = 0
CS
= VHC, Outputs Open, -40 to 85°C— 10µA
DD = 2.7V 0 to 70°C— 5
V
DD-0.2V respectively for all tests.
.
(1, 2)
CS
= VIH, VOUT = VSS to VDD —1µA
3777 tbl 07
(5)
(3)
(4)
-100 ns — 17
Max. Unit
40°C—2
25°C—1
3
IDT71T016
LOW POWER 2V CMOS STATIC RAM 1 MEG (64K x 16-BIT) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(VLC = 0.2V, VHC = VDD - 0.2V)
Symbol Parameter Test Condition Min. Typ.
DR VCC for Data Retention — 1.5 — — V
V
CCDR Data Retention Current — <1 5 µA
I
(3)
CDR
t
Chip Deselect to Data
CS
≥ VHC 0——ns
Retention Time
(3)
t
R
NOTES: 3777 tbl 09
1. TA = +25°C.
RC = Read Cycle Time.
2. t
3. This parameter is guaranteed by device characterization, but is not production tested.
Operation Recovery Time tRC
(2)
(1)
Max. Unit
——ns
LOW VDD DATA RETENTION WAVEFORM
DATA
RETENTION
MODE
VDD
1.8V 1.8V
V
CS
IH VIH
AC TEST CONDITIONS
Input Pulse Levels GND to VDD
Input Rise/Fall Times 3ns
Input Timing Reference Levels V
Output Reference Levels V
AC Test Load See Figure 1
DD x 0.5
DD x 0.5
3777 tbl 09
V
DR ≥ 1.5V
DR
V
AC TEST LOAD
DATA
OUT
50pF*
tRtCDR
3777 drw 05
VDD
3070Ω
3150Ω
3777 drw 04
*Including jig and scope capacitance.
Figure 1. AC Test Load
4
IDT71T016
LOW POWER 2V CMOS STATIC RAM 1 MEG (64K x 16-BIT) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (VDD = 1.8 to 2.7V, All Temperature Ranges)
71T016L150 71T016L200
Symbol Parameter Min. Max. Min. Max. Units
Read Cycle
RC Read Cycle Time 150 — 200 — ns
t
AA Address Access Time — 150 — 200 ns
t
ACS Chip Select Access Time — 150 — 200 ns
t
(1)
CLZ
t
(1)
CHZ
t
OE Output Enable Low to Output Valid — 75 — 100 ns
t
(1)
OLZ
t
(1)
OHZ
t
OH Output Hold from Address Change 15 — 15 — ns
t
BE Byte Enable Low to Output Valid — 75 — 100 ns
t
(1)
BLZ
t
(1)
BHZ
t
Write Cycle
WC Write Cycle Time 150 — 200 — ns
t
AW Address Valid to End of Write 120 — 160 — ns
t
CW Chip Select Low to End of Write 120 — 160 — ns
t
BW Byte Enable Low to End of Write 120 — 160 — ns
t
AS Address Set-up Time 0 — 0 — ns
t
WR Address Hold from End of Write 0 — 0 — ns
t
WP Write Pulse Width 100 — 140 — ns
t
DW Data Valid to End of Write 60 — 80 — ns
t
DH Data Hold Time 0 — 0 — ns
t
(1)
OW
t
(1)
WHZ
t
NOTE: 3777 tbl 10
1. This parameter is guaranteed by device characterization, but is not production tested.
Chip Select Low to Output in Low-Z 20 — 20 — ns
Chip Select High to Output in High-Z — 30 — 40 ns
Output Enable Low to Output in Low-Z 20 — 20 — ns
Output Enable High to Output in High-Z — 30 — 40 ns
Byte Enable Low to Output in Low-Z 20 — 20 — ns
Byte Enable High to Output in High-Z — 30 — 40 ns
Write Enable High to Output in Low-Z 5 — 5 — ns
Write Enable Low to Output in High-Z — 40 — 50 ns
TIMING WAVEFORM OF READ CYCLE NO. 1
ADDRESS
tAA
tOH tOH
DATAOUT
NOTES:
1.WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3.OE,
BHE
, and
BLE
PREVIOUS DATAOUT VALID
are LOW.
(1,2,3)
tRC
DATAOUT VALID
3777 drw 06
5
IDT71T016
LOW POWER 2V CMOS STATIC RAM 1 MEG (64K x 16-BIT) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2
ADDRESS
AA
t
OE
CS
(2)
tACS
(3)
tCLZ
BHE
,
BLE
tBE
(3)
tBLZ
DATA
OUT
NOTES:
1.WE is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of CS,
3. Transition is measured ±200mV from steady state.
BHE
tOLZ
(2)
(1)
tRC
tOE
(3)
, or
BLE
transition LOW; otherwise t
tOH
tOHZ
tCHZ
tBHZ
DATA VALID
OUT
AA is the limiting parameter.
(3)
(3)
(3)
3777 drw 07
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WEWE CONTROLLED TIMING)
tWC
ADDRESS
tAW
CS
(3)
tCW
tBW
BHE,BLE
tWP
WE
(6)
DATAOUT
tAS tWHZ
PREVIOUS DATA VALID DATA VALID
(4)
tDW
DATAIN
NOTES:
1.WE or (
2. A write occurs during the overlap of a LOW CS, LOW
3.OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, t
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS LOW or
6. Transition is measured ±200mV from steady state.
BHE
and
BLE
) or
CS
must be HIGH during all address transitions.
off and data to be placed on the bus for the required t
minimum write pulse is as short as the specified t
BHE
and
BLE
LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
WP.
BHE
DW. If
or
BLE
, and a LOW WE.
OE
is HIGH during a WE controlled write cycle, this requirement does not apply and the
WP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn
DATAIN VALID
tWR
tOW
tDH
(6)
(1,2,3,5)
tCHZ
tBHZ
(6)
(6)
3777 drw 08
6
IDT71T016
LOW POWER 2V CMOS STATIC RAM 1 MEG (64K x 16-BIT) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
t
ADDRESS
t
AW
CS
t
AS
t
BHE,BLE
t
WP
WE
DATA
OUT
DATA
IN
CSCS CONTROLLED TIMING)
WC
(3)
t
CW
BW
t
WR
t
DW
DATA
IN
VALID
t
DH
(1,2,5)
3777 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO. 3 (
tWC
ADDRESS
tAW
CS
(3)
tCW
tAS
BHE,BLE
tWP
WE
DATAOUT
DATAIN
BHE
BHE
tBW
,
BLE
CONTROLLED TIMING)
BLE
tWR
tDW
tDH
DATAIN VALID
(1,2,5)
3777 drw 10
NOTES:
1.WE or (
2. A write occurs during the overlap of a LOW CS, LOW
3.OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, t
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS LOW or
6. Transition is measured ±200mV from steady state.
BHE
and
BLE
) or
CS
must be HIGH during all address transitions.
off and data to be placed on the bus for the required t
minimum write pulse is as short as the specified t
BHE
and
BLE
LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
WP.
BHE
DW. If
or
BLE
, and a LOW WE.
OE
is HIGH during a WE controlled write cycle, this requirement does not apply and the
WP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn
7
IDT71T016
LOW POWER 2V CMOS STATIC RAM 1 MEG (64K x 16-BIT) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
71T016
Device
Type
L
Power
XXX
SpeedXXPackage
X
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PH 400-mil TSOP Type II (SO44-2)
150
200
Speed in nanoseconds
3777 drw 11
8
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