查询IDT49FCT3805供应商
FAST CMOS
BUFFER/CLOCK DRIVER
Integrated Device Technology, Inc.
FEATURES:
• 0.5 MICRON CMOS Technology
• Guaranteed low skew < 500ps (max.)
• Very low duty cycle distortion < 1.0ns (max.)
• Very low CMOS power levels
• TTL compatible inputs and outputs
• Inputs can be driven from 3.3V or 5V components
• Two independent output banks with 3-state control
• 1:5 fanout per bank
• ‘Heartbeat’ monitor output
• Available in DIP, SOIC, SSOP, QSOP, Cerpack and
LCC packages
• Military product compliant to MIL-STD-883, Class B
•V
CC = 3.3V ± 0.3V
FUNCTIONAL BLOCK DIAGRAM
OEA
INA
INB
5
OA1-OA5
5
OB1-OB5
IDT49FCT3805/A
DESCRIPTION:
The FCT3805/A is a 3.3 volt, non-inverting clock driver built
using advanced dual metal CMOS technology. The device
consists of two banks of drivers, each with a 1:5 fanout and its
own output enable control. The device has a "heartbeat"
monitor for diagnostics and PLL driving. The MON output is
identical to all other outputs and complies with the output
specifications in this document. The FCT3805/A offers low
capacitance inputs with hysteresis.
The FCT3805/A is designed for high speed clock distribution where signal quality and skew are critical. The FCT 3805
also allows single point-to-point transmission line driving in
applications such as address distribution, where one signal
must be distributed to multiple receivers with low skew and
high signal quality.
PIN CONFIGURATIONS
V
V
CCA
OA
OA
OA
GND
OA
OA
GND
1
2
1
2
3
3
4
A
Q
5
4
6
5
7
8
P20-1
D20-1
SO20-2
SO20-7
SO20-8
&
E20-1
20
19
18
17
16
15
14
13
CCB
OB
OB
OB
GND
OB
OB
MON
1
2
3
B
4
5
OE
B
B
IN
3102 drw 02
OB2
OB3
GNDB
OB4
OB5
3102 drw 03
OEB
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MON
3102 drw 01
OE
IN
INDEX
GNDA
GNDQ
A
A
OA3
OA4
OA5
9
10
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
OA2
OA1
VCCA
3 2 20 19
4
5
6
7
8
1
L20-2
910111213
INA
INB
OEA
LCC
TOP VIEW
VCCB
OEB
12
11
OB1
18
17
16
15
14
MON
MILITARY AND COMMERCIAL TEMPERATURE RANGES OCTOBER 1995
1996 Integrated Device Technology, Inc. 9.5 DSC-3102/4
1
IDT49FCT3805/A
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION FUNCTION TABLE
Pin Names Description
OEA,
OE
INA, IN
OAn, OB
B
B
n
3-State Output Enable Inputs (Active LOW)
Clock Inputs
Clock Outputs
MON Monitor Output
3102 tbl 01
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Rating Commercial Military Unit
VTERM
(2)
Terminal Voltage
–0.5 to +4.6 –0.5 to +4.6 V
with Respect to
GND
VTERM
(3)
Terminal Voltage
–0.5 to +7.0 –0.5 to +7.0 V
with Respect to
GND
(4)
VTERM
Terminal Voltage
with Respect to
GND
TA Operating
–0.5 to V
+ 0.5
CC
–0.5 to VCC
+ 0.5
0 to +70 –55 to +125 °C
V
Temperature
TBIAS Temperature
–55 to +125 –65 to +135 °C
Under Bias
TSTG Storage
–55 to +125 –65 to +150 °C
Temperature
IOUT DC Output
–60 to +60 –60 to +60 mA
Current
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Output and I/O terminals.
3102 lnk 03
OE
OE
NOTE: 3102 tbl 02
1. H = HIGH, L = LOW, Z = High Impedance
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter
CIN Input
COUT Output
NOTE:
1. This parameter is measured at characterization but not tested.
Inputs Outputs
A,
OE
B INA, INB OAn, OBn MON
OE
LLLL
LHHH
HLZL
HH ZH
(1)
Capacitance
Capacitance
(1)
Conditions Typ. Max. Unit
VIN = 0V 3.5 5.0 pF
VOUT = 0V 3.5 5.0 pF
3102 lnk 04
9.5 2
IDT49FCT3805/A
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 3.3V ± 0.3V; Military: TA = –55°C to +125°C, VCC = 3.3V ± 0.3V
Symbol Parameter Test Conditions
(1)
Min. Typ.
VIH Input HIGH Level (Input pins) Guaranteed Logic HIGH Level 2.0 — 5.5 V
Input HIGH Level (I/O pins) 2.0 — VCC+0.5
VIL Input LOW Level Guaranteed Logic LOW Level –0.5 — 0.8 V
(Input and I/O pins)
(6)
(6)
(6)
VCC = Max. VI = 5.5V — — ±1 µA
VI = VCC ——±1
(6)
VI = GND — — ±1
VI = GND — — ±1
II H Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
II L Input LOW Current (Input pins)
Input LOW Current (I/O pins)
IOZH High Impedance Output Current VCC = Max. VO = VCC ——±1µA
IOZL (3-State Output pins)
(6)
VO = GND — — ±1
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
IODH Output HIGH Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V
IODL Output LOW Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V
(3)
(3)
–36 –60 –110 mA
50 90 200 mA
VOH Output HIGH Voltage VCC = Min. IOH = –0.1mA VCC–0.2 — — V
VIN = VIH or VIL IOH = –6mA MIL.
I
OH = –8mA COM'L.
2.4
(5)
VOL Output LOW Voltage VCC = Min. IOL = 0.1mA — — 0.2 V
VIN = VIH or VIL IOL = 16mA — 0.2 0.4
IOL = 24mA — 0.3 0.50
(4)
(6)
VCC = 0V, VIN ≤ 4.5V — — ±1 µA
VCC = Max., VO = GND
(3)
–60 –135 –240 mA
IOFF Input Power Off Leakage
IOS Short Circuit Current
VH Input Hysteresis — — 150 — mV
ICCL Quiescent Power Supply Current VCC = Max., COM'L. — 0.1 10 µA
ICCH
VIN = GND or VCC MIL. — 0.1 100
ICCZ
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. V
OH = VCC -0.6V at rated current.
6. The test limit for this parameter is ±5µA at TA = –55°C.
(2)
Max. Unit
3.0 —
3102 lnk 05
9.5 3
IDT49FCT3805/A
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
ICCD Dynamic Power Supply Current
VCC = Max.
IN = VCC –0.6V
V
(4)
VCC = Max.
(3)
Outputs Open
A = OEB = GND
OE
(1)
IN = VCC
V
VIN = GND
Min. Typ.
— 2.0 30 µA
— 0.035 0.06 mA/
Per Output Toggling
50% Duty Cycle
IC Total Power Supply Current
(6)
VCC = Max.
Outputs Open
IN = VCC
V
VIN = GND
— 0.9 1.6 mA
fo = 25MHz
50% Duty Cycle
A = OEB =VCC
OE
IN = VCC –0.6V
V
IN = GND
V
— 0.9 1.6
Mon. Output Toggling
VCC = Max.
Outputs Open
IN = VCC
V
VIN = GND
— 20.0 33.0
fo = 50MHz
50% Duty Cycle
A = OEB = GND
OE
IN = VCC –0.6V
V
IN = GND
V
— 20.0 33.0
Eleven Outputs
Toggling
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
3. Per TTL driven input (V
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the I
CC = 3.3V, +25°C ambient.
IN = VCC -0.6V); all other inputs at VCC or GND.
C formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fONO)
CC = Quiescent Current (ICCL, ICCH and ICCZ)
I
CC = Power Supply Current for a TTL High Input (VIN = VCC -0.6V)
∆I
H = Duty Cycle for TTL Inputs High
D
T = Number of TTL Inputs at DH
N
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
O = Output Frequency
f
O = Number of Outputs at fO
N
All currents are in milliamps and all frequencies are in megahertz.
(2)
Max. Unit
MHz
(5)
(5)
3102 tbl 06
9.5 4
IDT49FCT3805/A
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(3,4)
FCT3805 FCT3805A
Com'l. Mil. Com'l. Mil.
Symbol Parameter Condition
tPLH
tPHL
Propagation Delay
IN
A
to OAn, INB to OBn
CL = 50pF
R
L = 500Ω
(1)
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
1.5 5.8 1.5 5.0 ns
(2)
Max.
tR Output Rise Time — 2.0 — — 2.0 — ns
tF Output Fall Time — 2.0 — — 2.0 — ns
tSK(o) Output skew: skew between outputs of all
— 0.7 — — 0.5 — ns
banks of same package (inputs tied together)
tSK(p) Pulse skew: skew between opposite
transitions of same output (|t
PHL–tPLH|)
tSK(t) Package skew: skew between outputs of
— 1.2 — — 1.0 — ns
— 1.5 — — 1.2 — ns
different packages at same power supply
voltage, temperature, package type and
speed grade
tPZL
tPZH
tPLZ
tPHZ
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. t
4. Propagation delay range indicated by Min. and Max. limit is due to V
Output Enable Time
OE
A to OAn, OEB to OBn
Output Disable Time
OE
A to OAn, OEB to OBn
PLH, tPHL, tSK(t) production tested. All other parameters guaranteed but not production tested.
limits do not imply skew.
CC, operating temperature and process parameters. These propagation delay
1.5 6.5 1.5 6.0 ns
1.5 5.5 1.5 5.0 ns
Unit
3102 tbl 07
9.5 5
IDT49FCT3805/A
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUIT FOR ALL OUTPUTS
V
CC
V
OUT
50pF
Pulse
Generator
VIN
D.U.T.
T
R
PACKAGE DELAY
INPUT
OUTPUT
tPLH tPHL
tR
tF
500Ω
500Ω
2.0V
0.8V
6.0V
GND
3102 drw 04
3V
1.5V
0V
VOH
1.5V
VOL
3102 drw 05
ENABLE AND DISABLE TIME
SWITCH POSITION
Test Switch
Disable LOW
Enable LOW
Disable HIGH
Enable HIGH
DEFINITIONS:
L = Load capacitance: includes jig and probe capacitance.
C
R
T = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
OUTPUT SKEW- t
INPUT
OUTPUT 1
OUTPUT 2
SK(o)
tPLH1
tSK(o)
tPLH2
tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
6.0V
GND
tPHL1
tSK(o)
tPHL2
3102 tbl 08
3V
1.5V
0V
V
OH
1.5V
OL
V
VOH
1.5V
V
OL
3102 drw 06
3V
1.5V
INPUT
tPLH
tPHL
0V
V
1.5V
OUTPUT
tSK(p) = |tPHL - tPLH|
V
3102 drw 07
ENABLE AND DISABLE TIMES
ENABLE DISABLE
CONTROL
INPUT
PLZt PZL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
3.5V
1.5V
t PZH
OUTPUT
NORMALLY
HIGH
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: f ≤ 1.0MHz; t
SWITCH
OPEN
1.5V
0V
t
0.3V
t
PHZ
0.3V
F ≤ 2.5ns; tR ≤ 2.5ns
OH
OL
3V
1.5V
0V
3.5V
V
OL
V
OH
0V
3102 drw 09
PACKAGE SKEW- t
INPUT
PACKAGE 1 OUTPUT
PACKAGE 2 OUTPUT
SK(t)PULSE SKEW- tSK(p)
SK(t)
tPHL1
tSK(t)
tPHL2
tPLH1
t
tPLH2
tSK(t) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
3V
1.5V
0V
OH
V
1.5V
V
OL
VOH
1.5V
OL
V
3102 drw 08
9.5 6
IDT49FCT3805/A
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT 49FCT
XXX
Device TypeXXPackage
X
Process/
Temperature
Range
Blank
B
P
D
E
L
SO
PY
Q
3805
3805A
Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
Shrink Small Outline IC
Quarter-size Small Outline IC
Non-Inverting 3.3V Buffer/Clock Driver
3102 drw 10
9.5 7
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