Integrated Device Technology Inc IDT49C466APQF, IDT49C466PQF Datasheet

Integrated Device Technology, Inc.

64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

IDT49C466

IDT49C466A

FEATURES:

• 64-bit wide Flow-thruEDC

• Separate System and Memory Data Input/Output Buses

• — Error Detect Time: 10ns — Error Correct Time: 15ns

• Corrects all single bit errors; Detects all double bit errors and some multiple bit errors

• Configurable 16-deep bus read/write FIFOs with flags

• Simultaneous check bit generation and correction of memory data

• Supports partial word writes on byte boundaries

• Low noise output

• Sophisticated error diagnostics and error logging

• Parity generation on system data bus

• 208-pin Plastic Quad Flatpack

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

ERR

MERR

READ BUFFER

16 WORDS BY

M U X

LATCH

OUT

M U X

ERROR

CORRECT

DESCRIPTION:

The IDT49C466/A 64-bit Flow-thruEDC is a high-speed error detection and correction unit that ensures data integrity in memory systems. The flow-thru architecture, with separate system and memory data buses, is ideally suited for pipelined memory systems.

Implementing a modified Hamming code, the IDT49C466/A corrects all single bit hard and soft errors, and detects all double bit errors. The read/write FIFOs can store up to sixteen words. FIFO full and empty flags indicate whether additional data can be written to or read from the EDC.

Check bit generation for partial word writes on byte boundaries is supported on the IDT49C466/A.

Diagnostic features include a check bit register, syndrome registers, a four bit error counter which logs up to 15 errors, and an error data register which stores the complete error data word. Parity can be generated and checked on the system bus by the IDT49C466/A.

DIAGNOSTIC

& STATUS

CHECK-BIT

COMPARATOR &

SYNDROME

GENERATOR &

ERROR

DETECTOR

REGISTERS

CHECK-BIT

GENERATOR

CHK-BIT

LATCH

CBI0-7

SD0-63

PARITY

P0-7

The IDT logo is a registered trademark and Flow-thruEDC is a trademark of Integrated Device Technology Inc.

WRITE BACK PATH

LATCH

WRITE

BUFFER

16 WORDS BY

PARITY

GENERATE &

PARITY CHECK

MD0-63

B Y

M U X

T E

M U X

CHECK-BIT

GENERATOR

LATCH

OUT

CHK-BIT

LATCH

CBSYN0-7

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1996 Integrated Device Technology, Inc. 11.7 DSC-2617/9

IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES

0-7

CBI

MUX

SYNDROME

Mode Bit 2

Latch

ChkBit

Check Bit

Generator

GENERATOR

MDILE

Chkbit

Diagnostic Registers

0-7

8-15

Err Count

Err Type

Syndrome

(on 1st error)

16-23

28-29

24-27

SYNCLK

ERR

Syndrome

(on every error)

30-37

MUX

from

CLEAR

MERR

Error data

MUX

Check Bit Injection Mode

mode

ERROR

CORRECT

DEMUX

Latch

0-63

BYTE MUX

Out

Latch

MUX

MOE

SDOLE

CBSEL

MUX

0-7

CBSYN

Latch

ChkBit

Check-bit

Generator

MUX

WBSEL

POWER

SUPPLY

GND



49C466/A 64-Bit Flow-ThruEDC

MD to SD Path

Diagnostic path

SD to MD Path

ERROR

DETECT

ERR

MERR

MCLK

MDOLE

RBEN

0-1

RBSEL

RBREN

Control

RBEF

RBFF

64 wide

Read Fifo

0-7

SOE

RBHF

SCLK

RWBD (Bit 4, Mode Reg)

Latch

MUX

Write Back Path

Out

0-63

Latch

0-15

SDILE

72 wide

control

Write Fifo

MODE

MEN

0-1

RWBD (Bit 4, Mode Reg)

MCLK

SCLK

WBEN

WBREN

GEN

PARITY

0-7

CHECK

PARITY

WBFF

WBEF

Mode Bit 5

PERR

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IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATION

MD58

MD59

MD60

GND

MD55

MD56

MD57

MD61

MD62

MD63

CBSYN7

CBSYN6

CBSYN5

CBSYN4

GND

CBSYN1

CBSYN3

CBSYN2

CBSYN0

GND

VCC

WBSEL

CBSEL

WBREN

WBEN

GND

SYNCLK

WBFF

WBEF

SD63

SD62

SD61

SD60

BE7

GND

SD59

SD58

SD57

SD56

SD55

SD54

SD53

SD52

BE6

SD51

SD50

SD49

SD48

VCC

SD47

GND MD54 MD53 MD52 MD51 MD50 MD49 MD48 MD47 MD46 MD45 MD44 MD43 MD42 MD41 MD40 MD39 MD38 MD37 MD36 MD35 MD34 MD33 MD32

SDOLE

MOE

MDILE

MD31

GND MD30 MD29 MD28 MD27 MD26 MD25 MD24 MD23 MD22 MD21 MD20

GND MD19 MD18 MD17 MD16 MD15 MD14 MD13 MD12 MD11 MD10

VCC

208

PQ208-2

157

156

105

104

GND SD46 SD45 SD44 BE5 P5 SD43 SD42 SD41 SD40 SD39 SD38 SD37 SD36 BE4 GND P4 SD35 SD34 SD33 SD32 PERR MCLK MDOLE RS1 MEN GND RS_0 SDILE SCLK SOE SD31 SD30 SD29 SD28 BE3 P3 SD27 SD26 SD25 SD24 SD23 SD22 SD21 SD20 BE2 P2 SD19 SD18 SD17 SD16 GND

GND

MD9

MD8

MD6

MD7

MD4

MD5

MD2

MD3

MD1

MD0

ERR

MERR

CBI7

CBI6

CBI4

CBI5

GND

CBI3

CBI2

CBI1

CBI0

RBEN

GND

RBSEL

RBREN

VCC

RBHF

RBFF

RBEF

SD0

SD1

SD2

SD3

GND

BE0

SD4

SD5

SD7

SD6

SD8

SD9

SD10

SD11

BE1

SD13

SD12

SD14

PQFP

Top View

11.7 3

GND

SD15

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PIN DESCRIPTION

Pin Name I/O Description

Data Buses

0-63 I/O System Data Bus: is a bidirectional 64-bit bus interfacing to the system or CPU. When System Output

Enable,

SOE

, is HIGH or Byte Enable, BE

SOE

, is LOW and Byte Enable, BE

0-63 I/O Memory Data Bus: is a bidirectional 64-bit bus interfacing to the memory. During a read cycle, (

HIGH) memory data is input for error detection and correction. Data is output on the Memory Data Bus, when

CBI

0-7 I Check Bit Inputs: interface to the check bit memory.

CBSYN

0-7 O Check Bit/Syndrome Output: When

CBSEL is HIGH and

MOE

is LOW.

MOE

is HIGH, the syndrome bits are output. The bus is tristated when

1 and CBSEL = 0.

0-7 I/O Parity for bytes 0 to 7: These pins are parity inputs when the corresponding Byte Enable (BE) is LOW

SOE

is HIGH, and are used to generate the parity error signal (

the corresponding Byte Enable (BE) is HIGH and

Control Inputs

SOE

0-7 I Byte Enable: is used along with

I System Output Enable: enables system data bus output drivers if the corresponding Byte Enable

(BE

0-7) is HIGH.

example, if BE

1 is HIGH, the System data outputs for byte 1 (SD8-15) are enabled. The BE0-7 pins also

control the byte mux. If a particular BE is HIGH during a memory read cycle, that byte is fed back to the memory data bus. This is used during partial word write operations and writing corrected data back to memory.

MOE

I Memory Output Enable: when LOW, enables the output buffers of the memory data bus (MD) and

CBSYN bus. It also controls the CBSYN mux. When LOW, checkbits are selected, when HIGH, syndrome is selected.

MDILE I Memory Data Input Latch Enable: on the HIGH-to-LOW transition, latches MD and CBI in MD input

latch and MD check bit latch respectively. The latches are transparent when MDILE is HIGH.

MDOLE

SDOLE

I Memory Data Output Latch Enable: latches data in the MD output latch on the LOW-to-HIGH

transition of

MDOLE

. When

MDOLE

I System Data Output Latch Enable: latches data in the SD output latch and the SD checkbit latch

on the LOW-to-HIGH transition of

SDILE I System Data Input Latch Enable: latches SD in the SD input latch on the HIGH-to-LOW transition.

When SDILE is HIGH, the SD input latch is transparent.

WBSEL I Write FIFO Select: when HIGH, the write FIFO is selected. When WBSEL is LOW, the SD input latch

is selected.

WBEN WBREN

I Write FIFO Enable: when

LOW,

I Write FIFO Read Enable: when

allows SD data to be written to the write FIFO on the SCLK rising edge.

edge.

0-1 I Reset and Select pins (read and write FIFO FIFOs)

1 RS0 Function

0 0 Reset 16-deep FIFO or first 8-deep FIFO 0 1 Reset second 8-deep FIFO 1 0 Select 16-deep FIFO or first 8-deep FIFO 1 1 Select second 8-deep FIFO

0-7, is LOW, data can be input. When System Output Enable,

0-7, is HIGH, the SD bus output drivers are enabled.

MOE

is LOW the generated check bits are output. When

PERR

). These pins are outputs when

SOE

is LOW.

SOE

, to enable the System Data outputs for a particular byte. For

is LOW, the MD output latch is transparent.

SDOLE

. The latch is transparent when

LOW,

allows data to be read from the the write FIFO on MCLK rising

SDOLE

is LOW.

MOE

2617 tbl 01

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PIN DESCRIPTION (Continued)

Pin Name I/O Description

RBSEL I Read FIFO Select: when HIGH, read FIFO is selected (data goes through read FIFO, not MD output

latch). When LOW, the MD output latch is selected.

RBEN

RBREN

CBSEL

MEN

Clock Inputs

MCLK I Memory Clock: on the LOW-to-HIGH transition of MCLK, memory data is written to the read FIFO

SCLK I System Clock: on the LOW-to-HIGH transition of the SCLK, data is read from the read FIFO when

SYNCLK I Syndrome Clock: Used to load diagnostic registers. When an error occurs, Error Counter is

Status Outputs

WBEF

WBFF RBEF

RBHF

RBFF ERR MERR

PERR

Power Supply

CC P Power Supply Voltage.

GND P Ground.

I Read FIFO Enable: when LOW, allows data to be written into the read FIFO on the LOW-to-HIGH

transition of the memory clock.

I Read FIFO Enable: when LOW, allows data to be read from the read FIFO on the LOW-to-HIGH

transition of SCLK

I Checkbit Syndrome Output Enable: Controls the CBSYN output buffer.When HIGH, the buffer is

enabled. When CBSEL is LOW,

I Mode Enable Input: when LOW, SD

MOE

controls the buffer.

0-15 is loaded into the EDC mode register on the LOW-to-HIGH

transition of the SCLK. This pin must be held LOW for the entire SCLK HIGH period, as shown in Figure

when

RBEN

is LOW. Data is read from the write FIFO when

WBREN

is LOW, on the LOW-to-HIGH

transition of MCLK.

RBREN

the LOW-to-HIGH transition of SCLK. Clocks data into mode register when

is LOW. Data on the system data bus is written into the write FIFO when

MEN

WBEN

is LOW on

is LOW.

incremented on the rising SYNCLK edge (up to 15 errors). On the first error after a diagnostic reset, SYNCLK rising edge clocks data into Check Bit, Syndrome, Error Type and Error Data registers. One of the syndrome registers has new data clocked in on every SYNCLK rising edge.

O Write FIFO Empty Flag: when LOW, indicates that the write FIFO is empty. After a reset, the

WBEF

goes LOW. O Write FIFO Full Flag: when LOW, indicates that the write FIFO is full. After a reset, O Read FIFO Empty Flag: when LOW, indicates that the read FIFO is empty. After a reset, the

WBFF

goes HIGH.

RBEF

goes LOW. O Read FIFO Half-full Flag: when LOW, indicates that there are eight or more data words (in the 16-

deep configuration) or four or more data words (in the dual 8-deep configuration) in the read FIFO. The

flag will return HIGH when less than eight (or four) data words are in the FIFO. O Read FIFO Full Flag: when LOW, indicates that the read FIFO is full. After a reset, O Error Flag: when O Multiple Error Flag: when

ERR

is LOW, a data error is indicated. The

MERR

is LOW, a multiple data error is indicated. The

ERR

is not latched internally.

RBFF

MERR

goes HIGH.

is not latched

internally. O Parity Error Flag: when LOW, indicates a parity error on the system data bus input.

2617 tbl 02

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IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES

DETAILED DESCRIPTION —

64-BIT MODIFIED HAMMING CODE - CHECKBIT ENCODING CHART

Generated Participating Data Bits

Checkbits Parity 0123456789101112131415

CB0 Even (XOR) X X X X X X X X CB1 Even (XOR) X X X XXXXX CB2 Odd (XNOR) X X X X X X X X CB3 Odd (XNOR) X X X X X X X X CB4 Even (XOR) X X XXXX XX CB5 Even (XOR) XXXXXXXX CB6 Even (XOR) XXXXXXXX CB7 Even (XOR) XXXXXXXX

Generated Participating Data Bits

Checkbits Parity 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Generated Participating Data Bits

Checkbits Parity 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Generated Participating Data Bits

Checkbits Parity 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

NOTES: 2617 tbl 06

1. The table indicates the data bits participating in the checkbit generation. For example, checkbit CB0 is the Exclusive-OR function of the 64 data input bits marked with an X.

2. The checkbit is generated as either an XOR or an XNOR of the 64 data bits noted by an “X” in the table.

(1, 2)

2617 tbl 03

2617 tbl 04

2617 tbl 05

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IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES

DETAILED DESCRIPTION —

64-BIT SYNDROME DECODE TO BIT-IN-ERROR

HEX 0123456789ABCDEF

S7 0000000011111111 S6 0000111100001111

Syndrome S5 0011001100110011

Bits S4 0101010101010101

HEX S3 S2 S1 S0

00000 *C4C5TC6TT62C7TT46TMM 10001 C0TT14TMMTTMMTMTT 20010 C1TTMT3456TT5040TMTT 30011 T188TMTTMMTTMT224 40100 C2TT15T3557TT5141TMTT 50101 T199TMTT63MTT47T325 60110 T2010TMTTMMTTMT426 70111 MTTMT3658TT5242TMTT 81000 C3TTMT3759TT5343TMTT

91001 T2111TMTTMMTTMT527 A1010 T2212T33TTM49TTMT628 B1011 17TTMT3860TT5444T1TT C1100 T2313TMTTMMTTMT729 D1101 MTTMT3961TT5545TMTT E1110 16TTMTMMTTMMT0TT

F1111 TMMT32TTM48TTMTMM

NOTES: 2617 tbl 07

1. The table indicates the decoding of the eight syndrome bits to identify the bit-in-error for a single-bit error, or whether a double or triple-bit error was detected. The all-zero case indicates no error detected. * = No errors detected # = The number of the single data bit-in-error T = Two errors detected M = Three or more detected C# = The number of the single checkbits in error

(1)

T M M

T M

T M M

IDT49C466 OPERATION

The EDC is involved in two types of operation — memory reads and memory writes. With the IDT49C466, both these can be accomplished by utilizing either of two possible data paths — one incorporating the FIFO and the other without the FIFO. These operations are treated separately below.

Memory Write

The involvement of the EDC in this type of operation is relatively minimal since it does not call for any error checking. It only generates the check bits associated with each 64-bit wide data word. The EDC can be in generate-detect or normal mode for this operation.

When a write operation is performed, it must be ensured that the SD output buffer (enabled by disabled so that no attempt is made to simultaneously transfer read data onto the System Data (SD) Bus.

When the write FIFO (WFIFO) is bypassed (WBSEL LOW), data passes through the SD Latch In. To latch data, the SDILE signal should be pulled LOW. The special case of a

SOE

and BE

0-7) is

partial word write or byte merge is discussed later. Here it is assumed that all 64 bits are being written. Consequently,

0-7 must all be LOW.

The data is fed to the SD Checkbit generator where appropriate checkbits are generated. Both system data and the generated checkbits can be latched by pulling the signal HIGH. Asserting

MOE

enables the MD output buffer and data is output to the Memory Data (MD) bus. or

MOE

(=0) need to be asserted to enable the CBSYN output

SDOLE

CBSEL

buffer and output checkbits on CBSYN0-7.

When the write FIFO is selected (WBSEL = 1), instead of asserting SDILE, the write FIFO on the rising edge of SCLK.

WBEN

is asserted and data is clocked into

WBFF

is asserted when the WFIFO is full and this inhibits further write attempts (see section on "Clock Skew" and "R/W FIFO Operation at Boundaries") to the WFIFO. When

WBREN

is asserted, data can be clocked out of the write FIFO on the rising edge of MCLK.

WBEF

is asserted when the WFIFO is empty and this inhibits further read attempts (see section on "Clock Skew") from the WFIFO.

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IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES

BEn = 0 => Path A BEn = 1 => Path B

BE0-7

LATCH OUT

PATH B

LATCH IN

WRITE BUFFER

Figure 1. Byte Merge

Memory Read

During a memory read, data and the corresponding input

checkbits are read from the MD bus and CBI

0-7, respectively.

The memory and checkbit data may both be latched as they come in (MD Latch In and MD Checkbit latch) by the MDILE signal. Memory data is sent to the MD checkbit generator (where checkbits corresponding to the input data are generated) and to the error correct circuitry. The generated checkbits are X-ORed with the input checkbits to produce the syndrome word. This is sent to the error correction circuitry which generates the corrected data (normal mode). The corrected data is output to the SD bus via either of two data paths. When RBSEL is LOW, data flows through MD Latch Out. Pulling

MDOLE

by asserting

HIGH latches this data. The output buffer is enabled

SOE

(=0) and BE

0-7 (=1). Corrected data can be

written back to memory by enabling the MD output buffer. In order to ensure selection of the write back path (Path B in figure 1) at the byte mux, BEO-7 should be all 1's while WBSEL = 0. If WBSEL = 1, buffered BEO-7 from the output of the write FIFO controls the byte mux.

If the read FIFO (RFIFO) is selected (RBSEL HIGH), data is clocked into the FIFO (Read_FIFO Write) when LOW, on the rising edge of MCLK.

RBFF

is asserted when the

RBEN

RFIFO is full and this inhibits further write attempts to the RFIFO (see section on "Clock Skew" and "R/W FIFO operation at Boundaries"). Data is clocked out of the FIFO (Read_FIFO Read) when of SCLK.

RBEF

is asserted when the RFIFO is empty and this

RBREN

is LOW on the rising edge

inhibits further read attempts (see section on "Clock Skew") from the RFIFO. Note: In case of multiple error SD should be ignored in correct mode

MD BUS

LATCH OUT

WBSEL

2617 drw 05

M U X

PATH A

BYTE

MUX

Clock Skew

A skew between the read and write clocks, as specified by tskew, is recommended. This specification is not a stringent one, in the manner of setup and hold times, but is important in preempting latencies at FIFO boundaries. For example – When a word is written to an empty FIFO, there is a finite delay before the FIFO is recognized as no longer being empty and hence allowing a read from the same FIFO. Similarly when a word is read from a full FIFO, there is a delay before a write can successfully be attempted. The tskew specification accounts for these cases. During cycles other than on full/empty FIFO boundaries, the clock skew is not required and the device functions correctly even when the reads and writes occur simultaneously. If the tskew specification is ignored and SCLK and MCLK were permanently tied together, there is an extra cycle latency in the cases mentioned above. Clock skew violation is illustrated in Figure 13.

FIFO Write Latency

The first data written to either of the (read or write) FIFOs, after the FIFO is reset, suffers a single clock latency. Data that is set-up with respect to the first clock is ignored and the data that is set-up with respect to the second clock edge after the reset, is stored as the first data in the FIFO (Refer to Figures 9 and 10). The empty-flag is deasserted after this second clock edge and 15 more data words (in a 16 deep configuration) can be written to the FIFO after this.

The latency can be reduced or eliminated by providing a "dummy" or "set-up" clock edge before the actual write to the FIFO. The dummy write clock can be provided any time after reset and before the next buffer write operation takes place. The latency described here (shown in Figures 10 and 13) occurs only after a FIFO reset. In other cases where the FIFO becomes empty there is no latency.

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IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES

R/W FIFO Operation At Boundaries

In the 49C466 the write pointer is incremented on every FIFO write. Similarly the read pointer is incremented on every FIFO read. In most cases on a FIFO read, the last data read remains at the output of the FIFO, until the read pointer is further incremented. On the last (the write that fills the FIFO) FIFO write after the FIFO read, however, this last read data is overwritten by the 16th write following the empty condition and consequently the data at the FIFO output is liable to change. The situation is depicted in the diagram below.

reset

WRITE1 (data = AA)

WRITE1 (data = BB)

WRITE2 (data =CC)

overwritten and the FIFO output changes from AA to the data just written, namely QQ.

This operation needs to be taken into account in the design of the system. In case of a burst operation where FIFO data is output at a much slower rate than the rate at which data is input and the full flag is expected to inhibit further writes, the user cannot expect the FIFO output to remain static through the 16th write of the burst. If this is a requisite to the design, the FIFO output should be latched. In the case of the write FIFO this can be accomplished on-chip by latching the FIFO

FIFO (empty)

FIFO

FIFO (empty)

FIFO

READ1 (data = AA)

No READs (data = AA)

WRITE15 (data = PP) No READs

WRITE16 (data = QQ)

FIFO

RP WP

Figure 2. R/W FIFO Operation

The diagram in figure 2 progresses from the FIFO initialization(reset) through a sequence of write operations. After the first write, a read is executed which establishes the data at the FIFO output(AA). On the last write to the FIFO(the write that fills the FIFO), the location of the last read data is

(data = AA)

FIFO (full)

No READs (data = QQ)

output in the SD output latch. For the read FIFO, the FIFO output must be latched externally to accomplish the same thing, since there is no latch on-chip following the FIFO. If this cannot be done and the situation described above is expected to occur in normal operation, the write must be inhibited one cycle before the FIFO becomes full.

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Integrated Device Technology Inc IDT49C466APQF, IDT49C466PQF Datasheet

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Frequently Asked Questions

User Manual