Integrated Device Technology Inc IDT49C465PQFB, IDT49C465AG, IDT49C465AGB, IDT49C465APQF, IDT49C465APQFB Datasheet

Integrated Device Technology, Inc.

32-BIT FLOW-THRU
ERROR DETECTION
AND CORRECTION UNIT

IDT49C465

IDT49C465A

FEATURES

• 32-bit wide Flow-thruEDC unit, cascadable to 64 bits

• Single-chip 64-bit Generate Mode

• Separate system and memory buses

• On-chip pipeline latch with external control

• Supports bidirectional and common I/O memories

• Corrects all single-bit errors

• Detects all double-bit errors, some multiple-bit errors

• Error Detection Time — 12ns

• Error Correction Time — 14ns

• On chip diagnostic registers.

• Parity generation and checking on system data bus

• Low power CMOS — 100mA typical at 20MH

Z

• 144-pin PGA and PQFP packages

• Military product compliant to MIL-STD 883, Class B

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

MD0–31

MD

Latch

MLE

Memory

Checkbit

Generator

DESCRIPTION

The IDT49C465/A is a 32-bit, two-data bus, Flow-thruEDC
unit. The chip provides single-error correction and two and
three bit error detection of both hard and soft memory errors.
It can be expanded to 64-bit widths by cascading 2 units,
without the need for additional external logic. The Flow­thruEDC has been optimized for speed and simplicity of
control.

The EDC unit has been designed to be used in either of two
configurations in an error correcting memory system. The
bidirectional configuration is most appropriate for systems
using bidirectional memory buses. A second system
configuration utilizes external octal buffers, and is well suited
for systems using memory with separate I/O buses.

The IDT49C465/A supports partial word writes, pipelining
and error diagnostics. It also provides parity protection for
data on the system side.

Correct

Logic

0–7

CBI

PCBI0–7

SD0–31

SD

Latch

SLE
PLE

The IDT logo is a registered trademark and Flow-thruEDC is a trademarkof Integrated Device Technology Inc.

Checkbit

Latch

Pipeline

Mux

CONTROL

Latch

Byte
Mux

CONTROL

Generator

Syndrome

System

Checkbit

Generator

Detect

Logic

Logic

Expansion

CONTROL

Mux

CONTROL

ERR

MERR

0–7

CBO

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MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1995

1995 Integrated Device Technology, Inc. 11.7 DSC-9028/7

1

IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATION

1

0

0

CC

V

4BE0

SD

SD3

2

SD

0

SD1SD

PCBI7PCBI6PCBI5PCBI4PCBI3PCBI2PCBI1PCBI

0

CODE ID

CODE ID

GND

GND

1

MODE

MODE

MERR

SYO7SYO6SY05SY0

ERR

4

3

GND

SY0

0

SYO2SYO1SYO

2

MD0MD1MD

CC

V

V

CC

SD
SD

SD
SD

SD
SD
SD
GND

BE
SD
SD

SD
SD

SLE
PLE

SOE

GND
SD

SD
SD
SD

BE
SD
SD
SD

GND
SD

SD
SD

SD
SD

BE
SD

V

CC

V

CC

10
11

12
13
14
15

16
17

18
19

20
21
22

23
24
25
26
27

28

72 37

73

5
6

7
8
9

1

49C465Y

PQ144-2

2

3

108

36

V

CC

V

CC

MD
MD

MD
MD
MD
MD
MD

3
4

5
6
7
8
9

GND
MD

10

MD

11

MD

12

MD

13

MD

14

MD

15

MLE
MOE
GND
MD

16

MD

17

MD

18

MD

19

MD

20

MD

21

MD

22

MD

23

GND
MD

24

MD

25

MD

26

MD

27

MD

28

MD

29

MD

30

1

V

CC

144109

VCC

29

SD

31SD30

SD

0

CBO

2

1

CBO

CBO

3

CBO

4

CBO

CBOE

5

CBO

6

CBO

7

PSEL

CBO

3

P

PERR

TOP VIEW

GND

0P1

P

MODE 2

CLEAR

SYNCLK

SCLKEN

0

CBI

1

CBI

2

CBI

3

CBI

4

CBI

GND

5

CBI

6

CBI

7

CBI

31

CC

V

MD

2552 drw 02

2

P

GND

PQFP

11.7 2

IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATION

15

14

13

12

11

10

9

8

7

6

5

VCC SD 2
SD 6 SD 4

SD 5

SD 9

SD 11

SD 7

SD 10SD 12

SD 15

SLE

SOE

BE 1 GND

SD 13

PLE GND

SD 19SD 17

SD 18

BE

PCBI 6 PCBI 5

BE 0 SD 3 SD 0

VCC

SD 8

SD 14

SD 16

2

SD 20

SD 25SD 22SD 21

PCBI
PCBI 4PCBI 7

CODE

3

ID
PCBI 1

PCBI 2

1

CODE

0

ID
PCBI 0SD 1

MODE

1

MODE

0

G144-2

MERR ERR
SYO 6 SYO 4

SYO 7

SYO 5

SYO 2

SYO 0

SYO 3

MD 0

VCCGNDGNDGND

SYO 1

MD 1

MD 2 VCC

MD 4 MD 8

MD 12

MD

GND

MD

MD 27

20

GND

MD 21

MD 23

MD 25

VCC

MD 5

MD

GND

MD 11MD 10MD 7

MD

14MOE MLE

MD 16MD 17

MD 18

MD 19

MD 22

9MD 6MD 3

15MD 13

4

SD 23

3

SD 27 SD 29

2

1

SD

GND

VCC

VCC SD 30

24 BE 3

SD 28SD 26

CB0 1 CB0 3

NC*

VCC

SD 31

CB0 0 CBOE

CB0 2

CB0 4

CB0 5

CB0 7

CB0 6
PERRPSEL

GND

P

3

P2

GND

MODE

2

P1

SCLK

EN

SYN­CLK

0

P

GND

CB1

CLEAR

0

CB1 6

CB1 3
CB1 1

VCC

CB1 7

CB1 4
CB1 2

MD 28

MD 30

MD 31
CB1 5 VCC

ABC DEFGHJ KLMNPR

*Tied to Vcc internally

PGA (CAVITY UP)

TOP VIEW

MD 24

MD 26

MD 29

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11.7 3

IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

DETAILED FUNCTIONAL BLOCK DIAGRAM

CBI0–7

MLE

8

MUX

8

8

BIT

LATCH

CHECK

MUX

8

MD

CHECKBIT

Dashed Line = Diagnostic path

8

0–7

SYNDROME

PCBI

8

GENERATOR

8

MD

LATCH

GENERATOR

8

ERROR

CORRECT

0–31

MD

CLEAR

INTERNAL SYNCLK

BYTE MUX

LATCHES

ERROR DATA LATCH

DIAGNOSTIC

MUX

MOE

4

BE 0–3

0–7

CBO

8 8

MUX

8

SD

CHECKBIT

GENERATOR

CBOE

SD

CHECKBIT

GENERATOR

8

PCBI0–7

8

ME

FINAL

SYNDRO

INTERNAL

MUX MUX

8

8

PIPE

LATCH

MUX

ERROR

DETECT

ERR

MERR

8

0–7

SYO

PLE

SOE

4

0–3

1 OF 4

BYTES

BE

SD0–31

SD

LATCH

SLE

PSEL

GEN

PARITY

4

4

0–3

P

CHECK

PARITY

4

INTERNAL SYNCLK

/ERR

PERR

CLEAR

SYNCLK

SCLKEN

LOGIC

CONTROL

2

3

0–2

MODE

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CODE ID 0,1

11.7 4

IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

SYSTEM CONFIGURATIONS

The IDT49C465 EDC unit can be used in various
configurations in an EDC system. The basic configurations
are shown below.

Figure 1 illustrates a bidirectional configuration, which is
most appropriate for systems using bidirectional memory
buses. It is the simplest configuration to understand and use.
During a correction cycle, the corrected data word can be
simultaneously output on both the system bus and memory
bus. Logically, no other parts are required for the correction
function. During partial-word-write operations, the new bytes
are internally combined with the corrected old bytes for
checkbit generation and writing to memory.

CPU

I/O

SD MD

EDC

CBI

CBO

Figure 1. Common I/O Configuration

MEMORY

I/O

CHECKBITS

2552 drw 05

Figure 3 illustrates a third configuration which utilizes
external buffers and is also well suited for systems using
memory with separate I/O buses. Since data from memory
does not need to pass through the part on every cycle, the
EDC system may operate in “bus-watch” mode. As in the
separate I/O configuration, corrected data is output on the SD
outputs.

MEMORY

INPUT BUS

EXT. BUFFER

EXT.BUFFER

Figure 3. Bypassed Separate I/O Configuration

CHECKBIT

I/O

CBICBO

SD MD

EDC

CPU BUS

MEMORY

OUTPUT BUS

EXT. BUFFER

2552 drw 07

Figure 2 illustrates a separate I/O configuration. This is
appropriate for systems using separate I/O memory buses.
This configuration allows separate input and output memory
buses to be used. Corrected data is output on the SD outputs
for the system and for re-write to memory. Partial word-write
bytes are combined externally for writing and checkbit
generation.

CPU

EXT. BUFFER

EDC

SD

MD

CBI

CBO

MEMORY

INPUTS

MEMORY

OUTPUTS

CHECKBITS

2552 drw 06

Figure 4 illustrates the single-chip generate-only mode for
very fast 64-bit checkbit generation in systems that use
separate checkbit-generate and detect-correct units. If this is
not desired, 64-bit checkbit generation and correction can be
done with just 2 EDC units. 64-bit correction is also straight­forward, fast and requires no extra hardware for the
expansion.

MEMORY

INPUT BUS

BUFFER

CHECK

BITS OUT

CBO

64-BIT

GEN.

ONLY

EDC

MEMORY

INPUT BUS

CHECK
BITS IN

BUFFER BUFFER BUFFER

CPU BUS

MEMORY

OUTPUT BUS

CBI

LOWER

DATA

EDC EDC

UPPER

DATA

2552 drw 08

Figure 2. Separate I/O Configuration

Figure 4. Separate Generate/Correction Units

with 64-Bit Checkbit Generation

11.7 5

IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL DESCRIPTION

The error detection/correction codes consist of a modified
Hamming code; it is identical to that used in the IDT49C460.

32-BIT MODE (CODE ID 1,0=00)

VCC

8

PCBI
CBI7

CHECKBITS–IN

0–6

CBI

Figure 5. 32-Bit Mode

64-BIT MODE (CODE ID 1,0=10 & 11)

The expansion bus topology is shown in Figure 6. This
topology allows the syndrome bits used by the correction logic
to be generated simultaneously in both parts used in the
expansion. During a 64-bit detection or correction operation,

PARTIAL–CHECKBITS–OUT (11)

8

(CORRECTION ONLY)

CBO

SYO

PARTIAL–CHECKBITS–OUT (10)

PARTIAL–CHECKBITS–OUT (10)

8

(GENERATE ONLY)

(GENERATE ONLY)

PARTIAL–SYNDROME
(DETECT/CORRECT ONLY)

Figure 6. 64-Bit Mode — 2 Cascaded IDT49C465 Devices

CHECKBITS–IN

PCBI

CBI

8 8

LOWER EDC

(CODE ID 1,0 = 10) (CODE ID 1,0 = 11)

CBO

SYO

EDC

7

77

SYNDROME–OUT

2552 drw 09

“Partial-Checkbit” data and “Partial-Syndrome” data is simul­taneously exchanged between the two EDC units in opposite
directions on dedicated expansion buses. This results in very
short 64-bit detection and correction times.

CHECKBITS–OUT

PCBI

CBI

UPPER EDC

CBO

SYO

ERR

8 FINAL

CHECKBITS–OUT

(DETECT AND CORRECT)

2552 drw 10

64-BIT GENERATE-ONLY MODE (CODE ID 1,0=01)

If the Identity pins CODE ID 1,0 = 01, a single EDC is placed
in the 64-bit “Generate-only” mode. In this mode, the lower 32
bits of the 64-bit data word enter the device on the MD

0-31

inputs and the upper 32-bits of the 64 bit data word enter the

LOWER 32 BITS (0–31)

32

UPPER 32 BITS (32–63)

32

Figure 7. 64-Bit "Generate-Only" Mode (Single Chip)

device on the SD0-31 inputs. This provides the device with the
full 64-bit word from memory. The resultant generated
checkbits are output on the CBO

0-7

outputs. The generate

time is less than that resulting from using a 2-chip cascade.

CBOMD0–31

8

SD0–31

EDC

11.7 6

CHECKBITS–OUT

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IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTIONS

Symbol I/O Name and Function

I/O Buses and Controls

0-7 I/O System Data Bus: Data from MD0-31 appears at these pins corrected if MODE 2-0 = x11, or uncor-

SD
SD

8-15 rected in the other modes. The BEn inputs must be high and the

SD

16-23 output buffers during a read cycle. (Also, see diagnostic section.)

SD

24-31 Separate I/O memory systems: In a write or partial-write cycle, the byte not-to-be-modified is output on

SD

n to n+7 for re-writing to memory, if BEn is high and

are input on the SD

n pins, for writing checkbits to memory, if BEn is low.

SOE

Bi-directional memory systems: In a write or partial-write cycle, the byte not-to-be-modified is re-directed
to the MD I/O pins, if BE

n is high, for checkbit generation and rewriting to memory via the MD I/O pins.

must be high to avoid enabling the output drivers to the system bus in this mode. The new bytes to be written
are input on the SD

n pins for checkbit generation and writing to memory. BEn must be low to direct input

data from the System Data bus to the MD I/O pins for checkbit generation and writing to the checkbit memory.

SLE I System Latch Enable: SLE is an input used to latch data at the SD inputs. The latch is transparent when

SLE is high; the data is latched when SLE is low.

PLE

I Pipeline Latch Enable:

PLE

is an input which controls a pipeline latch, which controls data to be output on

the SD bus and the MD bus during byte merges. Use of this latch is optional. The latch is transparent when

PLE

SOE

is low; the data is latched when

I System Output Enable: When low, enables System output drivers and Parity output drivers if correspond-

PLE

is high.

ing Byte Enable inputs are high.

BE

0-3 I Byte Enables: In systems using separate I/O memory buses, BEn is used to enable the SD and Parity

outputs for byte n. The BE

n pins also control the “Byte mux”. When BEn is high, the corrected or uncorrected

data from the Memory Data latch is directed to the MD I/O pins and used for checkbit generation for byte
n. This is used in partial-word-write operations or during correction cycles. When BE
the System Data latch is directed to the MD I/O pins and used for checkbit generation for byte n.

BE

0 controls SD0-7 BE2 controls SD16-23

BE1 controls SD8-15 BE3 controls SD24-31

MD0-31 I/O Memory Data Bus: These I/O pins accept a 32-bit data word from main memory for error detection and/

or correction. They also output corrected old data or new data to be written to main memory when the EDC
unit is used in a bi-directional configuration.

MLE I Memory Latch Enable: MLE is used to latch data from the MD inputs and checkbits from the CBI inputs.

The latch is transparent when MLE is high; data is latched when MLE is low. When identified as the upper
slice in a 64-bit cascade, the checkbit latch is bypassed.

MOE

P

0-3 I/O Parity I/O: The parity I/O pins for Bytes 0 to 3. These pins output the parity of their respective bytes when

I Memory Output Enable:

MOE

enables Memory Data Bus output drivers when low.

that byte is being output on the SD bus. These pins also serve as parity inputs and are used in generating
the Parity ERRor (

PERR

) signal under certain conditions (see Byte Enable definition). The parity is odd or

even depending on the state of the Parity SELect pin (PSEL).

PSEL I Parity SELect: If the Parity SELect pin is low, the parity is even.

If the Parity SELect pin is high, the parity is odd.

SOE

pin must be low to enable the SD

is low. The new bytes to be written to memory

SOE

n is low, the data from

Inputs

CBI

0-7 I CheckBits-In (00) CheckBits-In-1 (10) Partial-Syndrome-In (11):

In a single EDC system or in the lower slice of a cascaded EDC system, these inputs accept the checkbits
from the checkbit memory. In the upper slice in a cascaded EDC system, these inputs accept the “Partial­Syndrome” from the lower slice (Detect/Correct path).

PCBI

0-7 I Partial-CheckBits-In (10) Partial-CheckBits-In (11):

In a single EDC system, these inputs are unused but should not be allowed to float. In a cascaded EDC
system, the “Partial-Checkbits” used by the lower slice are accepted by these inputs (Correction path only).
In the upper slice of a cascaded EDC system, “Partial-Checkbits” generated by the lower slice are accepted
by these inputs (Generate path).

CODE ID

1,0 I CODE IDentity: Inputs which identify the slice position/ functional mode of the IDT49C465.

(00) Single 32-bit EDC unit (10) Lower slice of a 64-bit cascade
(01) 64-bit “Checkbit-generate-only” unit (11) Upper slice of a 64-bit cascade

11.7 7

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32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTIONS (Con’t.)

Symbol I/O Name and Function

Inputs (Con’t.)

2-0 I MODE select: Selects one of four operating modes.

MODE

(x11) “Normal” Mode: Normal EDC operation (Flow-thru correction and generation).
(x10) “Generate-Detect” Mode: In this mode, error correction is disabled. Error generation and detection are

normal.

(000) “Error-Data-Output” Mode: Allows the uncorrected data captured from an error event by the Error-Data

Register to be read by the system for diagnostic purposes. The Error-Data Register is cleared by toggling

CLEAR

low. The Syndrome Register and Error-Data Register record the syndrome and uncorrected data
from the first error that occurs after they are reset by the
Register are updated when there is a positive edge on SYNCLK, an error condition is indicated (
and the Error Counter indicates zero.
All-Zero-Data Source: In Error-Data-Output Mode, clearing the Error-Data Register provides a source of
all-zero-data for hardware initialization of memory, if this desired.

(x01) Diagnostic-Output Mode: In this mode, the contents of the Syndrome Register , Error Counter and Error-

Type Register are output on the SD bus. This allows the syndrome bytes for an indicated error to be read
by the system for error-logging purposes. The Syndrome Register and the Error-Data Register are updated
when there is a positive edge on SYNCLK, an error condition is indicated and the Error Counter indicates
zero errors. Thus, the Syndrome Register saves the syndrome that was present when the first error occurred
after the Error Counter was cleared. The Syndrome Register and the Error Counter are cleared by toggling

CLEAR

low. The Error Counter lets the system tell if more than one error has occurred since the last time
the Syndrome Register or Error-Data Register was read.

(100) Checkbit-Injection Mode: In the “Checkbit-Injection” Mode, diagnostic checkbits may be input on System

Data Bus bits 0-7 (see Diagnostic Features - Detailed Description).

CLEAR

I CLEAR: When the

CLEAR

pin is taken low, the Error-Data Register, the Syndrome Register, the Error

Counter and the Error-Type Register are cleared.

SYNCLK I SYNdrome CLocK: If

ERR

is low, and the Error Counter indicates zero errors, syndrome bits are clocked
into the Syndrome Register and data from the outputs of the Memory Data input latch are clocked into the
Error-Data Register on the low-to-high edge of SYNCLK. If
the low-to-high edge of SYNCLK, unless the Error Counter indicates fifteen errors.

SCLKEN

I SynCLK ENable: The

SCLKEN

enables the SYNCLK signal. SYNCLK is ignored if

Outputs and Enables

CBO

0-7 O CheckBits-Out (00, 01) Partial-CheckBits-Out (10) Checkbits-Out (11):

In a single EDC system, the checkbits are output to the checkbit memory on these outputs. In the lower slice
in a cascaded EDC system, the “Partial-checkbits” used by the upper slice are output by these outputs
(Generate path only). In the upper slice in a cascade, the “Final-Checkbits” appear at these outputs
(Generate path only).

CBOE

SYO

0-7 O SYndrome-Out (00) Partial-SYndrome-Out (10) Partial-Checkbits-Out (11):

I CheckBits Out Enable: Enables CheckBit Output drivers when low.

In a 32-bit EDC system, the syndrome bits are output on these pins. In the lower slice in a 64-bit cascaded
system, the “Partial-Syndrome” bits appear at these outputs (Detect/ Correct path). In the upper slice in a
cascaded EDC system, the “Partial-Checkbits” appear at these outputs (Correct path only). In a 64-bit
cascaded system, the “Final-Syndrome” may be accessed in the “Diagnostic-Output” Mode from either the
lower or the upper slice since the final syndrome is contained in both.

ERR

MERR

PERR

O ERROR: When in “Normal” and “Detect only” modes, a low on this pin indicates that one or more errors have

been detected.

ERR

is not gated or latched internally.

O Multiple ERRor: When in “Normal” and “Detect only” modes, a low on this pin indicates that two or more

errors have been detected.

MERR

is not gated or latched internally.

O Parity ERRor: A low on this pin indicates a parity error which has resulted from the active bytes defined by

the 4 Byte Enable pins. Parity ERRor (

PERR

) is not gated or latched internally (see Byte Enable definition).

Power Supply Pins

Vcc

1- 10 P +5 Volts

GND

1-12 P Ground

CLEAR

pin. The Syndrome Register and Error-Data

ERR

is low, the Error Counter will increment on

SCLKEN

ERR

= low),

is high.

2552 tbl 02

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IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

DIAGNOSTIC DATA FORMAT (SYSTEM BUS)

Data Out (Unlatched)

Checkbits

Error
Type

Re-

served

Latched Data

Error

Counter

Syndrome bits

Partial Checkbits

Byte 3 Byte 2 Byte 1 Byte 0

3

S M - - 2 2 2 2

30

2

27

01

76543210

7654321076543210

DIAGNOSTIC FEATURES — DETAILED DESCRIPTION

Mode 2-0

x11 “NORMAL” Mode

In this mode, operation is “Normal” or non-diagnostic.

x10 “GENERATE-DETECT” Mode

When the EDC unit is in the “Generate-Detect” Mode, data is not corrected or altered by the error correction network.
(Also referred to as the “Detect-only” Mode.)

000 “ERROR-DATA-OUTPUT” Mode

In this mode, the 32-bit data from the Error-Data Register is output on the SD bus.
Error Data Register: The uncorrected data from the Memory Data bus input latch is stored in the Error-Data Register

if the error counter contents indicates “0” and there is a positive transition on the SYNCLK input when the
low. Thus, the Error-Data Register contains memory data corresponding to the first error to occur since the register was
cleared. This register is cleared by pulling the
the “Error-Data-Output” Mode and enabling the System Data bus output drivers.

All-Zero-Data: The Error-Data Register can be used as an “all-zero-data” data source for memory initialization in systems
where the initialization process is to be done entirely by hardware.

x01 “DIAGNOSTIC-OUTPUT” Mode

In this mode, data from the diagnostic registers, the PCBI bus and the CBI bus is output on the SD bus.
Direct Checkbit Readback: Internal data paths allow both the “Partial-CheckBit-Input” bus and the data in the “CheckBit-

Input” latch to be read directly by the system bus for diagnostic purposes. Both the Checkbit Input Bus and the Partial
Checkbit Input Bus are read via the System Data bus by entering the “Diagnostic-Output” Mode and enabling the System
Data bus output drivers. The checkbits are output on System Data bus bits 0-7; the Partial Checkbits are output on bits
8-15.

Syndrome Register: After an error has been detected, the syndrome bits generated are clocked into the internal
Syndrome Register if the error counter contents indicates “0” and there is a positive transition on the SYNCLK input when
the

ERR

signal is low. This register is cleared by pulling the
bus by entering the “Diagnostic-Output” Mode and enabling the System Data bus outputs. This data is output on SD
bits 16-23.

Error Counter: The 4-bit on-board error counter is incremented if the error counter contents do not indicate FF HEX, which
corresponds to a count of 15, and there is a positive transition on the SYNCLK input when the
counter is cleared by pulling the
“Diagnostic-Output” Mode and enabling the System Data bus output drivers. This data is output on System Data bus
bits 24-27.

Test Register: These 2 bits are reserved for factory diagnostics only and must not be used by system software. This data
is output on System Data bus bits 28-29.

Error-Type Register: The Error-Type Register, clocked by the SYNCLK input, saves 2 bits which indicate whether a
recorded error was a single or a multiple-bit error. This register holds only the first error type to occur after the last Clear
operation. This data is output on System Data bus bits 30-31.

100 Direct Read-Path Checkbit Injection: In the “Checkbit-Injection” Mode, bits 0-7 of the System Data input latch are

presented to the inputs of the Checkbit Input latch. If MLE is strobed, the checkbit latch will be loaded with this value in
place of the checkbits from memory. By inserting various checkbit values, operation of the correction function of the EDC
can be verified “on-board”. Except for the “Checkbit-Injection” function, operation in this mode is identical to “Normal” Mode
operation.

CLEAR

CLEAR

input low. The register is read via the System Data bus by entering

CLEAR

input low. The register is read via the System Data

ERR

signal is low. This

input low. The counter is read via the System Data bus by entering the

ERR

08 716 1524 2331

2552 drw 12

signal is

2552 tbl 03

11.7 9

IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

OPERATING MODE CHARTS
SLICE IDENTIFICATION

CODE ID 1 CODE ID 0 Slice Definition

0 0 32-bit Flow-Thru EDC
0 1 64-bit GENERATE Only EDC
1 0 64-bit EDC- Lower 32 bits (0-31)
1 1 64-bit EDC- Upper 32 bits (32-63)

2552 tbl 04

SLICE POSITION CONTROL

Checkbit Buses

Slice Position/

CODE Functional Operation PCBI CBI CBO SYO P

ID

SOE

SOE

SD Bus

MOE

MOE

MD Bus Bus Bus Bus Bus Bus

1 0 Width = 32 32 8 8 8 8 4 1
0 0 Single 32-bit EDC unit

Generate

Detect/Correct

(1)

1 Sys. 0–31 0 Sys. Byte Mux — — CBs out — P in active

(2)

0 Pipe. latch 1 MD 0–31 — CBs in — Syn. out P out —
0 1 “64-bit Generate-only” 1 Sys. 32–63 1 Sys. 0–31 — — CBs out — — —
1 0 Lower word, 64-bit bus

Generate

Detect/Correct

1 1 Upper word, 64-bit bus

Generate

Detect/Correct

NOTES: 2552 tbl 05

1. Checkbits generated from the data in the SD Latch.

2. Corrected data residing in the Pipe Latch.

(1)

1 Sys. 0–31 0 MD 0–31 — — PCBs out — P in active

(2)

0 Pipe. latch 1 MD 0–31 U-SYOout CBs in — Par.Synd P out —

(1)

1 Sys. 32–63 0 MD 32–63 L-CBOout — F.CBs out — P in active

(2)

0 Pipe. latch 1 MD 32–63 — L-SYOout — Par.Cbits P out —

PCBI CBI CBO SYO P

PERR

PERR

FUNCTIONAL MODE CONTROL

Checkbit Buses

Functional Mode

of SD Bus PCBI CBI CBO SYO P

MODE

2 1 0 Width = 32 32 8 8 8 8 4 1
x11 “Normal”

Generate 1 CPU Data 0 Pipe. latch — — CB out — P in active

Correct 0 Pipe. latch 1 RAM Data — CB in — — P out —

x10 “Generate-Detect”

Generate 1 CPU Data 0 Pipe. latch — — CB out — P in active

Detect 0 Pipe. latch 1 RAM Data — CB in — — P out —
000 “Error-Data-Output” 0 Err. D. latch — — — — — — — —
x01 “Diagnostic-Output” 0 CBin latch — — PCBI in CB in — — — —

100 “Checkbit-Injection”

Generate 1 SDin latch 0 Pipe. latch — — CB out — P in active

Inject Checkbits 1 SD0–7 in 0 Pipe. latch — — — — — —

Correct 0 Pipe. latch 1 RAM Data — CB in — — P out —

SOE

SOE

SD Bus

PCBIin bus

Syn. register

Err. counter

Er. type reg.

MOE

MD Bus Bus Bus Bus Bus Bus

MOE

PERR

PERR

2552 tbl 06

11.7 10

IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

PRIMARY DATA PATH vs. MEMORY CONFIGURATION

SEPARATE I/O MEMORIES: COMMON I/O MEMORIES:

1. Checkbit Generation
Write New Word to Memory

CPU

BUFFER

SD MD
P

IDT49C465

2. Data Correction
Read Memory Word

CPU

BUFFER

CORRECTED

SD MD
P

IDT49C465

CBO

CBI

CBO

CBI

IN

D

MAIN

MEMORY

D

OUT

CHECKBIT

MEMORY

D

IN

MAIN

MEMORY

D

OUT

CHECKBIT

MEMORY

1. Checkbit Generation
Write New Word to Memory

CPU

SD MD

P

CBO

IDT49C465

CBI

2. Data Correction
Read Memory Word

CORRECTED

CPU

SD MD

P

CBO

IDT49C465

CBI

I/O

MAIN

MEMORY

CHECKBIT

MEMORY

I/O

MAIN

MEMORY

CHECKBIT

MEMORY

3. Memory Generation
Re-write Corrected Word to Memory

CPU

BUFFER

CORRECTED

SD MD
P

CBO

IDT49C465

CBI

D

IN

MAIN

MEMORY

D

OUT

CHECKBIT

MEMORY

3. Memory Generation
Re-write Corrected Word to Memory

CORRECTED CORRECTED

CPU

SD MD

P

CBO

IDT49C465

CBI

I/O

MAIN

MEMORY

CHECKBIT

MEMORY

2552 drw 13

11.7 11

IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

PARTIAL-WORD-WRITE OPERATIONS

FOR COMMON I/O MEMORIES:

MD LATCH

CORRECTION

BLOCK

SD BUS

B3 = 1

2 = 1

B
B

1 = 1
0 = 0

B

BYTE 3
BYTE 2
BYTE 1
BYTE 0

SD LATCHPIPE LATCH

8
8
8
8

B3
B2
B1
B0

BYTE

MUX

A3

A2

A1

A0

CHECKBIT

GENERATOR

IDT49C465

MD BUS

BYTE 3
BYTE 2
BYTE 1
BYTE 0

CBO

CBI

MAIN

MEMORY

CHECKBIT

MEMORY

2552 drw 14

In order to perform a partial-word-write operation, the
complete word in question must be read from memory. This
must be done in order to correct any error which may have
occurred in the old word. Once the complete, corrected word
is available, with all the bytes verified, the new word may be
assembled in the byte mux and the new checkbits generated.

The example shown above illustrates the case of combin­ing 3 bytes from an old word with a new lower order byte to
form a new word. The new word, along with the new checkbits,
may now be written to memory.

In the separate I/O memory configuration, the situation is
similar except that the new word is output on the SD Bus
instead of the MD Bus (refer to previous page).

11.7 12