ICST AV9250F-13, ICS9250F-13 Datasheet

Integrated Circuit Systems, Inc.
General Description Features
ICS9250-13
Block Diagram
Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation
Frequency Generator & Integrated Buffers for PENTIUM/Pro
TM
9250-13 Rev A 3/25/99
Pin Configuration
3.3V outputs: SDRAM, PCI, REF, 48/24MHz  2.5V or 3.3V outputs: CPU  20 ohm CPU clock output impedance  20 ohm PCI clock output impedance  Skew from CPU (earlier) to PCI clock - 1 to 4 ns,
center 2.6 ns.  No external load cap for CL=18pF crystals  ±250 ps CPU, PCI clock skew  400ps (cycle to cycle) CPU jitter  Smooth frequency switch, with selections from
50 to 83.3 MHz CPU. I2C interface for programming  2ms power up clock stable time  Clock duty cycle 45-55%.  56 pin 300 mil SSOP package  3.3V operation, 5V tolerant input.
56-Pin SSOP
Power Groups
VDDREF = REF (0:1), X1, X2 VDDPCI = PCICLK_F, PCICLK(0:5) VDDSDR = SDRAM (0:11), supply for PLL core, VDD48 = 24MHz, 48MHz VDDLIOAPIC = IOAPIC VDDL2CPU = CPUCLK (0:3)
* Internal Pull-up Resistor of 120K to VDD on indicated inputs
The ICS9250-13 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro or Cyrix. Eight different reference frequency multiplying factors are externally selectable with smooth frequency transitions.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-13 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Recomended Application:
440LX/EX type chipset Motherboard single chip
clock solution.
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2
ICS9250-13
Pin Descriptions
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
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3
ICS9250-13
Functionality
VDD1,2,3 = 3.3V±5%, V
DDL
1,2 = 2.5V±5% or 3.3±5%, TA=0 to 70°C
Crystal (X1, X2) = 14.31818MHz
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CPU 3.3#_2.5V Buffer selector for CPUCLK and IOAPIC drivers.
Power Management Functionality
Mode Pin - Power Management Input Control
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1000 10.1810.1800.04813.41 1001 00.0800.0856.14813.41 1010 13.3813.3842.43813.41 1011 94.8694.8642.43813.41 1100 00.8700.8700.93813.41 1101 00.5700.5705.73813.41 1110 99.1799.1799.53813.41 1111 28.6628.6614.33813.41
4
ICS9250-13
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
 Controller (host) sends a start bit.  Controller (host) sends the write address D2
(H)
 ICS clock will acknowledge  Controller (host) sends a dummy command code  ICS clock will acknowledge  Controller (host) sends a dummy byte count  ICS clock will acknowledge  Controller (host) starts sending first byte (Byte 0)
through byte 5
 ICS clock will acknowledge each byte one at a time.  Controller (host) sends a Stop bit
How to Read:
 Controller (host) will send start bit.  Controler (host) sends the read address D3
(H)
 ICS clock will acknowledge  ICS clock will send the byte count  Controller (host) acknowledges  ICS clock sends first byte (Byte 0) through byte 5  Controller (host) will need to acknowledge each byte  Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit Address
D3
(H)
AC
K
Byte Count
ACK
Byte
0
ACK
Byte 1
ACK
Byte
2
ACK
Byte
3
ACK
Byte 4
ACK
Byte
5
ACK
Stop Bit
How to Read:
Controller (Host) ICS (Slave/Receiver)
Start Bit Address
D2
(H)
AC
K
Dummy Command Code
AC
K
Dummy Byte Count
AC
K
Byte 0
AC
K
Byte 1
AC
K
Byte 2
ACK
Byte 3
AC
K
Byte 4
AC
K
Byte 5
AC
K
Stop Bit
How to Write:
5
ICS9250-13
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note 1. Default at Power-up will be for latched logic inputs to define frequenc,. Bits 2, 6:4 are default to 0000.
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011000.4800.4800.24
111000.2800.2800.14
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