ICST AV9248G-92, ICS9248G-92 Datasheet
Integrated
Circuit
Systems, Inc.
Features
ICS9248-92
Block Diagram
Mobile Pentium IITM System Clock Chip
9248-92 Rev E 02/21/01
Pentium is a trademark on Intel Corporation.
• Generates system clocks for CPU, SDRAM, PCI, plus
14.318 MHz REF(0:2), USB, Plus Super I/O
•I2C serial configuration interface provides output clock
disabling and other functions
• MODE input pin selects optional power management
input control pins
• Two fixed outputs separately selectable as 24 or 48MHz
• 2.5V outputs: CPU
• 3.3V outputs: SDRAM, PCI, REF, 48/24 MHz
• No power supply sequence requirements
• Uses external 14.318MHz crystal
• 48 pin 240 mil TSSOP package
• Output enable register
for serial port control: 1 = enable
0 = disable
General Description:
Features include two strong CPU, seven PCI and eight SDRAM
clocks. Three reference outputs are available equal to the
crystal frequency. Stronger drive CPUCLK outputs typically
provide greater than 1 V/ns slew rate into 20pF loads. This
device meets rise and fall requirements with 2 loads per CPU
output (ie, one clock to CPU and NB chipset, one clock to two
L2 cache inputs).
PWR_DWN# pin allows low power mode by stopping crystal
OSC and PLL stages. For optional power management,
CPU_STOP# can stop CPU (0:1) clocks and PCI_STOP# will
stop PCICLK (0:5) clocks
PCICLK outputs typically provide better than 1V/ns slew rate
into 30pF loads while maintaining 50±5% duty cycle. The REF
clock outputs typically provide better than 0.5V/ns slew rates.
The ICS9248-92 accepts a 14.318MHz reference crystal or
clock as its input and runs on a 3.3V core supply.
Functionality
Crystal (X1, X2) = 14.31818 MHz
Pin Configuration
48-Pin TSSOP 240 mil Package
LES
#66/001
KLCUPC
)zHM(
KLCICP
)zHM(
06.663.33
10013.33
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
Recommended Application:
The ICS9248-92 is a fully compliant timing solution for the
Intel mobile 440BX/MX chipset requirements.
2
ICS9248-92
Pin Descriptions
Power Groups
VDDCOR = Supply for PLL core
VDDREF = REF [0:2], X1, X2
VDDPCI = PCICLK_F, PCICLK [0:5]
VDDSDR = SDRAM [0:7]
VDD48 = 48/24MHzA, 48/24MHz
VDDLCPU = CPUCLK [0:1]
REBMUNNIPEMANNIPEPYTNOITPIRCSED
2,1,54]0:2[FERTUOtuptuOkcolcecnerefeR
,42,71,01,3
34,73,13
DNGRWP)nommoc(dnuorG
41XNIpacdaollatsyrclanretnisah,tupniecnereferrolatsyrC
52XTUO
kcabdeefdnapacdaollanretnisah,tuptuolatsyrC
1Xotrotsiser
6EDOMNI)3egapelbatees(noitcelesnoitcnuftupnI
51,7ICPDDVRWPV3.3lanimon,]5:0[KLCICP,F_KLCICProfylppuS
8F_KLCICPTUO#POTS_ICPybdetceffaton,kcolcICPgninnureerF
61,41,31,21,11,9]5:0[KLCICPTUOskcolcICP
81#66/001LESNI
UPCdnaMARDSrofzHM001rozHM6.66stceleS
)3,1egapselbatees(
91ATADSNII
2
tupniatadC
02KLCSNII
2
tupnikcolcC
1284DDVRWPV3.3lanimon,BzHM42/84,AzHM42/84rofylppuS
22AzHM42/84TUOO/IrepuSroBSUroftuptuorevirdzHM42/84
32BzHM42/84TUOO/IrepuSroBSUroftuptuorevirdzHM42/84
52ROCDDVRWPV3.3lanimon,erocLLProfylppuS
62
7MARDSTUOnipNI_FUBmorftuptuoreffubtuonaf,tuptuokcolcMARDS
#POTS_ICPNIwolnehwlevel"0"cigolta]5:0[suBICPstlaH
72
6MARDSTUOnipNI_FUBmorftuptuoreffubtuonaf,tuptuokcolcMARDS
#POTS_UPCNIwolnehwlevel"0"cigoltaskcolcUPCstlaH
43,82RDSDDVRWP
,#POTS_UPC/6MARDS,]5:0[MARDSrofylppuS
V3.3lanimon,#POTS_ICP/7MARDS
04UPCLDDVRWPlanimonV5.2]1:0[KLCUPCrofylppuS
14,24]1:0[KLCUPCTUO2LDDVybderewop,tuptuokcolcKLCUPC
92,03,23,33,53,63]5:0[MARDSTUO
morfstuptuoreffubtuonaf,stuptuokcolcMARDS
nipNI_FUB
83BFTUOtuokcabdeeF
93NI_FUBNIsreffubMARDSroftupnI
44#NWD_RWPNI
wolotniecivedehtnwodsrewop)wol(evitcanevirdnehW
latsyrcdnaOCV,delbasideraskcolclanretnI.etatsrewop
.deppotseraCSO
64,84FERDDVRWPV3.3lanimon,2X,1X,]2:0[FERrofylppuS
3
ICS9248-92
Power-On Conditions
Example:
a) if MODE = 1, pins 26 and 27 are configured as SDRAM7 and SDRAM6 respectively.
b) if MODE = 0, pins 26 and 27 are configured as PCI_STOP# and CPU_STOP# respectively.
Power-On Default Conditions
At power-up and before device programming, all clocks will default to an enabled and “on” condition. The frequencies that are then produced
are on the MODE pin as shown in the table below.
KCOLC PU-REWOPTANOITIDNOCTLUAFED
)2:0(FER zHM81813.41
zHM42/84zHM84
LES
#6.66/001
EDOM#NIPNOITPIRCSEDNOITCNUF
11
24,14sKLCUPCelbasid/elbanegifnoclaires/w-zHM001
,21,31,41,61
8,9,11
sKLCICPelbasid/elbanegifnoclaires/w-zHM3.33
01
24,14sKLCUPCelbasid/elbanegifnoclaires/w-zHM6.66
,21,31,41,61
8,9,11
sKLCICPelbasid/elbanegifnoclaires/w-zHM3.33
10
62#POTS_ICP
skcolC]5:0[ICP,tnemeganaMrewoP
wolnehwdeppotS
72#POTS_UPC
skcolC]5:0[UPC,tnemeganaMrewoP
wolnehwdeppotS
8F_KLCICPgninnureerFkcolCICP-zHM3.33
24,14sKLCUPC
lairesdnalortnoCpotSlanretxe/wskcolCUPC-zHM001
.elbasid/elbanelaudividnigifnoc
,21,31,41,61
9,11
sKLCICP
lairesdnalortnocpotSlanretxe/wskcolCICP-zHM3.33
.elbasid/elbanelaudividnigifnoc
00
62#POTS_ICP
skcolC]5:0[ICP,tnemeganaMrewoP
wolnehwdeppotS
72#POTS_UPC
skcolC]5:0[UPC,tnemeganaMrewoP
wolnehwdeppotS
8F_KLCICPtnemeganaMrewoProfgninnureerFkcolCICP-zHM3.33
24,14sKLCUPC
lairesdnalortnocpotSlanretxe/wskcolCUPC-zHM6.66
.elbasid/elbanelaudividnigifnoc
,21,31,41,61
9,11
sKLCICP
lairesdnalortnocpotSlanretxe/wskcolCICP-zHM3.33
.elbasid/elbanelaudividnigifnoc
4
ICS9248-92
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controler (host) sends the read address D3
(H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
A
CK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Read:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
A
CK
Dummy Command Code
A
CK
Dummy Byte Count
A
CK
Byte 0
A
CK
Byte 1
ACK
Byte 2
A
CK
Byte 3
A
CK
Byte 4
A
CK
Byte 5
A
CK
Stop Bit
How to Write:
5
ICS9248-92
Notes:
1. TCLK is a test clock driven on the X1 (crystal in pin) input during test mode.
Select Functions
TIB#NIPNOITPIRCSEDDWP
7tiB- devreseR0
6tiB- devreseR0
5tiB-
epytslortnoC,murtcepSdaerpSnI
)daerpsnwod=1,deretnec=0(
1
4tiB
gnidaerpSslortnoC,murtcepSdaerpSnI
)%52.0±=1%5.0±=0(
0
3tiB32zHM42=0,zHM84=1)tceleSycneuqerF(zHM42/841
2tiB22zHM42=0,zHM84=1)tceleSycneuqerF(zHM42/841
1tiB
0tiB
-
1tiB
1
1
0
0
0tiB
etatS-irT-1
elbanEmurtcepSdaerpS-0
edomtseT-1
noitarepolamroN-0
01
Serial Configuration Command Bitmaps
Byte 0: Functional and Frequency Select Clock Register (default on Bits 7, 6, 5, 4, 1, 0 = 0)
(default on Bits 3, 2 = 1)
Note: PWD = Power-Up Default
ytilanoitcnuFUPC
,ICP
F_ICP
MARDSFER
zHM42
noitceleS
zHM84
noitceleS
etatsirTZ-IHZ-IHZ-IHZ-IHZ-IHZ-IH
edomtseT2/KLCT
1
4/KLCT
1
2/KLCT
1
KLCT
1
4/KLCT
1
2/KLCT
1
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