ICST AV9248G-50-T, AV9248F-50-T, ICS9248F-50-T, ICS9248G-50-T Datasheet

Integrated Circuit Systems, Inc.

General Description Features

ICS9248-50

Block Diagram

Frequency Timing Generator for Pentium II Systems

9248-50 Rev - H 03/19/01

Pin Configuration

Pentium is a trademark on Intel Corporation.

• Generates the following system clocks:

- 2 CPU (2.5V) up to 100MHz.

- 6 PCI (3.3V) @ 33.3MHz (Includes one free running).

- 2 REF clks (3.3V) at 14.318MHz.

• Skew characteristics:

- CPU – CPU

<175ps

- PCI – PCI < 500ps

- CPU(early) – PCI = 1.5ns – 4ns.

• Supports Spread Spectrum modulation for CPU and PCI clocks, 0.5% down spread

• Efficient Power management scheme through stop clocks and power down modes.

• Uses external 14.318MHz crystal, no external load cap required for CL=18pF crystal.

• 28-pin (209 mil) SSOP and (6.1mm) TSSOP package

The ICS9248-50 is the Main clock solution for Notebook designs using the Intel 440BX style chipset. Along with an SDRAM buffer such as the ICS9179-03, it provides all necessary clock signals for such a system.

Spread spectrum may be enabled by driving pin 26, SPREAD# active (Low) at power-on. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-50 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.

Power Groups

VDD, GND = PLL core VDDREF , GNDREF = REF(0:1), X1, X2 VDDPCI, GNDPCI = PCICLK_F, PCICLK (0:4) VDD48, GND48 = 48MHz, 48/24MHz

28-Pin SSOP & TSSOP

ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

ICS9248-50

Pin Descriptions

Pin number Pin nam e Type Descri pt ion

1 GNDREF Power Ground for 14.318 MHz reference clock outputs 2 X1 Input 14.318 MHz crystal input 3 X2 Output 14.318 MHz crystal output 4 PCICLK_F Output 3.3 V free running PCI clock output , wi ll not be stopped by t he P CI_STOP#

5,6, 9, 10,11 PCICLK (1:5) Output 3.3 V P CI cl oc k outputs , generating ti m ing requi rements for Penti um II

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7 GNDPCI Power Ground for PCI cloc k out puts

8 VDDPCI Power 3.3 V power for the P CI clock outputs 12 VDD48 Power 3.3 V power for 48/24 MHz cloc k s 13 48 MHz O ut put 3.3 V 48 MHz clock out put , fixed frequency clock typic al ly used with US B devices

14 TS#/48/24MHz Output

3.3 V 48 or 24 MHz out put and Tri-st at e opt i on, active low = tri s t ate mode for test ing, act i ve high = normal operat ion

15 G ND48 Power Ground for 48/24 MHz clocks

16 SEL 100/ 66# Input

cont rol for t he frequenc y of clocks at the CPU & PCICLK output pins. If logic "0" is used t he 66. 6 M Hz frequency is s elected. If Logic " 1" i s used, t he 100 M Hz frequency i s select ed. The PCI clock is m ul t i plexed to run at 33. 3 MHz for both selected cases.

17 PD# Input

As ynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the V CO and the crystal are stopped. The latency of the power down will not be greater than 3ms.

18 CPU_STOP# I nput

As y nchronous act i ve low input pin us ed t o stop the CPUCLK in active low stat e, al l other c locks will c ontinue to run. The CPUCLK will have a "Turnon " latency of at least 3 CP U c l ocks.

19 VDD Power Isolat ed 3. 3 V power for core 20 PCI-Stop# Input

Sy nc hronous acti ve low input used t o stop the P CICLK in ac tive low state. It will not

effect PCICLK_F or any other outputs . 21 GND P ower Isolat ed ground for core 22 GNDL Power Ground for CPU cl ock outputs

23,24 CP UCLK (1: 0) Output 2.5 V CPU clock out puts

25 VDDL Power 2.5 V power for CPU clock output s

26 REF1/SPREAD# Output

3.3 V 14. 318 MHz reference clock output and power-on spread spectrum enable

option. Active low = spread spectrum clocking enable. Active high = spread spec trum

clocking di sable. 27 REF0/SEL48# Output

3.3 V 14. 318 MHz reference clock output and power-on 48/24 MHz s el ect option.

Ac t i ve low = 48 MHz out put at pin 14. A c tive high = 24 MHz out put at pin 14. 28 V DDREF P ower 3.3 V power for 14.318 MHz reference c l oc k outputs.

ICS9248-50

Select Functions

(Functionality determined by TS# and SEL100/66# pin, see below)

Notes:

1. TCLK is a test clock driven on the X1 (crystal in pin) input during test mode.

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Po wer Management

ICS9248-50 Power Management Requirements

Clock Enable Configuration

Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power up and power down operations using the PD# pin will not cause clocks of a short or longer pulse than that of the running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.

Notes.

1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.

2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.

3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.

4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only. The REF will be stopped independant of these.

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ICS9248-50

PCI_STOP# Timing Diagram

PCI_STOP# is an asynchronous input to the ICS9248-50. It is used to turn off the PCICLK (0:4) clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-50 internally . The minimum that the PCICLK (0:4) clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:4) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.

CPU_STOP# Timing Diagram

CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9248-50. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100 CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will alw ays be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.

Notes:

1. All timing is referenced to the internal CPUCLK.

2. CPU_STOP# is an asynchronous input and metastable conditions may exist.

This signal is synchronized to the CPUCLKs inside the ICS9248-50.

3. All other clocks continue to run undisturbed.

4. PD# and PCI_STOP# are shown in a high (true) state.

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)

2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248.

3. All other clocks continue to run undisturbed.

4. PD# and CPU_STOP# are shown in a high (true) state.

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