ICST AV9248F-98-T, ICS9248F-98-T Datasheet

Integrated
Circuit
Systems, Inc.

ICS9248-98

Third party brands and names are the property of their respective owners.

Block Diagram

9248-98 Rev D 11/6/00

Functionality

Pin Configuration

48-Pin 300mil SSOP

Recommended Application:

440BX/VIA Apollo 133 style chipset.

Output Features:

• 2 - CPUs @2.5V, up to 166MHz.

• 1 - IOAPIC @ 2.5V

• 13 - SDRAM @ 3.3V

• 6 - PCI @3.3V,

• 1 - 48MHz, @3.3V fixed.

• 1 - 24MHz @ 3.3V

• 2 - REF @3.3V, 14.318MHz.

Features:

• Up to 166MHz frequency support

• Support power management: PCI, CPU stop and Mode

• Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).

• Uses external 14.318MHz crystal

Skew Specifications:

• CPU – CPU: <175ps

• SDRAM - SDRAM: <250ps

• PCI – PCI: <500ps

• BUFFER_IN-SDRAM: <5ns

• CPU(early)-PCI: Min=1.0ns, Typ=2.3ns, Max=4.0ns

Frequency Generator & Integrated Buffers for Celeron & PII/III™

CLK_STOP#

PCI_STOP#

PLL2

PLL1

Spread

Spectrum

48MHz
24MHz

IOAPIC

CPUCLK_F

CPUCLK 1

SDRAM (11:0)

PCICLK (4:0)
PCICLKF

SDRAM_F

X1

X2

BUFFER IN

XTAL
OSC

PCI
CLOCK
DIVDER

STOP

STOP

STOP

STOP

SDATA

SCLK

FS(3:0)

MODE

Control

Logic

Config.

Reg.

/2

REF(1:0)

LATCH

POR

2

12

5

4

4

* Internal Pull-up Resistor of 120K to VDD
** Internal Pull-down resistor of 120K to GND

3SF2SF1SF0SF

UPC

)zHM(

KLCICP

)zHM(
0000 00.0800.04
0001 00.5705.73
0010 13.3856.14
0011 28.6614.33
0100 00.30133.43
0101 10.21143.73
0110 10.8610.43
0111 32.00114.33

1000 00.02100.04
1001 99.41133.83
1010 99.90166.63
1011 00.50100.53
1100 00.04100.53
1101 00.05105.73
1110 00.42100.13
1111 99.23152.33

ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

VDD1

*PCI_STOP/REF0

GND

X1
X2

VDD2

*MODE/PCICLK_F

**FS3/PCICLK0

GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4

VDD2

BUFFER IN

GND

SDRAM11
SDRAM10

VDD3
SDRAM9
SDRAM8

GND

SDATA

SCLK

VDDL1
IOAPIC
REF1/FS2*
GND
CPUCLK_F
CPUCLK1
VDDL2
CLK_STOP#*
SDRAM_F
GND
SDRAM0
SDRAM1
VDD3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDD3
SDRAM6
SDRAM7
VDD4
48MHz/FS0*
24MHz/FS1*

ICS9248-98

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

2

ICS9248-98

Third party brands and names are the property of their respective owners.

Pin Descriptions

Notes:

1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor

to program logic Hi to VDD or GND for logic low.

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3

ICS92 48-98

Third party brands and names are the property of their respective owners.

General Description

The ICS9248-98 is a single chip clock solution for Desktop
designs. It provides all necessary clock signals for such a
system.

Spread spectrum may be enabled through I

2

C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-98
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.

Serial programming I

2

C interface allows changing functions,

stop clock programming and frequency selection.

Power Groups

VDD1 = REF, X1, X2
VDD2 = PCICLK_F, PCICLK
VDD3 = SDRAM, supply for PLL core
VDD4 = 24MHz, 48MHz
VDDL1 = IOAPIC
VDDL2 = CPUCLK 1, CPUCLK_F

Mode Pin - Power Management Input Control

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4

ICS9248-98

Third party brands and names are the property of their respective owners.

1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for

verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.

2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

3. The input is operating at 3.3V logic levels.

4. The data byte format is 8 bit bytes.

5. To simplify the clock generator I

2

C interface, the protocol is set to use only "Block-Writes" from the controller. The

bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.

6. At power-on, all registers are set to a default condition, as shown.

General I2C serial interface information

The information in this section assumes familiarity with I2C programming.

For more information, contact ICS for an I

2

C programming application note.

How to Write:

 Controller (host) sends a start bit.
 Controller (host) sends the write address D2

(H)

 ICS clock will acknowledge
 Controller (host) sends a dummy command code
 ICS clock will acknowledge
 Controller (host) sends a dummy byte count
 ICS clock will acknowledge
 Controller (host) starts sending first byte (Byte 0)

through byte 5

 ICS clock will acknowledge each byte one at a time.
 Controller (host) sends a Stop bit

How to Read:

 Controller (host) will send start bit.
 Controller (host) sends the read address D3

(H)

 ICS clock will acknowledge
 ICS clock will send the byte count
 Controller (host) acknowledges
 ICS clock sends first byte (Byte 0) through byte 5
 Controller (host) will need to acknowledge each byte
 Controller (host) will send a stop bit

Notes:

Controller (Host) ICS (Slave/Receiver)

Start Bit
Address

D3

(H)

AC

K

Byte Count

ACK

Byte

0

ACK

Byte 1

ACK

Byte

2

ACK

Byte

3

ACK

Byte 4

ACK

Byte

5

ACK

Stop Bit

How to Read:

Controller (Host) ICS (Slave/Receiver)

Start Bit
Address

D2

(H)

AC

K

Dummy Command Code

AC

K

Dummy Byte Count

AC

K

Byte 0

AC

K

Byte 1

ACK

Byte 2

AC

K

Byte 3

AC

K

Byte 4

AC

K

Byte 5

AC

K

Stop Bit

How to Write:

5

ICS92 48-98

Third party brands and names are the property of their respective owners.

Byte0: Functionality and Frequency Select Register (default = 0)

Serial Configuration Command Bitmap

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4:7tiB

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00000 00.0800.04
00001 00.5705.73
00010 13.3856.14
00011 28.6614.33
00100 00.30133.43
00101 10.21143.73
00110 10.8610.43
00111 32.00114.33
01000 00.02100.04
01001 99.41133.83
01010 99.90166.63
01011 00.50100.53
01100 00.04100.53
01101 00.05105.73
01110 00.42100.13
01111 99.23152.33

10000 00.53157.33
10001 99.92105.23
10010 00.62105.13
10011 00.81133.93
10100 89.51166.83
1010 1 00.5976.13
10110 00.0900.03
10111 10.5843.82
11000 00.66105.14
11001 10.06100.04
11010 99.45157.83
11011 59.74199.63
11100 89.54105.63
11101 89.34199.53
11110 99.14105.53
11111 10.83105.43

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Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.