ICST AV9248F-96-T, ICS9248F-96-T Datasheet

Integrated
Circuit
Systems, Inc.

ICS9248-96

Third party brands and names are the property of their respective owners.

Block Diagram

9248- 96 Rev A 2/7/00

Recommended Application:

810/810E type chipset.

Output Features:

• 2- CPUs @ 2.5V, up to 155MHz.

• 9 - SDRAM @ 3.3V, up to 155MHz including
1 free running

• 8 - PCICLK @ 3.3V

• 1 - IOAPIC @ 2.5V,

• 2 - 3V66MHz @ 3.3V, 2X PCI MHz

• 2 - 48MHz, @ 3.3V fixed.

• 1 - 24/48MHz, @3.3V selectable by I

2

C

• 1 - REF @v3.3V, 14.318MHz.

Features:

• Up to 157MHz frequency support

• Support FS0-FS3 strapping status bit for I

2

C read back.

• Support power management: Through Power down
Mode from I

2

C programming.

• Spread spectrum for EMI control ( ± 0.25% center).

• Uses external 14.318MHz crystal

Skew Specifications:

• CPU – CPU: <175ps

• SDRAM - SDRAM: < 250ps

• 3V66 – 3V66: <175ps

• PCI – PCI: <500ps

• CPU-SDRAM<500ps

• For group skew specifications, please refer to group
timing relationship.

Functionality

Pin Configuration

48-Pin 300mil SSOP

* These inputs have a 120K pull up to VDD.
** 60K pull-up to VDD on indicated input
1 These are double strength.

Frequency Generator & Integrated Buffers for Celeron & PII/III™

Additional frequencies selectable through I2C programming.

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0000 08.6602.00108.6604.3307.6104.33
0001 00.8600.20100.8600.4300.7100.43
0010 03.00103.00178.6634.3327.6134.33
0011 00.30100.30176.8633.4371.7133.43
0100 37.33103.00178.6634.3327.6134.33
0101 00.54157.80105.2752.6331.8152.63
0110 37.33103.00178.6634.3327.6134.33
0111 33.73100.30176.8633.4371.7133.43
100 0 00.04100.50100.0700.5305.7100.53
100 1 00.04100.04133.3976.6433.3276.64
1010 00.81100.81176.8733.9376.9133.93
101 1 00.42100.42176.2833.1476.0233.14
1100 07.33107.33131.9875.4482.2275.44
110 1 00.73100.73133.1976.5438.2276.54
1110 00.05105.21100.5705.7357.8105.73
1111 05.2757.80105.2752.6331.8152.63

Preliminary Product Preview

PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.

2

ICS9248-96

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

General Description

Pin Configuration

PIN NUMBER PIN NAME TYPE DESCRIPTION

FREQ_IOAPIC IN

If FREQ_APIC = 0, APIC Clock = PCICLK
If FREQ_APIC = 1, APIC Clock = PCICLK/2 (default)

REF0 OUT 14.318 MHz reference clock.

2, 9, 10, 18, 25, 30,

38

VDD PWR

3.3V Power supply for SDRAM output buffers , PCI output buffers,

r

eference output buffers and 48MHz output
3 X1 IN Crystal input,nominally 14.318MHz.
4 X2 OUT Crystal output, nominally 14.318MHz.

5, 6, 14, 21, 29, 34,

42

GND P WR Ground pin for 3V ou tpu ts .

8, 7 3V66 [1:0] OUT 3.3V Clocks

FS0 IN Frequency se lect pin.

PCICLK0 OUT PCI clock output

FS1 IN Frequency se lect pin.

PCICLK1 OUT PCI clock output

SEL24_48MHz# IN

Logic inputs frequency select I/O/USB output,
When a "0" is latched, output frequency = 48MHz

W

hen a "1" is latched, output frequency = 24MHz

PCICLK2 OUT PCI clock output

20, 19, 17, 16, 15 PCICLK [7:3] OUT PCI clock outputs.

22

PD# IN

Asynchronous active low input pin used to power down the device into a low
power s tate. The internal clocks are disabled and the VCO and th e crystal ar e

s

topped. The latency of the powe r down will not be greater than 3ms.

23 SCLK IN Clock input of I2C input, 5V tolerant input
24

SDATA IN Data input for I2C serial input, 5V tolerant input

FS3 IN Frequency se lect pin.

48MHz_0 OUT 48MHz output clocks

27 48MH z_1 OUT 48MHz output clocks

FS2 IN Frequency select pin.

24_48MHz OUT 24 or 48MHz output

31 SDRAM_F OUT

Free running SDRAM - used for feed back to chipset, should remain on

a

lways.

32, 33, 35, 36, 37,

39, 40, 41,

SDRAM [7:0] OUT SDRA M clock outputs

43 GND LCPU PWR Ground pin for the CPU clocks.

44, 45 CPUCLK [1:0] OUT CPU clock outputs.

46 VDD LCPU PWR Power pin for the CPUCLKs. 2.5V
47 IOAPIC OUT 2.5V clock output
48 VDD LAP IC PWR Power pin for the IOAPIC. 2.5V

1

26

28

11

12

13

Power Groups

GNDREF, VDDREF = REF0, X1, X2
GNDPCI , VDDPCI = PCICLK [9:0]
GNDSDR, VDDSDR = SDRAM [7:0], SDRAM_F,
supply for PLL core
GND3V66 , VDD3V66 = 3V66
GND48 , VDD48 = 48MHz, 24_48MHz,
VDDLAPIC = IOAPIC
GNDLCPU , VDDLCPU = CPUCLK [1:0]

The ICS9248-96 is the single chip clock solution for designs
using the 810/810E style chipset. It provides all necessary
clock signals for such a system.

Spread spectrum may be enabled through I

2

C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-96
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.

Serial programming I

2

C interface allows changing functions,

stop clock programming and frequency selection.

3

ICS92 48-96

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for

verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.

2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

3. The input is operating at 3.3V logic levels.

4. The data byte format is 8 bit bytes.

5. To simplify the clock generator I

2

C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.

6. At power-on, all registers are set to a default condition, as shown.

General I2C serial interface information

The information in this section assumes familiarity with I2C programming.

For more information, contact ICS for an I

2

C programming application note.

How to Write:

 Controller (host) sends a start bit.
 Controller (host) sends the write address D2

(H)

 ICS clock will acknowledge
 Controller (host) sends a dummy command code
 ICS clock will acknowledge
 Controller (host) sends a dummy byte count
 ICS clock will acknowledge
 Controller (host) starts sending first byte (Byte 0)

through byte 5

 ICS clock will acknowledge each byte one at a time.
 Controller (host) sends a Stop bit

How to Read:

 Controller (host) will send start bit.
 Controller (host) sends the read address D3

(H)

 ICS clock will acknowledge
 ICS clock will send the byte count
 Controller (host) acknowledges
 ICS clock sends first byte (Byte 0) through byte 5
 Controller (host) will need to acknowledge each byte
 Controller (host) will send a stop bit

Notes:

Controller (Host) ICS (Slave/Receiver)

Start Bit
Address

D3

(H)

ACK

Byte Count

ACK

Byte 0

ACK

Byte 1

ACK

Byte 2

ACK

Byte 3

ACK

Byte 4

ACK

Byte 5

ACK

Stop Bit

H

ow to Read:

Controller (Host) ICS (Slave/Receiver)

Start Bit
Address

D2

(H)

ACK

Dummy Command Code

ACK

Dummy Byte Count

ACK

Byte 0

ACK

Byte 1

ACK

Byte 2

ACK

Byte 3

ACK

Byte 4

ACK

Byte 5

ACK

Stop Bit

H

ow to Write:

4

ICS9248-96

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Byte0: Functionality and Frequency Select Register (default = 0)

Serial Configuration Command Bitmap

Note 1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
* These frequencies with spread enabled are equal to original Intel defined frequency with -0.5% down spread.

I2C is a trademark of Philips Corporation

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00001 00.8600.20100.8600.4300.7100.43retneC%52.0-/+
00010 03.00103.00178.6634.3327.6134.33retneC%52.0-/+
00011 00.30100.30176.8633.4371.7133.43retneC%52.0-/+
00100 37.33103.00178.6634.3327.6134.33retneC%52.0-/+
00101 00.54157.80105.2752.6331.8152.63retneC%52.0-/+
00110 37.33103.00178.6634.3327.6134.33retneC%52.0-/+
00111 33.73100.30176.8633.4371.7133.43retneC%52.0-/+
01000 00.04100.50100.0700.5305.7100.53retneC%52.0-/+
01001 00.04100.04133.3976.6433.3276.64retneC%52.0-/+
01010 00.81100.81176.8733.9376.9133.93retneC%52.0-/+
01011 00.42100.42176.2833.1476.0233.14retneC%52.0-/+
01100 07.33107.33131.9875.4482.2275.44retneC%52.0-/+
01101 00.73100.73133.1976.5438.2276.54retneC%52.0-/+
01110 00.05105.21100.5705.7357.8105.73retneC%52.0-/+
01111 05.2757.80105.2752.6331.8152.63retneC%52.0-/+
10000 00.5705.21100.5705.7357.8105.73retneC%52.0-/+
10001 00.3800.3876.7238.3129.638.31retneC%52.0-/+
10010 00.01100.01133.3776.6333.8176.63retneC%52.0-/+
10011 00.02100.02100.0800.0400.0200.04retneC%52.0-/+
10100 00.52100.52133.3876.1438.0276.14retneC%52.0-/+
1010 1 52.9688.30152.9636.4313.7136.43retneC%52.0-/+
10110 00.0700.50100.0700.5305.7100.53retneC%52.0-/+
10111 76.6700.51176.6733.8371.9133.83retneC%52.0-/+
11000 00.54100.54176.6933.8471.4233.84retneC%52.0-/+
11001 05.6657.9905.6652.3336.6152.33retneC%52.0-/+
11010 00.05100.05100.00100.0500.5200.05*retneC%52.0-/+
11011 57.9957.9905.6652.3336.6152.33*retneC%52.0-/+
11100 00.55100.55133.30176.1538.5276.15retneC%52.0-/+
11101 05.66105.66100.11105.5557.7205.55retneC%52.0-/+
11110 33.35100.51176.6733.8371.9133.83retneC%52.0-/+
11111 00.33157.9905.6652.3336.6152.33*retneC%52.0-/+

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