• Adjacent channel selectivityWide 78 dB typ.Wide 70 dB min.
–Middle 70 dB min.
Narrow 56 dB typ.Narrow 60 dB min.
Digital 63 dB typ.Digital 45 dB min.
• Spurious responseWide/Narrow 70 dBWide/Middle/Narrow 70 dB min.
Digital 65 dBµV emfDigital 70 dBµ Vemf min.
• IntermodulationWide 70 dB min.
–Middle 70 dB min.
Narrow 70 dB min.
Digital 71 dBµV emf min.
• Hum and noiseWide 50 dB typ.Wide 45 dB min.
–Middle 43 dB min.
Narrow 45 dB typ.Narrow 40 dB min.
Digital 55 dB typ.Digital 55 dB min.
• Audio output power
(at 5% distortion with a 4 Ω load)
• Audio output impedance4
4.0 W typ.3.5 W min.
Ω
Specifications are measured in accordance with TIA–603–B (for Wide and Narrow) or EN 300 166 (Digital) for FR6000.
Specifications are measured in accordance with EN 300 086 (for Wide, Middle and Narrow) or EN 300 166 (Digital) for FR6100.
All stated specifications are subject to change without notice or obligation.
1 - 2
SECTION 2 INSIDE VIEWS
1st mixer (DBM)
(D62, L27, 32)
Discriminator
(X3)
TX power AMP
(IC22)
Ref. OSC
(X1)
PLL IC (TX lopp)
(IC3)
• MAIN UNIT
(TOP VIEW)
IF IC
(IC5)
RX VCOs
PLL IC (RX loop)
(IC4)
2nd IF filter (Wide)
(FI1)
2nd IF filter (Narrow)
(FI2)
FUNCTION
(Ref.No.)
AF SW
(IC35)
AF AMP
(IC34)
DSP
(IC12)
Optional digital unit slot
FUNCTION
(Ref.No.)
• MAIN UNIT
(BOTTOM VIEW)
TX VCOs
Liner codec
(IC8)
FUNCTION
(IC40)
5V regulator (CPU5V)
(IC30)
Power SW (VCC line)
(Q57)
8V regulator (8V line)
(IC27)
8V regulator (T8V line)
(Q45)
5V regulator (+5V line)
(Q41)
CPU
(IC20)
CPU clock
(X5)
EEPROM
(IC21)
5V regulator (DSP5V line)
(IC39)
2 - 1
AF POWER AMP.
(IC509)
SPEAKER SW
(Q508)
• FRONT UNIT
ANALOG SW
(IC506)
LCD DRIVER
(IC500)
FRONT CPU
(IC503)
CLOCK OSC
(X501)
2 - 2
SECTION 3 DISASSEMBLY INSTRUCTION
1. Removing the front panel
q Unscrew 11 screws from the top cover.
P
0
P
1
P
2
P
3
P
4
e Disconnect the cable from the MAIN UNIT assembly, and remove the front panel.
w Unscrew 7 screws from the front panel.
P
0
P
1
P
2
P
3
P
4
P
0
P
1
P
2
P
3
P
4
2. Removing the MAIN UNIT assembly
q Uscrew 5 screws which settles the MAIN UNIT assembly.
w Turn the MAIN UNIT assembly upside down.
3. Removing the MAIN UNIT
q Unscrew 9 screws, and remove the cover.
(If you are going to install an optional unit, see page 4-1 for the installation.)
PWR TX RX
TX RX
PWR
PWR TX RX
(To be continued to next page)
3 - 1
MAIN
J4
Black
Black
Red
Red
w Unsolder 2 points at the ANT cases.
e Unscrew 4 screws from the ANT cases,
and remove them.
r Disconnect the flat cabe from J4 and the
speaker cable from J9.
Flat cable
J4
Disconnect
MAIN
Unsolder
ANT case
Unscrew
ANT case
t Unsolder 2 points at the bottom of ANT connectors.
y Unsolder 4 points at the PA module leads.
u Unscrew 2 screws from W4.
J9J9J9
Disconnect
i Remove the clip from the side of chassis.
o Unscrew 15 screws from the MAIN UNIT, then take off
the MAIN UNIT PCB from the chassis.
Unsolder 2 points
Black
Black
Red
Red
W4
Unscrew
W4
Unsolder 4 points
Clip
15 screws
3 - 2
SECTION 4 OPTIONAL UNIT INSTALLATION
Install UT-109R or UT-110R as follows.
q Disassembly the repeater until the MAIN UNIT is exposed. (See the page 3-1)
w Modify the patterns on the MAIN UNIT as below.
<MAIN UNIT (bottom side)>
A and F; Cut the pattern
e Remove the protective paper of optional unit, and install it to the J1 as below.
r Replace the cover, screws, etc. to recover the whole assembly.
B; Short the pattern
PWR TX RX
NOTE: When uninstalling the scrambler unit
Be sure to recover the disconnected or connected points, otherwise no TX modulation or AF output is available.
4 - 1
SECTION 5 CIRCUIT DESCRIPTION
5-1 TRANSMITTER CIRCUITS
TX PLL CIRCUIT
TX PLL IC (IC3) outputs resulting signal of phasecomparison of REF signal (15.3 MHz) and feedback OSC
signal from TX VCO. The phase-difference signal is passed
through the active loop fi lter (Q4, 10, 13)and applied to the
TX VCO. The voltage of TX LV is adjusted to appropr iate
one. The OSC signal of TX VCO is FM-modulated by applied
modulation signals.
TX VCO CIRCUITS
There are 2 VCOs; VCO for band LOW (Q23, D10, 14, L19)
and band HIGH (Q22, D9, 13, L18), and these VCO (=OSC
freq.) are switched by the VCO SW (Q27, 28). The OSC
frequencies of these VCO are adjusted (=Locked) by the TX
LV signal (Lock Voltage). The modulation signals applied to
the Var iable Capacitor (VD; D17 or D18) vary the capacitor
reactance of it for FM modulation. The output signals of
these VCOs are applied to the power AMP circuits via
buffers (Q24, 35).
A portion of these output signals are passed through the
doubler (Q33) to extract 2nd harmonics, then applied to the
PLL IC (IC3) via the LPF.
YGR/PA CIRCUITS
The output signals from TX VCOs are amplifi ed by pre-AMPs
(Q37, 38), the amplified the PA module (IC22) to obtain
required TX power. The power-amplified TX signals are
passed through the ANT SW (D44) and LPF (for harmonics
removal) then applied to the TX ANT.
APC CIRCUIT
D45, D48 and D49 detect the TX power and the detected
voltage are applied to the IC23 of APC circuit. Comparing
the detected voltage (in proportion to TX power) and power
setting voltage (as a reference voltage), IC23 adjusts the
bias (pin 2: VGG) of PA module to control the TX power.
MODULATION CIRCUITS
The audio signals from the Microphone (MIC signals) are
applied to the MIC AMP (IC25). The amplifi ed MIC signals
are passed through the SW IC (IC35) which signal selects
the source of MIC signals from J5 (from MIC) and from
D-SUB connector (DEXM).
5-2 RECEIVER CIRCUITS
RX PLL CIRCUIT
The RX PLL IC (IC4) outputs resulting signal of phasecomparison of REF signal from the TCXO (X2: 15.3 MHz)
and feedback OSC signal from RX VCO. The phasedifference signal is passed through the active loop fi lter (Q6,
11, 14) and applied to the RX VCO. The voltage of RX LV (lock
voltage) is adjusted to appropriate one by “RX LVA” signal.
A portion of reference frequency signal from the TCXO (X2:
15.3 MHz) is passed through the tripler (Q2) to extract 3rd
harmonics, then applied to theIF IC (IC5).
RX VCO
There are 2 VCOs; VCO for band LOW (Q21, D8, 16, L21)
and band HIGH (Q20, D7, 15, L20), and these VCO (=OSC
freq.) are switched by the VCO SW (Q26, 30). The OSC
frequencies of these VCO are adjusted (=Locked) by the RX
LV signal (Lock Voltage). The output signals of these VCOs
are applied to the 1st mixer (L27, 32, D62) via buffers (Q25,
34) and LO AMP (Q65).
A portion of these output signals are passed through the
buffer (Q25) doubler (Q32) to extract 2nd harmonics, then
applied to the PLL IC (IC4) via the LPF.
RF BPF CIRCUITS
RX signals from the RX ANT connector (J11) are passed
through the 1st stage of BPF (D28, 29, 31, 32, L44, 47)
then amplified by the RF AMP (Q36). The amplified RX
signals are passed through the 2nd stage of BPF to remove
unwanted signals for good image response then applied to
the 1st mixer (L27, 32, D62).
Being mixed with 1st LO from the RX VCO, the RX signals
are converted into the 46.35 MHz 1st IF signal. The 1st and
2nd stage of the BPF are tune to the pass band frequency
by applying the tracking voltage “T1” and “T2” from the DAC
(IC17). The gain of low noise RF AMP (Q36) is controlled
by the AGC circuit (Q39, D27) according to the RX signal
strength.
The MIC signals from the SW IC are amplifi ed by an AMP
(IC1) then applied to the LINEAR CODEC IC (IC8) where
the MIC signals are converted in to the digital signals. The
converted digital signals are processed (pre-emphasis,
limit, etc.) by the DSP (IC12), then recovered to the analog
audio signals. The AF signals are amplifi ed by IC1 and leveladjusted by Ele.VR (IC2), then applied to the TX VCO and
TCXO (X1) as the modulation signals.
SIGNALING (ENCODE)
The Continious Tone (CTCSS/DTCS), Single Tone (5-Tone/
DTMF/CW_ID) signals are encoded in the DSP (IC12), and
mixed with MIC signals, level-adjusted by Ele. VR (IC2), then
applied to the TX VCO and TCXO (X1) for modulation.
5 - 1
IF FILTER/IF AMP CIRCUITS
The 1st IF signal from the 1st mixer (L27, 32, D62) is
amplified by the post AMP (Q63, 64) and 1st stage of IF
AMP (Q7) then fi ltered by crystal fi lter (FI3 or FI4), and then
applied to the IF IC (IC5).
The crystal fi lters (FI3 or FI4) are switched by the “NWC1”
signal from the CPU (IC20) according to the RX mode; Wide
(Middle), Narrow and Digital.
<ANALOG RX>
Being mixed with the 2nd LO, the 1st IF signal is converted
into the 450 kHz 2nd IF signal then detected by the internal
quadrature detector (X3 as a discriminator) to demodulate.
The demodulated AF signals are amplifi ed by the AF AMP
(IC36), and applied to the LINER CODEC (IC8). The AF
signals are converted into the digital signal then processed
by the DSP (IC12) then recovered to the analog audio
signals.
The ceramic fi lters (FI1 or FI2) are switched by the “NWC2”
signal from the CPU (IC20) according to the RX mode; Wide
(Middle), Narrow and Digital.
5-3 OTHER CIRCUITS
POWER SUPPLY
The power supply is switched by Q57 (ON/OFF). 5V (REF5)
from the regulator (IC30) is passed through L58 to supply to
CPU. The 5V also supplies to other sections of the repeater
via Q41 as “+5V.”
8V from the regulator (IC27) are supplies to various circuits,
and also supplies to TX circuits as “T8V” and RX circuits as
“8V.”
5V from the regulator (IC39) supplies DSP as “DSP5” and
supplies logic circuits; CPU, DSP, etc. via regulators (IC13,
14, 15).
The regulator “F8V” (IC41) provides the supply for FRONT
UNIT.
COMPANDER
The compander in the DSP (IC12) compresses the
amplitude of MIC signals in TX, and expands in RX to
provide high quality recovered sounds.
<DIGITAL RX>
The 450 kHz 2nd IF signal is amplifi ed by IC7 then applied
to the DSP (IC12) via ADC (IC9) and digital demodulated.
The processed digital signal is converted into the analog
audio signal by the LINEAR CODEC (IC8).
AF AMPLIFIER CIRCUITS
The AF signals from the LINEAR CODEC are amplifi ed by
the AF AMP (IC36) and level-adjusted by DAC (IC2), then
applied to IC28 via IC29 to be power-amplifi ed.
SIGNALING (DECODE)
The Continious Tone (CTCSS/DTCS), Single Tone (5-Tone/
DTMF/CW_ID) signals in the demodulated AF signals are
decoded in the DSP (IC8).
LED
DS1 (BUSY), DS2(PWR) and DS3 (TX) indicate the
repeater’s status: Power ON, T/RX and Cloning.
5 - 2
5-4 CPU (M: IC20) PORT ALLOCATION
Pin
No.
140–144D0–D4DSP data bus line.I/O–
1–11D5–D15DSP data bus line.I/O–
15–28A1–A14DSP data bus line.I/O–
29HRWDSP data line.I/O–
32FANSCooling fan (CH: MF1) rotation detect.I"H"=While the cooling fan is rotating.
33TLEDTX indicator LED control signal.O"H"=TX
34LEDRRX indicator LED control signal.O"H"=Squelch open.
35PLSCKPLL (M: IC4) serial clock.O–
36PLSSOPLL (M:IC4) serial data.O–
41PWONPower line "VCC" control signal.O"H"=Power ON.
42AFON2AF power AMP. (M: IC28) control signal.O"H"=AF power AMP ON.
43AFONAF output select signal.O
44ESCLSerial clock to the EEPROM (M: IC21).O–
45ESDASerial data to the EEPROM (M: IC21).O–
46TXCTX power line "T8V" control signal.O"H"=TX
47RXCRX power line "R8V" control signal.O"H"=RX
48RPLSTRX PLL (M: IC4) strobe.O–
49TPLSTTX PLL (M: IC3) strobe.O–
50RUNLKRX PLL (M: IC4) unlock signal.I"L"=Unlocked
51TUNLKTX PLL (M: IC3) unlock signal.I"L"=Unlocked
52XCTSSerial data from the RS-232 line driver (M: IC26).I–
53XRTSSerial data to the RS-232 line driver (M: IC26).O–
55EXDAExternal D/A port.O–
56BEEPBeep sounds (square waves).O–
57–59OPV3–OPV1 Optional unit detect.I–
60MMUTMIC mute signal to the installed optional unit.O"H"=MIC mute
61HANGMicrophone hang-up detect.I"L"=Hang-up
62PTT[PTT] key input. (pull up)I–
63RMUTRX mute signal to the installed optional unit.O"H"=RX mute
64EXADExternal A/D port.I–
65TEMPTemperature detect.I–
68RLVINRX PLL lock voltage.I–
69BATVVoltage monitor (divided voltage of "VCC").I–
70TLVINTX PLL lock voltage.I–
71RSSIRSSI signal from the IF IC (M: 5).I–
74XTXDExternal data to the RS-232 driver (M: IC26).O–
75XRXDExternal data from the RS-232 driver (M: IC26).I–
76TMUTTX mute signal.O"H"=TX mute
77HINTDSP IC control signal.O–
78INT1DSP IC control signal.O–
79HRDYDSP IC control signal.O–
81HDS1DSP IC control signal.O–
82HDS2DSP IC control signal.O–
100RESCPU reset signal from the reset IC (F: IC501).O–
101–108 EXIO1–EXIO8 External data bus line.I/O+5 V pull-up
112POSW[PWR] key input. (pull-up)I–
113NOISNoise detect.I"H"=RX signal is absent (squelch close).
114CSFTClock frequency shift signal.O–
119SSOSerial data to the seri-para converter (M: IC31).O–
120SCKClock signal to the seri-para converter (M: IC31).O–
121EXIO9External data bus line.I/O+5 V pull-up
122DSDASerial data to the DAC (M: IC17).O–
LINE NAMEDESCRIPTION
IN/
OUT
"H= AF signals are output from the
[ACCESSORY CONNECTOR].
CONDITION
5 - 3
3-4 CPU (M: IC20) PORT ALLOCATION (continued)
Pin
No.
123DASTStrobe to the DAC (M: IC2).O–
125FMDAData from the FRONT CPU (F: IC502).I–
126MFDAData to the FRONT CPU (F: IC502).O–
127OPT2Port for optional unit.O–
128OPT1Port for optional unit.I–
129OPT3Port for optional unit.I–
131CSOPort for optional unit.O–
132CSIPort for optional unit.I–
133EXOEOutput enable signal to the seri-para converter (M: IC31).O–
134EXSTStrobe to the seri-para converter (M: IC31).O–
135DRESReset signal to the DSP IC (M: IC12).O–
136HCSDSP data line.I/O–
138GPIO2DSP data line.I/O–
139GPIO1DSP data line.I/O–
LINE NAMEDESCRIPTION
IN/
OUT
CONDITION
5 - 4
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