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Note
Before using this information and the product it supports, be sure to read the
general information under Appendix C.
First Edition (April 1998)
The following paragraph does not apply to the United Kingdom or any country
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3-3.PCMCIA PC Card Slot Pin Assignments....... 3-10
viii
Preface
This technical reference contains hardware and software interface
information specific to the IBM ThinkPad 600 computer. This
technical reference is intended for those who develop hardware and
software products for the computer. Users should understand
computer architecture and programming concepts.
This publication consists of the following sections and appendixes:
Section 1, “System Overview,” describes the system, features,
and specifications.
Section 2, “System Board,” describes the system-specific
hardware implementations.
Section 3, “Subsystems,” describes the hardware functions
specific to the ThinkPad 600 computer.
Appendix A, “System Resources,” describes the available
system resources for the computer and docking stations.
Appendix B, “System Management API (SMAPI) BIOS
Overview,” describes the system software interface built into the
system, called the System Management Application Program
Interface (SMAPI) BIOS, which controls the system information,
system configuration, and power management features of the
ThinkPad computer.
Appendix C, “Appendix C,” contains special notices and
trademark information.
An index is also included.
Attention
The term
should not be changed. Use of reserved areas can cause
compatibility problems, loss of data, or permanent damage to the
hardware. When the contents of a register are changed, the state of
the reserved bits must be preserved. Read the register first and
change only the bits that must be changed.
Copyright IBM Corp. 1998 ix
Reserved
describes certain signals, bits, and registers that
The IBM ThinkPad 600 computer (hereafter called the
computer
or the
computer
) is a notebook-size computer that features
ThinkPad
AT bus architecture. Each computer supports one UltraSlim Bay and
one internal hard disk drive. The ThinkPad 600 computer also
supports an internal CD-ROM drive or a diskette drive in the
UltraSlim Bay.
Programs can distinguish the foregoing computer model from other
ThinkPad models by reading the system ID:
Interrupt 15H
Function code (AH)=C0H.
Returns
ES:(BX+2) : Model Byte
ES:(BX+3) : Submodel Byte
The system microprocessor contains an internal cache and a cache
controller.
Figure 1-1 lists the model bytes, submodel bytes, and system clock
speed of the system board for each model.
ModelModel Byte
(Hex)
600FC0133 MHz
Submodel Byte
(Hex)
System Clock
Figure 1-1. Model and Submodel Bytes
For a listing of the other systems, refer to the
IBM Personal
System/2 and Personal Computer BIOS Interface
1-2 System Overview
.
System Board Devices and Features
Figure 1-2 lists the system board devices and their features. The
IBM Personal System/2 Hardware Interface Technical Reference
describes devices common to PS/2 products by type number.
DeviceTypeFeatures
Microprocessor–Intel Pentium processor with the MMX
External cache–512 KB (write back)
System timers1Channel 0: system timer
ROM subsystem–128 KB by 4 banks (1 KB equals 1024 bytes)
RAM subsystem–32 to 160 MB (1 MB equals 1,048,576 bytes)
CMOS RAM
subsystem
EEPROM
subsystem
Video subsystem–XGA video functions:
–128 bytes CMOS RAM with real-time
–1 K bits
technology
233 MHz
or
Intel Pentium II processor
233 or 266 MHz
Channel 1: refresh generation
Channel 2: tone generator for speaker
clock/calendar + 4 KB NVRAM
Up to 65,536 colors on the TFT XGA
(1024x768) LCD and HPA XGA (1024 x
768).
Up to 16,777,216 colors on an external
monitor
See “Video Subsystem” on page 3-2 for more
details on the video subsystem.
Figure 1-2 (Part 1 of 2). System Board Devices and Features
System Overview1-3
DeviceTypeFeatures
Interrupt controller115 levels of system interrupts
Keyboard/auxiliary
device controller
Diskette drive
controller
Serial controller
port
Parallel controller
port
Expansion bus
adapter (PCI-bus)
PCMCIA slots–Conforms to the standards for:
Modem subsystem–Is driven by:
Infrared subsystem–Supports:
Universal serial bus
(USB)
1Internal keyboard
2Supports:
2EIA-232-E interface (16550 compatible)
1Programmable as parallel port 1, 2, or 3
–Supports externally attached devices:
–Supports:
(interrupts are edge-triggered)
TrackPoint
Auxiliary device connector
Password security
3.5-in. diskette (1.44 MB)
3.5-in. diskette (1.2 MB)
3.5-in. diskette (720 KB)
Programmable as serial port 1, 2, 3, or 4
One 9-pin, D-sub connector
IEEE P1284-A compatible
Supports bidirectional input and output
Enhanced Parallel Port (EPP) compatible
Extended Capabilities Port (ECP) compatible
SelectaDock docking system
Port replicator
CardBus
Two Type I or II PC cards
One Type III PC card
MDSP 3780i
SRAM 32 Kb by 40 bits
Crystal Audio
Voice band CODEC for modem
Internal DAA
Internal omnidirectional microphone
ThinkPad IR/SIR/D-ASK (500 KHz) IR
USB input and output devices
Personal Computer Memory Card
International Association
Figure 1-2 (Part 2 of 2). System Board Devices and Features
1-4 System Overview
System Board I/O Address Map
Figure 1-3 is the I/O address map.
Address (Hex)Device
0000–001FDMA Controller (0–3)
0020, 0021Interrupt Controller (Master)
0022–002FReserved
0040–0043System Timer 1
0048–004BReserved
0060Keyboard, Auxiliary Device
0061System Control Port B
0062, 0066Slave Controller
0064Keyboard, Auxiliary Device
0070, 0071RT/CMOS and NMI Mask
0072, 0073Extended RT and CMOS
0074, 0075, 0076Reserved
0081–0083, 0087DMA Page Registers (0–3)
0089–008B, 008FDMA Page Registers (4–7)
0092System Control Port A
0096Reserved
0098System Flash ROM Control Register (DCR
00A0, 00A1Interrupt Controller (Slave)
00B2–00B3Power Management Register
00C0–00DFDMA Controller (4–7)
00F0–00FFReserved
0130–013FThinkPad Modem
0170–0177Secondary IDE Registers
01F0–01F7Primary IDE Registers
0201Joystick Port
0220–0233Audio Subsystem - Sound Blaster
0240–0253Audio Subsystem - Sound Blaster
026E, 026FSuper I/O Configuration Registers
0260–0273Audio Subsystem - Sound Blaster
0278–027AParallel Port 3
027B–027FReserved
0280–0283Audio Subsystem - Sound Blaster
02E8–02EFSerial Port 4
02E8–02EFIR Port 4
02F8–02FFSerial Port 2
02F8–02FFIR Port 2
0300–0303MIDI Port 1
0310–0313MIDI Port 2
0320–0323MIDI Port 3
2282)
Figure 1-3 (Part 1 of 2). System Board I/O Address Map
System Overview1-5
Address (Hex)Device
0330–0333MIDI Port 4
0350–035FThinkPad Modem
0376, 0377Secondary IDE Registers
0378–037AParallel Port 2
037B–037FReserved
0388–038BAudio Subsystem - FM Synthesizer
0398–0399Reserved
03B4, 03B5, 03BAVideo Subsystem
03BC–03BEParallel Port 1
03C0–03C5Video Subsystem
03C6–03C9Video DAC
03CA, 03CC, 03CE, 03CF,Video Subsystem
03D4, 03D5, 03DA,
03D8–03DA
03E0–03E1PCMCIA Interface (DCR 2959)
03E8–03EFSerial Port 3
03E8–03EFIR Port 3
03F0–03F5, 03F7Diskette-Drive Controller
03F6, 03F7Primary IDE Registers
03F8–03FFSerial Port 1
03F8–03FFIR Port 1
0530–0537Audio - WSS 1
0538–053FAudio Control Port 1
0604–060BAudio - WSS 2
0770–077FThinkPad Modem
0CF8–0CFBPCI Configuration Address Register
0CFC–0CFFPCI Configuration Data Register
0DB0–0DBFThinkPad Modem
0D38–0D3FAudio Control Port 2
0E80–0E87Audio - WSS 3
0E88–0E8FAudio Control Port 3
0F40–0F47Audio - WSS 4
0FF0–0FF7Audio Control Port 4
15E8–15EFPower Management Register
2120–21FFReserved
23C0–23C7Reserved
EF00–EF37Power Management Register
EFA0–EFADSMBus IO Space Register
F104Reserved
Figure 1-3 (Part 2 of 2). System Board I/O Address Map
1-6 System Overview
Specifications
Figure 1-4 to Figure 1-7 list the specifications for the computers.
Performance Specifications
Device/Cycle
Microprocessor233 or 266
L1 cache (64bit)
read/write hit
L2 cache (64bit) (for not all
models)
read hit (back-to-back)
write hit (back-to-back)
Memory (64bit) (see Note)
read, page hit
read, bank miss
read, page miss
posted write
write retire rate from
write buffer
Note:
The cycle times shown for access to system
board RAM are based on 66 MHz memory bus
(SDRAM, CAS LATENCY=2)
Clock Counts
(66 MHz)
MHz
1 CPUCLK
3-1-1-1(1-1-1-1)
5-1-1-1
8-1-1-1
11-1-1-1
3-1-1-1
-1-1-1
Figure 1-4. Performance Specifications
System Overview1-7
Physical Specifications
Size
Width:300.0 mm (12 in.)
Depth: 240.0 / 254.0 mm (9.6 / 10.16 in.)
Height: 36.5 mm (1.46 in.)
Weight by model (approximate value)
Air Temperature
Humidity
Maximum altitude : 3,048 m (10,000 ft) in unpressurized conditions
Heat output: 56 W
Acoustical readings (see Figure 1-7 on page 1-9)
Electrical (see Figure 1-6 on page 1-9)
Electromagnetic compatibility: FCC class B
With battery pack installed.
This is the maximum altitude at which the specified air temperatures apply. At
higher altitudes, the maximum air temperatures are lower than those specified.
OperateShows the value while using the hard disk drive.
All measurements made in accordance with ANSI S12.10 and reported in
conformance with ISO 9296.
in belsL
WAd
4.604.3037.534.031.028.0
Is the declared sound power level for the random sample of
machines.
Is the mean value of the A-weighted sound pressure levels at the
operator position (if any) for the random sample of machines.
Is the mean value of the A-weighted sound pressure levels at the
1 meter position for the random sample of machines.
in dB<LpA>m in dB
pAm
Figure 1-7. Acoustical Readings
System Overview1-9
Power Supply
The power supply converts the ac voltage to dc voltage and provides
power for the following:
System board set
Diskette drive
Hard disk drive
CD-ROM drive
Auxiliary devices
Keyboard
LCD panel
PCMCIA cards
Voltages
The power supply generates six different dc voltages: VCC5M,
VCC3M, VCC12, and VCCSW. Figure 1-8 shows the maximum
current for each voltage.
OutputVoltage (V dc)Current (A)
VCC5M+5.05.0
VCC3M+3.35.0
VCC12+12.00.50
VCCSW+5.00.006
Figure 1-8. Power Supply Maximum Current
1-10 System Overview
Output Protection
A short circuit placed on any dc output (between two outputs or
between an output and a dc return) latches all dc outputs into a
shutdown state, with no hazardous condition to the power supply.
If an overvoltage fault occurs in the power supply, the power supply
latches all dc outputs into a shutdown state before any output
exceeds 135% of the nominal value of the power supply.
Voltage Sequencing
When power is turned on, the output voltages reach their operational
voltages within 2 seconds.
Power Supply Connector
The following connector is used with the AC Adapter. The total
power capacity of this connector must not exceed 4.0 A.
Refer to Figure 1-9 for the appropriate adapter pin assignments.
PinVoltage
1+7.0 V dc to +17.0 V dc (depending on charging conditions)
2Ground
Figure 1-9. Voltage Pin Assignments for the 56W AC Adapter
System Overview1-11
Battery Pack
The ThinkPad computer uses a lithium-ion (Li-ion) battery pack that
meets the following electrical specifications:
Nominal Voltage+10.8 V dc
Capacity (average)3.2 ampere hours (AH)
ProtectionOvercurrent protection
This section describes the microprocessor, connectors, memory
subsystems, and miscellaneous system functions and ports for the
ThinkPad 600 computer.
Microprocessor
The ThinkPad 600 uses the Intel Pentium II 233 MHz processor
with MMX technology or the Intel Pentium233 or 266 MHz
processor.
The processor has a 32-bit address bus and a 64-bit data bus. It is
software-compatible with all previous microprocessors. The
processor has an internal, split data and instruction, 32-KB
write-back cache. It includes pipelined math coprocessor functions
and superscalar architecture (two execution units).
Cache Memory Operation
In addition to the 32 KB of internal Level 1 (L1) cache memory in the
microprocessor, the system board of the ThinkPad 600 computer
contains an additional 512 KB of external Level 2 (L2) cache
memory.
The cache memory in the Intel Pentium II microprocessor and the L2
external cache memory enable the microprocessor to read
instructions and data much faster than if the microprocessor had to
access system memory. When an instruction is first used or data is
first read or written, it is transferred to the cache memory from main
memory. This enables future accesses to the instructions or data to
occur much faster.
The cache is disabled and empty when the microprocessor comes
out of the reset state. The cache is tested and enabled during the
power-on self-test (POST).
The cache memory in the Intel Pentium II microprocessor is loaded
from system memory in 32-byte increments, each referred to as a
cache line
reference to any byte contained in a cache line results in the entire
line being read into the cache memory (if the data was not already in
the cache). When the microprocessor gives up control of the system
2-2 System Board
. A cache line is aligned on a paragraph boundary. A
bus, the cache memory enters “snoop” mode and monitors all write
and read operations. If memory data is written to a location in the
cache and the cache line is in the “modified” state, the corresponding
cache line is written back to system memory and invalidated.
When the microprocessor performs a memory read, the data address
is used to find the data in the cache. If the data is found (a hit), it is
read from the cache memory and no external bus cycle occurs. If
the data is not found (a miss), an external bus cycle is used to read
the data from system memory. If the address of the missed data is
in cacheable address space, the data is stored in the cache memory
and the remainder of the cache line is read.
When the microprocessor performs a memory write, the data
address is used to search the cache. If the address is found (a hit),
the data is written to the cache and no external bus cycle is used to
write the data to system memory. (If the address of the write
operation was not in the cache memory but was in cacheable
address space, the data is read back into the cache memory and the
remainder of the cache line is read.)
Cacheable Address Space
Cacheable address space is defined as system memory that resides
on the system board (0–640 KB and 1 MB–256 MB). Cacheability of
system memory is up to 64 MB for Pentium or 512 MB for Pentium II
in the L2 cache. Nothing in address range hex A0000–BFFFF, I/O
address space, or memory in any AT slot is cached.
ROM address space (hex C0000–C9FFF and F0000–FFFFF) is L1
cacheable for
range is already in cache memory and the address range is written
to, the cached line is invalidated and is read again from RAM, where
the BIOS is shadowed.
Bus Adapter
When the computer is attached to the ThinkPad SelectaDock III
docking system, the PCI adapters or AT-bus adapters can be used
through the docking system.
code read operations only
. If data in this address
System Board2-3
Keyboard/Mouse Connector
Each ThinkPad computer has a keyboard/mouse connector, where
the IBM mouse, keyboard, or numeric keypad is connected.
Signals
The keyboard and mouse signals are driven by open-collector drivers
pulled to 5 V dc through a pull-up resistor. Figure 2-1 lists the
signals.
Sink current1 mAMaximum
High-level output voltage5.0 V dc minus pullupMinimum
Low-level output voltage0.5 V dcMaximum
High-level input voltage2.0 V dcMinimum
Low-level input voltage0.8 V dcMaximum
Figure 2-1. Keyboard and Mouse Signals
Connector
The keyboard/mouse connector uses a 6-pin, miniature DIN
connector.
56
34
12
PinI/OSignal Name
1I/OMouse Data
2I/OKeyboard Data
3–Ground
4–+5 V dc
5I/OMouse Clock
6I/OKeyboard Clock
Note: The maximum current for +5 V dc (pin 4) is 0.5 A.
Scan Codes
Figure 2-3 shows the key numbers assigned to keys on the 85-key
keyboard (for the U.S.).
2-4 System Board
Figure 2-3. Key Numbers for the 85-Key Keyboard
Figure 2-4 shows the key numbers assigned to keys on the 86-key
keyboard (for countries other than the U.S.and Japan).
Figure 2-4. Key Numbers for the 86-Key Keyboard
Figure 2-5 on page 2-6 shows the key numbers assigned to the
keys on the 90-key keyboard (for Japan).
System Board2-5
Figure 2-5. Key Numbers for the 90-Key Keyboard
For scan codes assigned to each numbered key, refer to the
Personal System/2 Hardware Interface Technical Reference
IBM
.
Keyboard ID
The keyboard ID consists of 2 bytes: hex 83AB (the built-in keyboard
with the external numeric keypad) or hex 84AB (the built-in keyboard
only). Interrupt 16H, function code (AH)=0AH, returns the keyboard
ID in BX.
2-6 System Board
Figure 2-6 shows the key numbers assigned to keys on the external
numeric keypad. For scan codes assigned to each numbered key,
refer to the
Reference
IBM Personal System/2 Hardware Interface Technical
.
9095
91
92
93
99
96
97
98
100
101
102
103
104
105
106
108
Figure 2-6. Key Numbers for the External Numeric Keypad
Displayable Characters and Symbols
For displayable characters and symbols that are keyable from the
keyboard, refer to the
Technical Reference
IBM Personal System/2 Hardware Interface
.
System Board2-7
Hard Disk Drive Connector
The hard disk drive connected to the system board is removable.
Figure 2-7 shows the pin assignments for the connector on the
system board.
Figure 2-7. Hard Disk Drive Connector Pin Assignments
External Bus Connector
The docking station is connected through the 240-pin external bus
connector on the rear panel. This connector is installed on the
system board and has the following pin assignments:
Figure 2-8 (Part 2 of 2). 240-Pin External Bus Connector Pin
Assignments
2-10 System Board
UltraSlim Bay Connector
The removable diskette drive or CD-ROM drive can be connected to
the UltraSlim Bay connector on the system board. This connector
has the following pin assignments.
The ROM subsystem consists of four banks of 128-KB memory.
ROM is active when power is turned on and is assigned to the top of
the first and last 1 MB of address space (hex 000F0000–000FFFFF
and hex FFFF0000–FFFFFFFF). After POST checks that system
memory is operating correctly, the ROM code is copied to RAM at
the same address space, and ROM is disabled.
RAM Subsystem
The RAM subsystem on the system board starts at address
hex 00000000 of the address space. The RAM subsystem for the
ThinkPad 600 computer is 64 bits wide.
The 32-MB base memory is on the system board. Two 144-pin
8-byte dual inline memory module (DIMM) connectors are provided
on the system board. Both connectors accept an 8-MB, a 16-MB, a
32-MB, or a 64-MB DIMM. The memory capacity can be increased
up to 160 MB.
The total amount of usable memory is less than the amount of
memory installed because of ROM-to-RAM remapping and power
management.
System Board2-15
System Memory Map
Memory is mapped by the memory controller registers.
Figure 2-11 shows the memory map for a correctly functioning
system. Memory can be mapped differently if POST detects an error
in system board memory or RT/CMOS RAM. In the figure, the
variable x represents the number of 1-MB blocks of system board
memory starting at or above the hex 100000 boundary.
Hex Address RangeFunction
00000000 to 0009FFFF640-KB system board RAM
000A0000 to 000BFFFFVideo RAM
000C0000 to 000C9FFFSystem board video BIOS ROM mapped to
000C8000 to 000EFFFFChannel ROM
000F0000 to 000FFFFF64-KB system board ROM mapped to RAM
00100000 to (00100000 +
MB)
FFFF0000 to FFFFFFFF64-KB system board ROM
Figure 2-11. System Memory Map
RAM
x
x
MB system board RAM
(same as 000F0000 to 000FFFFF)
2-16 System Board
System Board Memory for the DIMM Connectors
The system board has two DIMM connectors.
Figure 2-12 shows the pin assignments for the DIMM connector.
The RT/CMOS RAM (real-time clock/complementary metal-oxide
semiconductor RAM) module contains the real-time clock and 128
bytes of CMOS RAM. The clock circuitry uses 14 bytes of this
memory; the remainder is allocated to configuration and
system-status information. A battery is built into the module to keep
the RT/CMOS RAM active when the power supply is not turned on.
In addition to the 128 bytes of CMOS/RAM, a CMOS/RAM extension
of 4 KB is provided for configuration and other system information.
Figure 2-13 lists the RT/CMOS RAM bytes and their addresses.
Address (Hex)RT/CMOS RAM Bytes
000–00DReal-time clock
00EDiagnostic status
00FShutdown status
010Diskette drive type
011Hard disk 2 and 3 drive type
012Hard disk 0 and 1 drive type
013Reserved
014Equipment
015, 016Low and high base memory
017, 018Low and high expansion memory
019Hard disk 0 extended byte
01AHard disk 1 extended byte
01BHard disk 2 extended byte
01CHard disk 3 extended byte
01D–02DReserved
02E, 02FChecksum
030, 031Low and high usable memory above 1 MB
032Date-century
033–07FReserved
Figure 2-13. RT/CMOS RAM Address Map
2-18 System Board
RT/CMOS Address and NMI Mask Register (Hex 0070)
The NMI mask register is used with the RT/CMOS data register (hex
0071) to read from and write to the RT/CMOS RAM bytes.
Attention
The operation following a write to hex 0070 should access hex 0071;
otherwise, intermittent failures of the RT/CMOS RAM can occur.
BitFunction
7NMI mask
6–0RT/CMOS RAM address
Figure 2-14. RT/CMOS Address and NMI Mask Register (Hex 0070)
Bit 7When this write-only bit is set to 1, the NMI is masked
(disabled). This bit is set to 1 by a power-on reset.
Bits 6–0These bits are used to select RT/CMOS RAM
addresses.
RT/CMOS Data Register (Hex 0071)
The RT/CMOS data register is used with the RT/CMOS address and
NMI mask register (hex 0070) to read from and write to the
RT/CMOS RAM bytes.
BitFunction
7–0RT/CMOS data
Figure 2-15. RT/CMOS Data Register (Hex 0071)
System Board2-19
RT/CMOS RAM I/O Operations
During I/O operations to the RT/CMOS RAM addresses, you should
mask interrupts to prevent other interrupt routines from changing the
RT/CMOS address register before data is read or written. After I/O
operations, you should leave the RT/CMOS address and NMI mask
register (hex 0070) pointing to status register D (hex 00D).
Attention
The operation following a write to hex 0070 should access hex 0071;
otherwise, intermittent failures of the RT/CMOS RAM can occur.
Writing to the RT/CMOS RAM requires the following:
1. Write the RT/CMOS RAM address to the RT/CMOS address and
NMI mask register (hex 0070).
2. Write the data to the RT/CMOS data register (hex 0071).
3. Write the address, hex 0F, to the RT/CMOS and NMI mask
register; this leaves hex 0070 pointing to the shutdown status
byte (hex 0F).
4. Read address hex 0071 to restore the RT/CMOS.
Reading from the RT/CMOS RAM requires the following steps:
1. Write the RT/CMOS RAM address to the RT/CMOS and NMI
mask register (hex 0070).
2. Read the data from the RT/CMOS data register (hex 0071).
3. Write the address, hex 0F, to the RT/CMOS and NMI mask
register; this leaves hex 0070 pointing to the shutdown status
byte (hex 0F).
4. Read address hex 0071 to restore the RT/CMOS.
2-20 System Board
Real-Time Clock Bytes (Hex 000–00D):
Bit definitions and
addresses for the real-time clock bytes are shown in Figure 2-16.
Note: The setup program initializes status registers A and B when
the time and date are set. Interrupt 1AH is the BIOS
interface to read and set the time and date; it initializes the
registers in the same way that the setup program does.
Status Register A (Hex 00A)
BitFunction
7Update in progress (UIP)
6-4Division Chain Select (DVx)
3–0Rate-selection bits
Figure 2-17. Status Register A (Hex 00A)
Bit 7This bit is a status flag that can be monitored. If this bit
is 1, the update transfer will soon occur. If this bit 0, the
update transfer will not occur for at least 244 µs.
Bits 6–4These bits control the divider chain for the oscillator.
Bits 3–0These bits allow the selection of a divider output
Bit 7If set to 0, this bit updates the cycle, normally by
advancing the count at a rate of one cycle per second. If
set to 1, it immediately ends any update cycle in
progress, and the program can initialize the 14 time bytes
without any further updates occurring until this bit is set
to 0.
Bit 6This is a read/write bit that allows an interrupt to occur at
a rate specified by the rate and divider bits in status
register A. If set to 1, this bit enables the interrupt. The
system initializes this bit to 0.
Bit 5If set to 1, this bit enables the alarm interrupt. The
system initializes this bit to 0.
Bit 4If set to 1, this bit enables the update-ended interrupt.
The system initializes this bit to 0.
Bit 3If set to 1, this bit enables the square-wave frequency as
set by the rate-selection bits in status register A. The
system initializes this bit to 0.
Bit 2This bit indicates whether the binary-coded-decimal (BCD)
or binary format is used for time-and-date calendar
updates. If set to 1, this bit indicates binary format. The
system initializes this bit to 0.
Bit 1This bit indicates whether the hours byte is in 12-hour or
24-hour mode. If set to 1, this bit indicates the 24-hour
mode. The system initializes this bit to 1.
Bit 0If set to 1, this bit enables the daylight-saving-time mode.
If set to 0, this bit disables the daylight-saving-time mode,
and the clock reverts to standard time. The system
initializes this bit to 0.
2-22 System Board
Status Register C (Hex 00C)
BitFunction
7Interrupt request flag
6Periodic interrupt flag
5Alarm interrupt flag
4Update-ended interrupt flag
3–0Reserved
Figure 2-19. Status Register C (Hex 00C)
Note: Interrupts are enabled by bits 6, 5, and 4 in status register B.
Bit 7If set to 1, this bit indicates that an interrupt has
occurred; bits 6, 5, and 4 indicate the type of interrupt.
Bit 6If set to 1, this bit indicates that a periodic interrupt has
occurred.
Bit 5If set to 1, this bit indicates that an alarm interrupt has
occurred.
Bit 4If set to 1, this bit indicates that an update-ended
interrupt has occurred.
Bits 3–0These bits are reserved.
Status Register D (Hex 00D)
BitFunction
7Valid RAM
6–0Reserved
Figure 2-20. Status Register D (Hex 00D)
Bit 7This read-only bit monitors the internal battery. If set to
1, this bit indicates that the real-time clock has power. If
set to 0, it indicates that the real-time clock has lost
power and the data in CMOS is no longer valid.
Bits 6–0These bits are reserved.
System Board2-23
CMOS RAM Configuration
Figure 2-21 shows the bit definitions for the CMOS RAM
configuration bytes.
Diagnostic Status Byte (Hex 00E)
BitFunction
7Real-time clock power
6Configuration record and checksum status
5Incorrect configuration
4Memory size mismatch
3Hard disk controller/drive C initialization status
2Time status indicator
1, 0Reserved
Figure 2-21. Diagnostic Status Byte (Hex 00E)
Bit 7If set to 1, this bit indicates that the real-time clock has
lost power.
Bit 6If set to 1, this bit indicates that the checksum is incorrect.
Bit 5This bit indicates the results of a power-on check of the
equipment byte (hex 014). If set to 1, this bit indicates
that the configuration information is incorrect.
Bit 4If set to 1, this bit indicates that the memory size does not
match the configuration information.
Bit 3If set to 1, this bit indicates that the controller or hard disk
drive failed initialization.
Bit 2If set to 1, this bit indicates that the time is invalid.
Bits 1, 0These bits are reserved.
Shutdown Status Byte (Hex 00F):
power-on diagnostic programs.
2-24 System Board
This byte is defined by the
Diskette Drive Type Byte (Hex 010):
This byte indicates the type
of the installed diskette drive.
BitDrive Type
7–4Diskette drive type
3–0Reserved
Figure 2-22. Diskette Drive Type Byte (Hex 010)
Bits 7–4These bits indicate the diskette drive type.
Bits 7–4Description
0 1 1 0
0 1 0 0
Note: Combinations not shown are reserved.
Diskette drive (2.88MB)
Diskette drive (1.44MB)
Figure 2-23. Diskette Drive Type Bits 7–4
Bits 3–0These bits are reserved.
Hard Disk Drive Type Byte (Hex 011):
This byte defines the type
of hard disk drive installed. Hex 00 indicates that no hard disk drive
is installed.
BitDrive Type
7–4
3–0
Hard disk drive type 2
Hard disk drive type 3
Figure 2-24. Hard Disk Type Byte (Hex 011)
Bit 7–4Description
0 0 0 0
1 1 1 1
No drive installed for hard disk drive 2
Use CMOS 1BH for hard disk drive 2
Figure 2-25. Hard Disk Drive Type 2 (Bits 7–4)
Bit 3–0Description
0 0 0 0
1 1 1 1
No drive installed for hard disk drive 3
Use CMOS 1CH for hard disk drive 3
Figure 2-26. Hard Disk Drive Type 3 (Bits 3–0)
System Board2-25
Hard Disk Drive Type Byte (Hex 012):
This byte defines the type
of hard disk drive installed. Hex 00 indicates that no hard disk drive
is installed.
Bits 3–2These bits are reserved.
Bit 1If set to 1, this bit indicates that a coprocessor is
installed.
Bit 0If set to 1, this bit indicates that physical diskette drive 0
is installed.
Low and High Base Memory Bytes (Hex 015 and Hex 016):
low and high base memory bytes define the amount of memory
below the 640-KB address space.
The value in these bytes represents the number of 1-KB blocks of
base memory. For example, hex 0280 indicates 640 KB. The low
byte is hex 015; the high byte is hex 016.
The
Low and High Expansion Memory Bytes (Hex 017 and Hex
018):
of memory above the 1-MB address space.
The value in these bytes represents the number of 1-KB blocks of
expansion memory. For example, hex 0800 indicates 2048 KB. The
low byte is hex 017; the high byte is hex 018.
configuration checksum bytes contain the checksum character for
bytes hex 010 through hex 02D of the 64-byte CMOS RAM. The
high byte is hex 02E; the low byte is hex 02F.
The low and high expansion memory bytes define the amount
These bytes are reserved.
The
Low and High Usable Memory Bytes (Hex 030 and Hex 031):
The low and high usable memory bytes define the total amount of
contiguous memory from 1 MB to 20 MB.
The hexadecimal values in these bytes represent the number of
1-KB blocks of usable memory. For example, hex 0800 is equal to
2048 KB. The low byte is hex 30; the high byte is hex 31.
Date-Century Byte (Hex 032):
byte contain the binary-coded decimal value for the century. For
information about reading and setting this byte, refer to the
Personal System/2 and Personal Computer BIOS Interface
Reserved Bytes (Hex 033–07F):
Bits 7 through 0 of the date-century
IBM
.
These bytes are reserved.
System Board2-27
Miscellaneous System Functions and Ports
This section provides information about nonmaskable interrupts
(NMIs), the power-on password, and hardware compatibility.
Nonmaskable Interrupt (NMI)
The NMI signals the system microprocessor that a channel check
timeout has occurred. This situation can cause lost data or an
overrun error on some I/O devices. The NMI masks all other
interrupts. The interrupt return (IRET) instruction restores the
interrupt flag to the state it was in before the interrupt occurred. A
system reset causes a reset of the NMI.
The NMI requests from a system board channel check are subject to
mask control with the NMI mask bit in the RT/CMOS Address
register. See “RT/CMOS Address and NMI Mask Register (Hex
0070)” on page 2-19. The power-on default of the NMI mask is 1
(NMI disabled).
Attention
The operation following a write to hex 0070 should access hex 0071;
otherwise, intermittent failures of the RT/CMOS RAM can occur.
2-28 System Board
System Control Port A (Hex 0092)
BitFunction
7–4Reserved
3Security lock latch
2Reserved (must be set to 0)
1Alternate gate A20
0Alternate hot reset
Figure 2-31. System Control Port A (Hex 0092)
Bits 7–4These bits are reserved.
Bit 3This bit provides a security lock for the secured area of
RT/CMOS. If this bit is set to 1, the 8-byte power-on
password is locked by the software. After this bit is set
by POST, it can be cleared only by turning the system
off.
Bit 2This bit is reserved.
Bit 1This bit is used to enable the ‘address 20’ signal (A20)
when the microprocessor is in the real address mode. If
this bit is set to 0, A20 cannot be used in real mode
addressing. This bit is set to 0 during a system reset.
Bit 0This bit provides an alternative method of resetting the
system microprocessor. This alternative method
supports operating systems requiring faster operation
than that provided on the IBM Personal Computer AT.
Resetting the system microprocessor switches the
microprocessor from protected mode to real address
mode.
This bit is set to 0 by either a system reset or a write
operation. If a write operation changes this bit from 0 to
1, the ‘processor reset’ signal is pulsed after the reset
has occurred. While the reset is occurring, the latch
remains set so that POST can read this bit. If the bit is
set to 0, POST assumes that the system was just
powered on. If the bit is set to 1, POST assumes that
the microprocessor has been switched from protected
mode to real mode.
If bit 0 is used to reset the system microprocessor to the
real mode, use the following procedure:
1. Disable all maskable and nonmaskable interrupts.
System Board2-29
2. Reset the system microprocessor by writing a 1 to
bit 0.
3. Issue a Halt instruction to the system
microprocessor.
4. Reenable all maskable and nonmaskable interrupts.
If you do not follow this procedure, the results are
unpredictable.
Note: Whenever possible, use BIOS as an interface to
reset the system microprocessor to the real
mode. For more information about resetting the
system microprocessor, refer to the
IBM Personal
System/2 and Personal Computer BIOS
Interface
.
System Control Port B (Hex 0061)
Bit definitions for the write and read functions of this port are shown
in the following figures:
BitFunction
7–4Reserved
3Enable channel check
2Enable PCI SERR#
1Enable speaker data
0Timer 2 gate to speaker
Figure 2-32. System Control Port B (Hex 0061, Write)
BitFunction
7PCI SERR# (PCI error) status
6Channel check status
5Timer 2 output
4Toggles with each refresh request
3Enable channel check
2Enable PCI SERR# (PCI error) check
1Enable speaker data
0Timer 2 gate to speaker
Figure 2-33. System Control Port B (Hex 0061, Read)
Bit 7If a system board error occurs and the PCI SERR# line is
activated, this bit is set to 1.
2-30 System Board
Bit 6If set to 1, this bit indicates that a channel check has
occurred.
Bit 5If read, this bit indicates the condition of the timer/counter
2 ‘output’ signal.
Bit 4If read, this bit toggles for each refresh request.
Bit 3If set to 0, this bit enables the channel check. This bit is
set to 1 during a power-on reset.
Bit 2If set to 0, this bit enables the PCI SERR#.
Bit 1If set to 1, this bit enables the speaker data.
Bit 0If set to 1, this bit enables the timer 2 gate.
Power-On Password
RT/CMOS RAM has 8 bytes reserved for the power-on password
and the check character. The 8 bytes are initialized to hex 00. The
microprocessor can access these bytes only during POST. After
POST is completed, if a power-on password is installed, the
password bytes are locked and cannot be accessed by any program.
During power-on password installation, the password (1 to 7
characters) is stored in the security space.
Installing the password is a function of the built-in system program
Easy-Setup
when it is installed, changed, or removed. After the power-on
password has been installed, it can be changed or removed only
during POST.
The computer also can have a keyboard password. For more
information, see the keyboard and auxiliary device controller section
of the
Reference
. The power-on password does not appear on the screen
IBM Personal System/2 Hardware Interface Technical
.
Other Passwords
In addition to the power-on password, the computer provides two
more passwords:
The hard-disk password (HDP) protects the data on your
removable hard disk drive from being accessed by unauthorized
persons.
System Board2-31
The supervisor password protects the system information in
Easy-Setup from being changed by unauthorized persons.
For more information about these passwords, refer to the
User's Guide
.
ThinkPad
Selectable Drive-Startup Sequence
Selectable drive-startup (selectable boot) allows you to control the
startup sequence of the drives in your computer. The order in which
the computer looks for the drives for your operating system is the
drive-startup sequence
systems, you might want to change the drive-startup sequence to
load the operating system from the hard disk without first checking
the diskette drive, or to do a remote program load (RPL).
Attention
When changing your startup sequence, you must be extremely
careful when doing write operations (such as copying, saving, or
formatting). Your data or programs can be overwritten if you select
the wrong drive.
For more information about the selectable drive-startup sequence,
refer to the
ThinkPad User's Guide
. If you are working with multiple operating
.
2-32 System Board
Hardware Compatibility
The computer supports most of the interfaces used by the IBM
Personal Computer AT* and the Personal System/2* (PS/2*)
products. In many cases, the command and status organization of
these interfaces is maintained.
The functional interfaces for the computer are compatible with the
following:
The Intel 8259 interrupt controllers (edge trigger mode).
The Intel 8254 timers driven from 1.193 MHz (channels 0, 1, and
2).
The Intel 8237 DMA controller-address/transfer counters, page
registers, and status fields only. The command and request
registers, and the rotate and mask functions, are not supported.
The mode register is partially supported.
The NS16550 serial communications controller.
The Intel Pentium microprocessor.
The Intel 8086**, 8088**, 80286**, 80386**, and i486DX
microprocessors.
The Intel 8087**, 80287**, and 80387** math coprocessors.
The Intel 82077AA** diskette drive controller.
The keyboard interface at addresses hex 0060 and hex 0064.
Display modes supported by the IBM Monochrome Display and
Printer Adapter, the IBM Color/Graphics Monitor Adapter, and the
IBM Enhanced Graphics Adapter.
The parallel printer ports (Parallel 1, Parallel 2, and Parallel 3) in
compatibility mode.
System Board2-33
Error Codes
POST returns a three or more character code message to indicate
which test failed. Figure 2-34 lists the failure indicated with the
associated error code.
Error
Code
101Interrupt failure.
102Timer failure.
103Timer interrupt failure.
104Protected mode failure.
105Last 8042 command not accepted.
107NMI test failure.
108Timer bus test failure.
109Low meg-chip select test.
110Planar parity.
111I/O parity.
118Planar parity error logged.
127Cache error.
158A supervisor password is set, but no hard disk password is set.
159The hard disk password is not identical to the supervisor password.
161Dead battery.
162Check sum or configuration error.
163Date and time are not set; clock not updated.
173CMOS CRC error.
174Configuration error.
175Bad EEPROM CRC 1.
177Bad supervisor password checksum.
178EEPROM is not functional.
179NVRAM error log full.
183Supervisor password is needed.
184Bad power-on password checksum.
185Corrupted startup boot sequence.
186Inconsistency between EEPROM and security lock latch 2.
188Bad EEPROM CRC 2.
190Critically low battery condition detected.
191PM general error.
192Fan error.
195Configuration mismatch error found during hibernation wake-up.
196Critical error found during hibernation wake-up.
201Memory data error.
202Memory line error 00 through 15.
203Memory line error 16 through 23.
215Memory test failure on on-board memory.
221ROM to RAM remap error.
225Unsupported memory module is installed.
301Keyboard error.
Description
Figure 2-34 (Part 1 of 2). Error Codes
2-34 System Board
Error
Code
601Diskette drive or controller error.
602No valid boot record on diskette.
604Invalid diskette drive error.
1101Serial-A test failure.
1201Serial-B test failure.
1701Hard disk controller failure.
1780, 1790Hard disk 0 error.
1781, 1791Hard disk 1 error.
2401System board video error.
8081PCMCIA presence test failure (PCMCIA revision number also
8082PCMCIA register test failure.
8601System bus error (8042 mouse interface).
8602External mouse error.
8603System bus error or mouse error.
8611System bus error (I/F between 8042 and IPDC).
8612TrackPoint error.
8613System board or TrackPoint error.
I9990301Hard disk error.
I9990302Invalid hard disk boot record.
I9990303Bank-2 flash ROM checksum error.
I9990305No bootable device.
This section describes the video, DSP, audio, IR, and PCMCIA
subsystems of the ThinkPad 600 computer.
Copyright IBM Corp. 19983-1
Video Subsystem
The video subsystem consists of the XGA video controller, which
inteprets the monitor buffer. The video subsystem supports an IBM
thin-film transistor (TFT) or High Performance Addressing (HPA) as
follows:
Color DepthResolution
LCD
Type
XGA TFT
XGA HPA
VRAM
Size
2 MB65,53616,777,2161024×768
On the
LCD
On the
External
Monitor
On the
LCD
On the
External
Monitor
640×480
800×600
1024×768
The video subsystem also supports PS/2 analog displays without any
additional adapters.
ColorResolution
640×480
65,536 colors
16,777,216 colors
800×600
1024×768
640×480
800×600
3-2 Subsystems
Video Modes
The video subsystem supports the modes listed in Figure 3-1 and
Figure 3-2 on page 3-4:
Pels
320×200
320×350
320×400
640×200
640×350
640×400
320×200
640×200
640×350
640×400
320×200
640×200
640×350
640×350
640×480
640×480
320×200
Max
Pages88
Box Size
Buffer
Start
Address
8×8
8×14
B8000
B8000
888
8×16
8×8
B8000
B8000
8×14
B8000
811
8×16
8×8
B8000
B8000
8
8842211
8×8
8×14
8×16
B8000
B0000
B0000
8×8
8×8
A0000
A0000
8×14
8×14
A0000
A0000
8×16
8×16
A0000
A0000
1
8×8
A0000
Alpha-
numeric
Format
40×25
40×25
40×25
80×25
80×25
80×25
40×25
80×25
80×25
Colors1616
Type
Mode
(Hex)
A/N
0, 1
A/N
161616
A/N
0*, 1*
0#, 1#
A/N
2, 3
A/N
2*, 3*
1642
A/N
APA
2#, 3#
4, 5
APA
6
–
A/N
Figure 3-1. BIOS Video VGA Modes
80×25
40×25
80×25
80×25
80×25
–1616–16216
A/N
APA
APA
APA
APA
7*
7#DEF101112
80×30
80×30
40×25
256
APA
APA
APA
13
Subsystems 3-3
The following shows the video BIOS extended modes for the
ThinkPad 600 computer (containing a NeoMagic NM2160 video chip,
which inteprets 2 MB VRAM):
LCD
XGA o o o o o o o o o o o o o o o o o o o o o o
External Monitor
60 70 75 85
o
o
o
o
o
o
o
o
o
o
o o o
o o o
o o o
o o o
o o o
o o o
o o o
o o o
o
o
o o o
o o o
o o o
VESA Mode Number
(Hex)
10D
10E
120
121
122
123
124
125
100
101
110
111
112
102
103
113
114
115
104
105
116
117
Video Mode
320x200x32k
320x200x64k
320x240x256
320x240x64k
400x300x256
400x300x64k
512x384x256
512x384x64k
640x400x256
640x480x256
640x480x32k
640x480x64k
640x480xTrue
800x600x16
800x600x256
800x600x32k
800x600x64k
800x600xTrue
1024x768x16
1024x756x256
1024x768x32k
1024x768x64k
Figure 3-2. Video BIOS Extended Modes—NeoMagic NM2160
3-4 Subsystems
Modem Subsystem
The modem subsystem is composed of a digital signal processor
(DSP) and a data access arrangement (DAA):
General MIDI-compatible, 40-voice wave table synthesizer
The crystal audio subsystem provides 16-bit stereo audio with
high-quality FM music synthesis using four operators per voice. It
can record, compress, and play back voice, sound, and music with
built-in mixer controls. It consists of an embedded microprocessor,
16-bit stereo, 20-voice FM music synthesizer (or 18 simultaneous
4-operator voices), MIDI serial port compatible MPU401 UART mode,
DMA control, and ISA bus interface logic.
The AudioDrive provides the computer with the following audio
features:
High-quality audio (44.1-kHz MPC-2 16-bit audio)
General MIDI compatible, 32-voice wave table synthesizer
Sound Blaster support
MIDI Port Function
The MIDI port I/O address is as follows (only when docked to the
docking station):
I/O Address
0300–0301
0330–0331 (default)
3-6 Subsystems
Sound Blaster Support Function
The Sound Blaster support function provides three system settings:
I/O address, IRQ level, and DMA channel.
The I/O address can be selected from the following with the system
utility program. The IR subsystem uses one serial port address and
one IR controller register address:
I/O Address
03F8–03FFSerial port 1 (default)
02F8–02FFSerial port 2
03E8–03EFSerial port 3
02E8–02EFSerial port 4
03F8–03FFIR controller register 1 (default)
02F8–02FFIR controller register 2
03E8–03EFIR controller register 3
02E8–02EFIR controller register 4
IRQ Level and DMA Channel
The IR subsystem uses one IRQ level and two DMA channels for
ThinkPad mode. (Generic mode and Sharp mode do not require
DMA channels.)
IRQ LevelDMA Channel
IRQ 3
IRQ 4 (default)
IRQ 5
3-8 Subsystems
DMA 0
DMA 3
PC Card Subsystem
The system board has two PC Card slots that support the following
types of PC Card:
16 bit PC Card Type–I, II, III 5V, 3.3V
32 bit PC Card Type–I, II, III 5V, 3.3V
DMA is not supported.
The maximum current per slot is:
500 mA at 5 V dc
500 mA at 3.3 V dc
50 mA at 12 V dc
The PCI1250 PCI-to-Cardbus Controller Unit1 is used as the PC
Card controller in the system unit. The available interrupt levels are
IRQ 3, 4, 5, 7, 9, 10, 11, and 15.
The system unit resumes operation from suspend mode when it
receives the ‘RI_OUT’ signal. The Type I and Type II PC Cards can
be installed into either the upper or the lower slot, or into both slots
at the same time. The Type III PC Card, however, must be installed
only in the lower slot. The Type II PC card cannot be used in the
upper slot when a Type III PC Card is used.
The PC Card slots are designed according to the PC Card standard
released in March 1997.
1
Manufactured by Texas Instruments Corporation.
Subsystems 3-9
Pin Assignments
Figure 3-3 shows the pin assignments for the PCMCIA slots.
Figure 3-3 (Part 2 of 2). PCMCIA PC Card Slot Pin Assignments
The maximum current for +5 V dc is .5 A for each slot (including both
slots and V pp).
The maximum current for +12 V dc is .5 A for each slot (including
both slots and V pp). When the computer is in suspend mode, it
requires a current of 0.05 A.
Subsystems 3-11
IDE Channel on the UltraSlim Bay
A primary IDE channel is provided on the UltraSlim Bay connector,
providing two system settings:
I/O AddressIRQ Level
01F0–01F7
03F6
A secondary IDE channel is provided on the UltraSlim Bay
connector, providing two system settings:
I/O AddressIRQ Level
0170–0177
0376
If a hard disk is attached to the hard disk connector, an IDE device
on the UltraSlim Bay becomes a primary slave. (The hard disk
attached to the hard disk connector is the primary master.) If no
hard disk is attached to the hard disk connector, an IDE device on
the UltraSlim Bay is a primary master.
IRQ 14
IRQ 15
MIDI/Joystick Port
Note: To use a the MIDI/joystick port, you need a SelectaBase 600.
The MIDI/joystick port consists of the following functions:
MIDI port (in/out)
Joystick port
A standard game port connector is provided with a MIDI/joystick
cable.
MIDI Interface
A MIDI communication function is provided with the DSP subsystem.
The MIDI interface is compatible with MPU-401 (UART mode).
3-12 Subsystems
Joystick Interface
A joystick interface is provided at I/O address 0201. You can select
whether to enable or disable it with the ThinkPad Configurations
program.
Subsystems 3-13
3-14 Subsystems
Appendix A. System Resources
The following summarizes the available system resources for the
computer and docking stations. Values in parentheses are
alternative values that are selectable in the ThinkPad Configuration
program or application programs. The default values are highlighted.
System
Resource
Timer00040–0043NoneNone
Keyboard10060 and 0064NoneNone
Serial portDisabledDisabledNoneNone
(the PC Card
slot in the
docking
station:
03E2–03E3)
(Dependent on
the PC Card
type)
Memory
Address (Hex)
NoneNone
NoneNone
None0, 1, 3,
NoneNone
NoneNone
NoneNone
(Dependent on
the PC Card
type)
DMA
Channel
None
A-2
System
Resource
SCSI controller
SelectaDock I,
SelectaDock II,
SelectaDock III
The IDE hard
disk drive or
IDE CD-ROM
drive in the
docking station
The ISA
adapter card
(option card) in
the docking
station
The PCI
adapter card
(option card) in
the
SelectaDock
Note:
The I/O addresses in parentheses are also used when ECP is enabled as the
printer operating mode from the ThinkPad Configuration program.
When you enable ECP as the printer operating mode from the ThinkPad
Configuration program, you must select one value from the four selections
(including “disabled”).
Sound Blaster and MIDI share the same IRQ.
IRQ 15 and I/O 0170–0177 and 0376 are applicable to the UltraSlim Bay
devices only.
IRQI/O Address
11, 3, 4,
5, 7, 9,
10, 15,
or
disabled
15, 10,
11
(Refer to the manual that came with the adapter card.)
11, 3, 4,
5, 7, 9,
10, 15,
or
disabled
(Hex)
Automatically
set by the
system
0170–0177
and
0376,
01F0–01F7
and
3F6,
01E8–01EF
and
03EE, or
0168–016F
and
036E
(Refer to the adapter card manual.)
Memory
Address (Hex)
NoneNone
NoneNone
DMA
Channel
A-3
A-4
Appendix B. System Management API
(SMAPI) BIOS Overview
The ThinkPad Basic Input/Output System (BIOS) provides a special
software interface, called the System Management Application
Program Interface (SMAPI) BIOS, to control the following unique
features of the ThinkPad system:
System Information
This BIOS provides unique ThinkPad information, such as
the system identifier (system ID).
System Configuration
The ThinkPad SMAPI BIOS provides system configuration
control for such features as display device selection or
resource configuration for built-in devices.
Power Management
Through the SMAPI BIOS, the operating system or
application software can control the ThinkPad power
management features (the power mode or
suspend/hibernation/resume options).
“Header Image” on page B-4 describes how to use the SMAPI BIOS.
SMAPI BIOSB-3
Header Image
Systems that support SMAPI BIOS must provide the following header
image in the F000 segment system ROM area at the 16-byte
boundary. The client needs to search and find this SMAPI BIOS
header image to get the entry point for the service.
FieldOffset
Signature004 bytes'$SMB' (ASCII)
Version (Major)04Byte01h
Version (Minor)05Byte00h
Length06Byte20h
Checksum07Byte–
Information Word08Word–
Reserved 10AWord–
Real mode 16-bit offset to entry
point
Real mode 16-bit code segment
address
Reserved 210Word–
16-bit protected mode offset to
entry point
16-bit protected mode code
segment base address
32-bit protected mode offset to
entry point
32-bit protected mode code
segment base address
(in
Hex)
0CWord–
0EWord–
12Word–
14Double
18Double
1CDouble
LengthValue
–
words
–
words
–
words
SignatureASCII Code '$SMB' is stored at the top of the header
image.
Version (Major or Minor)
Indicates the SMAPI BIOS version.
LengthThe length of the header image.
Checksum Checksum byte area. The client verifies that this
header image is valid by using this checksum; the client
should check all header image bytes, and the result will
be zero bytes.
B-4 SMAPI BIOS
Information Word
This area identifies the following BIOS service level:
Information Word
Bit : Real/V86 mode interface support
Bit 1: 16-bit protected mode support
Bit 2: 32-bit protected mode support
Bit 3-15 : Reserved
Real Mode Entry Point
The entry point is specified in segment, offset format.
Clients using Real/V86 mode can use this area for the
far-call value.
16-Bit or 32-Bit Protected Mode Entry Point
The code base code address specifies the physical
address for this BIOS, and the client must prepare the
selector for this BIOS. The length should be 64 KB.
SMAPI BIOSB-5
Calling Convention
The client can invoke the SMAPI BIOS with a far-call to the entry
point that is specified in the header file. All parameters for the BIOS
and other results are stored in the client data area; the client needs
to prepare an input parameter and output parameter area in its data
area, and informs this area by pushing those pointers onto its stack
before the far-calls.
The SMAPI BIOS uses the stack/data area directly with the selector
when the BIOS is invoked. Therefore, the caller needs to define the
same privilege level as the BIOS.
Parameter Structure
The memory allocation for the input/output field should be prepared
by the caller. The input field specifies the function request to the
SMAPI BIOS, and the BIOS fills in the return value to the output
field.
Input Field
FieldOffset
(in Hex)
Major Function Number00Byte
Minor Function Number01Byte
Parameter 102Word
Parameter 204Word
Parameter 306Word
Parameter 408Double word
Parameter 50CDouble word
Length
B-6 SMAPI BIOS
Output Field
FieldOffset
(in Hex)
Return Code00Byte
Auxiliary Return Code01Byte
Parameter 102Word
Parameter 204Word
Parameter 306Word
Parameter 408Double word
Parameter 50CDouble word
The following hexadecimal return codes are stored in both the AL
(AX) register and the return code field of the output parameter:
No error
53SMAPI function is not available
81 Invalid parameter
86Function is not supported
9 System error
91System is invalid
92System is busy
ADevice error (disk read error)
A1Device is busy
A2Device is not attached
A3Device is disabled
A4Request parameter is out of range
A5Request parameter is not accepted
All other values are reserved.
SMAPI BIOSB-11
Function Description
System Information Service
Get System Identification
Input Field
Major Function Number Minor Function Number Parameter 1- Reserved
Parameter 2- Reserved
Parameter 3- Reserved
Parameter 4- Reserved
Parameter 5- Reserved
Output Field
Return Code- Error status
Auxiliary Return Code - Return value format
= - ASCII format
= 1 - Binary format
Parameter 1- System ID
Parameter 2- Country Code
Parameter 3- System BIOS revision
Parameter 4- (Bits 31-16) Reserved
- (Bits 15- ) System Management BIOS revision
Parameter 5- (Bits 31-16) Reserved
- (Bits 15- ) SMAPI BIOS Interface revision
B-12 SMAPI BIOS
Get CPU Information
Input Field
Major Function Number Minor Function Number - 1
Parameter 1- Reserved
Parameter 2- Reserved
Parameter 3- Reserved
Parameter 4- Reserved
Parameter 5- Reserved
Output Field
Return Code- Error status
Auxiliary Return Code - Reserved
Parameter 1- Reserved
Parameter 2- CPU ID
Major Function Number Minor Function Number - 3
Parameter 1- Reserved
Parameter 2- Reserved
Parameter 3- Reserved
Parameter 4- Reserved
Parameter 5- Reserved
Output Field
Return Code- Error status
Auxiliary Return Code - Docking station status
Bit - Docking status
= : Undock
= 1 : Dock
Bits 5-1 - Reserved
Bit 6 - Security key status
= : Lock position
= 1 : Unlock position
Bit 7 - Bus status
= : BUS isolated
= 1 : BUS connected
Parameter 1- Docking station ID
Parameter 2- Reserved
Parameter 3- Reserved
Parameter 4- Reserved
Parameter 5- Reserved
SMAPI BIOSB-15
Get UltraBay II Information
Input Field
Major Function Number Minor Function Number - 4
Parameter 1- Reserved
Parameter 2- Reserved
Parameter 3- Reserved
Parameter 4- Reserved
Parameter 5- Reserved
Output Field
Return Code- Error status
Auxiliary Return Code - Reserved
Parameter 1- Reserved
Parameter 2- (Bits 15-8) UltraBay device information
= : FDD
= 1 : Serial device
= 2 : TV tuner
= 1 : IDE device
= 2 : PCMCIA adapter
= 3 : Battery
= 4 : AC Adapter
= FE : No UltraBay
= FF : Unknown
(Bit 7- ) UltraBay device ID
= : FDD
= 1 : Cellular
= 2 : TV tuner
= 1 : CD-ROM
= 11 : IDE-HDD
= 12 : DVD
= 13 : ZIP
= FF : ID is not available
Parameter 3- Reserved
Parameter 4- Reserved
Parameter 5- Reserved
B-16 SMAPI BIOS
Get Slave Micro Control Unit Information
Input Field
Major Function Number Minor Function Number - 6
Parameter 1- Reserved
Parameter 2- Reserved
Parameter 3- Reserved
Parameter 4- Reserved
Parameter 5- Reserved
Output Field
Return Code- Error status
Auxiliary Return Code - Return value format
Major Function Number Minor Function Number - 7
Parameter 1- Reserved
Parameter 2- Reserved
Parameter 3- Reserved
Parameter 4- Reserved
Parameter 5- Reserved
Output Field
Return Code- Error status
Auxiliary Return Code - Reserved
Parameter 1- Reserved
Parameter 2- Current Status
Major Function Number Minor Function Number - 8
Parameter 1- Reserved
Parameter 2- Reserved
Parameter 3- Reserved
Parameter 4- Reserved
Parameter 5- Reserved
Return Code- Error status
Auxiliary Return Code - Reserved
Parameter 1- Reserved
Parameter 2- Refresh rate capability for
specified mode:
Bit - 6 Hz available
Bit 1 - 72Hz available
Bit 2 - 75Hz available
Bit 3 - 43Hz(I) available
Bit 4 - 56Hz available
Bit 5 - 7 Hz available
Bit 6 - 85Hz available
Bit 7 - 48Hz(I) available
Bits 8-15 : Reserved (must be B' ')
Parameter 3- Reserved
Parameter 4- Reserved
Parameter 5- Reserved
SMAPI BIOSB-21
System Configuration Service
Get Display Device State
Input Field
Major Function Number - 1
Minor Function Number Parameter 1- Request type