IBM SA14-2339-04 User Manual

PowerPC 405

Embedded Processor Core

User’s Manual

SA14-2339-04

Fifth Edition (December 2001)

This edition of

IBM PPC405 Embedded Processor Core User’s Manual

applies to the IBM PPC405 32-bit

embedded processor core, until otherwise indicated in new versions or application notes.

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Contents

Figures ......................................................................................................................................xv

Tables .....................................................................................................................................xviii

About This Book .....................................................................................................................xxi

Who Should Use This Book .............................................................................................................................. xxi

How to Use This Book ...................................................................................................................................... xxi

Conventions ..................................................................................................................................................... xxii

Chapter 1. Overview ...............................................................................................................1-1

PPC405 Features ............................................................................................................................................ 1-1

PowerPC Architecture ...................................................................................................................................... 1-3

The PPC405 as a PowerPC Implementation ................................................................................................... 1-3

Processor Core Organization ........................................................................................................................... 1-4

Instruction and Data Cache Controllers ...................................................................................................... 1-4

Instruction Cache Unit ............................................................................................................................ 1-4

Data Cache Unit ..................................................................................................................................... 1-5

Memory Management Unit .......................................................................................................................... 1-5

Timer Facilities ............................................................................................................................................ 1-6

Debug .......................................................................................................................................................... 1-7

Development Tool Support ..................................................................................................................... 1-7

Debug Modes ......................................................................................................................................... 1-7

Core Interfaces ............................................................................................................................................ 1-7

Processor Local Bus ............................................................................................................................... 1-8

Device Control Register Bus ................................................................................................................... 1-8

Clock and Power Management ............................................................................................................... 1-8

JTAG ....................................................................................................................................................... 1-8

Interrupts ................................................................................................................................................ 1-8

Auxiliary Processor Unit .......................................................................................................................... 1-8

On-Chip Memory .................................................................................................................................... 1-8

Data Types .................................................................................................................................................. 1-8

Processor Core Register Set Summary ...................................................................................................... 1-9

General Purpose Registers .................................................................................................................... 1-9

Special Purpose Registers ..................................................................................................................... 1-9

Machine State Register .......................................................................................................................... 1-9

Condition Register .................................................................................................................................. 1-9

Device Control Registers ........................................................................................................................ 1-9

Addressing Modes ..................................................................................................................................... 1-10

Chapter 2. Programming Model ............................................................................................2-1

User and Privileged Programming Models ...................................................................................................... 2-1

Memory Organization and Addressing ............................................................................................................. 2-1

Storage Attributes ........................................................................................................................................ 2-2

Registers .......................................................................................................................................................... 2-2

General Purpose Registers (R0-R31) ......................................................................................................... 2-5

Special Purpose Registers .......................................................................................................................... 2-5

Count Register (CTR) ............................................................................................................................. 2-6

Link Register (LR) .................................................................................................................................. 2-7

Fixed Point Exception Register (XER) .................................................................................................... 2-7

Special Purpose Register General (SPRG0–SPRG7) ............................................................................ 2-9

Processor Version Register (PVR) ....................................................................................................... 2-10

Condition Register (CR) ............................................................................................................................ 2-10

CR Fields after Compare Instructions ................................................................................................... 2-11

Contents v

The CR0 Field ...................................................................................................................................... 2-12

The Time Base .......................................................................................................................................... 2-13

Machine State Register (MSR) ................................................................................................................. 2-13

Device Control Registers .......................................................................................................................... 2-15

Data Types and Alignment ............................................................................................................................ 2-16

Alignment for Storage Reference and Cache Control Instructions ........................................................... 2-16

Alignment and Endian Operation .............................................................................................................. 2-17

Summary of Instructions Causing Alignment Exceptions ......................................................................... 2-17

Byte Ordering ............................................................................................................................................... 2-17

Structure Mapping Examples .................................................................................................................... 2-18

Big Endian Mapping ............................................................................................................................. 2-19

Little Endian Mapping ........................................................................................................................... 2-19

Support for Little Endian Byte Ordering .................................................................................................... 2-19

Endian (E) Storage Attribute ..................................................................................................................... 2-19

Fetching Instructions from Little Endian Storage Regions ................................................................... 2-20

Accessing Data in Little Endian Storage Regions ................................................................................ 2-21

PowerPC Byte-Reverse Instructions .................................................................................................... 2-21

Instruction Processing ................................................................................................................................... 2-23

Branch Processing ........................................................................................................................................ 2-24

Unconditional Branch Target Addressing Options .................................................................................... 2-24

Conditional Branch Target Addressing Options ........................................................................................ 2-24

Conditional Branch Condition Register Testing ........................................................................................ 2-25

BO Field on Conditional Branches ............................................................................................................ 2-25

Branch Prediction ...................................................................................................................................... 2-26

Speculative Accesses .................................................................................................................................... 2-27

Speculative Accesses in the PPC405 ....................................................................................................... 2-27

Prefetch Distance Down an Unresolved Branch Path .......................................................................... 2-28

Prefetch of Branches to the CTR and Branches to the LR ................................................................... 2-28

Preventing Inappropriate Speculative Accesses ....................................................................................... 2-28

Fetching Past an Interrupt-Causing or Interrupt-Returning Instruction ................................................. 2-28

Fetching Past tw or twi Instructions ...................................................................................................... 2-29

Fetching Past an Unconditional Branch ............................................................................................... 2-29

Suggested Locations of Memory-Mapped Hardware ........................................................................... 2-29

Summary ................................................................................................................................................... 2-30

Privileged Mode Operation ............................................................................................................................ 2-30

MSR Bits and Exception Handling ............................................................................................................ 2-31

Privileged Instructions ............................................................................................................................... 2-31

Privileged SPRs ........................................................................................................................................ 2-32

Privileged DCRs ........................................................................................................................................ 2-32

Synchronization ............................................................................................................................................. 2-33

Context Synchronization ........................................................................................................................... 2-33

Execution Synchronization ........................................................................................................................ 2-35

Storage Synchronization ........................................................................................................................... 2-35

Instruction Set ................................................................................................................................................ 2-36

Instructions Specific to the IBM PowerPC Embedded Environment ...................................................... 2-37

Storage Reference Instructions ................................................................................................................ 2-37

Arithmetic Instructions ............................................................................................................................... 2-38

Logical Instructions ................................................................................................................................... 2-39

Compare Instructions ................................................................................................................................ 2-39

Branch Instructions ................................................................................................................................... 2-40

CR Logical Instructions ........................................................................................................................ 2-40

Rotate Instructions ............................................................................................................................... 2-40

Shift Instructions ................................................................................................................................... 2-41

Cache Management Instructions .......................................................................................................... 2-41

Interrupt Control Instructions ..................................................................................................................... 2-41

TLB Management Instructions .................................................................................................................. 2-42

vi PPC405 Core User’s Manual

Processor Management Instructions ......................................................................................................... 2-42

Extended Mnemonics ................................................................................................................................ 2-42

Chapter 3. Initialization ..........................................................................................................3-1

Processor State After Reset ............................................................................................................................ 3-1

Machine State Register Contents after Reset ............................................................................................. 3-2

Contents of Special Purpose Registers after Reset .................................................................................... 3-3

PPC405 Initial Processor Sequencing ............................................................................................................. 3-3

Initialization Requirements ............................................................................................................................... 3-4

Initialization Code Example .............................................................................................................................. 3-5

Chapter 4. Cache Operations ................................................................................................4-1

ICU and DCU Organization and Sizes ............................................................................................................. 4-2

ICU Overview ................................................................................................................................................... 4-3

ICU Operations ............................................................................................................................................ 4-4

Instruction Cachability Control ..................................................................................................................... 4-5

Instruction Cache Synonyms ....................................................................................................................... 4-5

ICU Coherency ............................................................................................................................................ 4-6

DCU Overview ................................................................................................................................................. 4-6

DCU Operations .......................................................................................................................................... 4-6

DCU Write Strategies .................................................................................................................................. 4-7

DCU Load and Store Strategies .................................................................................................................. 4-8

Data Cachability Control .............................................................................................................................. 4-8

DCU Coherency .......................................................................................................................................... 4-9

Cache Instructions ........................................................................................................................................... 4-9

ICU Instructions ........................................................................................................................................... 4-9

DCU Instructions ....................................................................................................................................... 4-10

Cache Control and Debugging Features ....................................................................................................... 4-11

CCR0 Programming Guidelines ................................................................................................................ 4-13

ICU Debugging .......................................................................................................................................... 4-14

DCU Debugging ........................................................................................................................................ 4-15

DCU Performance .......................................................................................................................................... 4-16

Pipeline Stalls ............................................................................................................................................ 4-16

Cache Operation Priorities ........................................................................................................................ 4-17

Simultaneous Cache Operations ............................................................................................................... 4-17

Sequential Cache Operations ................................................................................................................... 4-18

Chapter 5. Fixed-Point Interrupts and Exceptions ..............................................................5-1

Architectural Definitions and Behavior ............................................................................................................. 5-1

Behavior of the PPC405 Processor Core Implementation ............................................................................... 5-2

Interrupt Handling Priorities ............................................................................................................................. 5-3

Critical and Noncritical Interrupts ..................................................................................................................... 5-5

General Interrupt Handling Registers .............................................................................................................. 5-7

Machine State Register (MSR) .................................................................................................................... 5-7

Save/Restore Registers 0 and 1 (SRR0–SRR1) ......................................................................................... 5-9

Save/Restore Registers 2 and 3 (SRR2–SRR3) ......................................................................................... 5-9

Exception Vector Prefix Register (EVPR) ................................................................................................ 5-10

Exception Syndrome Register (ESR) ........................................................................................................ 5-11

Data Exception Address Register (DEAR) ................................................................................................ 5-13

Critical Input Interrupts ................................................................................................................................... 5-13

Machine Check Interrupts .............................................................................................................................. 5-14

Instruction Machine Check Handling ......................................................................................................... 5-14

Data Machine Check Handling .................................................................................................................. 5-15

Data Storage Interrupt ................................................................................................................................... 5-16

Instruction Storage Interrupt .......................................................................................................................... 5-17

External Interrupt ........................................................................................................................................... 5-18

External Interrupt Handling ........................................................................................................................ 5-18

Contents vii

Alignment Interrupt ........................................................................................................................................ 5-19

Program Interrupt .......................................................................................................................................... 5-20

FPU Unavailable Interrupt ............................................................................................................................. 5-21

System Call Interrupt ..................................................................................................................................... 5-22

APU Unavailable Interrupt ............................................................................................................................. 5-22

Programmable Interval Timer (PIT) Interrupt ................................................................................................. 5-22

Fixed Interval Timer (FIT) Interrupt ................................................................................................................ 5-23

Watchdog Timer Interrupt .............................................................................................................................. 5-24

Data TLB Miss Interrupt ................................................................................................................................. 5-25

Instruction TLB Miss Interrupt ........................................................................................................................ 5-25

Debug Interrupt .............................................................................................................................................. 5-26

Chapter 6. Timer Facilities ....................................................................................................6-1

Time Base ....................................................................................................................................................... 6-1

Reading the Time Base .............................................................................................................................. 6-3

Writing the Time Base ................................................................................................................................. 6-3

Programmable Interval Timer (PIT) ................................................................................................................. 6-4

Fixed Interval Timer (FIT) ........................................................................................................................... 6-5

Watchdog Timer .............................................................................................................................................. 6-6

Timer Status Register (TSR) ........................................................................................................................... 6-8

Timer Control Register (TCR) .......................................................................................................................... 6-9

Chapter 7. Memory Management ..........................................................................................7-1

MMU Overview ................................................................................................................................................ 7-1

Address Translation ......................................................................................................................................... 7-1

Translation Lookaside Buffer (TLB) ................................................................................................................. 7-2

Unified TLB ................................................................................................................................................. 7-2

TLB Fields ................................................................................................................................................... 7-3

Page Identification Fields ....................................................................................................................... 7-3

Translation Field ..................................................................................................................................... 7-4

Access Control Fields ............................................................................................................................. 7-5

Storage Attribute Fields .......................................................................................................................... 7-5

Shadow Instruction TLB .............................................................................................................................. 7-6

ITLB Accesses ....................................................................................................................................... 7-7

Shadow Data TLB ....................................................................................................................................... 7-7

DTLB Accesses ...................................................................................................................................... 7-7

Shadow TLB Consistency ........................................................................................................................... 7-7

TLB-Related Interrupts .................................................................................................................................... 7-9

Data Storage Interrupt .............................................................................................................................. 7-10

Instruction Storage Interrupt ..................................................................................................................... 7-10

Data TLB Miss Interrupt ............................................................................................................................ 7-11

Instruction TLB Miss Interrupt ................................................................................................................... 7-11

Program Interrupt ...................................................................................................................................... 7-11

TLB Management .......................................................................................................................................... 7-11

TLB Search Instructions (tlbsx/tlbsx.) ....................................................................................................... 7-12

TLB Read/Write Instructions (tlbre/tlbwe) ................................................................................................. 7-12

TLB Invalidate Instruction (tlbia) ............................................................................................................... 7-12

TLB Sync Instruction (tlbsync) .................................................................................................................. 7-12

Recording Page References and Changes ................................................................................................... 7-12

Access Protection .......................................................................................................................................... 7-13

Access Protection Mechanisms in the TLB ............................................................................................... 7-13

General Access Protection ................................................................................................................... 7-13

Execute Permissions ............................................................................................................................ 7-14

Write Permissions ................................................................................................................................ 7-14

Zone Protection .................................................................................................................................... 7-14

Access Protection for Cache Control Instructions ..................................................................................... 7-16

Access Protection for String Instructions .................................................................................................. 7-17

viii PPC405 Core User’s Manual

Real-Mode Storage Attribute Control ............................................................................................................. 7-17

Storage Attribute Control Registers ........................................................................................................... 7-19

Data Cache Write-through Register (DCWR) ....................................................................................... 7-19

Data Cache Cachability Register (DCCR) ............................................................................................ 7-20

Instruction Cache Cachability Register (ICCR) ..................................................................................... 7-20

Storage Guarded Register (SGR) ......................................................................................................... 7-20

Storage User-defined 0 Register (SU0R) ............................................................................................. 7-20

Storage Little-Endian Register (SLER) ................................................................................................. 7-20

Chapter 8. Debugging ............................................................................................................8-1

Development Tool Support .............................................................................................................................. 8-1

Debug Modes ................................................................................................................................................... 8-1

Internal Debug Mode ................................................................................................................................... 8-1

External Debug Mode .................................................................................................................................. 8-2

Debug Wait Mode ........................................................................................................................................ 8-2

Real-time Trace Debug Mode ..................................................................................................................... 8-3

Processor Control ............................................................................................................................................ 8-3

Processor Status .............................................................................................................................................. 8-4

Debug Registers .............................................................................................................................................. 8-4

Debug Control Registers ............................................................................................................................. 8-4

Debug Control Register 0 (DBCR0) ........................................................................................................ 8-4

Debug Control Register1 (DBCR1) ......................................................................................................... 8-6

Debug Status Register (DBSR) .................................................................................................................. 8-7

Instruction Address Compare Registers (IAC1–IAC4) ................................................................................ 8-9

Data Address Compare Registers (DAC1–DAC2) .................................................................................... 8-9

Data Value Compare Registers (DVC1–DVC2) ........................................................................................8-10

Debug Events ............................................................................................................................................ 8-10

Instruction Complete Debug Event ............................................................................................................ 8-11

Branch Taken Debug Event ...................................................................................................................... 8-11

Exception Taken Debug Event .................................................................................................................. 8-11

Trap Taken Debug Event .......................................................................................................................... 8-12

Unconditional Debug Event ....................................................................................................................... 8-12

IAC Debug Event ....................................................................................................................................... 8-12

IAC Exact Address Compare ................................................................................................................ 8-12

IAC Range Address Compare .............................................................................................................. 8-12

DAC Debug Event ..................................................................................................................................... 8-13

DAC Exact Address Compare .............................................................................................................. 8-13

DAC Range Address Compare ............................................................................................................. 8-14

DAC Applied to Cache Instructions ....................................................................................................... 8-15

DAC Applied to String Instructions ........................................................................................................ 8-16

Data Value Compare Debug Event ........................................................................................................... 8-16

Imprecise Debug Event ............................................................................................................................. 8-19

Debug Interface ............................................................................................................................................. 8-19

IEEE 1149.1 Test Access Port (JTAG Debug Port) ..................................................................................8-19

JTAG Connector ............................................................................................................................................ 8-20

JTAG Instructions ...................................................................................................................................... 8-21

JTAG Boundary Scan ................................................................................................................................ 8-21

Trace Port ...................................................................................................................................................... 8-22

Chapter 9. Instruction Set .....................................................................................................9-1

Instruction Set Portability ................................................................................................................................. 9-1

Instruction Formats .......................................................................................................................................... 9-2

Pseudocode ..................................................................................................................................................... 9-2

Operator Precedence .................................................................................................................................. 9-5

Register Usage ................................................................................................................................................ 9-5

Alphabetical Instruction Listing ........................................................................................................................ 9-5

add .............................................................................................................................................................. 9-6

Contents ix

addc ............................................................................................................................................................ 9-7

adde ............................................................................................................................................................ 9-8

addi ............................................................................................................................................................. 9-9

addic ......................................................................................................................................................... 9-10

addic. ........................................................................................................................................................ 9-11

addis ......................................................................................................................................................... 9-12

addme ....................................................................................................................................................... 9-13

addze ........................................................................................................................................................ 9-14

and ............................................................................................................................................................ 9-15

andc .......................................................................................................................................................... 9-16

andi. .......................................................................................................................................................... 9-17

andis. ........................................................................................................................................................ 9-18

b ................................................................................................................................................................ 9-19

bc .............................................................................................................................................................. 9-20

bcctr .......................................................................................................................................................... 9-26

bclr ............................................................................................................................................................ 9-30

cmp ........................................................................................................................................................... 9-34

cmpi .......................................................................................................................................................... 9-35

cmpl .......................................................................................................................................................... 9-36

cmpli .......................................................................................................................................................... 9-37

cntlzw ........................................................................................................................................................ 9-38

crand ......................................................................................................................................................... 9-39

crandc ....................................................................................................................................................... 9-40

creqv ......................................................................................................................................................... 9-41

crnand ....................................................................................................................................................... 9-42

crnor .......................................................................................................................................................... 9-43

cror ............................................................................................................................................................ 9-44

crorc .......................................................................................................................................................... 9-45

crxor .......................................................................................................................................................... 9-46

dcba .......................................................................................................................................................... 9-47

dcbf ........................................................................................................................................................... 9-49

dcbi ........................................................................................................................................................... 9-50

dcbst ......................................................................................................................................................... 9-51

dcbt ........................................................................................................................................................... 9-52

dcbtst ........................................................................................................................................................ 9-53

dcbz .......................................................................................................................................................... 9-54

dccci .......................................................................................................................................................... 9-56

dcread ....................................................................................................................................................... 9-57

divw ........................................................................................................................................................... 9-59

divwu ......................................................................................................................................................... 9-60

eieio .......................................................................................................................................................... 9-61

eqv ............................................................................................................................................................ 9-62

extsb ......................................................................................................................................................... 9-63

extsh ......................................................................................................................................................... 9-64

icbi ............................................................................................................................................................. 9-65

icbt ............................................................................................................................................................ 9-66

iccci ........................................................................................................................................................... 9-67

icread ........................................................................................................................................................ 9-68

isync .......................................................................................................................................................... 9-70

lbz ............................................................................................................................................................. 9-71

lbzu ........................................................................................................................................................... 9-72

lbzux .......................................................................................................................................................... 9-73

lbzx ............................................................................................................................................................ 9-74

lha ............................................................................................................................................................. 9-75

x PPC405 Core User’s Manual

lhau ............................................................................................................................................................ 9-76

lhaux .......................................................................................................................................................... 9-77

lhax ............................................................................................................................................................ 9-78

lhbrx ........................................................................................................................................................... 9-79

lhz .............................................................................................................................................................. 9-80

lhzu ............................................................................................................................................................ 9-81

lhzux .......................................................................................................................................................... 9-82

lhzx ............................................................................................................................................................ 9-83

lmw ............................................................................................................................................................ 9-84

lswi ............................................................................................................................................................ 9-85

lswx ........................................................................................................................................................... 9-87

lwarx .......................................................................................................................................................... 9-89

lwbrx .......................................................................................................................................................... 9-90

lwz ............................................................................................................................................................. 9-91

lwzu ........................................................................................................................................................... 9-92

lwzux ......................................................................................................................................................... 9-93

lwzx ........................................................................................................................................................... 9-94

macchw ..................................................................................................................................................... 9-95

macchws ................................................................................................................................................... 9-96

macchwsu ................................................................................................................................................. 9-97

macchwu ................................................................................................................................................... 9-98

machhw ..................................................................................................................................................... 9-99

machhws ................................................................................................................................................. 9-100

machhwsu ............................................................................................................................................... 9-101

machhwu ................................................................................................................................................. 9-102

maclhw .................................................................................................................................................... 9-103

maclhws .................................................................................................................................................. 9-104

maclhwsu ................................................................................................................................................ 9-105

maclhwu .................................................................................................................................................. 9-106

mcrf ......................................................................................................................................................... 9-107

mcrxr ....................................................................................................................................................... 9-108

mfcr ......................................................................................................................................................... 9-109

mfdcr ....................................................................................................................................................... 9-110

mfmsr ...................................................................................................................................................... 9-111

mfspr ....................................................................................................................................................... 9-112

mftb ......................................................................................................................................................... 9-114

mtcrf ........................................................................................................................................................ 9-116

mtdcr ....................................................................................................................................................... 9-117

mtmsr ...................................................................................................................................................... 9-118

mtspr ....................................................................................................................................................... 9-119

mulchw .................................................................................................................................................... 9-121

mulchwu .................................................................................................................................................. 9-122

mulhhw .................................................................................................................................................... 9-123

mulhhwu .................................................................................................................................................. 9-124

mulhw ...................................................................................................................................................... 9-125

mulhwu .................................................................................................................................................... 9-126

mullhw ..................................................................................................................................................... 9-127

mullhwu ................................................................................................................................................... 9-128

mulli ......................................................................................................................................................... 9-129

mullw ....................................................................................................................................................... 9-130

nand ........................................................................................................................................................ 9-131

neg .......................................................................................................................................................... 9-132

nmacchw ................................................................................................................................................. 9-133

nmacchws ............................................................................................................................................... 9-134

Contents xi

nmachhw ................................................................................................................................................. 9-135

nmachhws ............................................................................................................................................... 9-136

nmaclhw .................................................................................................................................................. 9-137

nmaclhws ................................................................................................................................................ 9-138

nor ........................................................................................................................................................... 9-139

or ............................................................................................................................................................. 9-140

orc ........................................................................................................................................................... 9-141

ori ............................................................................................................................................................ 9-142

oris .......................................................................................................................................................... 9-143

rfci ........................................................................................................................................................... 9-144

rfi ............................................................................................................................................................. 9-145

rlwimi ....................................................................................................................................................... 9-146

rlwinm ...................................................................................................................................................... 9-147

rlwnm ...................................................................................................................................................... 9-150

sc ............................................................................................................................................................ 9-151

slw ........................................................................................................................................................... 9-152

sraw ........................................................................................................................................................ 9-153

srawi ........................................................................................................................................................ 9-154

srw .......................................................................................................................................................... 9-155

stb ........................................................................................................................................................... 9-156

stbu ......................................................................................................................................................... 9-157

stbux ....................................................................................................................................................... 9-158

stbx ......................................................................................................................................................... 9-159

sth ........................................................................................................................................................... 9-160

sthbrx ...................................................................................................................................................... 9-161

sthu ......................................................................................................................................................... 9-162

sthux ....................................................................................................................................................... 9-163

sthx ......................................................................................................................................................... 9-164

stmw ........................................................................................................................................................ 9-165

stswi ........................................................................................................................................................ 9-166

stswx ....................................................................................................................................................... 9-167

stw ........................................................................................................................................................... 9-169

stwbrx ...................................................................................................................................................... 9-170

stwcx. ...................................................................................................................................................... 9-171

stwu ......................................................................................................................................................... 9-173

stwux ....................................................................................................................................................... 9-174

stwx ......................................................................................................................................................... 9-175

subf ......................................................................................................................................................... 9-176

subfc ....................................................................................................................................................... 9-177

subfe ....................................................................................................................................................... 9-178

subfic ....................................................................................................................................................... 9-179

subfme .................................................................................................................................................... 9-180

subfze ..................................................................................................................................................... 9-181

sync ......................................................................................................................................................... 9-182

tlbia ......................................................................................................................................................... 9-183

tlbre ......................................................................................................................................................... 9-184

tlbsx ......................................................................................................................................................... 9-186

tlbsync ..................................................................................................................................................... 9-187

tlbwe ........................................................................................................................................................ 9-188

tw ............................................................................................................................................................ 9-190

twi ............................................................................................................................................................ 9-193

wrtee ....................................................................................................................................................... 9-196

wrteei ...................................................................................................................................................... 9-197

xor ........................................................................................................................................................... 9-198

xii PPC405 Core User’s Manual

xori ........................................................................................................................................................... 9-199

xoris ......................................................................................................................................................... 9-200

Chapter 10. Register Summary ..........................................................................................10-1

Reserved Registers ....................................................................................................................................... 10-1

Reserved Fields ............................................................................................................................................. 10-1

General Purpose Registers ............................................................................................................................ 10-1

Machine State Register and Condition Register ............................................................................................ 10-1

Special Purpose Registers ............................................................................................................................. 10-2

Time Base Registers ...................................................................................................................................... 10-4

Device Control Registers ............................................................................................................................... 10-4

Alphabetical Listing of PPC405 Registers ..................................................................................................... 10-5

CCR0 ......................................................................................................................................................... 10-6

CR ............................................................................................................................................................. 10-8

CTR ........................................................................................................................................................... 10-9

DAC1–DAC2 ........................................................................................................................................... 10-10

DBCR0 .................................................................................................................................................... 10-11

DBCR1 .................................................................................................................................................... 10-13

DBSR ...................................................................................................................................................... 10-15

DCCR ...................................................................................................................................................... 10-17

DCWR ..................................................................................................................................................... 10-19

DEAR ...................................................................................................................................................... 10-21

DVCR1–DVCR2 ...................................................................................................................................... 10-22

ESR ......................................................................................................................................................... 10-23

EVPR ....................................................................................................................................................... 10-25

GPR0–GPR31 ......................................................................................................................................... 10-26

IAC1–IAC4 .............................................................................................................................................. 10-27

ICCR ........................................................................................................................................................ 10-28

ICDBDR ................................................................................................................................................... 10-30

LR ............................................................................................................................................................ 10-31

MSR ........................................................................................................................................................ 10-32

PID .......................................................................................................................................................... 10-34

PIT ........................................................................................................................................................... 10-35

PVR ......................................................................................................................................................... 10-36

SGR ......................................................................................................................................................... 10-37

SLER ....................................................................................................................................................... 10-39

SPRG0–SPRG7 ...................................................................................................................................... 10-41

SRR0 ....................................................................................................................................................... 10-42

SRR1 ....................................................................................................................................................... 10-43

SRR2 ....................................................................................................................................................... 10-44

SRR3 ....................................................................................................................................................... 10-45

SU0R ....................................................................................................................................................... 10-46

TBL .......................................................................................................................................................... 10-48

TBU ......................................................................................................................................................... 10-49

TCR ......................................................................................................................................................... 10-50

TSR ......................................................................................................................................................... 10-51

USPRG0 .................................................................................................................................................. 10-52

XER ......................................................................................................................................................... 10-53

ZPR ......................................................................................................................................................... 10-54

A. Instruction Summary ........................................................................................................ A-1

Instruction Set and Extended Mnemonics – Alphabetical ................................................................................ A-1

Instructions Sorted by Opcode ....................................................................................................................... A-33

Instruction Formats ........................................................................................................................................ A-41

Instruction Fields ....................................................................................................................................... A-41

Contents xiii

Instruction Format Diagrams ..................................................................................................................... A-43

I-Form A-44
B-Form A-44
SC-Form A-44
D-Form A-44
X-Form A-45
XL-Form A-45
XFX-Form A-46
X0-Form A-46
M-Form A-46

B. Instructions by Category ................................................................................................. B-1

Implementation-Specific Instructions ............................................................................................................... B-1

Instructions in the IBM PowerPC Embedded Environment ............................................................................. B-5

Privileged Instructions ..................................................................................................................................... B-7

Assembler Extended Mnemonics .................................................................................................................... B-9

Storage Reference Instructions ..................................................................................................................... B-29

Arithmetic and Logical Instructions ................................................................................................................ B-33

Condition Register Logical Instructions ......................................................................................................... B-37

Branch Instructions ........................................................................................................................................ B-38

Comparison Instructions ................................................................................................................................ B-39

Rotate and Shift Instructions ......................................................................................................................... B-40

Cache Control Instructions ............................................................................................................................ B-41

Interrupt Control Instructions ......................................................................................................................... B-42

TLB Management Instructions ....................................................................................................................... B-42

Processor Management Instructions ............................................................................................................. B-44

C. Code Optimization and Instruction Timings ..................................................................C-1

Code Optimization Guidelines ......................................................................................................................... C-1

Condition Register Bits for Boolean Variables ............................................................................................ C-1

CR Logical Instruction for Compound Branches ......................................................................................... C-1

Floating-Point Emulation ............................................................................................................................. C-1

Cache Usage .............................................................................................................................................. C-2

CR Dependencies ....................................................................................................................................... C-2

Branch Prediction ........................................................................................................................................ C-2

Alignment .................................................................................................................................................... C-2

Instruction Timings .......................................................................................................................................... C-3

General Rules ............................................................................................................................................. C-3

Branches ..................................................................................................................................................... C-3

Multiplies ..................................................................................................................................................... C-4

Scalar Load Instructions ............................................................................................................................. C-5

Scalar Store Instructions ............................................................................................................................. C-6

Alignment in Scalar Load and Store Instructions ........................................................................................ C-6

String and Multiple Instructions ................................................................................................................... C-6

Loads and Store Misses ............................................................................................................................. C-7

Instruction Cache Misses ............................................................................................................................ C-7

Index ........................................................................................................................................ X-1

xiv PPC405 Core User’s Manual

Figures

Figure 1-1. PPC405 Block Diagram ................................................................................................................1-4

Figure 2-1. PPC405 Programming Model—Registers ....................................................................................2-4

Figure 2-2. General Purpose Registers (R0-R31) ..........................................................................................2-5

Figure 2-3. Count Register (CTR) ...................................................................................................................2-7

Figure 2-4. Link Register (LR) .........................................................................................................................2-7

Figure 2-5. Fixed Point Exception Register (XER) ..........................................................................................2-8

Figure 2-6. Special Purpose Register General (SPRG0–SPRG7) ...............................................................2-10

Figure 2-7. Processor Version Register (PVR) .............................................................................................2-10

Figure 2-8. Condition Register (CR) .............................................................................................................2-11

Figure 2-9. Machine State Register (MSR) ...................................................................................................2-14

Figure 2-10. PPC405 Data Types .................................................................................................................2-16

Figure 2-11. Normal Word Load or Store (Big Endian Storage Region) .......................................................2-22

Figure 2-12. Byte-Reverse Word Load or Store (Little Endian Storage Region) ..........................................2-22

Figure 2-13. Byte-Reverse Word Load or Store (Big Endian Storage Region) .............................................2-22

Figure 2-14. Normal Word Load or Store (Little Endian Storage Region) ....................................................2-23

Figure 2-15. PPC405 Instruction Pipeline .....................................................................................................2-24

Figure 4-1. Instruction Flow ............................................................................................................................4-4

Figure 4-2. Core Configuration Register 0 (CCR0) .......................................................................................4-11

Figure 4-3. Instruction Cache Debug Data Register (ICDBDR) ....................................................................4-14

Figure 5-1. Machine State Register (MSR) .....................................................................................................5-7

Figure 5-2. Save/Restore Register 0 (SRR0) .................................................................................................5-9

Figure 5-3. Save/Restore Register 1 (SRR1) .................................................................................................5-9

Figure 5-4. Save/Restore Register 2 (SRR2) ...............................................................................................5-10

Figure 5-5. Save/Restore Register 3 (SRR3) ...............................................................................................5-10

Figure 5-6. Exception Vector Prefix Register (EVPR) ...................................................................................5-11

Figure 5-7. Exception Syndrome Register (ESR) .........................................................................................5-11

Figure 5-8. Data Exception Address Register (DEAR) .................................................................................5-13

Figure 6-1. Relationship of Timer Facilities to the Time Base ........................................................................6-1

Figure 6-2. Time Base Lower (TBL) ................................................................................................................6-2

Figure 6-3. Time Base Upper (TBU) ...............................................................................................................6-2

Figure 6-4. Programmable Interval Timer (PIT) ..............................................................................................6-5

Figure 6-5. Watchdog Timer State Machine ..................................................................................................6-7

Figure 6-6. Timer Status Register (TSR) ........................................................................................................6-8

Figure 6-7. Timer Control Register (TCR) .......................................................................................................6-9

Figure 7-1. Effective to Real Address Translation Flow ..................................................................................7-2

Figure 7-2. TLB Entries ...................................................................................................................................7-3

Figure 7-3. ITLB/DTLB/UTLB Address Resolution .........................................................................................7-9

Figure 7-4. Process ID (PID) .........................................................................................................................7-14

Figure 7-5. Zone Protection Register (ZPR) .................................................................................................7-15

Figure 7-6. Generic Storage Attribute Control Register ................................................................................7-19

Figure 8-1. Debug Control Register 0 (DBCR0) .............................................................................................8-4

Figure 8-2. Debug Control Register 1 (DBCR1) .............................................................................................8-6

Figures xv

Figure 8-3. Debug Status Register (DBSR) .................................................................................................... 8-8

Figure 8-4. Instruction Address Compare Registers (IAC1–IAC4) ................................................................. 8-9

Figure 8-5. Data Address Compare Registers (DAC1–DAC2) ..................................................................... 8-10

Figure 8-6. Data Value Compare Registers (DVC1–DVC2) ......................................................................... 8-10

Figure 8-7. Inclusive IAC Range Address Compares ................................................................................... 8-13

Figure 8-8. Exclusive IAC Range Address Compares .................................................................................. 8-13

Figure 8-9. Inclusive DAC Range Address Compares ................................................................................. 8-15

Figure 8-10. Exclusive DAC Range Address Compares .............................................................................. 8-15

Figure 8-11. JTAG Connector Physical Layout (Top View) .......................................................................... 8-20

Figure 10-1. Core Configuration Register 0 (CCR0) .................................................................................... 10-6

Figure 10-2. Condition Register (CR) ........................................................................................................... 10-8

Figure 10-3. Count Register (CTR) .............................................................................................................. 10-9

Figure 10-4. Data Address Compare Registers (DAC1–DAC2) ................................................................. 10-10

Figure 10-5. Debug Control Register 0 (DBCR0) ....................................................................................... 10-11

Figure 10-6. Debug Control Register 1 (DBCR1) ....................................................................................... 10-13

Figure 10-7. Debug Status Register (DBSR) .............................................................................................. 10-15

Figure 10-8. Data Cache Cachability Register (DCCR) ............................................................................. 10-17

Figure 10-9. Data Cache Write-through Register (DCWR) ........................................................................ 10-19

Figure 10-10. Data Exception Address Register (DEAR) ........................................................................... 10-21

Figure 10-11. Data Value Compare Registers (DVC1–DVC2) ................................................................... 10-22

Figure 10-12. Exception Syndrome Register (ESR) ................................................................................... 10-23

Figure 10-13. Exception Vector Prefix Register (EVPR) ............................................................................ 10-25

Figure 10-14. General Purpose Registers (R0-R31) .................................................................................. 10-26

Figure 10-15. Instruction Address Compare Registers (IAC1–IAC4) ......................................................... 10-27

Figure 10-16. Instruction Cache Cachability Register (ICCR) .................................................................... 10-28

Figure 10-17. Instruction Cache Debug Data Register (ICDBDR) ............................................................. 10-30

Figure 10-18. Link Register (LR) ................................................................................................................ 10-31

Figure 10-19. Machine State Register (MSR) ............................................................................................ 10-32

Figure 10-20. Process ID (PID) .................................................................................................................. 10-34

Figure 10-21. Programmable Interval Timer (PIT) ...................................................................................... 10-35

Figure 10-22. Processor Version Register (PVR) ....................................................................................... 10-36

Figure 10-23. Storage Guarded Register (SGR) ........................................................................................ 10-37

Figure 10-24. Storage Little-Endian Register (SLER) ................................................................................ 10-39

Figure 10-25. Special Purpose Registers General (SPRG0–SPRG7) ....................................................... 10-41

Figure 10-26. Save/Restore Register 0 (SRR0) ......................................................................................... 10-42

Figure 10-27. Save/Restore Register 1 (SRR1) ......................................................................................... 10-43

Figure 10-28. Save/Restore Register 2 (SRR2) ......................................................................................... 10-44

Figure 10-29. Save/Restore Register 3 (SRR3) ......................................................................................... 10-45

Figure 10-30. Storage User-defined 0 Register (SU0R) ............................................................................. 10-46

Figure 10-31. Time Base Lower (TBL) ....................................................................................................... 10-48

Figure 10-32. Time Base Upper (TBU) ....................................................................................................... 10-49

Figure 10-33. Timer Control Register (TCR) .............................................................................................. 10-50

Figure 10-34. Timer Status Register (TSR) ................................................................................................ 10-51

Figure 10-35. User SPR General 0 (USPRG0) .......................................................................................... 10-52

Figure 10-36. Fixed Point Exception Register (XER) ................................................................................. 10-53

Figure 10-37. Zone Protection Register (ZPR) ........................................................................................... 10-54

xvi PPC405 Core User’s Manual

Figure A-1. I Instruction Format ....................................................................................................................A-44

Figure A-2. B Instruction Format ...................................................................................................................A-44

Figure A-3. SC Instruction Format ................................................................................................................A-44

Figure A-4. D Instruction Format ...................................................................................................................A-44

Figure A-5. X Instruction Format ...................................................................................................................A-45

Figure A-6. XL Instruction Format .................................................................................................................A-45

Figure A-7. XFX Instruction Format ..............................................................................................................A-46

Figure A-8. XO Instruction Format ................................................................................................................A-46

Figure A-9. M Instruction Format ..................................................................................................................A-46

Figures xvii

Tables

Table 2-1. PPC405 SPRs ................................................................................................................................ 2-6

Table 2-2. XER[CA] Updating Instructions ...................................................................................................... 2-9

Table 2-3. XER[SO,OV] Updating Instructions ................................................................................................ 2-9

Table 2-4. Time Base Registers..................................................................................................................... 2-13

Table 2-5. Alignment Exception Summary .................................................................................................... 2-17

Table 2-6. Bits of the BO Field ...................................................................................................................... 2-25

Table 2-7. Conditional Branch BO Field ........................................................................................................ 2-26

Table 2-8. Example Memory Mapping............................................................................................................ 2-30

Table 2-9. Privileged Instructions .................................................................................................................. 2-31

Table 2-10. PPC405 Instruction Set Summary............................................................................................... 2-36

Table 2-11. Implementation-specific Instructions........................................................................................... 2-37

Table 2-12. Storage Reference Instructions .................................................................................................. 2-37

Table 2-13. Arithmetic Instructions ................................................................................................................ 2-38

Table 2-14. Multiply-Accumulate and Multiply Halfword Instructions ............................................................. 2-39

Table 2-15. Logical Instructions ..................................................................................................................... 2-39

Table 2-16. Compare Instructions ................................................................................................................. 2-39

Table 2-17. Branch Instructions ..................................................................................................................... 2-40

Table 2-18. CR Logical Instructions .............................................................................................................. 2-40

Table 2-19. Rotate Instructions ..................................................................................................................... 2-40

Table 2-20. Shift Instructions ......................................................................................................................... 2-41

Table 2-21. Cache Management Instructions ................................................................................................ 2-41

Table 2-22. Interrupt Control Instructions ...................................................................................................... 2-41

Table 2-23. TLB Management Instructions ................................................................................................... 2-42

Table 2-24. Processor Management Instructions .......................................................................................... 2-42

Table 3-1. MSR Contents after Reset .............................................................................................................. 3-2

Table 3-2. SPR Contents After Reset .............................................................................................................. 3-3

Table 4-1. Available Cache Array Sizes........................................................................................................... 4-2

Table 4-2. ICU and DCU Cache Array Organization........................................................................................ 4-3

Table 4-3. Cache Sizes, Tag Fields, and Lines................................................................................................ 4-3

Table 4-4. Priority Changes With Different Data Cache Operations .............................................................. 4-17

Table 5-1. Interrupt Handling Priorities ............................................................................................................ 5-4

Table 5-2. Interrupt Vector Offsets .................................................................................................................. 5-6

Table 5-3. ESR Alteration by Various Interrupts ............................................................................................ 5-13

Table 5-4. Register Settings during Critical Input Interrupts .......................................................................... 5-14

Table 5-5. Register Settings during Machine Check—Instruction Interrupts ................................................. 5-15

Table 5-6. Register Settings during Machine Check—Data Interrupts .......................................................... 5-15

Table 5-7. Register Settings during Data Storage Interrupts ......................................................................... 5-17

Table 5-8. Register Settings during Instruction Storage Interrupts ................................................................ 5-18

Table 5-9. Register Settings during External Interrupts ................................................................................. 5-19

Table 5-10. Alignment Interrupt Summary ..................................................................................................... 5-19

Table 5-11. Register Settings during Alignment Interrupts ............................................................................ 5-19

Table 5-12. ESR Usage for Program Interrupts ............................................................................................ 5-20

xviii PPC405 Core User’s Manual

Table 5-13. Register Settings during Program Interrupts ..............................................................................5-21

Table 5-14. Register Settings during FPU Unavailable Interrupts .................................................................5-21

Table 5-15. Register Settings during System Call Interrupts .........................................................................5-22

Table 5-16. Register Settings during APU Unavailable Interrupts .................................................................5-22

Table 5-17. Register Settings during Programmable Interval Timer Interrupts ..............................................5-23

Table 5-18. Register Settings during Fixed Interval Timer Interrupts ............................................................5-24

Table 5-19. Register Settings during Watchdog Timer Interrupts ..................................................................5-24

Table 5-20. Register Settings during Data TLB Miss Interrupts .....................................................................5-25

Table 5-21. Register Settings during Instruction TLB Miss Interrupts ............................................................5-25

Table 5-22. SRR2 during Debug Interrupts ....................................................................................................5-26

Table 5-23. Register Settings during Debug Interrupts ..................................................................................5-26

Table 6-1. Time Base Access ..........................................................................................................................6-3

Table 6-2. FIT Controls ....................................................................................................................................6-5

Table 6-3. Watchdog Timer Controls ...............................................................................................................6-6

Table 7-1. TLB Fields Related to Page Size ....................................................................................................7-4

Table 7-2. Protection Applied to Cache Control Instructions .........................................................................7-16

Table 8-1. Debug Events................................................................................................................................8-11

Table 8-2. DAC Applied to Cache Instructions ..............................................................................................8-15

Table 8-3. Setting of DBSR Bits for DAC and DVC Events............................................................................8-17

Table 8-4. Comparisons Based on DBCR1[DVnM]........................................................................................8-18

Table 8-5. Comparisons for Aligned DVC Accesses ......................................................................................8-18

Table 8-6. Comparisons for Misaligned DVC Accesses.................................................................................8-19

Table 8-7. JTAG Connector Signals ..............................................................................................................8-20

Table 8-8. JTAG Instructions..........................................................................................................................8-21

Table 9-1. Implementation-Specific Instructions...............................................................................................9-1

Table 9-2. Operator Precedence ......................................................................................................................9-5

Table 9-3. Extended Mnemonics for addi ........................................................................................................9-9

Table 9-4. Extended Mnemonics for addic ....................................................................................................9-10

Table 9-5. Extended Mnemonics for addic. ...................................................................................................9-11

Table 9-6. Extended Mnemonics for addis ....................................................................................................9-12

Table 9-7. Extended Mnemonics for bc, bca, bcl, bcla ..................................................................................9-21

Table 9-8. Extended Mnemonics for bcctr, bcctrl ...........................................................................................9-27

Table 9-9. Extended Mnemonics for bclr, bclrl ...............................................................................................9-30

Table 9-10. Extended Mnemonics for cmp ....................................................................................................9-34

Table 9-11. Extended Mnemonics for cmpi ...................................................................................................9-35

Table 9-12. Extended Mnemonics for cmpl ...................................................................................................9-36

Table 9-13. Extended Mnemonics for cmpli ...................................................................................................9-37

Table 9-14. Extended Mnemonics for creqv ..................................................................................................9-41

Table 9-15. Extended Mnemonics for crnor ...................................................................................................9-43

Table 9-16. Extended Mnemonics for cror .....................................................................................................9-44

Table 9-17. Extended Mnemonics for crxor ...................................................................................................9-46

Table 9-18. Transfer Bit Mnemonic Assignment...........................................................................................9-108

Table 9-19. Extended Mnemonics for mfspr ................................................................................................9-113

Table 9-20. Extended Mnemonics for mftb...................................................................................................9-114

Table 9-21. Extended Mnemonics for mftb ..................................................................................................9-115

Table 9-22. Extended Mnemonics for mtcrf .................................................................................................9-116

Tables xix

Table 9-23. Extended Mnemonics for mtspr ................................................................................................ 9-120

Table 9-24. Extended Mnemonics for nor, nor. ........................................................................................... 9-139

Table 9-25. Extended Mnemonics for or, or. ............................................................................................... 9-140

Table 9-26. Extended Mnemonics for ori ..................................................................................................... 9-142

Table 9-27. Extended Mnemonics for rlwimi, rlwimi. ................................................................................... 9-146

Table 9-28. Extended Mnemonics for rlwinm, rlwinm. ................................................................................. 9-147

Table 9-29. Extended Mnemonics for rlwnm, rlwnm. .................................................................................. 9-150

Table 9-30. Extended Mnemonics for subf, subf., subfo, subfo. ................................................................. 9-176

Table 9-31. Extended Mnemonics for subfc, subfc., subfco, subfco. .......................................................... 9-177

Table 9-32. Extended Mnemonics for tlbre .................................................................................................. 9-185

Table 9-33. Extended Mnemonics for tlbwe ................................................................................................ 9-189

Table 9-34. Extended Mnemonics for tw ..................................................................................................... 9-191

Table 9-35. Extended Mnemonics for twi .................................................................................................... 9-194

Table 10-1. PPC405 General Purpose Registers........................................................................................... 10-1

Table 10-2. Special Purpose Registers ......................................................................................................... 10-2

Table 10-3. Time Base Registers................................................................................................................... 10-4

Table A-1. PPC405 Instruction Syntax Summary ........................................................................................... A-1

Table A-2. PPC405 Instructions by Opcode ................................................................................................. A-33

Table B-1. PPC405 Instruction Set Categories............................................................................................... B-1

Table B-2. Implementation-specific Instructions ............................................................................................. B-1

Table B-3. Instructions in the IBM PowerPC Embedded Environment ........................................................... B-5

Table B-4. Privileged Instructions ................................................................................................................... B-7

Table B-5. Extended Mnemonics for PPC405 .............................................................................................. B-10

Table B-6. Storage Reference Instructions .................................................................................................. B-29

Table B-7. Arithmetic and Logical Instructions ............................................................................................. B-33

Table B-8. Condition Register Logical Instructions ....................................................................................... B-37

Table B-9. Branch Instructions ..................................................................................................................... B-38

Table B-10. Comparison Instructions ........................................................................................................... B-39

Table B-11. Rotate and Shift Instructions ..................................................................................................... B-40

Table B-12. Cache Control Instructions ........................................................................................................ B-41

Table B-13. Interrupt Control Instructions ..................................................................................................... B-42

Table B-14. TLB Management Instructions .................................................................................................. B-42

Table B-15. Processor Management Instructions ........................................................................................ B-44

Table C-1. Cache Sizes, Tag Fields, and Lines.............................................................................................. C-2

Table C-2. Multiply and MAC Instruction Timing............................................................................................. C-5

Table C-3. Instruction Cache Miss Penalties................................................................................................... C-7

xx PPC405 Core User’s Manual

About This Book

This user’s manual provides the architectural overview,programming model, and detailed information
about the registers, the instruction set, and operations of the IBM™ PowerPC™ 405 (PPC405 core)
32-bit RISC embedded processor core.

The PPC405 RISC embedded processor core features:

• PowerPC Architecture™

• Single-cycle execution for most instructions

• Instruction cache unit and data cache unit

• Support for little endian operation

• Interrupt interface for one critical and one non-critical interrupt signal

• JTAG interface

• Extensive development tool support

Who Should Use This Book

This book is for system hardware and software developers, and for application developers who need
to understand the PPC405 core. The audience should understand embedded processor design,
embedded system design, operating systems, RISC processing, and design for testability.

How to Use This Book

This book describes the PPC405 device architecture, programming model, external interfaces,
internal registers, and instruction set. This book contains the following chapters, arranged in parts:

Chapter 1 Overview
Chapter 2 Programming Model
Chapter 3 Initialization
Chapter 4 Cache Operations
Chapter 5 Fixed-Point Interrupts and Exceptions
Chapter 6 Timer Facilities
Chapter 7 Memory Management
Chapter 8 Debugging
Chapter 9 Instruction Set
Chapter 10 Register Summary

This book contains the following appendixes:

Appendix A Instruction Summary
Appendix B Instructions by Category
Appendix C Code Optimization and Instruction Timings

About This Book xxi

To help readers find material in these chapters, the book contains:

Contents, on page v.
Figures, on page xv.
Tables, on page xviii.
Index, on page X-1.

Conventions

The following is a list of notational conventions frequently used in this manual.

ActiveLow An overbar indicates an active-low signal.

n

0x
0b

n
n

A decimal number
A hexadecimal number
A binary number

= Assignment

∧ AND logical operator
¬ NOT logical operator
∨ OR logical operator
⊕ Exclusive-OR (XOR) logical operator

+ Twos complement addition
– Twos complement subtraction, unary minus

× Multiplication
÷ Division yielding a quotient

% Remainder of an integer division; (33 % 32) = 1.

|| Concatenation
=, ≠ Equal, not equal relations

<, > Signed comparison relations

u

u

, Unsigned comparison relations

>

<

if...then...else... Conditional execution; if

condition

thena elseb, wherea andb represent
one or more pseudocode statements. Indenting indicates the ranges of
andb. Ifb is null, the else does not appear.

do Do loop. “to” and “by” clauses specify incrementing an iteration variable;

“while” and “until” clauses specify terminating conditions. Indenting
indicates the scope of a loop.

leave Leave innermost do loop or do loop specified in a leave statement.
FLD An instruction or register field
FLD

b

FLD

b:b

xxii PPC405 Core User’s Manual

A bit in a named instruction or register field
A range of bits in a named instruction or register field

a

FLD
REG
REG
REG

b,b, . . .

b
b:b
b,b, . . .

A list of bits, by number or name, in a named instruction or register field
A bit in a named register
A range of bits in a named register

A list of bits, by number or name, in a named register
REG[FLD] A field in a named register
REG[FLD, FLD

] A list of fields in a named register

. . .

REG[FLD:FLD] Arange of fields in a named register
GPR(r) General Purpose Register (GPR) r, where 0 ≤ r ≤ 31.
(GPR(r)) The contents of GPR r, where 0 ≤ r ≤ 31.
DCR(DCRN) A Device Control Register (DCR) specified by the DCRF field in an

mfdcr or mtdcr instruction
SPR(SPRN) An SPR specified by the SPRF field in an mfspr or mtspr instruction
TBR(TBRN) A Time Base Register (TBR) specified by the TBRF field in an mftb

instruction
GPRs RA, RB,

. . .

(Rx) The contents of a GPR, wherex is A, B, S, or T
(RA|0) The contents of the register RA or 0, if the RA field is 0.
CR

FLD

c

0:3

n

b The bit or bit valueb is replicatedn times.

The field in the condition register pointed to by a field of an instruction.

A 4-bit object used to store condition results in compare instructions.

xx Bit positions which are don’t-cares.
CEIL(x) Least integer ≥ x.
EXTS(x) The result of extending

x

on the left with sign bits.
PC Program counter.
RESERVE Reserve bit; indicates whether a process has reserved a block of

storage.

CIA Current instruction address; the 32-bit address of the instruction being

described by a sequence of pseudocode. This address is used to set the
next instruction address (NIA). Does not correspond to any architected
register.

NIA Next instruction address; the 32-bit address of the next instruction to be

executed. In pseudocode, a successful branch is indicated by assigning
a value to NIA. For instructions that do not branch, the NIA is CIA +4.

n

MS(addr, n) The number of bytes represented by

addr

represented by

.

at the location in main storage

EA Effective address; the 32-bit address, derived by applying indexing or

indirect addressing rules to the specified operand, that specifies a
location in main storage.

About This Book xxiii

EA
EA

b
b:b

A bit in an effective address.
A range of bits in an effective address.

ROTL((RS),n) Rotate left; the contents of RS are shifted left the number of bits

specified byn.

MASK(MB,ME) Mask having 1s in positions MB through ME (wrapping if MB > ME) and

0s elsewhere.

instruction(EA) An instruction operating on a data or instruction cache block associated

with an EA.

xxiv PPC405 Core User’s Manual

Chapter 1. Overview

The IBM 405 32-bit reduced instruction set computer (RISC) processor core, referred to as the
PPC405 core, implements the PowerPC Architecture with extensions for embedded applications.

This chapter describes:

• PPC405 core features

• The PowerPC Architecture

• The PPC405 implementation of the IBM PowerPC Embedded Environment, an extension of the
PowerPC Architecture for embedded applications

• PPC405 organization, including a block diagram and descriptions of the functional units

• PPC405 registers

• PPC405 addressing modes

1.1 PPC405 Features

The PPC405 core provides high performance and low power consumption. The PPC405 RISC CPU
executes at sustained speeds approaching one cycle per instruction. On-chip instruction and data
caches arrays can be implemented to reduce chip count and design complexity in systems and
improve system throughput.

The PowerPC RISC fixed-point CPU features:

• PowerPC User Instruction Set Architecture (UISA) and extensions for embedded applications

• Thirty-two 32-bit general purpose registers (GPRs)

• Static branch prediction

• Five-stage pipeline with single-cycle execution of most instructions, including loads/stores

• Unaligned load/store support to cache arrays, main memory, and on-chip memory (OCM)

• Hardware multiply/divide for faster integer arithmetic (4-cycle multiply, 35-cycle divide)

• Multiply-accumulate instructions

• Enhanced string and multiple-word handling

• True little endian operation

• Programmable Interval Timer (PIT), Fixed Interval Timer (FIT), and watchdog timer

• Forward and reverse trace from a trigger event

• Storage control
– Separate, configurable, two-way set-associative instruction and data cache units; for the

PPC405B3, the instruction cache array is 16KB and the data cache array is 8KB
– Eight words (32 bytes) per cache line
– Support for any combination of 0KB, 4KB, 8KB, and 16KB, and 32KB instruction and data cache

arrays, depending on model

Overview 1-1

– Instruction cache unit (ICU) non-blocking during line fills, data cache unit (DCU) non-blocking

during line fills and flushes

– Read and write line buffers
– Instruction fetch hits are supplied from line buffer
– Data load/store hits are supplied to line buffer
– Programmable ICU prefetching of next sequential line into line buffer
– Programmable ICU prefetching of non-cacheable instructions, full line (eight words) or half line

(four words)

– Write-back or write-through DCU write strategies
– Programmable allocation on loads and stores
– Operand forwarding during cache line fills

• Memory Management
– Translation of the 4GB logical address space into physical addresses

– Independent enabling of instruction and data translation/protection
– Page level access control using the translation mechanism
– Software control of page replacement strategy
– Additional control over protection using zones

– WIU0GE (write-through, cachability, compresseduser-defined 0, guarded, endian) storage

attribute control for each virtual memory region

• WIU0GE storage attribute control for thirty-two real 128MB regions in real mode

• Support for OCM that provides memory access performance identical to cache hits

• Full PowerPC floating-point unit (FPU) support using the auxiliary processor unit (APU) interface
(the PPC405 does not include an FPU)

• PowerPC timer facilities
– 64-bit time base

– PIT, FIT, and watchdog timers
– Synchronous external time base clock input

• Debug Support
– Enhanced debug support with logical operators
– Four instruction address compares (IACs)
– Two data address compares (DACs)
– Two data value compares (DVCs)
– JTAG instruction to write to ICU
– Forward or backward instruction tracing

• Minimized interrupt latency

• Advanced power management support

1-2 PPC405 Core User’s Manual

1.2 PowerPC Architecture

The PowerPC Architecture comprises three levels of standards:

• PowerPC User Instruction Set Architecture (UISA), including the base user-level instruction set,

user-level registers, programming model, data types, and addressing modes. This is referred to as
Book I of the PowerPC Architecture.

• PowerPC Virtual Environment Architecture, describing the memory model, cache model, cache-

control instructions, address aliasing, and related issues. While accessible from the user level,
these features are intended to be accessed from within library routines provided by the system
software. This is referred to as Book II of the PowerPC Architecture.

• PowerPC Operating Environment Architecture, including the memory management model,

supervisor-level registers, and the exception model. These features are not accessible from the
user level. This is referred to as Book III of the PowerPC Architecture.

Book I and Book II define the instruction set and facilities available to the application programmer.
Book III defines features, such as system-level instructions, that are not directly accessible by user
applications. The PowerPC Architecture is described in

for a New Family of RISC Processors

The PowerPC Architecture provides compatibility of PowerPC Book I application code across all
PowerPC implementations to help maximize the portability of applications developed for PowerPC
processors. This is accomplished through compliance with the first level of the architectural definition,
the PowerPC UISA, which is common to all PowerPC implementations.

.

The PowerPC Architecture: A Specification

1.3 The PPC405 as a PowerPC Implementation

The PPC405 implements the PowerPC UISA, user-level registers, programming model, data types,
addressing modes, and 32-bit fixed-point operations. The PPC405 fully complies with the PowerPC
UISA. The UISA 64-bit operations are not implemented, nor are the floating point operations, unless a
floating point unit (FPU) is implemented. The floating point operations, which cause exceptions, can
then be emulated by software.

Most of the features of the PPC405 are compatible with the PowerPC Virtual Environment and
Operating Environment Architectures, as implemented in PowerPC processors such as the
6xx/7xx family. The PPC405 also provides a number of optimizations and extensions to these layers
of the PowerPC Architecture. The full architecture of the PPC405 is defined by the PowerPC
Embedded Environment and the PowerPC User Instruction Set Architecture.

The primary extensions of the PowerPC Architecture defined in the Embedded Environment are:

• A simplified memory management mechanism with enhancements for embedded applications

• An enhanced, dual-level interrupt structure

• An architected DCR address space for integrated peripheral control

• The addition of several instructions to support these modified and extended resources
Finally, some of the specific implementation features of the PPC405 are beyond the scope of the

PowerPC Architecture. These features are included to enhance performance, integrate functionality,
and reduce system complexity in embedded control applications.

Overview 1-3

1.4 Processor Core Organization

The processor core consists of a 5-stage pipeline, separate instruction and data cache units, virtual
memory management unit (MMU), three timers, debug, and interfaces to other functions.

Figure 1-1 illustrates the logical organization of the PPC405.

PLB Master Instruction

Interface OCM

I-Cache I-Cache

ControllerArray

Instruction

Cache

Unit

Cache Units

Data

Cache

Unit

D-Cache D-Cache

ControllerArray

PLB Master Data

Interface OCM

MMU

Instruction Shadow

TLB

(4 Entry)

Unified TLB

(64 Entry)

Data Shadow

TLB

(8 Entry)

405 CPU

Fetch

Decode

Logic

Execute Unit (EXU)

32 x 32

GPR

3-Element

and

ALU

Figure 1-1. PPC405 Block Diagram

Fetch
Queue
(PFB1,

PFB0,

DCD)

MAC

APU/FPU

Timers

(FIT,

PIT,

Watchdog)

Timers

&

Debug

Debug Logic

(4 IAC,
2 DAC,
2 DVC)

JTAG Instruction

Trace

1.4.1 Instruction and Data Cache Controllers

The instruction cache unit (ICU) and data cache unit (DCU) enable concurrent accesses and
minimize pipeline stalls. The storage capacity of the cache units, which can range from 0KB–32KB,
depends upon the implementation. Both cache units are two-way set-associative, use a 32-byte line
size. The instruction set provides a rich assortment of cache control instructions, including
instructions to read tag information and data arrays. See Chapter 4, “Cache Operations,” for detailed
information about the ICU and DCU.

The cache units are PLB-compliant for use in the IBM Core+ASIC program.

1.4.1.1 Instruction Cache Unit

The ICU provides one or two instructions per cycle to the execution unit (EXU) over a 64-bit bus. A
line buffer (built into the output of the array for manufacturing test) enables the ICU to be accessed
only once for every four instructions, to reduce power consumption by the array.

The ICU can forward any or all of the words of a line fill to the EXU to minimize pipeline stalls caused
by cache misses. The ICU aborts speculative fetches abandoned by the EXU, eliminating

1-4 PPC405 Core User’s Manual

unnecessary line fills and enabling the ICU to handle the next EXU fetch. Aborting abandoned
requests also eliminates unnecessary external bus activity to increase external bus utilization.

1.4.1.2 Data Cache Unit

The DCU transfers 1, 2, 3, 4, or 8 bytes per cycle, depending on the number of byte enables
presented by the CPU.The DCU contains a single-element command and store data queue to reduce
pipeline stalls; this queue enables the DCU to independently process load/store and cache control
instructions. Dynamic PLB request prioritization reduces pipeline stalls evenfurther.When the DCU is
busy with a low-priority request while a subsequent storage operation requested by the CPU is
stalled, the DCU automatically increases the priority of the current request to the PLB.

The DCU uses a two-line flush queue to minimize pipeline stalls caused by cache misses. Line
flushes are postponed until after a line fill is completed. Registers comprise the first position of the
flush queue; the line buffer built into the output of the array for manufacturing test serves as the
second position of the flush queue. Pipeline stalls are further reduced by forwarding the requested
word to the CPU during the line fill. Single-queued flushes are non-blocking. When a flush operation
is pending, the DCU can continue to access the array to determine subsequent load or store hits.
Under these conditions, load hits can occur concurrently with store hits to write-back memory without
stalling the pipeline. Requests abandoned by the CPU can also be aborted by the cache controller.

Additional DCU features enable the programmer to tailor performance for a given application. The
DCU can function in write-back or write-through mode, as controlled by the Data Cache Write-through
Register (DCWR) or the translation look-aside buffer (TLB). DCU performance can be tuned to
balance performance and memory coherency.Store-without-allocate, controlled by the SWOA field of
the Core Configuration Register 0 (CCR0), can inhibit line fills caused by store misses to further
reduce potential pipeline stalls and unwanted external bus traffic. Similarly, load-without-allocate,
controlled by CCR0[LWOA], can inhibit line fills caused by load misses.

1.4.2 Memory Management Unit

The 4GB address space of the PPC405 is presented as a flat address space.
The MMU provides address translation, protection functions, and storage attribute control for

embeddedembedded applications. The MMU supports demand paged virtual memory and other
management schemes that require precise control of logical to physical address mapping and flexible
memory protection. Working with appropriate system level software, the MMU provides the following
functions:

• Translation of the 4GB logical address space into physical addresses

• Independent enabling of instruction and data translation/protection

• Page level access control using the translation mechanism

• Software control of page replacement strategy

• Additional control over protection using zones

• Storage attributes for cache policy and speculative memory access control
The MMU can be disabled under software control. If the MMU is not used, the PPC405 core provides

other storage control mechanisms.
The translation lookaside buffer (TLB) is the hardware resource that controls translation and

protection. It consists of 64 entries, each specifying a page to be translated. The TLB is fully

Overview 1-5

associative; a page entry can be placed anywhere in the TLB. The translation function of the MMU
occurs pre-cache for data accesses. Cache tags and indexing use physical addresses for data
accesses; instruction fetches are virtually indexed and physically tagged.

Software manages the establishment and replacement of TLB entries. This gives system software
significant flexibility in implementing a custom page replacement strategy. For example, to reduce
TLB thrashing or translation delays, software can reserve several TLB entries for globally accessible
static mappings. The instruction set provides several instructions to manage TLB entries. These
instructions are privileged and require the software to be executingin supervisor state. Additional TLB
instructions are provided to move TLB entry fields to and from GPRs.

The MMU divides logical storage into pages. Eight page sizes (1KB, 4KB, 16KB, 64KB, 256KB, 1MB,
4MB, 16MB) are simultaneously supported, so that, at any given time, the TLB can contain entries for
any combination of page sizes. For a logical to physical translation to occur, a valid entry for the page
containing the logical address must be in the TLB. Addresses for which no TLB entry exists cause
TLB-Miss exceptions.

To improve performance, 4 instruction-side and 8 data-side TLB entries are kept in shadow arrays.
The shadow arrays prevent TLB contention. Hardware manages the replacement and invalidation of
shadow-TLB entries; no system software action is required. The shadow arrays can be thought of as
level 1 TLBs, with the main TLB serving as a level 2 TLB.

When address translation is enabled, the translation mechanism provides a basic level of protection.
Physical addresses not mapped by a page entry are inaccessible when translation is enabled. Read
access is implied by the existence of the valid entry in the TLB. The EX and WR bits in the TLB entry
further define levels of access for the page, by permitting execute and write access, respectively.

The Zone Protection Register (ZPR) enables the system software to override the TLB access
controls. For example, the ZPR provides a way to deny read access to application programs. The
ZPR can be used to classify storage by type; access by type can be changed without manipulating
individual TLB entries.

The PowerPC Architecture provides WIU0GE (write-back/write through, cachability, user-defined 0,
guarded, endian) storage attributes that control memory accesses, using bits in the TLB or, when
address translation is disabled, storage attribute control registers.

When address translation is enabled (MSR[IR, DR] = 1), storage attribute control bits in the TLB
control the storage attributes associated with the current page. When address translation is disabled
(MSR[IR, DR] = 0), bits in each storage attribute control register control the storage attributes
associated with storage regions. Each storage attribute control register contains 32 fields. Each field
sets the associated storage attribute for a 128MB memory region. See “Real-Mode Storage Attribute
Control” on page 7-17 for more information about the storage attribute control registers.

1.4.3 Timer Facilities

The processor core contains a time base and three timers:

• Programmable Interval Timer (PIT)

• Fixed Interval Timer (FIT)

• Watchdog timer

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