IBM EM78P809N User Manual

EM78P809N

8-BIT

Microcontroller

Product

Specification

DOC. VERSION 1.0

ELAN MCCROELECTRONICS CORP.

July 2005

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are trademarks of ELAN Microelectronics Corporation.

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Contents

1 General Description ··············· ·· ······················ ········································· ··········· 1 2 Features ·············································································································· 1

2.1 CPU ········································································································································ 1

2.2 Applications ···························································································································· 2

3 Pin Assignment ························ ··· ··· ··· ····················· ······················ ··· ··················· 3 4 Pin Description ··································································································· 3 4 Function Description·························································································· 5

4.1 Functional Block Diagram ······································································································ 5

4.2 Operating Registers ··············································································································· 6

4.3 Special Purpose Registers··································································································· 23

4.4 CPU Operation Mode ··········································································································· 27

4.5 AD Converter························································································································ 29

4.6 Time Base Timer and Keytone Generator············································································ 31

4.7 UART (Universal Asynchronous Receiver/Transmitter)······················································· 33

4.8 SPI (Serial Peripheral Interface) ·························································································· 36

4.9 Timer/Counter 2 ··················································································································· 40

4.10 Timer/Counter 3 ··················································································································· 42

4.11 Timer/Counter 4 ··················································································································· 44

4.12 TCC/WDT & Prescaler ········································································································· 46

4.13 I/O Ports ······························································································································· 47

4.14 RESET and Wake-up ··········································································································· 47

4.15 Interrupt································································································································ 54

4.16 Oscillator ······························································································································ 55

4.17 Code Option Register··········································································································· 58

4.18 Power-on Considerations····································································································· 59

4.19 Instruction Set ······················································································································ 61

Product Specification (V1. 0) 07.26.2005 • iii

Contents

5 Absolute Maximum Ratings ·········· ··· ····················· ········································· · 63

5.1 Absolute Maximum Ratings ································································································· 63

5.2 Recommended Operating Conditions·················································································· 63

6 Electrical Characteristics··············· ··· ·· ··· ······················ ······················ ·············· 64

6.1 DC Electrical Characteristics································································································ 64

6.2 AC Electrical Characteristic·································································································· 67

6.3 Timing Diagram ··················································································································· 68

APPENDIX ·············································································································· 69

Package Types:······························································································································ 69

Specificati o n Re vis ion Hi st o r y

Version Revision Description Date

Preliminary

0.9

1.0

Initial Version

2004/03/04

2005/07/26

iv • Product Specification (V1.0) 07.26.2005

1 General Description

The EM78P809N is an 8-bit microprocessor with low-power, high-speed CMOS

technology and high noise immunity. It has a built-in 8K×13-bits Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides multi-protection bits to

prevent intrusion of user’s OTP memory codes. Seven Option bits are also available to

meet user’s requirements.

With its OTP-ROM feature, the EM78P809N is able to offer a convenient way of

developing and verifying user’s programs. Moreover, user can take advantage of

ELAN Writer to easily program his development code.

2 Features

2.1 CPU

 Operating voltage: 2.5V~5.5V

EM78P809N

8-Bit Microcontroller

 Operating temperature range: -40°C~85°C

 Operating frequency range (base on 2 clocks)

z Crystal mode: 1MHz ~ 8MHz at 4.5V, 1MHz ~ 4MHz at 2.5V

z RC mode: 1MHz ~ 4MHz at 2.5V

 Low power consumption:

z Typically 0.8 μA, during sleep mode

 8K × 13 bits on-chip ROM

 Multi-security bits to prevent intrusion of OTP memory codes

 One configuration register accommodates user’s requirements

 144 × 8 bits on-chip registers (SRAM, general purpose register)

 4 bi-directional I/O ports (22 pins)

z High sink current output pin: 14 pins

z 10 programmable pull high I/O pins

z 10 programmable pull low I/O pins

 8 level stacks for subroutine nesting

 High performance MCU: Two clocks per instruction cycle

 15 interrupts (External: 9, Internal: 6)

 Programmable free running watchdog timer

Product Specification ( V 1 . 0) 07 . 2 6 . 2 005

(This specification is subject to change without further notice)

• 1

EM78P809N

8-Bit Microcontroller

 16 bits Counter/Timer

 8 bits Timer/Counter

 Time Base Timer: (1Hz ~16kHz at 8MHz)

 Key tone output: (1kHz ~ 8kHz at 8MHz)

 Serial transmitter/receiver interface

 AD converter

z TC2: Timer/Counter/Window

z TCC: 8-bit real time clock/counter with overflow interrupt

z TC3: Timer/Counter/Capture

z TC4: Timer/Counter/ PWM (pulse width modulation)/PDO (Programmable

divider output)

z Serial Peripheral Interface (SPI): Three-wire synchronous communication

z Universal asynchronous receiver transmitter interface (UART): Two wire

asynchronous communication

z 8 channel 10 bits resolution AD converter

 Operating mode:

z Normal mode: Oscillation circuit turned on, CPU and Peripheral circuit in

operation

z Idle mode: Oscillation circuit turned on, CPU halt and Peripheral circuit in

operation

z Sleep mode: Oscillation circuit turned off, CPU and Peripheral circuit halt

 Package types:

z 28-pin DIP 600 mil: EM78P809NP

z 28-pin SOP 300 mil: EM78P809NM

z 28-pin SSOP 209 mil: EM78P809NS

 99.9% single instruction cycle commands

2.2 Applications

 General purpose

Product Specification (V1.0) 07.26.2005

2 •

(This specification is subject to change without further notice)

3 Pin Assignment

EM78P809N

8-Bit Microcontroller

(ACLK) OSCO

OSCI

TEST (AD0) P90 (AD1) P91 (AD2) P92 (AD3) P93 (AD4) P94 (AD5) P95 (AD6) P96

(AD7/VREF) P97

(TC3, INT3) P80

(TC4, /PWM, /PDO) P81

VSS

1 2

3 4 5 6 7 8 9 10 11 12 13 14 15

28 27 26 25 24 23 22 21 20 19 18 17 16

EM78P809N

Fig. 1. Pin Assignment

4 Pin Description

Table 1

Symbol Pin No. Type Function

VDD 28 - * Power supply

OSCI 2 I

OSCO 1 I/O

/RESET 27 I

P60~P67 19~26 I/O

P70~P73 15~18 I/O

* Crystal type: Crystal input terminal

* RC type: RC oscillator input pin

* Crystal type: Output terminal for crystal oscillator

* RC type: Instruction clock output

* External clock signal input

* Input pin with Schmitt trigger. If this pin remains at logic low, the

controller will also remain in reset condition.

* P60~P67 are bi-directional I/O pins

* P60 can be used as external interrupt 0 (/INT0)

* P61 can be used as external interrupt 1 (INT1)

* P62 can be used as 16-bit Timer/Counter 2 (TC2)

* P63 can be used as divider output (/TONE)

* P64 slave mode enable (/SS)

* P60 ~ P63 can be used as pull high or pull low pins

* P70~P77 are bi-directional I/O pins

* P70 can be used as SPI serial clock input/output (/SCK)

* P71 can be used as SPI serial data input (SI) or UART data receive input (RX)

* P72 can be used as SPI serial data output (SO) or UART data

transmit output (TX)

* P73 can be used as SLEEP mode release input (/SLEEP) or external

interrupt input 5 (/INT5)

* P70 ~ P73 can be used as pull high or pull low pins

VDD

/RESET (VPP)

P67 (DINCK) P66 (DATAIN) P65 (PGMB) P64 (/SS)(OEB)

P63 (/TONE)

P62 (TC2)

P61 (INT1) P60 (/INT0) P73 (/SLEEP, /INT5)

P72 (TX,SO) P71(RX,SI) P70 (/SCK)

Product Specification ( V 1 . 0) 07 . 2 6 . 2 005

(This specification is subject to change without further notice)

• 3

EM78P809N

8-Bit Microcontroller

Symbol Pin No. Type Function

P80~P81 12~13 I/O

P90~P97 4~11 I/O

VSS 14 - * Ground

NC 3 - * No connection

VPP 27 I Programming voltage input

ACLK 1 I CLK for OTP memory address increment

DATAIN 25 I/O ROM code series input and series output pin

DINCK 26 I ROM code input clock

PGMB 24 I Program write enable pin. Active low.

OEB 23 I Output enable pin. Active low.

* P80~P83 are bi-directional I/O pins

* P80 can be used as 8-bit Timer/Counter 3 (TC3) or external Interrupt

Input 3 (INT3)

* P81 can be used as 8-bit Timer/Counter 4 (TC4) or programmable

divider output (PDO)

* P80 ~ P81 can be used as pull high or pull low pins

* P90~P97 are bi-directional I/O pins

* P90~P97 can be used as 8 channel 10-bit resolution A/D converter

* P97 can be used as AD reference power supply input (VREF)

OTP Programming Pins

Product Specification (V1.0) 07.26.2005

4 •

(This specification is subject to change without further notice)

4 Function Description

4.1 Functional Block Diagram

OSCI OSCO

WDT timer

Oscillator

Timing Control

R1 (TCC)

Control Sleep and

Wake-up I/O Port

WDT Prescaler

TCC Prescaler

General RAM

DATA a nd CONTRO L BU S

Interrupt

Control

ROM

Instruction

Decoder

EM78P809N

8-Bit Microcontroller

Stack

ALU

ACC

TC 2 (16-bit Timer/Counte r) TC 3 (8-bit Timer/Counter, Capture Mode) TC 4 (8-bit Timer/Counter, PWM, PDO) SPI (Serial Periphera l Interface) UART (Universal Asynchronous Receiver/Transmitter) 8 channel 10 bit ADC Keytone TBT (Time Base Timer)

PORT6

IOC6 R6

P60 ~ P67 P70 ~ P73 P80 ~ P81 P90 ~ P97

PORT7

IOC7 R7

PORT8

IOC8 R8

PORT9

IOC9 R9

Fig. 2. Functional Block Diagram

Product Specification ( V 1 . 0) 07 . 2 6 . 2 005

(This specification is subject to change without further notice)

• 5

EM78P809N

8-Bit Microcontroller

4.2 Operating Registers

Address

00 01 02 03 04 05 06 07 08 09

0A 0B 0C 0D 0E 0F

BANK 0

R0/ IAR

R1/ TCC

R2/ PC

R3/ SR

R4/ RSR

SCR

PORT6

PORT7

PORT8

PORT9

Reserved

TC4CR

TC4D

ISFR0

ISFR1

ISFR2

16 Byte

Common Register

BANK 1

R3 (7,6)= (0,1)

TC3CR

TC3DA

TC3DB

TC2CR/ ADDL

TC2DH

TC2DL

ADCR

ADIC

ADDH

TBKTC

Reserved

BANK 2

R3 (7,6)= (1,0) R3 (7,6)= (1,1)

URC1

URC2

URS

URRD

URTD

Reserved

BANK 3

SPIC1

SPIC2

Reserved

SPID

PHC1

PLC1

PHC2

PLC2

CONTROL REGISTER

Reserved

IOC6

IOC7

IOC8

IOC9

Reserved

INTCR

ADOSCR

Reserved

IMR1

IMR2

BANK 0

R4 (7,6) = (0,0)

32 Byte

Common Register

BANK 1

R4 (7,6) = (0,1)

32 Byte

Common Register

BANK2

R4 (7,6) = (1,0)

32 Bytes

Common Register

BANK 3

R4 (7,6) = (1,1)

32 Bytes

Common Register

Fig. 3. Operating Registers

Product Specification (V1.0) 07.26.2005

6 •

(This specification is subject to change without further notice)

EM78P809N

8-Bit Microcontroller

R0/IAR − Indirect Addressing Register ( Address: 00h )

R0 is not a physically implemented register. Its major function is to act as an indirect

addressing pointer. Any instruction using R0 as a pointer actually accesses data

pointed by the RAM Select Register (R4).

R1/TCC − Time Cloc k /Counter ( Address: 01h )

This register is writable and readable just like the other registers. The contents of the

prescaler counter are cleared only when a value is written into the TCC register.

R2/PC − Program Counter & Stack ( Address: 02h )

 Depending on the device type, R2 and hardware stack are 10-bit wide. The

structure is depicted in Fig.4.

 Generates 8192 ×13 bits on-chip OTP ROM addresses to the relative

programming instruction codes. One program page is 1024 words long.

 R2 is set as all "0"s when under RESET condition

 "JMP" instruction allows direct loading of the lower 10 program counter bits.

Thus, "JMP" allows the PC to go to any location within a page.

 "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is

pushed into the stack. Thus, the subroutine entry address can be located

anywhere within a page.

 "RET" ("RETL k", "RETI") instruction loads the program counter with the

contents of the top-level stack.

 All instructions are single instruction cycle (fclk/2 or fclk/4) except for the

instruction that would change the contents of R2. Such instruction will need

one more instruction cycle.

 For an interrupt trigger, the program ROM will jump to individual interrupt

vector at Page 0. The CPU will store ACC, R3 status and R5 PAGE

automatically, it will restore after instruction RETI.

Product Specification ( V 1 . 0) 07 . 2 6 . 2 005

(This specification is subject to change without further notice)

• 7

EM78P809N

8-Bit Microcontroller

A12

000 : PAGE0 0000~03FF 001 : PAGE1 0400~07FF 010 : PAGE2 0800~0BFF 011 : PAGE3 0C00~0FFF 100 : PAGE4 1000~13FF 101 : PAGE5 1400~17FF 110 : PAGE6 1800~1BFF 111 : PAGE7 1C00~1FFF

A11 A10 A9 A8 A7 ~ A0

CALL RET RETL RETI

STACK LEVEL 1 STACK LEVEL 2 STACK LEVEL 3 STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6 STACK LEVEL 7 STACK LEVEL 8

Store ACC, R3, R5

Reset Vector WDT Timer Overflow External INT0 Pin Interrupt Occurs TCC Overflow External INT1 pin Interrupt Occurs Time Base Timer Interrupt UART Transmit Data Buffer Empty UART Receive Data Buffer Full UART Receive Error TC3 Interrupt SPI Interrupt TC4 Interrupt External INT3 Pin Interrupt Occurs AD Conversion Complete External INT5 Pin Interrupt Occurs

On-chip Program Memory

0000h

0003h

0006h

0009h

000Fh

0012h

0015h

0018h

001Bh

0021h

0024h

0027h

0030h

0033h

0036h

User Memory Space

1FFFh

Fig. 4. Program Counter Organiz ation

R3/SR − Status Reg ister ( Address: 03h )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RBS1 RBS0 0 T P Z DC C

Bit 7 ~ Bit 6 (RBS1 ~ RBS0) : R-Register page select

RBS1 RBS0 Register Bank (Address 05H ~ 0FH)

0 0 Bank 0

0 1 Bank 1

1 0 Bank 2

1 1 Bank 3

Bit 5 : Not used

Bit 4 (T) : Time-out bit. Set to “1” with the "SLEP" and "WDTC" commands, or

during power up, and reset to “0” with the WDT time-out.

Product Specification (V1.0) 07.26.2005

8 •

(This specification is subject to change without further notice)

EM78P809N

8-Bit Microcontroller

Bit 3 (P) : Power down bit. Set to “1” during power on or by a "WDTC" command

and reset to “0” by a "SLEP" command.

Bit 2 (Z) : Zero flag. Set to "1" if the result of an arithmetic or logic operation is

zero.

Bit 1 (DC) : Auxiliary carry flag Bit 0 (C) : Carry flag

R4/RSR − RAM Select Register ( Address: 04h )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

GRBS1 RBS0 RSR5 RSR4 RSR3 RSR2 RSR1 RSR0

Bit 7: 6 ( GRBS1 : GRBS0 ) : determine which general purpose banks are

activated among the 4 banks. Use BANK instruction (e.g. BABK 1) to

change bank.

GRBS1 GRBS0 General Purpose Register Bank (Address 20H ~ 3FH)

0 0 Bank 0

0 1 Bank 1

1 0 Bank 2

1 1 Bank 3

Bit 5: 0 ( RS R5 : RSR0 ) : are used to select the registers (address: 00h~3Fh) in

the indirect addressing mode. If no indirect addressing is used, the RSR

can be used as an 8-bit general-purpose read/write register. See the

data memory configuration in Fig. 3.

SCR − System Control Register, Program ROM Page Select ( Address: 05h )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 PS2 PS1 PS0 0 1 SIS REM

Bit 6 (PS2 ) ~ 4 (PS 0) : ROM Page select bits. User can use PAGE instruction (e.g.

PAGE 1) or set PS2~PS0 bits to change the ROM page. When

executing a "JMP", "CALL", or other instructions which cause the

program counter to change (e.g. MOV R2, A), PS2~PS0 are loaded into

the 13th to 11th bits of the program counter and select one of the

available program memory pages. Note that RET (RETL, RETI)

instruction does not change the PS2~PS0 bits. That is, return will

always be to the page from where the subroutine was called, regardless

of the PS2~PS0 bits current setting.

Product Specification ( V 1 . 0) 07 . 2 6 . 2 005

(This specification is subject to change without further notice)

• 9

EM78P809N

8-Bit Microcontroller

PS2 PS1 PS0 Program Memory Page [Address]

0 0 0 Page 0 [0000~03FF]

0 0 1 Page 1 [0400~07FF]

0 1 0 Page 2 [0800~0BFF]

0 1 1 Page 3 [0C00~0FFF]

1 0 0 Page 4 [1000~13FF]

1 0 1 Page 5 [1400~17FF]

1 1 0 Page 6 [1800~1BFF]

1 1 1 Page 7 [1C00~1FFF]

Bit 1 ( SIS ) : SLEEP and IDLE mode select.

SIS = “0” : IDLE mode SIS = “1” : SLEEP mode

Bit 0 ( REM ) : Release method for sleep mode.

REM = “0” : /SLEEP pin input rising edge release REM = “1” : /SLEEP pin input “H” level release

PORT6 − Port 6 I/O Data Register ( Address: 06h )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

P67 P66 P65 P64 P63 P62 P61 P60

Bit 7 ~ Bit 0 ( P67 ~ P60 ) : 8-bits Port 6 I/O data register

User can use IOC6 register to define each bit whether input or output.

PORT7 — Port 7 I/O Data Register ( Address: 07h )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 0 0 0 P73 P72 P71 P70

Bit 3 ~ Bit 0 ( P73 ~ P70 ) : Port 73 ~ Port 70 I/O data register

User can use IOC7 register to define each bit whether input or output.

PORT8 − Port 8 I/O Data Register ( Address: 08h )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 0 0 0 0 0 P81 P80

Bit 1 ~ Bit 0 ( P81 ~ P80 ) : Port 81 ~ Port 80 I/O data register

User can use IOC8 register to define input or output each bit.

Product Specification (V1.0) 07.26.2005

10 •

(This specification is subject to change without further notice)

EM78P809N

8-Bit Microcontroller

PORT9 − Port 9 I/O Data Register ( Address: 09h )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

P97 P96 P95 P94 P93 P92 P91 P90

Bit 7 ~ Bit 0 ( P97 ~ P90 ) : 8-bit Port 97 ~ Port 90 I/O data register

User can use IOC9 register to define each bit whether input or output.

TC4CR — Timer/Counter 4 Control Register ( Address: 0Bh )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC4FF1 TC4FF0 TC4S TC4CK2 TC4CK1 TC4CK0 TC4M1 TC4M0

Bit 7 ~ Bit 6 ( TC4FF1 ~ TC4FF0 ) : Timer/Counter4 flip-flop control.

TC4FF1 TC4FF0 Operating Mode

0 0 Clear

0 1 Toggle

1 0 Set

1 1 Reserved

Bit 5 ( TC4S ) : Timer/Counter 4 start control.

TC4S = “0” : Stop and clear counter TC4S = “1” : Start

Bit 4 ~ Bit 2 ( TC4CK2 ~ TC4CK 0 ) : Timer/Counter 4 Clock Source Select

TC4CK2 TC4CK1 TC4CK0

0 0 0 Fc/2^11 250uS 64mS

0 0 1 Fc/2^7 16uS 4mS

0 1 0 Fc/2^5 4uS 1mS

0 1 1 Fc/2^3 1uS 255uS

1 0 0 Fc/2^2 500nS 127.5uS

1 0 1 Fc/2^1 250nS 63.8uS

1 1 0 Fc 125nS 31.9uS

1 1 1 External clock (TC4 pin) -- --

Clock Source

( Normal, Idle )

Resolution

( Fosc=8M )

Max. Time

( Fosc=8M )

Bit 1 ~ Bit 0 ( TC4M1 ~ TC4M0 ) : Timer/Counter 4 Operating Mode Select

TC4M1 TC4M0 Operating Mode

0 0 Timer/Counter

0 1 Reserved

1 0 Programmable Divider output

1 1 Pulse Width Modulation output

Product Specification ( V 1 . 0) 07 . 2 6 . 2 005

(This specification is subject to change without further notice)

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EM78P809N

8-Bit Microcontroller

TC4D − Timer 4 Data Buffer ( Address: 0Ch )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC4D7 TC4D6 TC4D5 TC4D4 TC4D3 TC4D2 TC4D1 TC4D0

ISFR0 − Interrupt Status Flag Register 0 and INT3 Edge Detect Flag.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit 7 ~ Bit 0 ( TC4D7 ~ TC4D0 ) : Data buffer of 8-bit Timer/Counter 4.

( Address : 0Dh )

0 0 INT3F INT3R 0 0 WDTIF EXIF0

Bit 5 ( INT3F ) : External interrupt 3 falling edge detect flag.

INT3F = “0” : Falling edge is not detected INT3F = “1” : Falling edge is detected

Bit 4 ( INT3R ) : External interrupt 3 rising edge detect flag.

INT3 R = “0” : Rising edge is not detected

INT3 R = “1” : Rising edge is detected Bit 1 ( WDTIF ) : WDT time-out flag, flag cleared by software. Bit 0 ( EXIF0 ) : External interrupt flag (INT0). Flag cleared by software. If the

INT0EN is reset to “0”, the flag is cleared.

ISFR1 − Interrupt Status Flag Register 1 ( Address: 0Eh )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

EXIF5 TCIF2 ADIF 0 EXIF3 TCIF4 SPIF TCIF3

Bit 7 ( EXIF5 ) : External Interrupt Flag (/INT5), flag cleared by software. Bit 6 ( TCIF2 ) : 16-bit Timer/Counter 2 Interrupt Flag, flag cleared by software. Bit 5 ( ADIF ) : AD conversion complete flag, flag cleared by software. Bit 3 ( EXIF3 ) : External Interrupt Flag (/INT3), flag cleared by software. Bit 2 ( TCIF4 ) : 8-bit Timer/Counter 4 Interrupt Flag, flag cleared by software. Bit 1 ( SPIF ) : SPI Mode Interrupt Flag, flag cleared by software. Bit 0 ( TCIF3 ) : 8-bit Timer/Counter 3 interrupt flag, flag cleared by software.

"1" means interrupt request, "0" means non-interrupt

 ISFR1 can be cleared by instruction, but cannot be set by instruction

 IMR1 is the interrupt mask register

 Note that reading ISFR1 will obtain the result of the ISFR1 "logic AND" and

IMR1.

Product Specification (V1.0) 07.26.2005

12 •

(This specification is subject to change without further notice)

EM78P809N

8-Bit Microcontroller

ISFR2 − Interrupt Status Flag Register 2 ( Address: 0Fh )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 UERRIF RBFF TBEF TBIF EXIF1 0 TCIF0

Bit 6 (UERRIF) : UART Receiving Error Interrupt, cleared by software or UART

disabled.

Bit 5 (RBFF) : UART Receive Mode Data Buffer Full Interrupt Flag. Flag cleared

by software.

Bit 4 (TBEF) : UART Transmit Mode Data Buffer Empty Interrupt Flag. Flag

cleared by software.

Bit 3 (TBIF) : Time Base Timer Interrupt Flag. Flag cleared by software. Bit 2 (EXIF1) : External Interrupt Flag (INT1). Flag cleared by software. Bit 0 (TCIF0) : TCC Overflow Interrupt Flag. Set as TCC overflows; flag cleared

by software.

"1" means interrupt request, "0" means non-interrupt

 ISFR2 can be cleared by instruction, but cannot be set by instruction

 IMR2 is the interrupt mask register

 Note that reading ISFR2 will obtain the result of the ISFR2 "logic AND" and

IMR2

TC3CR − Timer/Counter 3 Control Register ( Address: 05h )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC3CAP TC3S TC3CK1 TC3CK0 TC3M 0 0 0

Bit 7 ( TC3CAP ) : Software capture control

TC3CAP = “0” : -

TC3CAP = “1” : Software capture Bit 6 ( TC3S ) : Timer/Counter 3 start control

TC3S = “0” : Stop and counter clear TC3S = “1” : Start

Product Specification ( V 1 . 0) 07 . 2 6 . 2 005

(This specification is subject to change without further notice)

• 13

EM78P809N

8-Bit Microcontroller

TC3CK1 TC3CK0

TC3DA − Timer 3 Data Buffer A ( Address: 06h )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC3DA7 TC3DA6 TC3DA5 TC3DA4 TC3DA3 TC3DA2 TC3DA1 TC3DA0

Bit 5 ~ Bit 4 ( TC3CK1 ~ TC3CK0 ) : Timer/Counter3 Clock Source Select

Clock source

( Normal, Idle )

0 0 Fc/212 512μS 131.1mS

0 1 Fc/210 128μS 32.6mS

1 0 Fc/27 16μS 4.1mS

1 1 External clock (TC3 pin) - -

Resolution

( Fc=8M )

Max. time

( Fc=8M )

Bit 3 ( TC3M ) : Timer/Counter 3 mode select

TC3M = “0” : Timer/Counter3 mode

TC3M = “1” : Capture mode

Bit 7 ~ Bit 0 ( TC3DA7 ~ TC3DA0 ) : Data buffer of 8-bit Timer/Counter 3.

Reset does not affect this register.

TC3DB − Timer 3 Data Buffer B ( Addres s: 07h )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC3DB7 TC3DB6 TC3DB5 TC3DB4 TC3DB3 TC3DB2 TC3DB1 TC3DB0

Bit 7 ~ Bit 0 ( TC3DB7 ~ TC3DB0 ) : Data buffer of 8-bit Timer/Counter 3

Reset does not affect this register.

TC2CR/ ADDL — Timer/Counter 2 Control Register, AD Low 2 bits Data

Buffer ( A d dress: 08h )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ADD1 ADD0 0 TC2M TC2S TC2CK2 TC2CK1 TC2CK0

Bit 7 ~ Bit 6 ( ADD1 ~ ADD0 ) : AD low 2-bit data buffer Bit 4 ( TC2M ) : Timer/Counter 2 mode select

TC2M = “0” : Timer/counter mode

TC2M = “1” : Window mode

Bit 3 ( TC2S ) : Timer/Counter 2 start control

TC2S = “0” : Stop and counter clear

TC2S = “1” : Start

Product Specification (V1.0) 07.26.2005

14 •

(This specification is subject to change without further notice)

EM78P809N

8-Bit Microcontroller

Bit 2 ~ Bit 0 ( TC2CK2 ~ TC2CK0 ) : Timer/Counter 2 Clock Source Select

TC2CK2 TC2CK1 TC2CK0

0 0 0 Fc/223 1.05s 19.1h

0 0 1 Fc/213 1.02ms 1.1min

0 1 0 Fc/28 32μs 2.1s

0 1 1 Fc/23 1μs 65.5ms

1 0 0 Fc 125ns 7.9ms

1 0 1 - - -

1 1 0 - - -

1 1 1 External clock (TC2 pin)

Clock Source

( Normal, Idle )

Resolution

( Fc=8M )

Max. Time

( Fc=8M )

TC2DH − Timer 2 Data Buffer High Byte ( Address: 09h )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC2D15 TC2D14 TC2D13 TC2D12 TC2D11 TC2D10 TC2D9 TC2D8

Bit 7 ~ Bit 0 ( TC2D15 ~ TC2D8 ) : 16-bit Timer/Counter 2 data buffer high byte.

TC2DL − Timer 2 Data Buffer Low Byte ( Address: 0Ah )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC2D7 TC2D6 TC2D5 TC2D4 TC2D3 TC2D2 TC2D1 TC2D0

Bit 7 ~ Bit 0 ( TC2D7 ~ TC2D0 ) : 16-bit Timer/Counter 2 data buffer low byte.

ADCR − AD Control Register ( Address: 0Bh )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ADREF ADRUN ADCK1 ADCK0 ADP ADIS2 ADIS1 ADIS0

Bit 7 ( ADREF ) : AD reference voltage input select.

ADREF = “0” : Internal VDD, P97 is used as IO.

ADREF = “1” : External reference pin, P97 is used as reference input pin. Bit 6 ( ADRUN ) : AD Conversion start

ADRUN = “0” : Reset on completion of the conversion by hardware, this bit

cannot be reset by software.

ADRUN = “1” : Conversion starts

Product Specification ( V 1 . 0) 07 . 2 6 . 2 005

(This specification is subject to change without further notice)

• 15

EM78P809N

8-Bit Microcontroller

Bit 5~ Bit 4 ( ADCK1 ~ ADCK0 ) : AD Conversion Time Select

ADCK1 ADCK0

0 0 Fc/4 1MHz

0 1 Fc/16 4MHz

1 0 Fc/32 8MHz

1 1 Reserved -

Clock Source

( Normal, Idle )

Max. Op erating Frequency (Fc)

Bit 3 ( ADP ) : AD power control

ADP = “0” : Power on

ADP = “1” : Power down

Bit 2 ~ Bit 0 ( ADIS2 ~ ADIS0 ) : Analog Input Pin Select

ADIS2 ADIS1 ADIS0 Analog Input Pin

0 0 0 AD0

0 0 1 AD1

0 1 0 AD2

0 1 1 AD3

1 0 0 AD4

1 0 1 AD5

1 1 0 AD6

1 1 1 AD7

ADIC − AD Input Pin Control ( Address: 0Ch )

Bit 7 Bit 6 Bit 5 Bit 4 Bi t 3 Bit 2 Bit 1 Bit 0

ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0

Bit 7 ~ Bit 0 ( ADE7 ~ ADE0 ) : AD input pin enable control.

ADEx = “0” : PORT9.x act as I/O pin.

ADEx = “1” : PORT9.x act as analog input pin.

ADDH − AD High 8-bit Data Buffer ( Address: 0Dh )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2

Bit 7 ~ Bit 0 ( ADD9 ~ ADD2 ) : AD high 8-bit data buffer.

Product Specification (V1.0) 07.26.2005

16 •

(This specification is subject to change without further notice)

EM78P809N

8-Bit Microcontroller

TBKTC − TBT/Keytone Control ( Address: 0Eh )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TEN TCK1 TCK0 0 TBTEN TBTCK2 TBTCK1 TBTCK0

Bit 7 ( TEN ) : Keytone enable control

TEN = “0” : Disable

TEN = “1” : Enable Bit 6 ~ Bit 5 ( TCK1 ~ TCK0 ) : Keytone Output Clock Source Select

TCK1 TCK0

0 0 Fc/213 0.976kHz

0 1 Fc/212 1.953kHz

1 0 Fc/211 3.906kHz

1 1 Fc/210 7.812kHz

Clock Source

( Normal, Idle )

Bit 3 ( TBTEN ) : Time Base Timer Enable Control

TBTEN = “0” : Disable

Keytone Output Frequency

( Fc = 8MHz )

TBTEN = “1” : Enable Bit 2 ~ Bit 0 ( TBTCK2 ~ TBTCK0 ) : Time Base Timer Clock Source Select

TBTCK2 TBTCK1 TBTCK0

0 0 0 Fc/223 0.95Hz

0 0 1 Fc/221 3.81Hz

0 1 0 Fc/216 122.07Hz

0 1 1 Fc/214 488.28Hz

1 0 0 Fc/213 976.56Hz

1 0 1 Fc/212 1953.12Hz

1 1 0 Fc/211 3906.25Hz

1 1 1 Fc/29 15625Hz

URC1 − UART Control Register 1 ( Address: 05h )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

URTD8 UMODE1 UMODE0 BRATE2 BRATE1 BRATE0 UTBE TXE

Clock Source

( Normal, Idle )

Interrupt Frequency

( Fc = 8MHz )

Bit 7 ( URTD8 ) : Transmission data bit 8

Product Specification ( V 1 . 0) 07 . 2 6 . 2 005

(This specification is subject to change without further notice)

• 17

EM78P809N

8-Bit Microcontroller

Bit 6 ~ Bit 5 ( UMODE1 ~ UMODE0 ) : UART Transmission Mode Select Bit

UMODE1 UMODE0 UART Mode

0 0 Mode1: 7-bits

0 1 Mode2: 8-bits

1 0 Mode3: 9-bits

1 1 Reserved

Bit 4 ~ Bit 2 ( BRAT E2 ~ BRATE1 ) : Transmit Baud Rate Select

BRATE2 BRATE1 BRATE0 Baud Rate e.g. Fc=8MH z

0 0 0 Fc/13 38400

0 0 1 Fc/26 19200

0 1 0 Fc/52 9600

0 1 1 Fc/104 4800

1 0 0 Fc/208 2400

1 0 1 Fc/416 1200

1 1 0 TC4

1 1 1 Fc/96

Bit 1 ( UTBE ) : UART transfer buffer empty flag. Set to 1 when transfer buffer is

empty. Reset to 0 automatically when writing into the URTD register. UTBE bit will

be cleared by hardware when enabling the transmission. UTBE bit is read-only.

Therefore, writing to the URTD register is necessary when we want to start

transmission shifting.

Bit 0 ( TXE ) : Enable transmission

TXE = “0” : Disable

TXE = “1” : Enable

URC2 − UART Control Register 2 ( Address: 06h )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 0 SBIM1 SBIM0 UINVEN 0 0 0

Bit 5 ~ Bit 4 ( SBIM1 ~ SBIM0 ) : Serial bus interface operation mode select.

TC2CK1 TC2CK0 Operation Mode

0 0 I/O mode

0 1 SPI mode

1 0 UART mode

1 1 Reserved

Bit 3 ( UINVEN ) : Enable UART TXD and RXD port inverse output.

UINVEN = “0” : Disable TXD and RXD port inverse output.

UINVEN = “1” : Enable TXD and RXD port inverse output.

Product Specification (V1.0) 07.26.2005

18 •

(This specification is subject to change without further notice)

EM78P809N

8-Bit Microcontroller

URS − UART Status Register ( Address: 07h )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

URRD8 EVEN PRE PRERR OVERR FMERR URBF RXE

Bit 7 ( URRD8 ) : Receiving data bit 8 Bit 6 ( EVEN ) : Select parity check EVEN = “0” : Odd parity EVEN = “1” : Even parity Bit 5 ( PRE ) : Enable parity addition PRE = “0” : Disable PRE = “1” : Enable Bit 4 ( PRERR ) : Parity error flag.

Set to 1 when parity error occurred, and cleared to 0 by software.

Bit 3 ( OVERR ) : Overrun error flag.

Set to 1 when overrun error occurred, and cleared to 0 by software.

Bit 2 ( FMERR ) : Framing error flag.

Set to 1 when framing error occurred, and cleared to 0 by software.

Bit 1 ( URBF ) : UART read buffer full flag.

Set to 1 when one character is received. Reset to 0 automatically when read

from the URS register. URBF will be cleared by hardware when receiving is

enabled. URBF bit is read-only. Therefore, reading the URS register is

necessary to avoid an overrun error.

Bit 0 ( RXE ) : Enable receiving RXE = “0” : Disable RXE = “1” : Enable

URRD − UART Receive Data Buffer ( Address: 08h )

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

URRD7 URRD6 URRD5 URRD4 URRD3 URRD2 URRD1 URRD0

Bit 7 ~ Bit 0 ( URRD7 ~ URRD0 ) : UART receive data buffer. Read only.

Product Specification ( V 1 . 0) 07 . 2 6 . 2 005

(This specification is subject to change without further notice)

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