IBM EM78P447N User Manual

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EM78P447N

8-Bit Microcontroller

with OTP ROM

Product

Specification

DOC. VERSION 1.1

ELAN MICROELECTRONICS CORP.

March 2005

Trademark Acknowledgments:

IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation.

ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation.

Copyright © 2005 by ELAN Microelectronics Corporation

All Rights Reserved

Printed in Taiwan

The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order.

In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material.

The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement.

ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited.

NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.

ELAN MICROELECTRONICS CORPORATION

Headquarters:

No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw

Hong Kong:

USA:

Elan (HK) Microelectronics

Elan Information

Corporation, Ltd.

Technology Group

Rm. 1005B, 10/F Empire Centre

1821 Saratoga Ave., Suite 250

68 Mody Road, Tsimshatsui

Saratoga, CA 95070

Kowloon , HONG KONG

USA

Tel: +852 2723-3376

Tel: +1 408 366-8223

Fax: +852 2723-7780

Fax: +1 408 366-8220

elanhk@emc.com.hk

 

Europe:

Shenzhen:

Shanghai:

Elan Microelectronics Corp.

Elan Microelectronics

Elan Microelectronics

(Europe)

Shenzhen, Ltd.

Shanghai Corporation, Ltd.

Siewerdtstrasse 105

SSMEC Bldg., 3F, Gaoxin S. Ave.

23/Bldg. #115 Lane 572, Bibo Road

8050 Zurich, SWITZERLAND

Shenzhen Hi-Tech Industrial Park

Zhangjiang Hi-Tech Park

Tel: +41 43 299-4060

Shenzhen, Guandong, CHINA

Shanghai, CHINA

Fax: +41 43 299-4079

Tel: +86 755 2601-0565

Tel: +86 021 5080-3866

http://www.elan-europe.com

Fax: +86 755 2601-0500

Fax: +86 021 5080-4600

 

 

 

 

 

 

 

Contents

 

 

 

 

 

 

 

Contents

 

 

1

GENERAL DESCRIPTION .........................................................................................

1

 

2

FEATURES

.................................................................................................................

1

 

3

PIN ASSIGNMENT .....................................................................................................

3

 

4

FUNCTION ........................................................................................DESCRIPTION

6

 

 

4.1

Operational .........................................................................................Registers

7

 

 

 

4.1.1 .......................................................................

R0 (Indirect Addressing Register)

7

 

 

 

4.1.2 ....................................................................................R1 (Time Clock /Counter)

7

 

 

 

4.1.3 ...........................................................................R2 (Program Counter) & Stack

7

 

 

 

4.1.4 ..........................................................................................

R3 (Status Register)

10

 

 

 

4.1.5 .................................................................................R4 (RAM Select Register)

10

 

 

 

4.1.6 .....................................................................................R5~R7 (Port 5 ~ Port7)

10

 

 

 

4.1.7 ........................................R8~R1F and R20~R3E (General Purpose Register)

10

 

 

 

4.1.8 .........................................................................R3F (Interrupt Status Register)

11

 

 

4.2

Special ...............................................................................Purpose Registers

11

 

 

 

4.2.1 .................................................................................................

A (Accumulator)

11

 

 

 

4.2.2 ...................................................................................

CONT (Control Register)

11

 

 

 

4.2.3 ..........................................................IOC5 ~ IOC7 (I/O Port Control Register)

12

 

 

 

4.2.4 ......................................................IOCB (Wake-up Control Register for Port6)

12

 

 

 

4.2.5 ...........................................................................IOCE (WDT Control Register)

13

 

 

 

4.2.6 .........................................................................IOCF (Interrupt Mask Register)

14

 

 

4.3

TCC/WDT .....................................................................................& Prescaler

15

 

 

4.4

I/O Ports ...........................................................................................................

16

 

 

4.5

RESET .......................................................................................and Wake-up

17

 

 

 

4.5.1 ..............................................................................................................

RESET

17

 

 

 

4.5.2 .............................................The Status of RST, T, and P of STATUS Register

21

 

 

4.6

Interrupt ............................................................................................................

22

 

 

4.7

Oscillator ..........................................................................................................

23

 

 

 

4.7.1 ................................................................................................

Oscillator Modes

23

 

 

 

4.7.2 ..................................................

Crystal Oscillator/Ceramic Resonators(XTAL)

24

 

 

 

4.7.3 .............................................................................External RC Oscillator Mode

25

 

 

4.8

CODE .....................................................................................Option Register

26

 

 

 

4.8.1 .........................................................................Code Option Register (Word 0)

26

 

 

 

4.8.2 .........................................................................Customer ID Register (Word 1)

28

 

 

4.9

Power ................................................................................On Considerations

28

 

 

4.10 External ......................................................................Power On Reset Circuit

28

 

 

4.11

Residue ..............................................................................-Voltage Protection

29

 

 

4.12

Instruction ..................................................................................................Set

30

 

 

4.13 Timing ................................................................................................Diagram

33

 

 

 

 

Product Specification (V1.1) 03.30.2005

iii

 

Contents

5

ABSOLUTE MAXIMUM RATINGS ...........................................................................

34

6

DC ELECTRICAL CHARACTERISTICS ..................................................................

34

 

6.1

DC Electrical Characteristic..............................................................................

34

 

6.2

AC Electrical Characteristic..............................................................................

35

 

6.3

Device Characteristic .......................................................................................

36

 

 

APPENDIX

A

Package Types.........................................................................................................

50

B

Package Information...............................................................................................

50

Specification Revision History

Doc. Version

Revision Description

Date

1.0

Initial version

10/29/2004

 

 

 

1.1

Add four kinds of package type

03/30/2005

 

 

 

iv

Product Specification (V1.1) 03.30.2005

EM78P447N

8-Bit Microcontroller with OTP ROM

1 GENERAL DESCRIPTION

EM78P447N is an 8-bit microprocessor with low-power and high-speed CMOS technology and high noise immunity. It is equipped with 4K*13-bits Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides three PROTECTION bits to prevent user’s code in the OTP memory from being intruded. Seven OPTION bits are also available to meet user’s requirements.

With its OTP-ROM feature, the EM78P447N is able to offer a convenient way of developing and verifying user’s programs. Moreover, user can take advantage of ELAN Writer to easily program his development code.

2 FEATURES

Operating voltage range: 2.5V~5.5V.

Operating temperature range: -40°C~85°C.

Operating frequency rang( base on 2 clocks)

Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz at 2.5V.

RC mode: DC~4MHz at 5V, DC~4MHz at 3V, DC~4MHz at 2.5V.

Low power consumption:

Less then 2.2 mA at 5V/4MHz

Typically 35 µA, at 3V/32KHz

Typically 2 µA, during sleep mode

4K × 13 bits on chip ROM

Three protection bits to prevent intrusion of OTP memory codes

One configuration register to accommodate user’s requirements

148× 8 bits on chip registers(SRAM, general purpose register)

3 bi-directional I/O ports

5 level stacks for subroutine nesting

8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt

Two clocks per instruction cycle

Power down (SLEEP) mode

Two available interruptions

TCC overflow interrupt

External interrupt

Product Specification (V1.1) 03.30.2005

1

(This specification is subject to change without further notice)

EM78P447N

8-Bit Microcontroller with OTP ROM

Programmable free running watchdog timer

10 programmable pull-high pins

2 programmable open-drain pins

2 programmable R-option pins

Package types:

 

20 pin DIP 300mil

:EM78P447NDP

20 pin SOP 300mil

:EM78P447NDM

24 pin Skinny DIP 300mil

:EM78P447NCK

24 pin SOP 300mil

:EM78P447NCM

28 pin DIP 600mil

:EM78P447NAP

28 pin SOP 300mil

:EM78P447NAM

28 pin SSOP 209mil

:EM78P447NAS

32 pin DIP 600mil

:EM78P447NBP

32 pin SOP 450mil

:EM78P447NBWM

99.9% single instruction cycle commands

The transient point of system frequency between HXT and LXT is around 400KHz

2

Product Specification (V1.1) 03.30.2005

(This specification is subject to change without further notice)

EM78P447N

8-Bit Microcontroller with OTP ROM

3 PIN ASSIGNMENT

TCC

 

1

 

VDD

 

2

 

NC

 

3

 

Vss

 

4

 

/INT

 

5

 

P50

 

6

 

P51

 

7

 

P52

 

8

 

 

9

P53

 

 

10

P60

 

 

11

P61

 

 

12

P62

 

 

13

P63

 

 

14

P64

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P55

 

1

 

 

32

 

P56

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

28

 

 

/RESET

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P54

 

2

 

 

31

 

P57

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vss

 

 

1

 

28

 

 

/RESET

 

TCC

 

3

 

 

30

 

/RESET

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

27

 

 

OSCI

 

TCC

 

 

2

 

27

 

 

OSCI

 

VDD

 

4

 

 

29

 

OSCI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

26

 

 

OSCO

 

VDD

 

 

3

 

26

 

 

OSCO

 

 

NC

 

5

 

 

28

 

OSCO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

25

 

 

P77

 

/INT

 

 

4

 

25

 

 

P77

 

 

Vss

 

6

EM78P447NBWM

EM78P447NBP

27

 

P77

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EM78P447NAM

EM78P447NAP

24

 

 

P76

 

P50

 

 

5

EM78P447NAS

24

 

 

P76

 

/INT

 

7

26

 

P76

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

23

 

 

P75

 

P51

 

 

6

 

23

 

 

P75

 

 

P50

 

8

 

 

25

 

P75

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

22

 

 

P74

 

P52

 

 

7

 

22

 

 

P74

 

 

P51

 

9

 

 

24

 

P74

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

21

 

 

P73

 

 

 

 

 

8

 

21

 

 

P73

 

 

P52

 

10

 

 

23

 

P73

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P53

 

 

 

 

 

 

 

 

 

 

 

 

20

 

 

P72

 

 

 

 

 

9

 

20

 

 

 

 

 

 

 

 

 

11

 

 

22

 

P72

 

 

 

 

 

P60

 

 

 

 

P72

 

 

P53

 

 

 

 

 

 

19

 

 

P71

 

 

 

 

 

10

 

19

 

 

 

 

 

 

 

 

 

12

 

 

21

 

P71

 

 

 

 

 

P61

 

 

 

 

P71

 

 

P60

 

 

 

 

 

 

18

 

 

P70

 

P62

 

 

11

 

18

 

 

P70

 

 

P61

 

13

 

 

20

 

P70

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

17

 

 

 

 

 

 

 

 

 

12

 

17

 

 

 

 

 

 

 

 

 

14

 

 

19

 

P67

 

 

 

 

P67

 

P63

 

 

 

 

 

P67

 

 

P62

 

 

 

 

 

 

16

 

 

P66

 

 

 

 

 

13

 

16

 

 

 

 

 

 

 

P63

 

15

 

 

18

 

P66

 

 

 

 

 

P64

 

 

 

 

 

P66

 

 

 

 

 

 

 

 

15

 

 

 

 

 

Vss

 

14

 

15

 

 

 

 

 

 

 

 

 

16

 

 

17

 

P65

 

 

 

 

P65

 

 

 

 

 

 

P65

 

 

P64

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIP

 

 

 

 

 

 

 

 

 

 

SSOP

 

 

 

 

 

 

 

 

 

 

 

DIP

 

 

 

SOP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SOP

 

 

 

 

 

P54

 

 

 

 

 

 

 

/RESET

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

24

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCC

 

 

2

 

23

 

 

OSCI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDD

 

 

3

 

22

 

 

OSCO

 

P54

 

 

1

 

 

20

 

/RESET

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vss

 

 

4

 

21

 

 

P77

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCC

 

 

2

 

 

19

 

OSCI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

/INT

 

 

5

EM78P447NCK EM78P447NCM

20

 

 

P76

 

 

 

EM78P447NDM

EM78P447NDP

 

 

 

 

 

 

 

 

 

 

 

 

P51

 

 

7

14

 

P74

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P53

 

 

9

16

 

 

P66

 

 

 

 

 

 

 

 

 

 

 

P50

 

 

6

 

19

 

 

P75

 

VDD

 

 

3

 

 

18

 

OSCO

 

 

 

 

 

 

P51

 

 

7

 

18

 

 

P74

 

 

Vss

 

 

4

 

 

17

 

P77

 

 

 

 

 

 

 

 

 

 

 

 

 

/INT

 

 

5

 

 

16

 

P76

 

 

 

 

 

 

 

P52

 

 

8

 

17

 

 

P67

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P50

 

 

6

 

 

15

 

P75

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P60

 

 

10

 

15

 

 

P65

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P52

 

 

8

 

 

13

 

P73

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P61

 

 

11

 

14

 

 

P64

 

P53

 

 

9

 

 

12

 

P72

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P62

 

 

 

 

 

P63

 

P60

 

 

10

 

 

11

 

P71

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Skinny DIP

 

 

 

 

 

 

 

 

 

 

DIP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SOP

 

 

 

 

 

 

 

 

 

 

 

 

SOP

 

 

 

 

 

 

 

 

Fig. 1 Pin Assignment

Product Specification (V1.1) 03.30.2005

3

(This specification is subject to change without further notice)

EM78P447N

8-Bit Microcontroller with OTP ROM

Table 1 EM78P447NAP and EM78P447NAM Pin Description

Symbol

 

Pin No.

 

Type

 

Function

 

VDD

 

2

 

-

 

■ Power supply.

OSCI

 

27

 

I

 

■ XTAL type: Crystal input terminal or external clock input pin.

 

 

 

■ RC type: RC oscillator input pin.

 

 

 

 

 

 

 

 

 

 

 

 

■ XTAL type: Output terminal for crystal oscillator or external clock input pin.

OSCO

 

26

 

I/O

 

■ RC type: Instruction clock output.

 

 

 

 

 

 

■ External clock signal input.

TCC

 

1

 

I

 

■ The real time clock/counter (with Schmitt trigger input pin) must be tied to

 

 

 

VDD or VSS if not in use.

 

 

 

 

 

 

/RESET

 

28

 

I

 

■ Input pin with Schmitt trigger. If this pin remains at logic low, the controller

 

 

 

will also remain in reset condition.

 

 

 

 

 

 

P50~P53

 

6~9

 

I/O

 

■ P50~P53 are bi-directional I/O pins.

P60~P67

 

10~17

 

I/O

 

■ P60~P67 are bi-directional I/O pins. These can be pulled-high internally by

 

 

 

software control.

 

 

 

 

 

 

 

 

 

 

 

 

■ P70~P77 are bi-directional I/O pins.

P70~P77

 

18~25

 

I/O

 

■ P74~P75 can be pulled-high internally by software control.

 

 

 

■ P76~P77 can have open-drain output by software control.

 

 

 

 

 

 

 

 

 

 

 

 

■ P70 and P71 can also be defined as the R-option pins.

/INT

 

5

 

I

 

■ External interrupt pin triggered by falling edge.

VSS

 

4

 

-

 

■ Ground.

NC

 

3

 

-

 

■ No connection.

Table 2 EM78P447NAS Pin Description

Symbol

 

Pin No.

 

Type

 

Function

 

 

 

 

 

 

 

 

 

VDD

 

3

 

-

 

■ Power supply.

 

OSCI

 

27

 

I

 

■ XTAL type: Crystal input terminal or external clock input pin.

 

 

 

 

■ RC type: RC oscillator input pin.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

■ XTAL type: Output terminal for crystal oscillator or external clock input pin.

 

OSCO

 

26

 

I/O

 

■ RC type: Instruction clock output.

 

 

 

 

 

 

 

■ External clock signal input.

 

TCC

 

2

 

I

 

■ The real time clock/counter (with Schmitt trigger input pin) must be tied to

 

 

 

 

VDD or VSS if not in use.

 

 

 

 

 

 

 

 

/RESET

 

28

 

I

 

■ Input pin with Schmitt trigger. If this pin remains at logic low, the controller

 

 

 

 

will also remain in reset condition.

 

 

 

 

 

 

 

 

P50~P53

 

5~8

 

I/O

 

■ P50~P53 are bi-directional I/O pins.

 

P60~P67

 

9~13,

 

I/O

 

■ P60~P67 are bi-directional I/O pins. These can be pulled -high internally by

 

 

15~17

 

 

software control.

 

 

 

 

 

 

 

■ P70~P77 are bi-directional I/O pins.

 

P70~P77

 

18~25

 

I/O

 

■ P74~P75 can be pulled -high internally by software control.

 

 

 

 

■ P76~P77 can have open-drain output by software control.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

■ P70 and P71 can also be defined as the R-option pins.

 

/INT

 

4

 

I

 

■ External interrupt pin triggered by falling edge.

 

VSS

 

1,14

 

-

 

■ Ground.

 

4

Product Specification (V1.1) 03.30.2005

(This specification is subject to change without further notice)

EM78P447N

8-Bit Microcontroller with OTP ROM

Table 3 EM78P447NBP and EM78P447NBWM Pin Description

Symbol

Pin No.

Type

Function

VDD

4

-

■ Power supply.

OSCI

29

I

■ XTAL type: Crystal input terminal or external clock input pin.

■ RC type: RC oscillator input pin.

 

 

 

 

 

 

■ XTAL type: Output terminal for crystal oscillator or external clock input pin.

OSCO

28

I/O

■ RC type: Instruction clock output.

 

 

 

■ External clock signal input.

TCC

3

I

■ The real time clock/counter (with Schmitt trigger input pin), must be tied to

VDD or VSS if not in use.

 

 

 

/RESET

30

I

■ Input pin with Schmitt trigger. If this pin remains at logic low, the controller

will keep in reset condition.

 

 

 

P50~P57

8~11,2~1,

I/O

■ P50~P57 are bi-directional I/O pins.

 

32~31

 

 

P60~P67

12~19

I/O

■ P60~P67 are bi-directional I/O pins. These can be pulled -high internally by

software control.

 

 

 

 

 

 

■ P70~P77 are bi-directional I/O pins.

P70~P77

20~27

I/O

■ P74~P75 can be pulled-high internally by software control.

■ P76~P77 can have open-drain output by software control.

 

 

 

 

 

 

■ P70 and P71 can also be defined as the R-option pins.

/INT

7

I

■ External interrupt pin triggered by falling edge.

VSS

6

-

■ Ground.

NC

5

-

■ No connection.

Table 4 EM78P447NCK and EN78P447NCM Pin Description

Symbol

 

Pin No.

 

Type

 

Function

 

VDD

 

3

 

-

 

■ Power supply.

OSCI

 

23

 

I

 

■ XTAL type: Crystal input terminal or external clock input pin.

 

 

 

■ RC type: RC oscillator input pin.

 

 

 

 

 

 

 

 

 

 

 

 

■ XTAL type: Output terminal for crystal oscillator or external clock input pin.

OSCO

 

22

 

I/O

 

■ RC type: Instruction clock output.

 

 

 

 

 

 

■ External clock signal input.

TCC

 

2

 

I

 

■ The real time clock/counter (with Schmitt trigger input pin) must be tied to

 

 

 

VDD or VSS if not in use.

 

 

 

 

 

 

/RESET

 

24

 

I

 

■ Input pin with Schmitt trigger. If this pin remains at logic low, the controller

 

 

 

will also remain in reset condition.

 

 

 

 

 

 

P50~P54

 

6~9,1

 

I/O

 

■ P50~P54 are bi-directional I/O pins.

P60~P67

 

10~17

 

I/O

 

■ P60~P67 are bi-directional I/O pins. These can be pulled-high internally by

 

 

 

software control.

 

 

 

 

 

 

 

 

 

 

 

 

■ P74~P77 are bi-directional I/O pins.

P74~P77

 

18~21

 

I/O

 

■ P74~P75 can be pulled-high internally by software control.

 

 

 

 

 

 

■ P76~P77 can have open-drain output by software control.

/INT

 

5

 

I

 

■ External interrupt pin triggered by falling edge.

VSS

 

4

 

-

 

■ Ground.

NC

 

3

 

-

 

■ No connection.

Product Specification (V1.1) 03.30.2005

5

(This specification is subject to change without further notice)

EM78P447N

8-Bit Microcontroller with OTP ROM

Table 5 EM78P447NDK and EM78P447NDM Pin Description

Symbol

 

Pin No.

 

Type

 

Function

 

VDD

 

3

 

-

 

■ Power supply.

 

OSCI

 

19

 

I

 

■ XTAL type: Crystal input terminal or external clock input pin.

 

 

 

 

■ RC type: RC oscillator input pin.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

■ XTAL type: Output terminal for crystal oscillator or external clock input pin.

 

OSCO

 

18

 

I/O

 

■ RC type: Instruction clock output.

 

 

 

 

 

 

 

■ External clock signal input.

 

TCC

 

2

 

I

 

■ The real time clock/counter (with Schmitt trigger input pin) must be tied to

 

 

 

 

VDD or VSS if not in use.

 

 

 

 

 

 

 

 

/RESET

 

20

 

I

 

■ Input pin with Schmitt trigger. If this pin remains at logic low, the controller

 

 

 

 

will also remain in reset condition.

 

 

 

 

 

 

 

 

P50~P54

 

6~9,1

 

I/O

 

■ P50~P54 are bi-directional I/O pins.

 

P60

 

10

 

I/O

 

■ P60 are bi-directional I/O pins. This can be pulled-high internally by

 

 

 

 

software control.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

■ P74~P77 are bi-directional I/O pins.

 

P71~P77

 

11~17

 

I/O

 

■ P74~P75 can be pulled-high internally by software control.

 

 

 

 

■ P76~P77 can have open-drain output by software control.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

■ P71 can also be defined as the R-option pins.

 

/INT

 

5

 

I

 

■ External interrupt pin triggered by falling edge.

 

VSS

 

4

 

-

 

■ Ground.

 

NC

 

3

 

-

 

■ No connection.

 

4 FUNCTION DESCRIPTION

O S C I O S C O /R E S E T

 

T C C

/IN T

 

 

 

 

 

 

 

 

 

W D T T im e r

 

 

 

P C

S T A C K 1

O s c illa to r/T im in g

 

 

 

 

 

 

 

 

 

S T A C K 2

C o n tro l

 

 

 

 

 

 

 

 

 

 

S T A C K 3

P re s c a le

 

 

 

 

 

 

 

 

 

r

 

 

 

R O M

 

S T A C K 4

W D T

 

 

 

 

 

S T A C K 5

 

 

 

 

 

 

T im -e o u t

 

In te rru p t

 

 

 

 

 

In s tru c tio n

 

 

 

 

C o n tro l

 

 

R 1 (T C C )

 

R e g is te r

 

 

 

 

 

 

A L U

 

 

 

 

 

S le e p

R A M

 

 

In s tru c tio n

 

 

 

 

D e c o d e r

 

 

&

 

 

 

 

R 3

 

W a k e

 

 

 

 

A C C

 

 

 

 

 

C o n tro l

R 4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D A T A & C O N T R O L B U S

 

 

IO C 5

 

IO C 6

 

IO C 7

 

R 5

 

R6

 

R 7

 

PPPPPPPP

 

PPPPPPPP

 

PPPPPPPP

 

55555555

 

66666666

 

77777777

 

0123 4567

 

0123 4567

 

01234567

 

 

Fig. 2

Functional Block Diagram

 

 

6

Product Specification (V1.1) 03.30.2005

(This specification is subject to change without further notice)

EM78P447N

8-Bit Microcontroller with OTP ROM

4.1 Operational Registers

4.1.1 R0 (Indirect Addressing Register)

R0 is not a physically implemented register. Its major function is to act as an indirect addressing pointer. Any instruction using R0 as a pointer actually accesses data pointed by the RAM Select Register (R4).

4.1.2 R1 (Time Clock /Counter)

Increased by an external signal edge, which is defined by TE bit (CONT-4) through the TCC pin, or by the instruction cycle clock.

Writable and readable as any other registers.

Defined by resetting PAB (CONT-3).

The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.

The contents of the prescaler counter will be cleared only when TCC register is written a value.

4.1.3 R2 (Program Counter) & Stack

Depending on the device type, R2 and hardware stack are 10-bit wide. The structure is depicted in Fig.3.

Generating 1024×13 bits on-chip OTP ROM addresses to the relative programming instruction codes. One program page is 1024 words long.

R2 is set as all "0"s when under RESET condition.

"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to go to any location within a page.

"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page.

"RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top-level stack.

"ADD R2,A" allows the contents of ‘A’ to be added to the current PC, and the ninth and tenth bits of the PC are cleared.

"MOV R2,A" allows to load an address from the "A" register to the lower 8 bits of the PC, and the ninth and tenth bits of the PC are cleared.

Any instruction that writes to R2 (e.g. "ADD R2,A", "MOV R2,A", "BC R2,6", ) will cause the ninth and tenth bits (A8~A9) of the PC to be cleared. Thus, the computed jump is limited to the first 256 locations of a page.

Product Specification (V1.1) 03.30.2005

7

(This specification is subject to change without further notice)

EM78P447N

8-Bit Microcontroller with OTP ROM

All instruction are single instruction cycle (fclk/2 or fclk/4) except for the instruction that would change the contents of R2. Such instruction will need one more instruction cycle.

R3

 

 

 

 

A11 A10 A9 A8

A7

~

A0

Hardware Vector

 

CALL

 

 

Software Vector

 

 

 

 

 

RET

 

 

 

 

RETL

 

 

On-chip Program

 

RETI

 

 

00 PAGE0 0000~03FF

Stack Level 1

Memory

 

01 PAGE1 0400~07FF

Stack Level 2

 

10 PAGE2 0800~0BFF

Stack Level 3

 

11 PAGE3 0C00~0FFF

Stack Level 4

 

 

 

Stack Level 5

Reset Vector

000H

001H

002H

Memory User

Space

FFFH

Fig. 3 Program Counter Organization

8

Product Specification (V1.1) 03.30.2005

(This specification is subject to change without further notice)

EM78P447N

8-Bit Microcontroller with OTP ROM

Aaddress

R PAGE registers

IOC PAGE registers

 

 

 

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

1F

20

3E

R0 (Indirect Addressing Register)

R1 (Time Clock Counter)

R2 (Program Counter)

R3 (Status Register)

R4 (RAM Select Register)

R5 (Port5)

R6 (Port6)

R7 (Port7)

General Register

General Register

General Register

General Register

General Register

General Register

General Register

General Register

General Registers

Bank0 Bank1 Bank2 Bank3

Reserve

CONT (Control Register)

Reserve

Reserve

Reserve

IOC5 (I/O Port Control Register)

IOC6 (I/O Port Control Register)

IOC7 (I/O Port Control Register)

Reserve

Reserve

Reserve

IOCB (Wake-Up Control Register for Port6 )

Reverse

Reverse

IOCE (WDT,SLEEP2,Open Drain,R -Option

Control Register)

IOCF (Interrupt Mask Register)

3F

R3F (Interrupt Status Register)

Fig. 4 Data Memory Configuration

Product Specification (V1.1) 03.30.2005

9

(This specification is subject to change without further notice)

EM78P447N

8-Bit Microcontroller with OTP ROM

4.1.4

R3 (Status Register)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

 

6

 

5

 

 

4

 

3

 

2

 

1

 

0

 

GP

 

 

PS1

 

PS0

 

 

T

 

P

 

Z

 

DC

 

C

 

Bit 7 (GP) General read/write bit.

Bits 6 (PS1) ~ 5 (PS0) Page select bits. PS1~PS0 are used to pre-select a program memory page. When executing a "JMP", "CALL", or other instructions which causes the program counter to change (e.g. MOV R2, A), PS1~PS0 are loaded into the 11th and 12th bits of the program counter and select one of the available program memory pages. Note that RET (RETL, RETI) instruction does not change the PS0~PS1 bits. That is, the return will always be to the page from where the subroutine was called, regardless of the PS1~PS0 bits current setting.

PS1

 

PS0

 

Program memory page [Address]

 

 

 

 

 

 

 

0

 

0

 

Page 0 [000-3FF]

 

0

 

1

 

Page 1 [400-7FF]

 

1

 

0

 

Page 2 [800-BFF]

 

1

 

1

 

Page 3 [C00-FFF]

 

Bit 4 (T)

Time-out bit. Set to 1 with the "SLEP" and "WDTC" commands, or during

 

 

power up, and reset to 0 with the WDT time-out.

Bit 3

(P)

Power down bit. Set to 1 during power on or by a "WDTC" command and

 

 

reset to 0 by a "SLEP" command.

Bit 2

(Z)

Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero.

Bit 1

(DC) Auxiliary carry flag.

Bit 0

(C)

Carry flag

4.1.5 R4 (RAM Select Register)

Bits 7~6 determine which bank is activated among the 4 banks.

Bits 5~0 are used to select the registers (address: 00~3F) in the indirect addressing mode.

If no indirect addressing is used, the RSR can be used as an 8-bit general-purpose read/writer register.

See the configuration of the data memory in Fig. 4.

4.1.6 R5~R7 (Port 5 ~ Port7)

R5, R6 and R7 are I/O registers

4.1.7 R8~R1F and R20~R3E (General Purpose Register)

R8~R1F, and R20~R3E (including Banks 0~3) are general-purpose registers.

10

Product Specification (V1.1) 03.30.2005

(This specification is subject to change without further notice)

EM78P447N

8-Bit Microcontroller with OTP ROM

4.1.8 R3F (Interrupt Status Register)

Bit 7

 

Bit 6

 

Bit 5

 

Bit 4

 

Bit 3

 

Bit 2

 

Bit 1

 

Bit 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-

 

-

 

-

 

-

 

EXIF

 

-

 

-

 

TCIF

 

Bit 3 (EXIF) External interrupt flag. Set by falling edge on /INT pin, flag cleared by software

Bit 0 (TCIF) the TCC overflow interrupt flag. Set as TCC overflows; flag cleared by software.

Bits 1, 2, 4~7 are not used and read are as “0”.

"1" means interrupt request, "0" means non-interrupt.

R3F can be cleared by instruction, but cannot be set by instruction.

IOCF is the interrupt mask register.

Note that reading R3F will obtain the result of the R3F "logic AND" and IOCF.

4.2 Special Purpose Registers

4.2.1 A (Accumulator)

Internal data transfer, or instruction operand holding.

It cannot be addressed.

4.2.2 CONT (Control Register)

7

 

6

 

5

 

4

/PHEN

 

/INT

 

TS

 

TE

 

 

2

 

1

 

0

 

PAB

 

PSR2

 

PSR1

 

PSR0

 

Bit 7 (/PHEN) Control bit used to enable the pull-high of P60~P67, P74 and P75 pins

0:Enable internal pull-high.

1:Disable internal pull-high.

CONT register is both readable and writable.

Bit 6 (/INT) Interrupt enable flag

0: masked by DISI or hardware interrupt 1: enabled by ENI/RETI instructions

Bit 5 (TS) TCC signal source

0:internal instruction cycle clock

1:transition on TCC pin

Product Specification (V1.1) 03.30.2005

11

(This specification is subject to change without further notice)

EM78P447N

8-Bit Microcontroller with OTP ROM

Bit 4 (TE) TCC signal edge

0:increment if the transition from low to high takes place on TCC pin

1:increment if the transition from high to low takes place on TCC pin

Bit 3 (PAB) Prescaler assignment bit.

0:TCC

1:WDT

Bit 2 (PSR2) ~ Bit 0 (PSR0) TCC/WDT prescaler bits.

PSR2

 

PSR1

 

PSR0

 

TCC Rate

 

 

0

 

0

 

0

 

1:2

 

1:1

0

 

0

 

1

 

1:4

 

1:2

0

 

1

 

0

 

1:8

 

1:4

0

 

1

 

1

 

1:16

 

1:8

1

 

0

 

0

 

1:32

 

1:16

1

 

0

 

1

 

1:64

 

1:32

1

 

1

 

0

 

1:128

 

1:64

1

 

1

 

1

 

1:256

 

1:128

4.2.3 IOC5 ~ IOC7 (I/O Port Control Register)

"1" put the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output.

IOC5 and IOC7 registers are both readable and writable.

4.2.4 IOCB (Wake-up Control Register for Port6)

7

 

6

 

5

 

4

 

3

 

2

 

1

 

0

 

/WUE7

 

/WUE6

 

/WUE5

 

/WUE4

 

/WUE3

 

/WUE2

 

/WUE1

 

/WUE0

 

Bit 7 (/WUE7) Control bit is used to enable the wake-up function of P67 pin.

Bit 6 (/WUE6) Control bit is used to enable the wake-up function of P66 pin.

Bit 5 (/WUE5) Control bit is used to enable the wake-up function of P65 pin.

Bit 4 (/WUE4) Control bit is used to enable the wake-up function of P64 pin.

Bit 3 (/WUE3) Control bit is used to enable the wake-up function of P63 pin.

Bit 2 (/WUE2) Control bit is used to enable the wake-up function of P62 pin.

Bit 1 (/WUE1) Control bit is used to enable the wake-up function of P61 pin.

Bit 0 (/WUE0) Control bit is used to enable the wake-up function of P60 pin.

0:Enable internal wake-up.

1:Disable internal wake-up.

IOCB Register is both readable and writable.

12

Product Specification (V1.1) 03.30.2005

(This specification is subject to change without further notice)

EM78P447N

8-Bit Microcontroller with OTP ROM

4.2.5 IOCE (WDT Control Register)

 

7

 

6

 

5

 

4

 

-

 

ODE

 

WDTE

 

SLPC

 

 

 

 

 

 

 

 

 

 

2

 

1

 

0

 

ROC

 

-

 

-

 

/WUE

 

 

 

 

 

 

 

 

 

Bit 6 (ODE) Control bit is used to enable the open-drain of P76 and P77 pins

0:Disable open-drain output.

1:Enable open-drain output.

The ODE bit can be read and written.

Bit 5 (WDTE) Control bit used to enable Watchdog timer.

The WDTE bit is useful only when ENWDT, the CODE Option bit, is "0". It is only when the ENWDT bit is "0" that WDTE bit. is able to disabled/enabled the WDT.

0:Disable WDT.

1:Enable WDT.

The WDTE bit is not used if ENWDT, the CODE Option bit ENWDT, is "1". That is, if the ENWDT bit is "1", WDT is always disabled no matter what the WDTE bit status is.

The WDTE bit can be read and written.

Bit 4 (SLPC) This bit is set by hardware at the low level trigger of wake-up signal and is cleared by software. SLPC is used to control the oscillator operation. The oscillator is disabled (oscillator is stopped, and the controller enters into SLEEP2 mode) on the high-to-low transition and is enabled (controller is awakened from SLEEP2 mode) on low-to-high transition. In order to ensure the stable output of the oscillator, once the oscillator is enabled again, there is a delay for approximately 18ms1 (oscillator start-up timer, OST) before the next instruction of the program is executed. The OST is always activated by a wake-up event from sleep mode regardless of the Code Option bit ENWDT status is "0" or otherwise. After waking up, the WDT is enabled if the Code Option ENWDT is "1". The block diagram of SLEEP2 mode and wake-up invoked by an input trigger is depicted in Fig. 5. The SLPC bit can be read and written.

Bit 3 (ROC) ROC is used for the R-option. Setting ROC to "1" will enable the status of R-option pins (P70, P71) for the controller to read. Clearing ROC will disable the R-option function. Otherwise, the R-option function is introduced. Users must connect the P71 pin or/and P70 pin to VSS with a 430KΩ external resistor (Rex). If Rex is connected/disconnected with VDD, the status of P70 (P71) will be read as "0"/"1" (refer to Fig. 7(b)). The ROC bit can be read and written.

1 <Note>: Vdd = 5V, set up time period = 16.2ms ± 30%

 

Vdd = 3V, set up time period = 19.6ms ± 30%

 

Product Specification (V1.1) 03.30.2005

13

(This specification is subject to change without further notice)

EM78P447N

8-Bit Microcontroller with OTP ROM

Bit 0 (/WUE) Control bit is used to enable the wake-up function of P74 and P75.

0:Enable the wake-up function.

1:Disable the wake-up function.

The /WUE bit can be read and written.

Bits 1~2, and 7 Not used.

4.2.6 IOCF (Interrupt Mask Register)

7

 

6

 

5

 

4

 

3

 

2

 

1

 

0

 

-

 

-

 

-

 

-

 

EXIE

 

-

 

-

 

TCIE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit 3 (EXIE) EXIF interrupt enable bit.

0:disable EXIF interrupt

1:enable EXIF interrupt

Bit 0 (TCIE) TCIF interrupt enable bit.

0:disable TCIF interrupt

1:enable TCIF interrupt

Bits 1, 2 and 4~7 Not used.

Individual interrupt is enabled by setting its associated control bit in the IOCF to "1".

Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction (refer to Fig. 9).

IOCF Register is Both Readable and Writable.

 

 

 

/WUE0

Oscillator

 

 

Enable

Disable

 

/WUE1

 

 

Reset

 

Q

PR D

 

 

Q

CLK

 

VCC

CL

 

 

Clear

Set

8

/WUE7

from S/W

P60~P67

VCC

/WUE

/PHEN

2

P74~P75

Fig. 5 Sleep Mode and Wake-Up Circuits on I/O Ports Block Diagram

14

Product Specification (V1.1) 03.30.2005

(This specification is subject to change without further notice)

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