IBM EM78P447N User Manual

EM78P447N

8-Bit Microcontroller

with OTP ROM

Product

Specification

DOC. VERSION 1.1

ELAN MICROELECTRONICS CORP.

March 2005

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Contents

1 GENERAL DESCRIPTION.........................................................................................1

2 FEATURES.................................................................................................................1

3 PIN ASSIGNMENT ..................................................................................................... 3

4 FUNCTION DESCRIPTION........................................................................................6

4.1 Operational Registers......................................................................................... 7

4.1.1 R0 (Indirect Addressing Register) .......................................................................7

4.1.2 R1 (Time Clock /Counter)....................................................................................7

4.1.3 R2 (Program Counter) & Stack ...........................................................................7

4.1.4 R3 (Status Register) ..........................................................................................10

4.1.5 R4 (RAM Select Register).................................................................................10

4.1.6 R5~R7 (Port 5 ~ Port7) .....................................................................................10

4.1.7 R8~R1F and R20~R3E (General Purpose Register)........................................10

4.1.8 R3F (Interrupt Status Register) .........................................................................11

4.2 Special Purpose Registers ............................................................................... 11

4.2.1 A (Accumulator)................................................................................................. 11

4.2.2 CONT (Control Register)...................................................................................11

4.2.3 IOC5 ~ IOC7 (I/O Port Control Register) ..........................................................12

4.2.4 IOCB (Wake-up Control Register for Port6)......................................................12

4.2.5 IOCE (WDT Control Register)...........................................................................13

4.2.6 IOCF (Interrupt Mask Register).........................................................................14

4.3 TCC/WDT & Prescaler .....................................................................................15

4.4 I/O Ports ........................................................................................................... 16

4.5 RESET and Wake-up ....................................................................................... 17

4.5.1 RESET ..............................................................................................................17

4.5.2 The Status of RST, T, and P of STATUS Register .............................................21

4.6 Interrupt ............................................................................................................ 22

4.7 Oscillator .......................................................................................................... 23

4.7.1 Oscillator Modes................................................................................................23

4.7.2 Crystal Oscillator/Ceramic Resonators(XTAL)..................................................24

4.7.3 External RC Oscillator Mode .............................................................................25

4.8 CODE Option Register ..................................................................................... 26

4.8.1 Code Option Register (Word 0).........................................................................26

4.8.2 Customer ID Register (Word 1).........................................................................28

4.9 Power On Considerations ................................................................................ 28

4.10 External Power On Reset Circuit...................................................................... 28

4.11 Residue-Voltage Protection.............................................................................. 29

4.12 Instruction Set .................................................................................................. 30

4.13 Timing Diagram ................................................................................................ 33

Product Specification (V1.1) 03.30.2005 • iii

Contents

5 ABSOLUTE MAXIMUM RATINGS...........................................................................34

6 DC ELECTRICAL CHARACTERISTICS..................................................................34

6.1 DC Electrical Characteristic.............................................................................. 34

6.2 AC Electrical Characteristic .............................................................................. 35

6.3 Device Characteristic ....................................................................................... 36

APPENDIX

A Package Types.........................................................................................................50

B Package Information............................................................................................... 50

Specification Revision History

Doc. Version Revision Description Date

1.0 Initial version 10/29/2004

1.1 Add four kinds of package type 03/30/2005

iv • Product Specification (V1.1) 03.30.2005

1 GENERAL DESCRIPTION

EM78P447N is an 8-bit microprocessor with low-power and high-speed CMOS

technology and high noise immunity. It is equipped with 4K*13-bits Electrical One Time

Programmable Read Only Memory (OTP-ROM). It provides three PROTECTION bits

to prevent user’s code in the OTP memory from being intruded. Seven OPTION bits

are also available to meet user’s requirements.

With its OTP-ROM feature, the EM78P447N is able to offer a convenient way of

developing and verifying user’s programs. Moreover, user can take advantage of

ELAN Writer to easily program his development code.

2 FEATURES

 Operating voltage range: 2.5V~5.5V.

 Operating temperature range: -40°C~85°C.

EM78P447N

8-Bit Microcontroller with OTP ROM

 Operating frequency rang( base on 2 clocks)

• Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz at 2.5V.

• RC mode: DC~4MHz at 5V, DC~4MHz at 3V, DC~4MHz at 2.5V.

 Low power consumption:

• Less then 2.2 mA at 5V/4MHz

• Typically 35 µA, at 3V/32KHz

• Typically 2 µA, during sleep mode

 4K × 13 bits on chip ROM

 Three protection bits to prevent intrusion of OTP memory codes

 One configuration register to accommodate user’s requirements

 148× 8 bits on chip registers(SRAM, general purpose register)

 3 bi-directional I/O ports

 5 level stacks for subroutine nesting

 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and

overflow interrupt

 Two clocks per instruction cycle

 Power down (SLEEP) mode

 Two available interruptions

• TCC overflow interrupt

• External interrupt

Product Specification (V1.1) 03.30.2005

(This specification is subject to change without further notice)

• 1

EM78P447N

8-Bit Microcontroller with OTP ROM

 Programmable free running watchdog timer

 10 programmable pull-high pins

 2 programmable open-drain pins

 2 programmable R-option pins

 Package types:

• 20 pin DIP 300mil :EM78P447NDP

• 20 pin SOP 300mil :EM78P447NDM

• 24 pin Skinny DIP 300mil :EM78P447NCK

• 24 pin SOP 300mil :EM78P447NCM

• 28 pin DIP 600mil :EM78P447NAP

• 28 pin SOP 300mil :EM78P447NAM

• 28 pin SSOP 209mil :EM78P447NAS

• 32 pin DIP 600mil :EM78P447NBP

• 32 pin SOP 450mil :EM78P447NBWM

 99.9% single instruction cycle commands

 The transient point of system frequency between HXT and LXT is around 400KHz

2 •

Product Specification (V1.1) 03.30.2005

(This specification is subject to change without further notice)

3 PIN ASSIGNMENT

EM78P447N

8-Bit Microcontroller with OTP ROM

TCC VDD

NC Vss

/INT

P50 P51 P52 P53 P60 P61 P62 P63 P64

P55 P54

28 27 26 25

24 23 22 21 20

P54

TCC VDD

Vss

/INT

P50 P51 P52 P53 P60 P61 P62

/RESET OSCI OSCO

P77 P76 P75 P74 P73 P72 P71 P70 P67 P66 P65

1 2 3 4 5 6 7 8

9 10 11 12

Skinny DIP

EM78P447NCM

EM78P447NCK

SOP

Vss TCC VDD /INT

P50

P51

P52

P53

P60

P61

P62

P63

P64

Vss

24 23 22 21

20 19 18 17 16

1 2 3 4 5 6 7 8

9 10 11 12 13 14

/RESET OSCI OSCO

P77 P76 P75 P74 P67 P66 P65 P64 P63

EM78P447NAS

SSOP

28 27 26 25

24 23 22 21 20

P54 TCC VDD

Vss

/INT

P50 P51 P52 P53 P60

/RESET OSCI OSCO P77 P76 P75 P74 P73 P72 P71 P70 P67 P66 P65

1 2 3 4 5 6 7 8

EM78P447NDM

EM78P447NDP

DIP

SOP

TCC VDD

NC Vss

/INT

P50 P51 P52 P53 P60 P61 P62 P63 P64

1 2 3 4 5 6

EM78P447NAM

EM78P447NAP

7 8

9 10 11 12 13 14

DIP

SOP

1 2 3 4 5 6

EM78P447NBWM

EM78P447NBP

7 8

9 10 11 12 13 14 15 16

DIP

SOP

/RESET

OSCI OSCO

18 17

P77 P76

P75 P74

14 13

P73

P72

P71

P56

32 31

P57 /RESET

OSCI

OSCO

P77

P76

P75

P74

P73

23 22

P72

P71

P70

P67

P66

P65

Fig. 1 Pin Assignment

Product Specification (V1.1) 03.30.2005

• 3

(This specification is subject to change without further notice)

EM78P447N

8-Bit Microcontroller with OTP ROM

Table 1 EM78P447NAP and EM78P447NAM Pin Description

Symbol Pin No. Type Function

VDD 2 - ■ Power supply.

OSCI 27 I

OSCO 26 I/O

TCC 1 I

/RESET 28 I

P50~P53 6~9 I/O ■ P50~P53 are bi-directional I/O pins.

P60~P67 10~17 I/O

P70~P77 18~25 I/O

/INT 5 I ■ External interrupt pin triggered by falling edge.

VSS 4 - ■ Ground.

NC 3 - ■ No connection.

■ XTAL type: Crystal input terminal or external clock input pin.

■ RC type: RC oscillator input pin.

■ XTAL type: Output terminal for crystal oscillator or external clock input pin.

■ RC type: Instruction clock output.

■ External clock signal input.

■ The real time clock/counter (with Schmitt trigger input pin) must be tied to

VDD or VSS if not in use.

■ Input pin with Schmitt trigger. If this pin remains at logic low, the controller will also remain in reset condition.

■ P60~P67 are bi-directional I/O pins. These can be pulled-high internally by software control.

■ P70~P77 are bi-directional I/O pins.

■ P74~P75 can be pulled-high internally by software control.

■ P76~P77 can have open-drain output by software control.

■ P70 and P71 can also be defined as the R-option pins.

Table 2 EM78P447NAS Pin Description

Symbol Pin No. Type Function

VDD 3 - ■ Power supply.

OSCI 27 I

OSCO 26 I/O

TCC 2 I

/RESET 28 I

P50~P53 5~8 I/O ■ P50~P53 are bi-directional I/O pins.

P60~P67

P70~P77 18~25 I/O

/INT 4 I ■ External interrupt pin triggered by falling edge.

VSS 1,14 - ■ Ground.

9~13,

15~17

I/O

■ XTAL type: Crystal input terminal or external clock input pin.

■ RC type: RC oscillator input pin.

■ XTAL type: Output terminal for crystal oscillator or external clock input pin.

■ RC type: Instruction clock output.

■ External clock signal input.

■ The real time clock/counter (with Schmitt trigger input pin) must be tied to

VDD or VSS if not in use.

■ Input pin with Schmitt trigger. If this pin remains at logic low, the controller will also remain in reset condition.

■ P60~P67 are bi-directional I/O pins. These can be pulled -high internally by software control.

■ P70~P77 are bi-directional I/O pins.

■ P74~P75 can be pulled -high internally by software control.

■ P76~P77 can have open-drain output by software control.

■ P70 and P71 can also be defined as the R-option pins.

4 •

Product Specification (V1.1) 03.30.2005

(This specification is subject to change without further notice)

8-Bit Microcontroller with OTP ROM

Table 3 EM78P447NBP and EM78P447NBWM Pin Description

Symbol Pin No. Type Function

VDD 4 - ■ Power supply.

OSCI 29 I

OSCO 28 I/O

TCC 3 I

/RESET 30 I

P50~P57

P60~P67 12~19 I/O

P70~P77 20~27 I/O

/INT 7 I ■ External interrupt pin triggered by falling edge.

VSS 6 - ■ Ground.

NC 5 - ■ No connection.

8~11,2~1,

32~31

I/O ■ P50~P57 are bi-directional I/O pins.

■ XTAL type: Crystal input terminal or external clock input pin.

■ RC type: RC oscillator input pin.

■ XTAL type: Output terminal for crystal oscillator or external clock input pin.

■ RC type: Instruction clock output.

■ External clock signal input.

■ The real time clock/counter (with Schmitt trigger input pin), must be tied to

VDD or VSS if not in use.

■ Input pin with Schmitt trigger. If this pin remains at logic low, the controller will keep in reset condition.

■ P60~P67 are bi-directional I/O pins. These can be pulled -high internally by software control.

■ P70~P77 are bi-directional I/O pins.

■ P74~P75 can be pulled-high internally by software control.

■ P76~P77 can have open-drain output by software control.

■ P70 and P71 can also be defined as the R-option pins.

EM78P447N

Table 4 EM78P447NCK and EN78P447NCM Pin Description

Symbol Pin No. Type Function

VDD 3 - ■ Power supply.

OSCI 23 I

OSCO 22 I/O

TCC 2 I

/RESET 24 I

P50~P54 6~9,1 I/O ■ P50~P54 are bi-directional I/O pins.

P60~P67 10~17 I/O

P74~P77 18~21 I/O

/INT 5 I ■ External interrupt pin triggered by falling edge.

VSS 4 - ■ Ground.

NC 3 - ■ No connection.

■ XTAL type: Crystal input terminal or external clock input pin.

■ RC type: RC oscillator input pin.

■ XTAL type: Output terminal for crystal oscillator or external clock input pin.

■ RC type: Instruction clock output.

■ External clock signal input.

■ The real time clock/counter (with Schmitt trigger input pin) must be tied to

VDD or VSS if not in use.

■ Input pin with Schmitt trigger. If this pin remains at logic low, the controller will also remain in reset condition.

■ P60~P67 are bi-directional I/O pins. These can be pulled-high internally by software control.

■ P74~P77 are bi-directional I/O pins.

■ P74~P75 can be pulled-high internally by software control.

■ P76~P77 can have open-drain output by software control.

Product Specification (V1.1) 03.30.2005

(This specification is subject to change without further notice)

• 5

EM78P447N

8-Bit Microcontroller with OTP ROM

Table 5 EM78P447NDK and EM78P447NDM Pin Description

Symbol Pin No. Type Function

VDD 3 - ■ Power supply.

OSCI 19 I

OSCO 18 I/O

TCC 2 I

/RESET 20 I

P50~P54 6~9,1 I/O ■ P50~P54 are bi-directional I/O pins.

P60 10 I/O

P71~P77 11~17 I/O

/INT 5 I ■ External interrupt pin triggered by falling edge.

VSS 4 - ■ Ground.

NC 3 - ■ No connection.

■ XTAL type: Crystal input terminal or external clock input pin.

■ RC type: RC oscillator input pin.

■ XTAL type: Output terminal for crystal oscillator or external clock input pin.

■ RC type: Instruction clock output.

■ External clock signal input.

■ The real time clock/counter (with Schmitt trigger input pin) must be tied to

VDD or VSS if not in use.

■ Input pin with Schmitt trigger. If this pin remains at logic low, the controller will also remain in reset condition.

■ P60 are bi-directional I/O pins. This can be pulled-high internally by software control.

■ P74~P77 are bi-directional I/O pins.

■ P74~P75 can be pulled-high internally by software control.

■ P76~P77 can have open-drain output by software control.

■ P71 can also be defined as the R-option pins.

4 FUNCTION DESCRIPTION

OSCI

OSCO

O s c illato r/T imin g

Control

Sleep

Wake

/RESET

WDT

Time-out

R1(TCC)

IO C 5

Prescale

/INTTCC

W DT Timer

Inte rru pt Control

RAM

DATA & CONTROL BUS

IO C 6

Fig. 2 Functional Block Diagram

ROM

Instructio n

Decoder

P C

P 7 0

IO C 7

STACK 1

STACK 2

STACK 3

STACK 4

STACK 5

ALU

ACC

6 •

Product Specification (V1.1) 03.30.2005

(This specification is subject to change without further notice)

4.1 Operational Registers

4.1.1 R0 (Indirect Addressing Register)

R0 is not a physically implemented register. Its major function is to act as an indirect

addressing pointer. Any instruction using R0 as a pointer actually accesses data

pointed by the RAM Select Register (R4).

4.1.2 R1 (Time Clock /Counter)

 Increased by an external signal edge, which is defined by TE bit (CONT-4) through

the TCC pin, or by the instruction cycle clock.

 Writable and readable as any other registers.

 Defined by resetting PAB (CONT-3).

 The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.

 The contents of the prescaler counter will be cleared only when TCC register is

written a value.

EM78P447N

8-Bit Microcontroller with OTP ROM

4.1.3 R2 (Program Counter) & Stack

 Depending on the device type, R2 and hardware stack are 10-bit wide. The

structure is depicted in Fig.3.

 Generating 1024×13 bits on-chip OTP ROM addresses to the relative

programming instruction codes. One program page is 1024 words long.

 R2 is set as all "0"s when under RESET condition.

 "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,

"JMP" allows PC to go to any location within a page.

 "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into

the stack. Thus, the subroutine entry address can be located anywhere within a

page.

 "RET" ("RETL k", "RETI") instruction loads the program counter with the contents

of the top-level stack.

 "ADD R2,A" allows the contents of ‘A’ to be added to the current PC, and the ninth

and tenth bits of the PC are cleared.

 "MOV R2,A" allows to load an address from the "A" register to the lower 8 bits of

the PC, and the ninth and tenth bits of the PC are cleared.

 Any instruction that writes to R2 (e.g. "ADD R2,A", "MOV R2,A", "BC R2,6",⋅⋅⋅⋅⋅) will

cause the ninth and tenth bits (A8~A9) of the PC to be cleared. Thus, the

computed jump is limited to the first 256 locations of a page.

Product Specification (V1.1) 03.30.2005

(This specification is subject to change without further notice)

• 7

EM78P447N

8-Bit Microcontroller with OTP ROM

 All instruction are single instruction cycle (fclk/2 or fclk/4) except for the instruction

that would change the contents of R2. Such instruction will need one more

instruction cycle.

A9 A8A11 A10

CALL RET RETL

RETI

00 PAGE0 0000~03FF

01 PAGE1 0400~07FF

10 PAGE2 0800~0BFF

11 PAGE3 0C00~0FFF

A7 ~ A0

Hardware Vector Software Vector

On-chip Program

Stack Level 1 Stack Level 2 Stack Level 3 Stack Level 4 Stack Level 5

Fig. 3 Program Counter Organization

Memory

Reset Vector

000H 001H

002H

FFFH

User Memory

Space

8 •

Product Specification (V1.1) 03.30.2005

(This specification is subject to change without further notice)

8-Bit Microcontroller with OTP ROM

Aaddress R PAGE registers IOC PAGE registers

EM78P447N

08 General Register Reserve

09 General Register Reserve

0A General Register Reserve

0B General Register

0C General Register Reverse

(Indirect Addressing Register) Reserve

(Time Clock Counter)

(Program Counter) Reserve

(Status Register) Reserve

(RAM Select Register) Reserve

(Port5)

(Port6)

(Port7)

CONT

IOC5

IOC6

IOC7

IOCB

(Control Register)

(I/O Port Control Register)

(Wake-Up Control Register for Port6 )

0D General Register Reverse

0E General Register

0F General Register

︰

：

Bank0 Bank1 Bank2 Bank3

R3F

General Registers

(Interrupt Status Register)

IOCE

IOCF

(WDT,SLEEP2,Open Drain,R -Option Control Register)

(Interrupt Mask Register)

Fig. 4 Data Memory Configuration

Product Specification (V1.1) 03.30.2005

(This specification is subject to change without further notice)

• 9

EM78P447N

8-Bit Microcontroller with OTP ROM

4.1.4 R3 (Status Register)

7 6 5 4 3 2 1 0

GP PS1 PS0 T P Z DC C

Bit 7 (GP) General read/write bit. Bits 6 (PS1) ~ 5 (PS0) Page select bits. PS1~PS0 are used to pre-select a program

memory page. When executing a "JMP", "CALL", or other instructions

which causes the program counter to change (e.g. MOV R2, A), PS1~PS0

are loaded into the 11th and 12th bits of the program counter and select one

of the available program memory pages. Note that RET (RETL, RETI)

instruction does not change the PS0~PS1 bits. That is, the return will

always be to the page from where the subroutine was called, regardless of

the PS1~PS0 bits current setting.

PS1 PS0 Program memory page [Address]

0 0 Page 0 [000-3FF]

0 1 Page 1 [400-7FF]

1 0 Page 2 [800-BFF]

1 1 Page 3 [C00-FFF]

Bit 4 (T) Time-out bit. Set to 1 with the "SLEP" and "WDTC" commands, or during

power up, and reset to 0 with the WDT time-out.

Bit 3 (P) Power down bit. Set to 1 during power on or by a "WDTC" command and

reset to 0 by a "SLEP" command.

Bit 2 (Z) Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero. Bit 1 (DC) Auxiliary carry flag. Bit 0 (C) Carry flag

4.1.5 R4 (RAM Select Register)

Bits 7~6 determine which bank is activated among the 4 banks. Bits 5~0 are used to select the registers (address: 00~3F) in the indirect addressing

mode.

If no indirect addressing is used, the RSR can be used as an 8-bit general-purpose

read/writer register.

See the configuration of the data memory in Fig. 4.

4.1.6 R5~R7 (Port 5 ~ Port7)

R5, R6 and R7 are I/O registers

4.1.7 R8~R1F and R20~R3E (General Purpose Register)

R8~R1F, and R20~R3E (including Banks 0~3) are general-purpose registers.

10 •

Product Specification (V1.1) 03.30.2005

(This specification is subject to change without further notice)

4.1.8 R3F (Interrupt Status Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

- - - - EXIF - - TCIF

Bit 3 (EXIF) External interrupt flag. Set by falling edge on /INT pin, flag cleared by

software

Bit 0 (TCIF) the TCC overflow interrupt flag. Set as TCC overflows; flag cleared by

software.

Bits 1, 2, 4~7 are not used and read are as “0”.

"1" means interrupt request, "0" means non-interrupt.

R3F can be cleared by instruction, but cannot be set by instruction.

IOCF is the interrupt mask register.

Note that reading R3F will obtain the result of the R3F "logic AND" and IOCF.

4.2 Special Purpose Registers

EM78P447N

8-Bit Microcontroller with OTP ROM

4.2.1 A (Accumulator)

 Internal data transfer, or instruction operand holding.

 It cannot be addressed.

4.2.2 CONT (Control Register)

7 6 5 4 3 2 1 0

/PHEN /INT TS TE PAB PSR2 PSR1 PSR0

Bit 7 (/PHEN) Control bit used to enable the pull-high of P60~P67, P74 and P75 pins

0: Enable internal pull-high.

1: Disable internal pull-high.

CONT register is both readable and writable.

Bit 6 (/INT) Interrupt enable flag

0: masked by DISI or hardware interrupt

1: enabled by ENI/RETI instructions

Bit 5 (TS) TCC signal source

0: internal instruction cycle clock

1: transition on TCC pin

Product Specification (V1.1) 03.30.2005

(This specification is subject to change without further notice)

• 11

EM78P447N

8-Bit Microcontroller with OTP ROM

Bit 4 (TE) TCC signal edge

0: increment if the transition from low to high takes place on TCC pin

1: increment if the transition from high to low takes place on TCC pin

Bit 3 (PAB) Prescaler assignment bit.

0: TCC

1: WDT

Bit 2 (PSR2) ~ Bit 0 (PSR0) TCC/WDT prescaler bits.

PSR2 PSR1 PSR0 TCC Rate WDT Rate

0 0 0 1:2 1:1

0 0 1 1:4 1:2

0 1 0 1:8 1:4

0 1 1 1:16 1:8

1 0 0 1:32 1:16

1 0 1 1:64 1:32

1 1 0 1:128 1:64

1 1 1 1:256 1:128

4.2.3 IOC5 ~ IOC7 (I/O Port Control Register)

 "1" put the relative I/O pin into high impedance, while "0" defines the relative I/O pin

as output.

 IOC5 and IOC7 registers are both readable and writable.

4.2.4 IOCB (Wake-up Control Register for Port6)

7 6 5 4 3 2 1 0

/WUE7 /WUE6 /WUE5 /WUE4 /WUE3 /WUE2 /WUE1 /WUE0

Bit 7 (/WUE7) Control bit is used to enable the wake-up function of P67 pin. Bit 6 (/WUE6) Control bit is used to enable the wake-up function of P66 pin. Bit 5 (/WUE5) Control bit is used to enable the wake-up function of P65 pin. Bit 4 (/WUE4) Control bit is used to enable the wake-up function of P64 pin. Bit 3 (/WUE3) Control bit is used to enable the wake-up function of P63 pin. Bit 2 (/WUE2) Control bit is used to enable the wake-up function of P62 pin. Bit 1 (/WUE1) Control bit is used to enable the wake-up function of P61 pin. Bit 0 (/WUE0) Control bit is used to enable the wake-up function of P60 pin.

0: Enable internal wake-up.

1: Disable internal wake-up.

IOCB Register is both readable and writable.

12 •

Product Specification (V1.1) 03.30.2005

(This specification is subject to change without further notice)

EM78P447N

8-Bit Microcontroller with OTP ROM

4.2.5 IOCE (WDT Control Register)

7 6 5 4 3 2 1 0

- ODE WDTE SLPC ROC - - /WUE

Bit 6 (ODE) Control bit is used to enable the open-drain of P76 and P77 pins

0: Disable open-drain output.

1: Enable open-drain output.

The ODE bit can be read and written.

Bit 5 (WDTE) Control bit used to enable Watchdog timer.

The WDTE bit is useful only when ENWDT, the CODE Option bit, is "0". It is only when the ENWDT bit is "0" that WDTE bit. is able to disabled/enabled the WDT.

0: Disable WDT.

1: Enable WDT.

The WDTE bit is not used if ENWDT, the CODE Option bit ENWDT, is "1". That is, if the ENWDT bit is "1", WDT is always disabled no matter what the WDTE bit status is.

The WDTE bit can be read and written.

Bit 4 (SLPC) This bit is set by hardware at the low level trigger of wake-up signal and

is cleared by software. SLPC is used to control the oscillator operation. The oscillator is disabled (oscillator is stopped, and the controller enters into SLEEP2 mode) on the high-to-low transition and is enabled (controller is awakened from SLEEP2 mode) on low-to-high transition. In order to ensure the stable output of the oscillator, once the oscillator is enabled again, there is a delay for approximately 18ms

(oscillator start-up timer, OST) before the next instruction of the program is executed. The OST is always activated by a wake-up event from sleep mode regardless of the Code Option bit ENWDT status is "0" or otherwise. After waking up, the WDT is enabled if the Code Option ENWDT is "1". The block diagram of SLEEP2 mode and wake-up invoked by an input trigger is depicted in Fig. 5. The SLPC bit can be read and written.

Bit 3 (ROC) ROC is used for the R-option. Setting ROC to "1" will enable the status

of R-option pins (P70, P71) for the controller to read. Clearing ROC will disable the R-option function. Otherwise, the R-option function is introduced. Users must connect the P71 pin or/and P70 pin to VSS with a 430KΩ external resistor (Rex). If Rex is connected/disconnected with VDD, the status of P70 (P71) will be read as "0"/"1" (refer to Fig. 7(b)). The ROC bit can be read and written.

<Note>: Vdd = 5V, set up time period = 16.2ms ± 30%

Vdd = 3V, set up time period = 19.6ms ± 30%

Product Specification (V1.1) 03.30.2005

(This specification is subject to change without further notice)

• 13

EM78P447N

8-Bit Microcontroller with OTP ROM

Bit 0 (/WUE) Control bit is used to enable the wake-up function of P74 and P75.

0: Enable the wake-up function.

1: Disable the wake-up function.

The /WUE bit can be read and written.

Bits 1~2, and 7 Not used.

4.2.6 IOCF (Interrupt Mask Register)

7 6 5 4 3 2 1 0

- - - - EXIE - - TCIE

Bit 3 (EXIE) EXIF interrupt enable bit.

0: disable EXIF interrupt

1: enable EXIF interrupt

Bit 0 (TCIE) TCIF interrupt enable bit.

0: disable TCIF interrupt

1: enable TCIF interrupt

Bits 1, 2 and 4~7 Not used.

Individual interrupt is enabled by setting its associated control bit in the IOCF to "1".

Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction

(refer to Fig. 9).

 IOCF Register is Both Readable and Writable.

/WUE0

Oscillator

Enable Disable

CLK

Clear

from S/W

Reset

Set

/WUE1

VCC

/WUE7

P60~P67

VCC

/WUE

/PHEN

P74~P75

Fig. 5 Sleep Mode and Wake-Up Circuits on I/O Ports Block Diagram

14 •

Product Specification (V1.1) 03.30.2005

(This specification is subject to change without further notice)

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