IBM EM78P312N User Manual

EM78P312N

8-BIT

Microcontroller

Green Product

Specification

DOC. VERSION 1.0

ELAN MICROELECTRONICS CORP.

October 2006

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ELAN and ELAN logo

are trademarks of ELAN Microelectronics Corporation.

Printed in Taiwan

The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order.

In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELA N Microelectronics shall not be liable for direct, indirect, special inciden tal, or co nsequential damages arising from th e use of su ch inform ation or materia l .

The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement.

ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectro nics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MA Y BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE E XPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.

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Contents

1 General Description.....................................................................................................1

2 Features........................................................................................................................1

3 Pin Assignment............................................................................................................1

4 Pin Description.............................................................................................................2

5 Function Description...................................................................................................3

5.1 Functional Block Diagram .................................................................................... 3

5.2 Operating Registers .............................................................................................4

5.3 Special Purpose Registers .................................................................................19

5.4 CPU Operation Mode .........................................................................................23

5.5 AD Converter...................................................................................................... 24

5.6 Time Base Timer and Keytone Generator .........................................................26

5.7 UART (Universal Asynchronous Receiver/Transmitter)..................................... 28

5.7.1 UART Mode ...................................................................................................... 29

5.7.2 Transmitting ...................................................................................................... 29

5.7.3 Receiving.......................................................................................................... 30

5.7.4 Baud Rate Generator ....................................................................................... 30

5.8 SPI (Serial Peripheral Interface) ........................................................................31

5.8.1 Serial Clock....................................................................................................... 32

5.8.2 Shift Direction and Sample Phase.................................................................... 32

5.8.3 Transfer Mode .................................................................................................. 32

5.9 Timer/Counter 2.................................................................................................. 35

5.9.1 Timer Mode....................................................................................................... 36

5.9.2 Counter Mode ................................................................................................... 36

5.9.3 Window Mode ................................................................................................... 36

5.10 Timer/Counter 3.................................................................................................. 37

5.10.1 Timer Mode....................................................................................................... 38

5.10.2 Counter Mode ................................................................................................... 38

5.10.3 Capture Mode ................................................................................................... 38

5.11 Timer/Counter 4.................................................................................................. 39

5.11.1 Timer Mode....................................................................................................... 40

5.11.2 Counter Mode................................................................................................... 40

5.11.3 PDO Mode ........................................................................................................ 40

5.11.4 PWM Mode ....................................................................................................... 41

5.12 TCC/WDT & Prescaler ....................................................................................... 41

5.13 I/O Ports..............................................................................................................42

Product Specification (V1. 0) 10.03.2006 • iii

Contents

5.14 Reset and Wake-up............................................................................................42

5.14.1 Reset ................................................................................................................ 42

5.14.2 Wake-up from Sleep Mode ............................................................................... 43

5.14.3 Wake-up from Idle Mode .................................................................................. 43

5.14.4 The Status of RST, T, and P of the Status Register .......................................... 48

5.15 Interrupt .............................................................................................................. 49

5.16 Oscillator.............................................................................................................50

5.16.1 Oscillator Modes ............................................................................................... 50

5.16.2 Crystal Oscillator/Ceramic Resonators (Crystal).............................................. 50

5.16.3 External RC Oscillator Mode ............................................................................ 52

5.17 Code Option Register.........................................................................................53

5.17.1 Code Option Register (Word 0) ........................................................................ 53

5.17.2 Customer ID Register ....................................................................................... 54

5.18 Power-on Considerations ...................................................................................54

5.18.1 External Power-on Reset Circuit ...................................................................... 54

5.18.2 Residue-Voltage Protection .............................................................................. 55

5.19 Instruction Set..................................................................................................... 56

6 Absolute Maximum Ratings .....................................................................................58

6.1 Absolute Maximum Ratings ...............................................................................58

6.2 Recommended Operating Conditions................................................................58

7 Electrical Characteristics..........................................................................................59

7.1 DC Electrical Characteristics..............................................................................59

7.2 AC Electrical Characteristic................................................................................62

7.3 Timing Diagram ..................................................................................................63

APPENDIX

A Package Type: ............................................................................................................64

Specification Revision History

Doc. Version Revision Description Date

1.0 Initial Version 2006/10/03

iv • Product Specification (V1.0) 10.03.2006

EM78P312N

8-Bit Microcontroller

1 General Description

The EM78P312N is an 8-bit microprocessor with low-power, high-speed CMOS technology and high noise immunity. It has an on-chip 4K×13-bits Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides multi-protecti on bits to prevent intrusion of user’s OTP memory codes. Seven Option bits are also available to meet user’s requirements. With its OTP-ROM feature, the EM78P312N provides a convenient way of developing and verifying user’s programs. Moreover, this OTP device offers the advantages of easy and effective program updates, using development and programming tools. User can avail of the ELAN Writer to easily program his development code.

2 Features

 CPU configuration

z 4K×13 bits on-chip ROM z 144×8 bits on-chip registers (SRAM) z 8-level stacks for subroutine nesting z Less than 3.5mA at 5V/8MHz z Typically 0.8 μA, during sleep mode z Typically 1.1 μA, during idle mode

 I/O port configuration

z 4 bidirectional I/O ports : P6, P7, P8, P9 z 22 I/O pins z 10 Programmable pull-down I/O pins z 10 programmable pull-high I/O pins z External interrupt : P60, P61, P73, P80

 Operating voltage range:

z OTP version

Operating voltage range:2.5v~5.5v

 Operating temperature range:

z -40~85°C

 Operating frequency range:

Main clock

• Crystal mode:

DC ~ 20MHz/2clks @ 5V; DC ~100ns inst. cycle @ 5V DC ~ 8MHz/2clks @ 3V;DC ~ 250ns inst. cycle @ 3V

• ERC mode:

DC ~ 16MHz/2clks @ 5V;DC ~ 125ns inst. cycle @ 5V DC ~ 8MHz/2clks @ 3V;DC ~ 250ns inst. cycle @ 3V

 Peripheral configuration

z Serial peripheral interface (SPI) available z Universal asynchronous receiver transmitter interface

(UART)available

z 16 bits Counter/Timer

TC2: Timer/Counter/Window

z 8 bits Timer/Counter

TCC: 8-bit real time clock/counter with overflow

interrupt

TC3: Timer/Counter/Capture

TC4: Timer/Counter/ PWM (pulse width modulation) /

PDO (Programmable divider output)

z 8-bit channels Analog-to-Digital Converter with 10-bit

resolution

z Time Base Timer:(1Hz~16kHz at 8MHz) z Key tone output:(1kHz~8kHz at 8MHz) z 8-bit channels Analog-to-Digital Converter with 10-bit

resolution

 Fifteen available interrupts:

z WDT time-out interrupt z TCC overflow interrupt z Time base timer interrupt (the first falling edge of the

source clock)

z Serial UART transmit interrupt z Serial UART receive interrupt z Serial UART receive error interrupt z Four External interrupt z ADC completion interrupt z TC2 overflow interrupt z TC3 overflow interrupt z TC4 overflow interrupt z Serial SPI interrupt

 Special features

z Programmable free running watchdog timer z Two clocks per instruction cycle z Power-on Reset z High noise immunity z Power saving Sleep mode z Selectable Oscillation mode

 Package type:

z 28-pin DIP 600 mil: EM78P312NP z 28-pin Skinny DIP 300 mil: EM78P312NAK z 28-pin Skinny DIP 400 mil: EM78P312N z 28-pin SOP 300 mil: EM78P312NM z 28-pin SSOP 209 mil: EM78P312NS

3 Pin Assignment

(ACLK) OSCO

OSCI

TEST (AD0) P90 (AD1) P91 (AD2) P92 (AD3) P93 (AD4) P94 (AD5) P95 (AD6) P96

(AD7/VREF) P97 (TC3, INT3) P80

(TC4, /PW M, /PDO) P81

Product Specification ( V 1 . 0) 10 . 0 3 . 2 006

(This specification is subject to change without further notice)

VSS

Fig. 3- Pin Assignment

• 1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

EM78P312N

VDD

/RESET (VPP)

P67 (DINCK)

P66 (DATAIN)

P65 (PGMB)

P64 (/SS)(OEB)

P63 (/TONE)

P62 (TC2)

P61 (INT1)

P60 (/INT0)

P73 (/SLEEP, /INT5)

P72 (TX, SO)

P71(RX,SI) P70 (/SCK)

EM78P312N

8-Bit Microcontroller

4 Pin Description

Table 1

Symbol Pin No. Type Function

VDD

OSCI

OSCO

/RESET

P60~P67

P70~P73

P80~P81

P90~P97

VSS

OTP Programming Pins

VPP

ACLK

DATAIN

DINCK

PGMB

OEB

28 − Power supply

2 I

1 I/O

27 I

19~26 I/O

15~18 I/O

12~13 I/O

4~11 I/O

14 − Ground

3 − No connection

27 I Programming voltage input

1 I CLK for OTP memory address increment

25 I/O ROM code series input and series output pin

26 I ROM code input clock

24 I Program write enable pin. Active low.

23 I Output enable pin. Active low.

Crystal type: Crystal input terminal RC type: RC oscillator input pin

Crystal type: Output terminal for crystal oscillator RC type: Instruction clock output External clock signal input

Input pin with Schmitt Trigger. If this pin remains at logic low, the controller will also remain in reset condition.

8-bit bidiectional input/output pins.

P60 can be used as external Interrupt 0 (/INT0). P61 can be used as external Interrupt 1 (INT1). P62 can be used as 16-bit Timer/Counter 2 (TC2). P63 can be used as divider output (/TONE).

P64 slave mode enable (/SS). P60 ~ P63 can be used as pull-high or pull-low pins.

8-bit bidiectional input/output pins. P70 can be used as SPI serial clock input/output (/SCK) P71 can be used as SPI serial data input (SI) or UART data receive

input (RX)

P72 can be used as SPI serial data output (SO) or UART data

transmit output (TX)

P73 can be used as Sleep mode release input (/SLEEP) or external

interrupt Input 5 (/INT5)

P70 ~ P73 can be used as pull-high or pull-low pins

2-bit bidiectional input/output pins. P80 can be used as 8-bit Timer/Counter 3 (TC3) or external

Interrupt Input 3 (INT3).

P81 can be used as 8-bit Timer/Counter 4 (TC4) or programmable

divider output (PDO).

P80 ~ P81 can be used as pull-high or pull-low pins.

8-bit bidiectional input/output pins. P90~P97 can be used as 8 channel 10-bit resolution A/D converter. P97 can be used as AD reference power supply input (VREF).

2 •

Product Specification (V1.0) 10.03.2006

(This specification is subject to change without further notice)

5 Function Description

5.1 Functional Block Diagram

EM78P312N

8-Bit Microcontroller

P90 P91

P92 P93 P94 P95 P96 P97

P80

P81

P70 P71

P72 P73 P74 P75 P76

P77

P60 P61 P62 P63 P64 P65 P66

P67

ACC

ROM

Instruction

Decoder

ALU

Status Reg.

8-level stack

(13 bit)

Interrupt

Control

Interrupt

Circuit

Ext.

OSC.

Oscillation

Generation

Reset

Mux

RAM

Ext.

Start-up

Timer

WDT

TC2

TC3

TC4

UART

SPI

TCC

TBKTC

ADC

TC2

TC3

TC4

TX RX

Sin Sout SCK

TCC

Keytone

Ext INT0

Ext INT3Ext INT1 Ext INT5

Fig. 5-1 Functional Block Diagram

Product Specification ( V 1 . 0) 10 . 0 3 . 2 006

(This specification is subject to change without further notice)

• 3

Ain 0~7

EM78P312N

8-Bit Microcontroller

5.2 Operating Registers

Address

00 01 02 03 04 05 06 07 08 09

0A 0B 0C 0D 0E 0F

Bank 0

R0/ IAR

R1/ TCC

R2/ PC

R3/ SR

R4/ RSR

SCR

Port 6

Port 7

Port 8

Port 9

Reserved

TC4CR

TC4D

ISFR0

ISFR1

ISFR2

16 Byte

Common Register

Bank 1

R3 (7, 6) = (0, 1)

TC3CR

TC3DA

TC3DB

TC2CR/ ADDL

TC2DH

TC2DL

ADCR

ADIC

ADDH

TBKTC

Reserved

Bank 2

R3 (7, 6) = (1, 0) R3 (7, ) = (1, 1)

URC1

URC2

URS

URRD

URTD

Reserved

Bank 3

SPIC1

SPIC2

SPID

Reserved

PHC1

PLC1

PHC2

PLC2

Reserved

Control

Reserved

IOC6

IOC7

IOC8

IOC9

Reserved

INTCR

ADOSCR

Reserved

IMR1

IMR2

Bank 0

R4 (7, 6) = (0, 0)

32 Byte

Common Register

Bank 1

R4 (7, 6) = (0, 1)

32 Byte

Common Register

Fig. 5-2 Operating Registers

4 •

Product Specification (V1.0) 10.03.2006

(This specification is subject to change without further notice)

EM78P312N

8-Bit Microcontroller

R0 (Indirect Addressing Register)

R0 is not a physically implemented register. Its major function is to act as an indirect

addressing pointer. Any instruction using R0 as a pointer actually accesses data

pointed by the RAM Select Register (R4).

R1 (Time Clock /Counter)

This register is writable and readable just like the other registers. The contents of the

prescaler counter are cleared only when a value is written into the TCC register.

R2 (Program Counter) & Stack

z Depending on the device type, R2 and hardware stack are 10-bit wide. The

structure is depicted in Fig.5-3.

z Generates 8192 ×13 bits on-chip OTP ROM addresses to the relative

programming instruction codes. One program page is 1024 words long.

z R2 is set as all "0"s when under RESET condition

z "JMP" instruction allows direct loading of the lower 10 program counter bits.

Thus, "JMP" allows the PC to go to any location within a page.

z "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed

onto the stack. Thus, the subroutine entry address can be located

anywhere within a page.

z "RET" ("RETL k", "RETI") instruction loads the program counter with the

contents of the top-level stack.

z All instructions are single instruction cycle (fclk/2 or fclk/4) except for the

instruction that would change the contents of R2. Such instruction will need

one more instruction cycle.

z For an interrupt trigger, the program ROM will jump to individual interrupt

vector at Page 0. The CPU will store ACC, R3 status and R5 PAGE

automatically, it will restore after instruction RETI.

Product Specification ( V 1 . 0) 10 . 0 3 . 2 006

(This specification is subject to change without further notice)

• 5

EM78P312N

8-Bit Microcontroller

A12

000 : PAGE0 0000~03F F 001 : PAGE1 0400~07F F 010 : PAGE2 0800~0BFF 011 : PAGE3 0C00~0FFF 100 : PAGE4 1000~13F F 101 : PAGE5 1400~17F F 110 : PAGE6 1800~1BFF 111 : PAGE7 1C00~1FFF

A11 A10 A9 A8 A7 ~ A0

CALL RET RETL RETI

Stack Level 1 Stack Level 2 Stack Level 3 Stack Level 4 Stack Level 5 Stack Level 6 Stack Level 7 Stack Level 8

Store ACC, R3, R5

Reset Vector WDT Timer Overflow External INT0 Pin Interrupt Occurs TCC Overflow External INT1 pin Interrupt Occurs Time Base Timer Interrupt UART Transmit Data Buffer Empty UART Receive Data Buffer Full UART Receive Error TC3 Interrupt SPI Interrupt TC4 Interrupt External INT3 Pin Interrupt Occurs AD Conversion Complete TC2 Interrupt External INT5 Pin Interrupt Occurs

On-chip Program Memory

0000h

0003h

0006h

0009h

000Fh

0012h

0015h

0018h

001Bh

0021h

0024h

0027h

002Ah

0030h

0033h

0036h

User Memory Space

1FFFh

Fig. 5-3 Program Counter Organization

R3 (Status Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RBS1 RBS0 0 T P Z DC C

Bit 7 ~ Bit 6 (RBS1 ~ RBS0): R-Register page select

RBS1 RBS0 Register Bank (Address 05H ~ 0FH)

0 0 Bank 0

0 1 Bank 1

1 0 Bank 2

1 1 Bank 3

Bit 5: Not used Bit 4 (T): Time-out bit. Set to “1” with the "SLEP" and "WDTC" commands, or during

power up, and reset to “0” with the WDT time-out.

6 •

Product Specification (V1.0) 10.03.2006

(This specification is subject to change without further notice)

EM78P312N

8-Bit Microcontroller

Bit 3 (P): Power down bit. Set to “1” during power on or by a "WDTC" command and

reset to “0” by a "SLEP" command.

Bit 2 (Z): Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero. Bit 1 (DC) : Auxiliary carry flag Bit 0 (C) : Carry flag

R4 (RAM Select Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

GRBS1 RBS0 RSR5 RSR4 RSR3 RSR2 RSR1 RSR0

Bit 7: 6 ( GRBS1: GRBS0 ): determine which general purpose banks are activated

among the two banks. Use BANK instruction (e.g. BABK 1) to change bank.

GRBS1 GRBS0 General Purpose Register Bank (Address 20H ~ 3FH)

0 0 Bank 0 0 1 Bank 1

Bit 5: 0 ( RSR5 : RSR0 ): used to select the registers (Address: 00h~3Fh) in indirect

addressing mode. If no indirect addressing is used, the RSR can be used as

an 8-bit general-purpose read/write register. See the data memory

configuration in Fig. 5-2.

R5 (System Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 0 PS1 PS0 0 1 SIS REM

Bits 5~4 (PS1~PS0): ROM Page select bits. User can use PAGE instruction (e.g.

PAGE 1) or set PS1~PS0 bits to change the ROM page. When executing a

"JMP", "CALL", or other instructions which cause the program counter to

change (e.g. MOV R2, A), PS1~PS0 are loaded into the 12th to11th bits of the

program counter and select one of the available program memory pages. Note

that RET (RETL, RETI) instruction does not change the PS1~PS0 bits. That

is, return will always be to the page from where the subroutine was called,

regardless of the PS1~PS0 bits current setting.

PS1 PS0 Program Memory Page [Address]

0 0 Page 0 [0000~03FF]

0 1 Page 1 [0400~07FF]

1 0 Page 2 [0800~0BFF]

1 1 Page 3 [0C00~0FFF]

Bit 1 ( SIS ) : Sleep and Idle mode select

SIS = “0” : Idle mode SIS = “1” : Sleep mode

Bit 0 ( REM ) : Release method for sleep mode

REM = “0” : /SLEEP pin input rising edge released REM = “1” : /SLEEP pin input “H” level released

Product Specification ( V 1 . 0) 10 . 0 3 . 2 006

(This specification is subject to change without further notice)

• 7

EM78P312N

8-Bit Microcontroller

R6 (Port 6 I/O Data Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

P67 P66 P65 P64 P63 P62 P61 P60

Bit 7 ~ Bit 0 ( P67 ~ P60 ) : 8-bit Port 6 I/O data register

User can use IOC6 register to define each bit whether input or output.

R7 (Port 7 I/O Data Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit 3 ~ Bit 0 ( P73 ~ P70 ) : Port 73 ~ Port 70 I/O data register

User can use IOC7 register to define each bit whether input or output.

R8 (Port8 I/O Data Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 0 0 0 P73 P72 P71 P70

0 0 0 0 0 0 P81 P80

Bit 1 ~ Bit 0 ( P81 ~ P80 ) : Port 81 ~ Port 80 I/O data register

User can use IOC8 register to define each bit whether input or output.

R9 (Port9 I/O Data Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

P97 P96 P95 P94 P93 P92 P91 P90

Bit 7 ~ Bit 0 ( P97 ~ P90 ) : 8-bit Port 97 ~ Port 90 I/O data register

User can use IOC9 register to define each bit whether input or output.

RB (Timer/Counter 4 Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC4FF1 TC4FF0 TC4S TC4CK2 TC4CK1 TC4CK0 TC4M1 TC4M0

Bit 7 ~ Bit 6 ( TC4FF1 ~ TC4FF0 ) : Timer/Counter 4 flip-flop control

TC4FF1 TC4FF0 Operating Mode

0 0 Clear

0 1 Toggle

1 0 Set

1 1 Reserved

Bit 5 ( TC4S ) : Timer/Counter 4 start control

TC4S = “0” : Stop and clear counter TC4S = “1” : Start

8 •

Product Specification (V1.0) 10.03.2006

(This specification is subject to change without further notice)

EM78P312N

8-Bit Microcontroller

Bit 4 ~ Bit 2 ( TC4CK2 ~ TC4CK 0 ) : Timer/Counter 4 Clock Source Select

TC4CK2 TC4CK1 TC4CK0

0 0 0 Fc/211 256μS 65mS

0 0 1 Fc/27 16μS 4mS

0 1 0 Fc/25 4μS 1mS

0 1 1 Fc/23 1μS 255μS

1 0 0 Fc/22 500nS 127.5μS

1 0 1 Fc/21 250nS 63.8μS

1 1 0 Fc 125nS 31.9μS

1 1 1 External clock (TC4 pin) − −

Clock Source

( Normal, Idle )

Bit 1 ~ Bit 0 ( TC4M1 ~ TC4M0 ) : Timer/Counter 4 Operating Mode Select

TC4M1 TC4M0 Operating Mode

0 0 Timer/Counter

0 1 Reserved

1 0 Programmable Divider output

1 1 Pulse Width Modulation output

Resolution

( Fosc=8M )

Max. Tim e

( Fosc=8M )

RC (Timer 4 Data Buffer)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC4D7 TC4D6 TC4D5 TC4D4 TC4D3 TC4D2 TC4D1 TC4D0

Bit 7 ~ Bit 0 ( TC4D7 ~ TC4D0 ) : Data buffer of 8-bit Timer/Counter 4.

RD (Interrupt Status Flag Register 0 and INT3 Edge Detect Flag)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 0 INT3F INT3R 0 0 WDTIF EXIF0

Bit 5 ( INT3F ) : External Interrupt 3 falling edge detect flag.

INT3F = “0” : Falling edge is not detected INT3F = “1” : Falling edge is detected

Bit 4 ( INT3R ) : External Interrupt 3 rising edge detect flag.

INT3R = “0” : Rising edge is not detected

INT3R = “1” : Rising edge is detected Bit 1 ( WDTIF ) : WDT time-out flag, flag cleared by software. Bit 0 ( EXIF0 ) : External interrupt flag (INT0). Flag cleared by software. If the INT0EN

is reset to “0”, the flag is cleared.

Product Specification ( V 1 . 0) 10 . 0 3 . 2 006

(This specification is subject to change without further notice)

• 9

EM78P312N

8-Bit Microcontroller

RE (Interrupt Status Flag Register 1)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

EXIF5 TCIF2 ADIF 0 EXIF3 TCIF4 SPIF TCIF3

Bit 7 ( EXIF5 ) : External Interrupt Flag (/INT5), flag cleared by software. Bit 6 ( TCIF2 ) : 16-bit Timer/Counter 2 Interrupt Flag, flag cleared by software. Bit 5 ( ADIF ) : AD conversion complete flag, flag cleared by software. Bit 3 ( EXIF3 ) : External Interrupt Flag (/INT3), flag cleared by software. Bit 2 ( TCIF4 ) : 8-bit Timer/Counter 4 Interrupt Flag, flag cleared by software. Bit 1 ( SPIF ) : SPI Mode Interrupt Flag, flag cleared by software. Bit 0 ( TCIF3 ) : 8-bit Timer/Counter 3 interrupt flag, flag cleared by software.

0 : means no interrupt request 1 : means with interrupt request

z ISFR1 can be cleared by instruction, but cannot be set by instruction

z IMR1 is the interrupt mask register

z Note that reading ISFR1 will obtain the result of the ISFR1 "logic AND" and

IMR1.

RF(Interrupt Status Flag Register 2)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 UERRIF RBFF TBEF TBIF EXIF1 0 TCIF0

Bit 6 (U ERRI F ) : UART Receiving Error Interrupt, cleared by software or UART

disabled.

Bit 5 (RBFF) : UART Receive Mode Data Buffer Full Interrupt Flag. Flag cleared by

software.

Bit 4 (TB E F ) : UART Transmit Mode Data Buffer Empty Interrupt Flag. Flag cleared by

software.

Bit 3 (TBIF) : Time Base Timer Interrupt Flag. Flag cleared by software. Bit 2 (EXIF1) : External Interrupt Flag (INT1). Flag cleared by software. Bit 0 (TCIF0) : TCC Overflow Interrupt Flag. Set as TCC overflows; flag cleared by

software.

0 : means no interrupt request 1 : means with interrupt request

10 •

Product Specification (V1.0) 10.03.2006

(This specification is subject to change without further notice)

EM78P312N

8-Bit Microcontroller

z ISFR2 can be cleared by instruction, but cannot be set by instruction

z IMR2 is the interrupt mask register

z Note that reading ISFR2 will obtain the result of the ISFR2 "logic AND" and

IMR2

Bank 1 R5 TC3CR (Timer/Counter 3 Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC3CAP TC3S TC3CK1 TC3CK0 TC3M 0 0 0

Bit 7 ( TC3CAP ) : Software capture control

TC3CAP = “0” : -

TC3CAP = “1” : Software capture Bit 6 ( TC3S ) : Timer/Counter 3 start control

TC3S = “0” : Stop and counter clear

TC3S = “1” : Start

Bit 5 ~ Bit 4 ( TC3CK1 ~ TC3CK0 ) : Timer/Counter 3 Clock Source Select

TC3CK1 TC3CK0

0 0 Fc/212 512μS 131.1mS

0 1 Fc/210 128μS 32.6mS

1 0 Fc/27 16μS 4.1mS

1 1 External clock (TC3 pin) - -

Clock source

( Normal, Idle )

Resolution

( Fc=8M )

Max. time

( Fc=8M )

Bit 3 ( TC3M ) : Timer/Counter 3 mode select

TC3M = “0” : Timer/Counter3 mode

TC3M = “1” : Capture mode

Bank 1 R6 TC3DA (Timer 3 Data Buffer A)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC3DA7 TC3DA6 TC3DA5 TC3DA4 TC3DA3 TC3DA2 TC3DA1 TC3DA0

Bit 7 ~ Bit 0 ( TC3DA7 ~ TC3DA0 ) : Data buffer of 8-bit Timer/Counter 3.

Reset does not affect this register.

Bank 1 R7 TC3DB (Timer 3 Data Buffer B)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC3DB7 TC3DB6 TC3DB5 TC3DB4 TC3DB3 TC3DB2 TC3DB1 TC3DB0

Bit 7 ~ Bit 0 ( TC3DB7 ~ TC3DB0 ) : Data buffer of 8-bit Timer/Counter 3

Reset does not affect this register.

Product Specification ( V 1 . 0) 10 . 0 3 . 2 006

(This specification is subject to change without further notice)

• 11

EM78P312N

8-Bit Microcontroller

Bank 1 R8 TC2CR/ ADDL (Timer/Counter 2 Control Register, AD Low 2 bits

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ADD1 ADD0 0 TC2M TC2S TC2CK2 TC2CK1 TC2CK0

Bit 7 ~ Bit 6 ( ADD1 ~ ADD0 ) : AD low 2-bit data buffer Bit 4 ( TC2M ) : Timer/Counter 2 mode select

Bit 3 ( TC2S ) : Timer/Counter 2 start control

Bit 2 ~ Bit 0 ( TC2CK2 ~ TC2CK0 ) : Timer/Counter 2 Clock Source Select

TC2CK2 TC2CK1 TC2CK0

Data Buffer)

TC2M = “0” : Timer/counter mode

TC2M = “1” : Window mode

TC2S = “0” : Stop and counter clear

TC2S = “1” : Start

Clock Source

( Normal, Idle )

0 0 0 Fc/223 1.05s 19.1h

0 0 1 Fc/213 1.02ms 1.1min

0 1 0 Fc/28 32μs 2.1s

0 1 1 Fc/23 1μs 65.5ms

1 0 0 Fc 125ns 7.9ms

1 0 1 - - -

1 1 0 - - -

1 1 1 External clock (TC2 pin)

Resolution

( Fc=8M )

Max. Time

( Fc=8M )

Bank 1 R9 TC2DH (Timer 2 Data Buffer High Byte)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC2D15 TC2D14 TC2D13 TC2D12 TC2D11 TC2D10 TC2D9 TC2D8

Bit 7 ~ Bit 0 ( TC2D15 ~ TC2D8 ) : 16-bit Timer/Counter 2 data buffer high byte.

Bank 1 RA TC2DL (Timer 2 Data Buffer Low Byte)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC2D7 TC2D6 TC2D5 TC2D4 TC2D3 TC2D2 TC2D1 TC2D0

Bit 7 ~ Bit 0 ( TC2D7 ~ TC2D0 ) : 16-bit Timer/Counter 2 data buffer low byte.

Bank 1 RB ADCR (AD Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ADREF ADRUN ADCK1 ADCK0 ADP ADIS2 ADIS1 ADIS0

Bit 7 ( ADREF ) : AD reference voltage input select.

ADREF = “0” : Internal VDD, P97 is used as IO.

ADREF = “1” : External reference pin, P97 is used as reference input pin.

12 •

Product Specification (V1.0) 10.03.2006

(This specification is subject to change without further notice)

8-Bit Microcontroller

Bit 6 ( ADRUN ) : AD Conversion start

ADRUN = “0” : Reset on completion of the conversion by hardware, this bit

cannot be reset by software.

ADRUN = “1” : Conversion starts Bit 5~ Bit 4 ( ADCK1 ~ ADCK0 ) : AD Conversion Time Select

EM78P312N

ADCK1 ADCK0

0 0 Fc/4 1MHz

0 1 Fc/16 4MHz

1 0 Fc/32 8MHz

1 1 Reserved -

Clock Source

( Normal, Idle )

Bit 3 ( ADP ) : AD power control

ADP = “0” : Power on

ADP = “1” : Power down Bit 2 ~ Bit 0 ( ADIS2 ~ ADIS0 ) : Analog Input Pin Select

ADIS2 ADIS1 ADIS0 Analog Input Pin

0 0 0 AD0

0 0 1 AD1

0 1 0 AD2

0 1 1 AD3

1 0 0 AD4

1 0 1 AD5

1 1 0 AD6

1 1 1 AD7

Max. Op erating Frequency (Fc)

Bank 1 RC ADIC (AD Input Pin Control)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0

Bit 7 ~ Bit 0 ( ADE7 ~ ADE0 ) : AD input pin enable control.

ADEx = “0” : Port 9.x functions as I/O pin

ADEx = “1” : Port 9.x functions as analog input pin

Bank 1 RD ADDH (AD High 8-bit Data Buf fer)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2

Bit 7 ~ Bit 0 ( ADD9 ~ ADD2 ) : AD high 8-bit data buffer

Product Specification ( V 1 . 0) 10 . 0 3 . 2 006

(This specification is subject to change without further notice)

• 13

EM78P312N

8-Bit Microcontroller

Bank 1 RE TBKTC (TBT/Keytone Control)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TEN TCK1 TCK0 0 TBTEN TBTCK2 TBTCK1 TBTCK0

Bit 7 ( TEN ) : Keytone enable control

Bit 6 ~ Bit 5 ( TCK1 ~ TCK0 ) : Keytone Output Clock Source Select

Bit 3 ( TBTEN ) : Time Base Timer Enable Control

TEN = “0” : Disable

TEN = “1” : Enable

TCK1 TCK0

0 0 Fc/213 0.976kHz

0 1 Fc/212 1.953kHz

1 0 Fc/211 3.906kHz

1 1 Fc/210 7.812kHz

Clock Source

( Normal, Idle )

Keytone Output Frequency

( Fc = 8MHz )

TBTEN = “0” : Disable

TBTEN = “1” : Enable Bit 2 ~ Bit 0 ( TBTCK2 ~ TBTCK0 ) : Time Base Timer Clock Source Select

TBTCK2 TBTCK1 TBTCK0

0 0 0 Fc/223 0.95Hz

0 0 1 Fc/221 3.81Hz

0 1 0 Fc/216 122.07Hz

0 1 1 Fc/214 488.28Hz

1 0 0 Fc/213 976.56Hz

1 0 1 Fc/212 1953.12Hz

1 1 0 Fc/211 3906.25Hz

1 1 1 Fc/29 15625Hz

Clock Source

( Normal, Idle )

Interrupt Frequency

( Fc = 8MHz )

Bank 2 R5 URC1 (UART Control Register 1)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

URTD8 UMODE1 UMODE0 BRATE2 BRATE1 BRATE0 UTBE TXE

Bit 7 ( URTD8 ) : Transmission data Bit 8 Bit 6 ~ Bit 5 ( UMODE1 ~ UMODE0 ) : UART Transmission Mode Select Bit

UMODE1 UMODE0 UART Mode

0 0 Mode 1: 7-bits

0 1 Mode 2: 8-bits

1 0 Mode 3: 9-bits

1 1 Reserved

14 •

Product Specification (V1.0) 10.03.2006

(This specification is subject to change without further notice)

EM78P312N

8-Bit Microcontroller

Bit 4 ~ Bit 2 ( BRATE2 ~ BRATE1 ) : Transmit Baud Rate Select

BRATE2 BRATE1 BRATE0 Baud Rate e.g. Fc=8MHz

0 0 0 Fc/13 38400

0 0 1 Fc/26 19200

0 1 0 Fc/52 9600

0 1 1 Fc/104 4800

1 0 0 Fc/208 2400

1 0 1 Fc/416 1200

1 1 0 TC4 -

1 1 1 reserved -

Bit 1 ( UTBE ): UART transfer buffer empty flag. Set to 1 when transfer buffer is empty.

Reset to 0 automatically when writing into the URTD register. UTBE bit

will be cleared by hardware when enabling the transmission. UTBE bit

is read-only. Therefore, writing to the URTD register is necessary

when starting transmission shifting.

Bit 0 ( TXE ): Enable transmission

TXE = “0” : Disable

TXE = “1” : Enable

Bank 2 R6 URC2 (UART Control Register 2)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 0 SBIM1 SBIM0 UINVEN 0 0 0

Bit 5 ~ Bit 4 ( SBIM1 ~ SBIM0 ) : Serial bus interface operation mode select.

TC2CK1 TC2CK0 Operation Mode

0 0 I/O mode

0 1 SPI mode

1 0 UART mode

1 1 Reserved

Bit 3 ( UINVEN ) : Enable UART TXD and RXD port inverse output.

UINVEN = “0” : Disable TXD and RXD port inverse output.

UINVEN = “1” : Enable TXD and RXD port inverse output.

Bank 2 R7 URS (UART Status Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

URRD8 EVEN PRE PRERR OVERR FMERR URBF RXE

Bit 7 ( URRD8 ) : Receiving data Bit 8

Product Specification ( V 1 . 0) 10 . 0 3 . 2 006

(This specification is subject to change without further notice)

• 15

EM78P312N

8-Bit Microcontroller

Bit 6 ( EVEN ) : Select parity check

Bit 5 ( PRE ) : Enable parity addition

Bit 4 ( PRERR ) : Parity error flag.

Bit 3 ( OVERR ) : Overrun error flag.

Bit 2 ( FMERR ) : Framing error flag.

Bit 1 ( URBF ) : UART read buffer full flag.

EVEN = “0” : Odd parity EVEN = “1” : Even parity

PRE = “0” : Disable PRE = “1” : Enable

Set to 1 when parity error occurred, and cleared to 0 by software.

Set to 1 when overrun error occurred, and cleared to 0 by software.

Set to 1 when framing error occurred, and cleared to 0 by software.

Set to 1 when one character is received. Reset to 0 automatically when read

from the URS register. URBF will be cleared by hardware when receiving is

enabled. URBF bit is read-only. Therefore, reading the URS register is

necessary to avoid an overrun error.

Bit 0 ( RXE ) : Enable receiving

RXE = “0” : Disable RXE = “1” : Enable

Bank 2 R8 URRD (UART Receive Data Buffer)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

URRD7 URRD6 URRD5 URRD4 URRD3 URRD2 URRD1 URRD0

Bit 7 ~ Bit 0 ( UR RD7 ~ URRD0 ) : UART receive data buffer. Read only.

Bank 2 R9 URTD ( UART Transmit Data Buffer)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

URTD 7 URTD 6 URTD 5 URTD 4 URTD 3 URTD 2 URTD 1 URTD0

Bit 7 ~ Bit 0 ( UR TD 7 ~ URTD 0) : UART transmit data buffer. Write only.

Bank 3 R5 SPIC1 (SPI Control Register 1)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SMP DCOL BRS2 BRS1 BRS0 EDS DORD WBE

Bit 7 ( SMP ) : SPI data input sample phase.

SMP = “0” : Input data sampled at middle of data output time SMP = “1” : Input data sampled at the end of data output time

16 •

Product Specification (V1.0) 10.03.2006

(This specification is subject to change without further notice)

EM78P312N

8-Bit Microcontroller

In using the external clock, data input sample is fixed at the middle of data output time.

Bit 6 ( DCOL ) : SPI Data collision.

DCOL = “0” : No occurrence of Data collision

DCOL = “1” : Data collision occurred. It should be cleared by software. Bit 5 ~ Bit 3 ( BRS0 ~ BRS2 ) : SPI Clock Source Select

BRS2 BRS1 BRS0

0 0 0 Fc/213 0.95Kbit/s

0 0 1 Fc/211 3.8Kbit/s

0 1 0 Fc/210 7.6Kbit/s

0 1 1 Fc/28 30.5Kbit/s

1 0 0 Fc/26 122Kbit/s

1 0 1 Fc/25 244Kbit/s

1 1 0 External clock (/SCK pin) Enable /ss pin

1 1 1 External clock (/SCK pin) Disable /ss pin

Clock Sour ce

( Normal, Idle )

Max. Transfer Rate

( Fc = 8MHz )

Bit 2 ( EDS ) : Data shift out edge select.

EDS = “0” : Rising edge

EDS = “1” : Falling edge Bit 1 ( DORD ) : Data transmission order.

DORD = “0” : Shift left (MSB first)

DORD = “1” : Shift right (LSB first) Bit 0 ( WBE ) : Write buffer empty flag. Read only.

WBE = “0” : Write buffer empty

WBE = “1” : Not empty, set to “1” automatically when writing data to the data

buffer.

Bank 3 R6 SPIC2 (SPI Control Register 2)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SPIS 0 0 0 0 SPIM1 SPIM0 RBF

Bit 7 ( SPIS ) : SPI start shift, set the bit to “1” and shift register starts to shift. It is

cleared by hardware when shifting is finished. In transferring the next data, it

must be set to “1” again.

SPIS = “0” : Finish shifting

SPIS = “1” : Start shifting

Product Specification ( V 1 . 0) 10 . 0 3 . 2 006

(This specification is subject to change without further notice)

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