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In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or
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or materia l .
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ELAN Microelectro nics product in such applications is not supported and is prohibited.
NO PART OF THIS SPECIFICATION MA Y BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY
ANY MEANS WITHOUT THE E XPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
A Package Type: ............................................................................................................64
Specification Revision History
Doc. Version Revision Description Date
1.0 Initial Version 2006/10/03
iv •Product Specification (V1.0) 10.03.2006
EM78P312N
8-Bit Microcontroller
1 General Description
The EM78P312N is an 8-bit microprocessor with low-power, high-speed CMOS technology and high noise immunity. It
has an on-chip 4K×13-bits Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides
multi-protecti on bits to prevent intrusion of user’s OTP memory codes. Seven Option bits are also available to meet
user’s requirements. With its OTP-ROM feature, the EM78P312N provides a convenient way of developing and verifying
user’s programs. Moreover, this OTP device offers the advantages of easy and effective program updates, using
development and programming tools. User can avail of the ELAN Writer to easily program his development code.
2 Features
CPU configuration
z 4K×13 bits on-chip ROM
z 144×8 bits on-chip registers (SRAM)
z 8-level stacks for subroutine nesting
z Less than 3.5mA at 5V/8MHz
z Typically 0.8 μA, during sleep mode
z Typically 1.1 μA, during idle mode
I/O port configuration
z 4 bidirectional I/O ports : P6, P7, P8, P9
z 22 I/O pins
z 10 Programmable pull-down I/O pins
z 10 programmable pull-high I/O pins
z External interrupt : P60, P61, P73, P80
Operating voltage range:
z OTP version
Operating voltage range:2.5v~5.5v
Operating temperature range:
z -40~85°C
Operating frequency range:
Main clock
• Crystal mode:
DC ~ 20MHz/2clks @ 5V; DC ~100ns inst. cycle @ 5V
DC ~ 8MHz/2clks @ 3V;DC ~ 250ns inst. cycle @ 3V
z 8-bit channels Analog-to-Digital Converter with 10-bit
resolution
z Time Base Timer:(1Hz~16kHz at 8MHz)
z Key tone output:(1kHz~8kHz at 8MHz)
z 8-bit channels Analog-to-Digital Converter with 10-bit
resolution
Fifteen available interrupts:
z WDT time-out interrupt
z TCC overflow interrupt
z Time base timer interrupt (the first falling edge of the
source clock)
z Serial UART transmit interrupt
z Serial UART receive interrupt
z Serial UART receive error interrupt
z Four External interrupt
z ADC completion interrupt
z TC2 overflow interrupt
z TC3 overflow interrupt
z TC4 overflow interrupt
z Serial SPI interrupt
Special features
z Programmable free running watchdog timer
z Two clocks per instruction cycle
z Power-on Reset
z High noise immunity
z Power saving Sleep mode
z Selectable Oscillation mode
Package type:
z 28-pin DIP 600 mil: EM78P312NP
z 28-pin Skinny DIP 300 mil: EM78P312NAK
z 28-pin Skinny DIP 400 mil: EM78P312N
z 28-pin SOP 300 mil: EM78P312NM
z 28-pin SSOP 209 mil: EM78P312NS
Crystal type: Output terminal for crystal oscillator
RC type: Instruction clock output
External clock signal input
Input pin with Schmitt Trigger. If this pin remains at logic low, the
controller will also remain in reset condition.
8-bit bidiectional input/output pins.
P60 can be used as external Interrupt 0 (/INT0).
P61 can be used as external Interrupt 1 (INT1).
P62 can be used as 16-bit Timer/Counter 2 (TC2).
P63 can be used as divider output (/TONE).
P64 slave mode enable (/SS).
P60 ~ P63 can be used as pull-high or pull-low pins.
8-bit bidiectional input/output pins.
P70 can be used as SPI serial clock input/output (/SCK)
P71 can be used as SPI serial data input (SI) or UART data receive
input (RX)
P72 can be used as SPI serial data output (SO) or UART data
transmit output (TX)
P73 can be used as Sleep mode release input (/SLEEP) or external
interrupt Input 5 (/INT5)
P70 ~ P73 can be used as pull-high or pull-low pins
2-bit bidiectional input/output pins.
P80 can be used as 8-bit Timer/Counter 3 (TC3) or external
Interrupt Input 3 (INT3).
P81 can be used as 8-bit Timer/Counter 4 (TC4) or programmable
divider output (PDO).
P80 ~ P81 can be used as pull-high or pull-low pins.
8-bit bidiectional input/output pins.
P90~P97 can be used as 8 channel 10-bit resolution A/D converter.
P97 can be used as AD reference power supply input (VREF).
2 •
Product Specification (V1.0) 10.03.2006
(This specification is subject to change without further notice)
5 Function Description
5.1 Functional Block Diagram
EM78P312N
8-Bit Microcontroller
P9
P90
P91
P92
P93
P94
P95
P96
P97
P8
P80
P81
P7
P70
P71
P72
P73
P74
P75
P76
P77
P6
P60
P61
P62
P63
P64
P65
P66
P67
ACC
ROM
Instruction
Register
Instruction
Decoder
ALU
R3
Status Reg.
PC
8-level stack
(13 bit)
Interrupt
Control
Register
Interrupt
Circuit
R4
Ext.
OSC.
Oscillation
Generation
Reset
Mux
.
RAM
Ext.
RC
Start-up
Timer
WDT
TC2
TC3
TC4
UART
SPI
TCC
TBKTC
ADC
TC2
TC3
TC4
TX RX
Sin Sout
SCK
TCC
Keytone
Ext INT0
Ext INT3Ext INT1Ext INT5
Fig. 5-1 Functional Block Diagram
Product Specification ( V 1 . 0) 10 . 0 3 . 2 006
(This specification is subject to change without further notice)
• 3
Ain 0~7
EM78P312N
8-Bit Microcontroller
5.2 Operating Registers
Address
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
:
1F
Register
Bank 0
R0/ IAR
R1/ TCC
R2/ PC
R3/ SR
R4/ RSR
SCR
Port 6
Port 7
Port 8
Port 9
Reserved
TC4CR
TC4D
ISFR0
ISFR1
ISFR2
16 Byte
Common Register
Register
Bank 1
R3 (7, 6) = (0, 1)
TC3CR
TC3DA
TC3DB
TC2CR/ ADDL
TC2DH
TC2DL
ADCR
ADIC
ADDH
TBKTC
Reserved
Register
Bank 2
R3 (7, 6) = (1, 0)R3 (7, ) = (1, 1)
URC1
URC2
URS
URRD
URTD
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Register
Bank 3
SPIC1
SPIC2
SPID
Reserved
Reserved
PHC1
PLC1
PHC2
PLC2
Reserved
Reserved
Control
Register
Reserved
IOC6
IOC7
IOC8
IOC9
Reserved
INTCR
ADOSCR
Reserved
IMR1
IMR2
20
:
3F
Bank 0
R4 (7, 6) = (0, 0)
32 Byte
Common Register
Bank 1
R4 (7, 6) = (0, 1)
32 Byte
Common Register
Fig. 5-2 Operating Registers
4 •
Product Specification (V1.0) 10.03.2006
(This specification is subject to change without further notice)
EM78P312N
8-Bit Microcontroller
R0 (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is to act as an indirect
addressing pointer. Any instruction using R0 as a pointer actually accesses data
pointed by the RAM Select Register (R4).
R1 (Time Clock /Counter)
This register is writable and readable just like the other registers. The contents of the
prescaler counter are cleared only when a value is written into the TCC register.
R2 (Program Counter) & Stack
z Depending on the device type, R2 and hardware stack are 10-bit wide. The
structure is depicted in Fig.5-3.
z Generates 8192 ×13 bits on-chip OTP ROM addresses to the relative
programming instruction codes. One program page is 1024 words long.
z R2 is set as all "0"s when under RESET condition
z "JMP" instruction allows direct loading of the lower 10 program counter bits.
Thus, "JMP" allows the PC to go to any location within a page.
z "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed
onto the stack. Thus, the subroutine entry address can be located
anywhere within a page.
z "RET" ("RETL k", "RETI") instruction loads the program counter with the
contents of the top-level stack.
z All instructions are single instruction cycle (fclk/2 or fclk/4) except for the
instruction that would change the contents of R2. Such instruction will need
one more instruction cycle.
z For an interrupt trigger, the program ROM will jump to individual interrupt
vector at Page 0. The CPU will store ACC, R3 status and R5 PAGE
automatically, it will restore after instruction RETI.
Product Specification( V 1 . 0) 10 . 0 3 . 2 006
(This specification is subject to change without further notice)
• 5
EM78P312N
8-Bit Microcontroller
R5
PC
A12
000 : PAGE0 0000~03F F
001 : PAGE1 0400~07F F
010 : PAGE2 0800~0BFF
011 : PAGE3 0C00~0FFF
100 : PAGE4 1000~13F F
101 : PAGE5 1400~17F F
110 : PAGE6 1800~1BFF
111 : PAGE7 1C00~1FFF
INT3R = “1” : Rising edge is detected
Bit 1 ( WDTIF ) : WDT time-out flag, flag cleared by software.
Bit 0 ( EXIF0 ) : External interrupt flag (INT0). Flag cleared by software. If the INT0EN
is reset to “0”, the flag is cleared.
Product Specification( V 1 . 0) 10 . 0 3 . 2 006
(This specification is subject to change without further notice)
• 9
EM78P312N
8-Bit Microcontroller
RE (Interrupt Status Flag Register 1)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
EXIF5 TCIF2 ADIF 0 EXIF3 TCIF4 SPIF TCIF3
Bit 7 ( EXIF5 ) : External Interrupt Flag (/INT5), flag cleared by software.
Bit 6 ( TCIF2 ) : 16-bit Timer/Counter 2 Interrupt Flag, flag cleared by software.
Bit 5 ( ADIF ) : AD conversion complete flag, flag cleared by software.
Bit 3 ( EXIF3 ) : External Interrupt Flag (/INT3), flag cleared by software.
Bit 2 ( TCIF4 ) : 8-bit Timer/Counter 4 Interrupt Flag, flag cleared by software.
Bit 1 ( SPIF ) : SPI Mode Interrupt Flag, flag cleared by software.
Bit 0 ( TCIF3 ) : 8-bit Timer/Counter 3 interrupt flag, flag cleared by software.
0 : means no interrupt request
1 : means with interrupt request
z ISFR1 can be cleared by instruction, but cannot be set by instruction
z IMR1 is the interrupt mask register
z Note that reading ISFR1 will obtain the result of the ISFR1 "logic AND" and
IMR1.
RF(Interrupt Status Flag Register 2)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 UERRIF RBFF TBEF TBIF EXIF1 0 TCIF0
Bit 6 (U ERRI F ) : UART Receiving Error Interrupt, cleared by software or UART
disabled.
Bit 5 (RBFF) : UART Receive Mode Data Buffer Full Interrupt Flag. Flag cleared by
software.
Bit 4 (TB E F ) : UART Transmit Mode Data Buffer Empty Interrupt Flag. Flag cleared by
software.
Bit 3 (TBIF) : Time Base Timer Interrupt Flag. Flag cleared by software.
Bit 2 (EXIF1) : External Interrupt Flag (INT1). Flag cleared by software.
Bit 0 (TCIF0) : TCC Overflow Interrupt Flag. Set as TCC overflows; flag cleared by
software.
0 : means no interrupt request
1 : means with interrupt request
10 •
Product Specification (V1.0) 10.03.2006
(This specification is subject to change without further notice)
EM78P312N
8-Bit Microcontroller
z ISFR2 can be cleared by instruction, but cannot be set by instruction
z IMR2 is the interrupt mask register
z Note that reading ISFR2 will obtain the result of the ISFR2 "logic AND" and
IMR2
Bank 1 R5 TC3CR (Timer/Counter 3 Control Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TC3CAP TC3S TC3CK1 TC3CK0 TC3M 0 0 0
Bit 7 ( TC3CAP ) : Software capture control
TC3CAP = “0” : -
TC3CAP = “1” : Software capture
Bit 6 ( TC3S ) : Timer/Counter 3 start control
TC3S = “0” : Stop and counter clear
TC3S = “1” : Start
Bit 5 ~ Bit 4 ( TC3CK1 ~ TC3CK0 ) : Timer/Counter 3 Clock Source Select
Individual interrupt is enabled by setting its associated control bit in the IMR2 to "1".
Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction.
The IMR2 register is both readable and writable.
22 •
Product Specification (V1.0) 10.03.2006
(This specification is subject to change without further notice)
5.4 CPU Operation Mode
Registers for CPU Operation Mode
R_BANK Address NAME Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 0 0X05 SCR 0 PS2 PS1 PS0 0 1 SIS REM
−−−− R/W R/W R/W − −R/W R/W
* R_BANK: Register Bank (Bits 7, 6 of R3), R/W: Read/Write
Reset Occurs
EM78P312N
8-Bit Microcontroller
SIS=1 + SLEP
Sleep Mode
CPU : Halts
Fosc: Stops
/SLEEP Pin Input
Idle Mode
CPU : Halts
Fosc: Oscillates
SIS=0 + SLEP
Normal Mode
CPU : Operating
Fosc: Oscillates
Interrupt
Fig. 5-4 Operation Mode and Switching
Table 2. Mode Switching Control
Mode Switch Switch Method Note
Normal Æ Sleep Set SIS = 1, execute SLEP instruction −
Sleep Æ Normal /SLEEP pin wake up −
Normal Æ Idle Set SIS = 0, execute SLEP instruction −
Idle Æ Normal Interrupt −
Table 3. Operation Mode
Operation Mode Frequency CPU Code
Reset Reset Reset
Signal
Clock
Normal Fosc
Idle
Sleep Turn off
Turn on
Halt
On-chip
Peripherals
Fosc
Halt
In Normal mode, the CPU core and on-chip peripherals operate in oscillator frequency.
In Idle mode, the CPU core halts, but the on-chip peripheral and oscillator circuit remain
active. Idle mode is released to Normal mode by any interrupt source. If the ENI
instruction is set, an interrupt will be serviced first followed by executing the next
instruction which is after the Idle mode is released and the interrupt service is finished.
If the ENI instruction is not set, the next instruction will be executed which is after the
Idle mode start instruction. Idle mode can also be released by setting the /RESET pin
to low and executing a reset operation.
Product Specification( V 1 . 0) 10 . 0 3 . 2 006
(This specification is subject to change without further notice)
• 23
EM78P312N
8-Bit Microcontroller
In Sleep mode, the internal oscillator is turned off and all system operation is halted. Sleep
mode is released by /SLEEP pin (level sensitive or edge sensitive can be set by System
Control Register (SCR) Bit 0 (REM)). After a warm-up period, the next instruction will be
executed which is after the Sleep mode start instruction. Sleep mode can also be released
by setting the /RESET pin to low and executing a reset operation. In level sensitive mode,
the /SLEEP pin must be confirmed in low level before entering Sleep mode. In edge
sensitive mode, Sleep mode is started even when the /SLEEP pin is in high level.
Table 4. Wake-up Methods
1. Individual interrupt source
in IMR1, IMR2
2. WDT interrupt request
3. /INT0
4. ENI instruction is not
executed
1. Individual interrupt source
in IMR1, IMR2
2. WDT interrupt request
3. /INT0
4. Execute ENI instruction
/SLEEP pin
/RESET pin Reset Reset Reset
WDT time out Reset Reset Reset
Note:* Don’t care
Sleep Mode
Wake-up Signal
R5 (SIS) = 1+SLEP
Instruction
No effect **
No effect **
1. Wake-up
2. Jump to the next
instruction or enter
Sleep mode
**Interrupt request flag will be recorded
Idle Mode
R5 (SIS)= 0 + SLEP
Normal Mode
R5 (SIS)=(*)
Instruction
1. Wake-up
2. Jump to the next
instruction or enter
No effect**
Idle mode
1. Wake-up
2. Jump to an Interrupt
vector after RETI
instruction, then jump
Interrupt
to the next instruction
or enter Idle mode
No effect No effect
5.5 AD Converter
Registers for AD Converter Circuit
R_BANK Address NAME Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 1 0X0B ADCR
Bank 1 0X0C ADIC
Bank 1 0X0D ADDH
Bank 1 0X08 ADDL
Bank 0 0x0E ISFR1
SPR 0x0C ADOSCR
SPR 0x0E IMR1
* R_BANK : Register Bank (Bits 7, 6 of R3), R/W: Read / Write
*SPR : Special Purpose Registers
24 •
Product Specification (V1.0) 10.03.2006
(This specification is subject to change without further notice)
ADREF ADRUN ADCK1 ADCK0 ADP ADIS2 ADIS1 ADIS0
R/W R/W R/W R/W R/W R/W R/W R/W
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
R/W R/W R/W R/W R/W R/W R/W R/W
ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2
R R R R R R R R
ADD1 ADD0 0 TC2M TC2S TC2CK2 TC2CK1 TC2CK0
R R -- R/W R/W R/W R/W R/W
EXIF5 TCIF2 ADIF 0 EXIF3 TCIF4 SPIF TCIF3
R/W R/W R/W 0 R/W R/W R/W R/W
CALI SIGN VOF[2] VOF[1] VOF[0]0 0 0
R/W R/W R/W R/W R/W -- -- --
EXIE5 TCIE2 ADIE 0 EXIE3 TCIE4 SPIE TCIE3
R/W R/W R/W 0 R/W R/W R/W R/W
AD7 (P97)
AD6 (P96)
AD5 (P95)
AD4 (P94)
AD3 (P93)
AD2 (P92)
AD1 (P91)
AD0 (P90)
EM78P312N
8-Bit Microcontroller
8 to 1 Analog swi tch
ADC
Fosc/4
Fosc/16
Fosc/32
4 to 1
MUX
(Successive Approximation)
VDD
VREF
Power Down
Start to Convert
7 - 02 1 0
5 4
559 8 7 6 5 4 3 2 1 0
IMR1ISFR1ADCRADCRADIC
DATA BUS
63 7
ADCR
Fig. 5-5 AD Converter
It is a 10-bit successive approximation type AD converter. The upper side of analog
reference voltage can select either internal VDD or external input pin P97 (VREF) by
setting the ADREF bit in ADCR.
ADC Dat a Re gister
When the A/D conversion is completed, the result is loaded to the ADDH (8 bit) and
ADDL (2 bit). The START/END bit is cleared, and the ADIF is set.
A/D Sampling Time
The accuracy, linearity, and speed of the successive approximation A/D converter are
dependent on the properties of the ADC. The source impedance and the internal
sampling impedance directly affect the time required to charge the sample holding
capacitor. The application program controls the length of the sample time to meet the
specified accuracy. Generally speaking, the program should wait for 2 μs for each KΩ
of the analog source impedance and at least 2 μs for the low-impedance source. The
maximum recommended impedance for the analog source is 10KΩ at V
DD =5V. After
the analog input channel is selected, this acquisition time must be done before A/D
conversion can be started.
A/D Conversion Time
ADCK0 and ADCK1 select the conversion time (Tct), in terms of instruction cycles.
This allows the MCU to run at maximum frequency without sacrificing accuracy of A/D
conversion. For the EM78P312N, the conversion time per bit is about 4μs. Table 5
shows the relationship between Tct and the maximum operating frequencies.
Table 5
ADCK1:0 Operation Mode
0 0 Fc/4 1MHz 250kHz (4μs) 48μs (20.8kHz)
0 1 Fc/16 4MHz 250kHz (4μs) 48μs (20.8kHz)
1 0 Fc/32 8MHz 250kHz (4μs) 48μs (20.8kHz)
1 1 Reserved - - -
Product Specification( V 1 . 0) 10 . 0 3 . 2 006
(This specification is subject to change without further notice)
Max. Frequency
• 25
(Fc)
Max. Conversion
Rate per Bit
Max. Conversion
Rate
EM78P312N
8-Bit Microcontroller
5.6 Time Base Timer and Keytone Generator
Registers for AD Converter Circuit
R_BANK Address Name Bit 7 Bit 6 Bit 5 Bit 4Bit 3 Bit 2 Bit 1 Bit 0
(This specification is subject to change without further notice)
• 39
EM78P312N
8-Bit Microcontroller
TC4 pin
fc/2
fc/2
fc/2
TC4M(1,*)
TC4FF
TC4 Interrupt
F/F
Clear
Set
Toggle
Q
TC4M (1,1)
11
7
3
TC4CK
MUX
3
TC4S
TC4CR
Clear
8-bit Up-counter
TCR4
Overflow
Match
Comparator
Fig. 5-24 Timer/Counter 4 Configurat ion
5.11.1 Timer Mode
In Timer mode, counting up is performed using the internal clock. When the contents of
the up-counter matched with the TCR4, then interrupt is generated and the counter is
cleared. Counting up resumes after the counter is cleared.
5.11.2 Counter Mode
In Counter mode, counting up is performed on the rising edge of the external clock
input pin (TC4 pin). When the contents of the up-counter matched with the TCR4, then
interrupt is generated and the counter is cleared. Counting up resumes after the
counter is cleared.
/PWM, /PDO Pin
5.11.3 PDO Mode
In Programmable Divider Output (PDO) mode, counting up is performed using the
internal clock. The contents of TCR4 are compared with the contents of the
up-counter. The F/F output is toggled and the counter is cleared each time a match is
found. The F/F output is inverted and output to /PDO pin. This mode can generate
50% duty pulse output. The F/F can be initialized by the program and it is initialized to
40 •
Product Specification (V1.0) 10.03.2006
(This specification is subject to change without further notice)
“0” during a reset. A TC4 interrupt is generated each time the /PDO output is toggled.
Source Clock
Up-counter
TCR4
F/F
/PDO Pin
TC4 Interrupt
n-1
21
01 3
n
n
0
n-1
Fig. 5-25 Timing Chart for PDO Mod e
n
01 n-1
n
012
EM78P312N
8-Bit Microcontroller
5.11.4 PWM Mode
In Pulse Width Modulation (PWM) Output mode, counting up is performed using the
internal clock. The contents of the TCR4 are compared with the contents of the
up-counter. The F/F is toggled when match is found. The counter is still counting, the
F/F is toggled again when the counter overflows, then the counter is cleared. The F/F
output is inverted and output to the /PWM pin. A TC4 interrupt is generated each time
an overflow occurs. TCR4 is configured as a 2-stage shift register and, during output,
will not switch until one output cycle is completed even if TCR4 is overwritten.
Therefore, the output can be changed continuously. TRC4 is also shifted the first time
by setting TC4S to “1” after data is loaded to TCR4.
Source Clock
Up-counter
01
n
n+1
n-1
n+2
FE FF
n-1
0
n
n+2
n+1
FE FF
1
0
m-1
m
TCR4
n/n
Match
F/F
/PWM
TC4 Interrupt
Fig. 5-26 Timing Chart for PWM Mode
5.12 TCC/WDT & Prescaler
An 8-bit counter is available as prescaler for the TCC. The PSR0~PSR2 bits determine
the ratio. The prescaler is cleared each time the instruction is written to TCC under
TCC mode.
R1 (TCC) is an 8-bit timer/counter. The clock source of TCC is the internal clock. If the
TCC signal source is from the internal clock, TCC will increase by 1 at every instruction
cycle (without prescaler). CLK=Fosc/2 or CLK=Fosc/4 selection is determined by the
CODE Option bit CLK status. CLK=Fosc/2 is used if CLK bit is "0", and CLK=Fosc/4 is
used if CLK bit is "1".
The watchdog timer is a free running on-chip RC oscillator. During normal operation
mode, a WDT time-out (if enabled) will cause the device to reset or interrupt by setting
WDTO. The WDT can be enabled or disabled any time during normal mode by
software programming. Without prescaler, the WDT time-out period is approximately
18 ms (default). The WDT can also be used as a timer to generate an interrupt at fixed
interval.
Overflow
n/mm/m
Match
Overwrite
Overflow
1 Period
Shift
Product Specification( V 1 . 0) 10 . 0 3 . 2 006
(This specification is subject to change without further notice)
• 41
EM78P312N
8-Bit Microcontroller
5.13 I/O Ports
The I/O registers, Port 6, Port 7, Port 8, and Port 9 are bi-directional tri-state I/O ports.
Each I/O pin can be defined as “input” or “output” pin by the I/O control register (IOC6 ~
IOC9). The I/O registers and I/O control registers are both readable and writable. The
I/O interface circuits for Port 6, Port 7, Port 8, and Port 9 are shown in Fig. 5-26.
PCRD
P
Q
D
R
CLK
C
Q
L
PCWR
PORT
Fig. 5-27 The I/O Port and I/O Control Register Circuit
5.14 Reset and Wake-up
5.14.1 Reset
A reset is initiated by one of the following events:
(1) Power-on reset
(2) /RESET pin input “low”
(3) WDT timeout. (if enabled)
The device is kept in a reset condition for a period of approx. 18ms
start-up timer period) after the reset is detected. Once a reset occurs, the following
functions are performed.
The oscillator starts or is running
P
Q
D
R
C
Q
L
0
M
U
1
X
CLK
PDWR
PDRD
IOD
1
(one oscillator
The Program Counter (R2) is reset to all “0”.
When power is switched on, the upper two bits of R3, the upper two bits of R4 and
the Bits 6 ~ 4 of R5 are cleared.
All I/O port pins are configured as input mode (high-impedance state).
1
Note: VDD = 5V, set up time period = 16.2ms ± 30%
V
DD = 3V, set up time period = 19.6ms ± 30%
42 •
Product Specification (V1.0) 10.03.2006
(This specification is subject to change without further notice)
EM78P312N
8-Bit Microcontroller
The Watchdog timer and prescaler are cleared.
Upon power on, the upper two bits of R3 are cleared.
Upon power on, the upper two bits of R4 are cleared.
Upon power on, the upper three bits of R5 are cleared.
The bits of CONT register are set to all “1” except Bit 6 (INT flag).
ISFR0, ISFR1, ISFR2 register and IMR1, IMR2 registers are cleared.
The controller has two modes for power saving.
(1) SLEEP mode: R5 (SIS) = 1, SLEP instruction.
The internal oscillator is turned off and all system operation is halted.
(2) Idle mode: R5 (SIS) = 0, SLEP instruction
The CPU core halts but the on-chip peripheral and oscillator circuit remain active.
5.14.2 Wake-up from Sleep Mode
(1) External /SLEEP pin
The controller will be waken up and execute the next instruction after entering Sleep
mode. All the registers will maintain their original values before “SLEP” instruction was
executed.
(2) /RESET pin pull low
This will reset the controller and starts the program at address zero.
(3) WDT time out
This will reset the controller and run the program at address zero.
5.14.3 Wake-up from Idle Mode
(1) All interrupt
In all these cases, user should always enable the circuit before entering Idle mode.
After wake-up, all registers will maintain their original values before entering “SLEP”
instruction, then service an interrupt subroutine or proceed with next instruction by
setting individual interrupt enable bit. After servicing an interrupt sub-routine (“RETI”
instruction), the program will jump from “SLEP” instruction to the next instruction.
(2) /RESET pin pull low
This will reset the controller and run the program at address zero.
(3) WDT time out
This will reset the controller and run the program at address zero.
Product Specification( V 1 . 0) 10 . 0 3 . 2 006
(This specification is subject to change without further notice)
• 43
EM78P312N
8-Bit Microcontroller
Address Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x06 IOC6
0x07 IOC7
0x08 IOC8
0x09 IOC9
0x0B INTCR
ADOSC
0x0C
0x0E IMR1
0x0F IMR2
N/A CONT
0x00
0x01
0x02
0x03
0x04
R
R0
(IAR)
R1
(TCC)
R2
(PC)
R3
(SR)
R4
(RSR)
Table 6. Summary of the Initialized Values for Registers
Bit Name C67 C66 C65 C64 C63 C62 C61 C60
Power-on 1 1 1 1 1 1 1 1
/RESET and WDT time out 1 1 1 1 1 1 1 1
Wake-up from Sleep, Idle mode P P P P P P P P
Bit Name X X X X C73 C72 C71 C70
Power-on U U U U 1 1 1 1
/RESET and WDT time out U U U U 1 1 1 1
Wake-up from Sleep, Idle mode U U U U P P P P
Bit Name X X X X X X C81 C80
Power-on U U U U U U 1 1
/RESET and WDT time out U U U U U U 1 1
Wake-up from Sleep, Idle mode U U U U U U P P
Bit Name C97 C96 C95 C94 C93 C92 C91 C90
Power-on 1 1 1 1 1 1 1 1
/RESET and WDT time out 1 1 1 1 1 1 1 1
Wake-up from Sleep, Idle mode P P P P P P P P
Bit Name INT1NR INT0ENX
Power-on 0 0 0 0 0 0 0 0
/RESET and WDT time out 0 0 0 0 0 0 0 0
Wake-Up from Sleep, Idle mode P P P P P P P P
Bit Name CALI SIGN VOF2 VOF1 VOF0 X X X
Power-on 0 0 0 0 0 U U U
/RESET and WDT time out 0 P P P P U U U
Wake-up from Sleep, Idle mode 0 P P P P U U U
Bit Name EXIE5 TCIE2 ADIE X EXIE3 TCIE4 SPIE TCIE3
Power-on 0 0 0 U 0 0 0 0
/RESET and WDT time out 0 0 0 U 0 0 0 0
Wake-up from Sleep, Idle mode P P P U P P P P
Bit Name X
Power-on U 0 0 0 0 0 U 0
/RESET and WDT time out U 0 0 0 0 0 U 0
Wake-Up from Sleep, Idle mode U P P P P P U P
Bit Name WDT0 /INT WDTP1 WDTP0 WDTE PSR2 PSR1 PSR0
Power-on 0 0 0 0 0 0 0 0
/RESET and WDT time out 0 0 0 0 0 0 0 0
Wake-up from Sleep, Idle mode P P P P P P P P
Bit Name - - - - - - - -
Power-on U U U U U U U U
/RESET and WDT time out P P P P P P P P
Wake-up from Sleep, Idle mode
Bit Name - - - - - - - -
Power-on 0 0 0 0 0 0 0 0
/RESET and WDT time out 0 0 0 0 0 0 0 0
Wake-up from Sleep, Idle mode P P P P P P P P
Bit Name - - - - - - - -
Power-on 0 0 0 0 0 0 0 0
/RESET and WDT time out 0 0 0 0 0 0 0 0
Wake-up from Sleep, Idle mode Jump to interrupt vector or execute next instruction
Bit Name RBS1 RBS0 X T P Z DC C
Power-on 0 0 0 1 1 U U U
/RESET and WDT time out 0 0 0 t t P P P
Wake-up from Sleep, Idle mode P P P t t P P P
Bit Name X GRBS0 RSR5 RSR4 RSR3 RSR2 RSR1 RSR0
Power-on 0 0 U U U U U U
/RESET and WDT time out 0 0 P P P P P P
Wake-Up from Sleep, Idle mode P P P P P P P P
UERRIE
P P P P P P P P
INT3ES1 INT3ES0
URIE UTIE TBIE EXIE1 X TCIE0
X INT1ES TC2ES
44 •
Product Specification (V1.0) 10.03.2006
(This specification is subject to change without further notice)
EM78P312N
8-Bit Microcontroller
Register Bank 0
Address Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit Name X X X PS0 X X SIS REM
0x05 SCR
0x06 Port 6
0x07 Port 7
0x08 Port 8
0x09 Port 9
0x0B TC4CR
0x0C TC4D
0X0D ISFR0
0X0E ISFR1
0X0F ISFR2
Power-on U 0 0 0 U U 0 0
/RESET and WDT time out U 0 0 0 U U 0 0
Wake-up from Sleep, Idle mode U P P P U U P P
Bit Name P67 P66 P65 P64 P63 P62 P61 P60
Power-on 1 1 1 1 1 1 1 1
/RESET and WDT time out 1 1 1 1 1 1 1 1
Wake-up from Sleep, Idle mode P P P P P P P P
Bit Name X X X X P73 P72 P71 P70
Power-on U U U U 1 1 1 1
/RESET and WDT time out U U U U 1 1 1 1
Wake-up from Sleep, Idle mode U U U U P P P P
Bit Name X X X X X X P81 P80
Power-on U U U U U U 1 1
/RESET and WDT time out U U U U U U 1 1
Wake-up from Sleep, Idle mode U U U U U U P P
Bit Name P97 P96 P95 P94 P93 P92 P91 P90
Power-on 1 1 1 1 1 1 1 1
/RESET and WDT time out 1 1 1 1 1 1 1 1
Wake-Up from Sleep, Idle mode P P P P P P P P
Bit Name TC4FF1 TC4 FF0 TC4S TC4CK2 TC4 CK1 TC4 CK0 TC4M1 TC4M0
Power-on 0 0 0 0 0 0 0 0
/RESET and WDT time out 0 0 0 0 0 0 0 0
Wake-up from Sleep, Idle mode P P P P P P P P
Bit Name TC4D7 TC4D6 TC4D5 TC4D4 TC4D3 TC4D2 TC4D1 TC4D0
Power-on 0 0 0 0 0 0 0 0
/RESET and WDT time out 0 0 0 0 0 0 0 0
Wake-up from Sleep, Idle mode P P P P P P P P
Bit Name X X INT3F INT3RX X WDTIF EXIF0
Power-on U U 0 0 U U 0 0
/RESET and WDT time out U U 0 0 U U 0 0
Wake-up from Sleep, Idle mode U U P P U U P P
Bit Name EXIF5 TCIF2 ADIF X EXIF3 TCIF4 SPIF TCIF3
Power-on 0 0 0 U 0 0 0 0
/RESET and WDT time out 0 0 0 U 0 0 0 0
Wake-up from Sleep, Idle mode U P P U P P P P
Bit Name X UE RRIF RBFF TBEF TBIF EXIF1 X TCIF0
Power-on U 0 0 0 0 0 U 0
/RESET and WDT time out U 0 0 0 0 0 U 0
Wake-up from Sleep, Idle mode U P P P P P U P
Product Specification( V 1 . 0) 10 . 0 3 . 2 006
(This specification is subject to change without further notice)
• 45
EM78P312N
8-Bit Microcontroller
Register Bank 1
Addres
0X0D ADDH
Name Reset Type Bit 7 Bit 6 Bi t 5 Bit 4 Bit 3 Bit 2 Bit 1 Bi t 0
s
Bit Name TC3CAP TC3 S TC3CK1 TC3 CK0 TC3M X X X
0x05 TC3CR
0x06 TC3DA
0x07 TC3DB
TC2CR/
0x08
0x09 TC2DH
0x0A TC2DL
0x0B ADCR
0x0C ADIC
0X0E TBKTC
Power-on 0 0 0 0 0 U U U
/RESET and WDT time out 0 0 0 0 0 U U U
Wake-up from Sleep, Idle mode P P P P P U U U
Bit Name TC3DA7 TC3DA6 TC3D A5 TC3DA 4 TC3DA3 TC3DA 2 TC3DA1 TC3DA 0
Power-on 0 0 0 0 0 0 0 0
/RESET and WDT time out 0 0 0 0 0 0 0 0
Wake-up from Sleep, Idle mode P P P P P P P P
Bit Name TC3DB7 TC3DB6 TC3D B5 TC3DB 4 TC3DB3 TC3DB 2 TC3DB1 TC3DB 0
Power-on 0 0 0 0 0 0 0 0
/RESET and WDT time out 0 0 0 0 0 0 0 0
Wake-up from Sleep, Idle mode P P P P P P P P
Bit Name ADD1 ADD0 X TC2M TC2S TC2 CK2 TC2CK1 TC2 CK0
Power-on U U U 0 0 0 0 0
ADDL
/RESET and WDT time out P P U 0 0 0 0 0
Wake-up from Sleep, Idle mode P P U P 0 P P P
Bit Name TC2D 15 TC2D14 TC2D13 TC2D12 TC2D11 TC2D10 TC2D9 TC2D8
Power-On 0 0 0 0 0 0 0 0
/RESET and WDT time out 0 0 0 0 0 0 0 0
Wake-up from Sleep, Idle mode P P P P P P P P
Bit Name TC2D7 TC2D6 TC2D5 TC2D4 TC2D3 TC2D2 TC2D1 TC2D0
Power-on 0 0 0 0 0 0 0 0
/RESET and WDT time out 0 0 0 0 0 0 0 0
Wake-up from Sleep, Idle mode P P P P P P P P
Bit Name ADREF ADRUN ADCK1 ADCK0 ADP ADIS2 ADIS1 ADIS0
Power-on 0 0 0 0 1 0 0 0
/RESET and WDT time out 0 0 0 0 1 0 0 0
Wake-up from Sleep, Idle mode P (*) P P P P P P
Bit Name ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
Power-on 0 0 0 0 0 0 0 0
/RESET and WDT time out 0 0 0 0 0 0 0 0
Wake-up from Sleep, Idle mode P P P P P P P P
Bit Name ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2
Power-on U U U U U U U U
/RESET and WDT time out P P P P P P P P
Wake-up from Sleep, Idle mode P P P P P P P P
Bit Name TEN TCK1 TCK0 X TBTEN TBTCK2 TB TCK1 TBTCK0
Power-on 0 0 0 0 0 0 0 0
/RESET and WDT time out 0 0 0 0 0 0 0 0
Wake-up from Sleep, Idle mode 0 P P P 0 P P P
46 •
Product Specification (V1.0) 10.03.2006
(This specification is subject to change without further notice)
EM78P312N
8-Bit Microcontroller
Register Bank 2
Address Name Reset Ty pe Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit Name URTD8 UMODE 1 UMODE0 BRATE2 BRATE1 BRATE0 UTBE TXE
0x05 URC1
0x06 URC2
0x07 URS
0x08 URRD
0x09 URTD
Power-on U 0 0 0 0 0 0 0
/RESET and WDT time out P P P P P P 0 0
Wake-up from Sleep, Idle mode P 0 P P P P P 0
Bit Name X X SBIM1 SBIM0 UINVENX X X
Power-on U U 0 0 0 U U U
/RESET and WDT time out U U P P P U U U
Wake-up from Sleep, Idle mode U U P P P U U U
Bit Name URRD8 EVEN PRE PRERR OVERR FMERR URBF RXE
Power-on U 0 0 0 0 0 0 0
/RESET and WDT time out P P P 0 0 0 0 0
Wake-up from Sleep, Idle mode P P P P P P P 0
Bit Name URRD7 URRD6 URRD5 URRD4 URRD3 URRD2 URRD1 URRD0
Power-on U U U U U U U U
/RESET and WDT time out P P P P P P P P
Wake-up from Sleep, Idle mode P P P P P P P P
Bit Name URTD 7 URTD 6 URTD 5 URTD 4 URTD 3 URTD 2 URTD 1 URTD0
Power-on U U U U U U U U
/RESET and WDT time out P P P P P P P P
Wake-up from Sleep, Idle mode P P P P P P P P
Register Bank 3
Address Name R ese t Type Bit 7 Bit 6 Bit 5 Bit 4 Bi t 3 Bit 2 Bit 1 Bit 0
Bit Name SMP DCOL BRS2 BRS1 BRS0 EDS DORD WBE
0x05 SPIC1
0x06 SPIC2
0x07 SPID1
0x0A PHC1
0x0B PLC2
0x0C PHC2
0x0D PLC2
Power-on 0 0 0 0 0 0 0 0
/RESET and WDT time out P P P P P P P 0
Wake-up from Sleep, Idle mode P P P P P P P P
Bit Name SPIS X X X X SPIM1 SPIM0 RBF
Power-on 0 0 0 0 0 0 0 0
/RESET and WDT time out 0 0 0 0 0 P P 0
Wake-up from Sleep, Idle mode 0 P P P P P P P
Bit Name SPID17 SPID16 SPID15 SPID14 SPID13 SPID12 SPID11 SPID10
Power-on U U U U U U U U
/RESET and WDT time out P P P P P P P P
Wake-up from Sleep, Idle mode P P P P P P P P
Bit Name X X /PHE81 /PHE80 /PHE63 /PHE62 /PHE61 /PHE60
Power-on U U 1 1 1 1 1 1
/RESET and WDT time out U U 1 1 1 1 1 1
Wake-up from Sleep, Idle mode U U P P P P P P
Bit Name X X /PLE81 /PLE80 /PLE63 /PLE62 /PLE61 /PLE60
Power-on U U 1 1 1 1 1 1
/RESET and WDT time out U U 1 1 1 1 1 1
Wake-up from Sleep, Idle mode U U P P P P P P
Bit Name X X X X /PHE73 /PHE72 /PHE71 /PHE70
Power-on U U U U 1 1 1 1
/RESET and WDT time out U U U U 1 1 1 1
Wake-up from Sleep, Idle mode U U U U P P P P
Bit Name X X X X /PLE73 /PLE72 /PLE71 /PLE70
Power-on U U U U 1 1 1 1
/RESET and WDT time out U U U U 1 1 1 1
Wake-up from Sleep, Idle mode U U U U P P P P
Product Specification( V 1 . 0) 10 . 0 3 . 2 006
(This specification is subject to change without further notice)
• 47
EM78P312N
8-Bit Microcontroller
Address Name R ese t Type Bit 7 Bit 6 Bit 5 Bit 4 Bi t 3 Bit 2 Bit 1 Bit 0
0x10
~
0x3F
Bit Name - - - - - - - -
R10
Power-on U U U U U U U U
~
/RESET and WDT time out P P P P P P P P
R3F
Wake-up from Sleep, Idle mode P P P P P P P P
General Purpose Registers
Legend: “×” = not used “P” = previous value before reset
“u” = unknown or don’t care “t” = check Table 7
5.14.4 The Status of RST, T, and P of the Status Register
The values of T and P are used to verify the event that triggered the processor to wake
up. Table 7 shows the events that may affect the status of T and P.
Table 7. The Values of RST, T and P after a reset
Reset Type T P
Power on 1 1
/RESET during Operation mode *P *P
/RESET wake-up during Sleep mode *P *P
/RESET wake-up during Idle mode *P *P
WDT during Operation mode 0 *P
WDT wake-up during Sleep mode 0 *P
WDT wake-up during Idle mode 0 *P
*P: Previous status before reset
Table 8 The Events that may affect the T and P Status
Event T P
Power on 1 1
WDTC instruction 1 1
WDT time-out 0 *P
SLEP instruction 1 0
Wake-Up during Sleep mode *P *P
*P: Previous value before reset
48 •
Product Specification (V1.0) 10.03.2006
(This specification is subject to change without further notice)
EM78P312N
8-Bit Microcontroller
VDD
Power-on
Reset
Voltage
Detector
WDTE
/RESET
5.15 Interrupt
The EM78P312N has 15 interrupts (9 external, 6 internal) as listed below:
Table 9 Interrupt Vector
Interrupt Source Enable Condition Int. Flag Int. Vector Priority
ISFR0, ISFR1 and ISFR2 are the interrupt status registers that record the interrupt
requests in the relative flags/bits. IMR1 and IMR2 are the interrupt mask registers. The
global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction.
When one of the interrupts (enabled) occurs, the next instruction will be fetched from
individual address. The interrupt flag bit must be cleared by instructions before leaving
the interrupt service routine and before interrupts are enabled to avoid recursive
interrupts.
Product Specification( V 1 . 0) 10 . 0 3 . 2 006
(This specification is subject to change without further notice)
• 49
EM78P312N
8-Bit Microcontroller
The flag (except ICIF bit) in the Interrupt Status Register (ISFR 2) is set regardless of
the status of its mask bit or the execution of ENI. The RETI instruction ends the
interrupt routine and enables the global interrupt (the execution of ENI).
5.16 Oscillator
5.16.1 Oscillator Modes
The EM78P312N can operate in two different oscillator modes, i.e., Crystal oscillator
mode and External RC oscillator mode (ERC) oscillator mode. User can select which
mode by Code Option Register. The maximum limit for operational frequencies of the
crystal/resonator under different VDDs is listed below.
EM78P312N has a clock generator. i.e. fc (high frequency) which can be driven by an
external clock signal through the OSCI pin.
In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or
ceramic resonator to generate oscillation. Table 12 provides the recommended values
of C1 and C2. Since each resonator has its own attribute, user should refer to its
specification for appropriate values of C1 and C2. A serial resistor Rs may be
necessary for AT strip cut crystal.
50 •
Product Specification (V1.0) 10.03.2006
(This specification is subject to change without further notice)
EM78P312N
8-Bit Microcontroller
OSCI
OSCO
EM78P312N
EM78P809N
Ext. Clock
Fig. 5-29 Crystal/Resonator Circuit
C1
OSCI
EM78P312N
EM78P809N
XTAL
OSCO
RS
C2
Fig. 5-30 Crystal/Resonator Circuit
Table12. Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator
Oscillator Type Frequency Mode Frequency C1 (p F) C2 (pF)
Ceramic Resonator HXT
Crystal Oscillator HXT
2.0 MHz 20~40 20~40
4.0 MHz 10~30 10~30
1.0 MHz 15~30 15~30
2.0 MHz 15 15
4.0 MHz 15 15
OSCI
EM78P312N
EM78P809N
Fig. 5-31 Crystal/Resonator-Series Mode Circuit
Product Specification ( V 1 . 0) 10 . 0 3 . 2 006
(This specification is subject to change without further notice)
• 51
740
4
740
4
33
0
33
0
C
740
4
XTAL
EM78P312N
8-Bit Microcontroller
4.7
K
10
K
Vdd
OSCI
EM78P809N
EM78P312N
740
4
10
740
4
K
XTAL
C1
C2
Fig. 5-32 Cr ystal/Resonator-Parall el Mode Cir cuit
5.16.3 External RC Oscill ato r Mode
For applications that do not need very precise timing calculation, the RC oscillator
offers a lot of cost savings. Nevertheless, it should be noted that the frequency of the
RC oscillator is influenced by the supply voltage, the values of the resistor (Rext), the
capacitor (Cext), and even by the operation temperature. Moreover, the frequency
also varies slightly from one chip to another due to the manufacturing process variation.
In order to maintain a stable system frequency, the values of the Cext should not be
less than 20pF, and the value of Rext should not be greater than 1 M
frequency is easily affected by noise, humidity, and leakage.
The smaller the Rext in the RC oscillator, the faster its frequency will be. On the
contrary, for very low Rext values, for instance, 1 K
Ω, the oscillator becomes unstable
because the NMOS cannot correctly discharge the current of the capacitance.
, otherwise, the
Hence, it must be noted that the supply voltage, the operation temperature, the RC
oscillator components, the package types, and the PCB layout, will affect the system
frequency.
Vdd
Rext
OSC1
OSCI
EM78P312N
EM78P809N
Cext
Fig. 5-33 External RC Oscillator Mode Circuit
52 •
Product Specification (V1.0) 10.03.2006
(This specification is subject to change without further notice)
Table13. RC Oscillator Frequencies
Cext Rext Average Fosc 5V, 25°C Average Fosc 3V, 25°C
3.3k 4.32 MHz 3.56 MHz
20 pF
100 pF
300 pF
1
Note:
: Measured based on DIP packages.
2
: The values are for design reference only.
5.1k 2.83 MHz 2.8 MHz
10k 1.62 MHz 1.57 MHz
100k 184kHz 187kHz
3.3k 1.39 MHz 1.35 MHz
5.1k 950kHz 930kHz
10k 500kHz 490kHz
100k 54kHz 55kHz
3.3k 580kHz 550kHz
5.1k 390kHz 380kHz
10k 200kHz 200kHz
100k 21kHz 21kHz
5.17 Code Option Register
The EM78P312N has one CODE option word that is not part of the normal program
memory. The option bits cannot be accessed during normal program execution.
EM78P312N
8-Bit Microcontroller
Code Option Register and Customer ID Register arrangement distribution:
Word 0 Word 1 Word 2
Bit 12~Bit 0 Bit 12~Bit 0 Bit 12~Bit 0
5.17.1 Code Opti on R egi st e r (Wo r d 0)
Word 0
Bit 12 ~ 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
- CLKS ENWDTB CYES - OSC HLP PR2 PR1 PR0
Bit 12 ~ 9 : Not used
Bit 8 ( CLKS) : Instruction period option bit
CLKS = “0” : two oscillator periods
CLKS = “1” : four oscillator periods.
Refer to the Instruction Set section.
Bit 7 (ENWDTB) : Watchdog timer enable bit
ENWDTB = “0” : Enable
ENWDTB = “1” : Disable
Bit 6 (CYES) : Cycle selection for JMP, CALL instruction
CYES = “0” : One cycle
CYES = “1” : Two cycles
Product Specification
(This specification is subject to change without further notice)
(V1.0) 10 . 03.2006• 53
EM78P312N
8-Bit Microcontroller
Bit 4 (OSC) : Oscillator type selection
Bit 3 (HLP) : Power selection
Bit 2~0 (PR2~PR0) : Protect Bit
PR2~PR0 are write-protect bits, configured as follow s:
5.17.2 Customer ID Register
OSC = “0” : RC type
OSC = “1” : Crystal type
HLP = “0” : Low power
HLP = “1” : High power
PR2 PR1 PR0 Protect
Others Enable
1 1 1 Disable
Word 1
Bit 12~Bit 0
XXXXXXXXXXXXX
XXXXXXXXXXXXX
Bits 12 ~ 0: Customer’s ID code
5.18 Power-on Considerations
Any microcontroller is not guaranteed to start and operate properly before the power
supply maintains at its steady state. The EM78P312N has a built-in Power On Voltage
Detector (POVD) with a detecting level of 2.1V. It will work well if V
(10 ms or less). In many critical applications, however, additional components are
required to provide solutions on probable power-up problems.
5.18.1 External P ow er-on Res et Circ ui t
The circuit shown in Fig. 5-33 use an external RC to produce the reset pulse. The
pulse width (time constant) should be kept long enough for V
operation voltage. This circuit is used when the power supply has slow rise time.
Because the current leakage from the /RESET pin is about
that R should not be greater than 40K. In this way, the /RESET pin voltage is held
below 0.2V. The diode (D) acts as a short circuit at the moment of power down. The
capacitor C will discharge rapidly and fully. Rin, the current-limited resistor, will prevent
high current or ESD (electrostatic discharge) from flowing to pin /RESET.
Word 2
Bit 12~Bit 0
DD rises fast enough
DD to reach minimum
±5μA, it is recommended
• Product Specification (V1.0) 10.03.2006
54
(This specification is subject to change without further notice)
EM78P312N
8-Bit Microcontroller
Vdd
Rin
R
D
C
/RESET
EM78P312N
EM78P809N
Fig. 5-34 External Power-Up Reset Circuit
5.18.2 Residue-Voltage Protection
When battery is replaced, device power (VDD) is taken off but residue-voltage remains.
The residue-voltage may trip below V
cause a poor power-on reset. Fig.35 and Fig. 36 show how to build the residue-voltage
protection circuit.
Vdd
EM78P312N
EM78P809N
DD minimum, but not to zero. This condition may
33K
Q1
10K
Vdd
/RESET
40K
Fig. 5-35 Residue Voltage Protect ion Circuit 1
Vdd
EM78P312N
EM78P809N
Q1
/RESET
40K
Product Specification
(This specification is subject to change without further notice)
(V1.0) 10 . 03.2006• 55
Fig. 5-36 Residue Voltage Protection Circuit 2
1N4684
Vdd
R1
R2
EM78P312N
8-Bit Microcontroller
5.19 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one
or more operands. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of 2 oscillator periods), unless the program counter is
changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or
logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6", "CLR R2",
execution takes two instruction cycles.
In case the instruction cycle specification is not suitable for certain applications, try to
modify the instruction as follows:
(A) Change one instruction cycle to consist of 4 oscillator periods.
(B) The following commands are executed within two instruction cycles; "JMP",
"CALL", "RET", "RETL", "RETI", including the conditional skip ("JBS", "JBC", "JZ",
"JZA", "DJZ", "DJZA") instructions. In addition, instructions that are written to the
program counter are executed within two instruction cycles.
Case (A) is selected by the CODE Option bit, called CLK. One instruction cycle
consists of two oscillator clocks if CLK is low, and four oscillator clocks if CLK is high.
Note that once the 4 oscillator periods within one instruction cycle is selected as in
Case (A), the internal clock source to TCC should be CLK=Fosc/4, not Fosc/2.
⋅⋅⋅⋅). In this case, the
Furthermore, the instruction set has the following features:
(1) Every bit of any register can be set, cleared, or tested directly.
(2) The I/O register can be regarded as general register. That is, the same instruction
can operate on I/O register.
Convention:
R = Register designator that specifies which one of the registers (including operation and general purpose
registers) is to be utilized by the instruction.
b = Bit field designator that selects the value for the bit located in the register R and which affects the
operation.
k = 8 or 10-bit constant or literal value
Binary Instruct io n Hex Mnemonic Operation
0 0000 0000 0000 0000 NOP No Operation None
0 0000 0000 0001 0001 DAA Decimal Adjust A C
0 0000 0000 0010 0002 CONTW A → CONT None
0 0000 0000 0011 0003 SLEP
0 0000 0000 0100 0004 WDTC 0 → WDT T, P
0 0000 0000 rrrr 000r IOW R A → IOCR None 1
0 0000 0001 0000 0010 ENI Enable Interrupt None
0 0000 0001 0001 0011 DISI Disable Interrupt None
0 0000 0001 0010 0012 RET [Top of Stack] → PC None
0 0000 0001 0011 0013 RETI
0 0000 0001 0100 0014 CONTR CONT → A None
0 0000 0001 rrrr 001r IOR R IOCR → A None 1
0 → WDT, Stop
oscillator
[Top of Stack] → PC,
Enable Interrupt
T, P
None
Status
Affected
• Product Specification (V1.0) 10.03.2006
56
(This specification is subject to change without further notice)
EM78P312N
8-Bit Microcontroller
Binary Instruct io n Hex Mnemonic Operation
0 0000 01rr rrrr 00rr MOV R, A A → R None
0 0000 1000 0000 0080 CLRA 0 → A Z
0 0000 11rr rrrr 00rr CLR R 0 → R Z
0 0001 00rr rrrr 01rr SUB A, R R-A → A Z,C,DC
0 0001 01rr rrrr 01rr SUB R, A R-A → R Z,C,DC
0 0001 10rr rrrr 01rr DECA R R-1 → A Z
0 0001 11rr rrrr 01rr DEC R R-1 → R Z
0 0010 00rr rrrr 02rr OR A, R A ∨ R → A Z
0 0010 01rr rrrr 02rr OR R, A A ∨ R → R Z
0 0010 10rr rrrr 02rr AND A, R A & R → A Z
0 0010 11rr rrrr 02rr AND R, A A & R → R Z
0 0011 00rr rrrr 03rr XOR A, R A ⊕ R → A Z
0 0011 01rr rrrr 03rr XOR R, A A ⊕ R → R Z
0 0011 10rr rrrr 03rr ADD A, R A + R → A Z,C,DC
0 0011 11rr rrrr 03rr ADD R, A A + R → R Z,C,DC
0 0100 00rr rrrr 04rr MOV A, R R → A Z
0 0100 01rr rrrr 04rr MOV R, R R → R Z
0 0100 10rr rrrr 04rr COMA R /R → A Z
0 0100 11rr rrrr 04rr COM R /R → R Z
0 0101 00rr rrrr 05rr INCA R R+1 → A Z
0 0101 01rr rrrr 05rr INC R R+1 → R Z
0 0101 10rr rrrr 05rr DJZA R R-1 → A, skip if zero None
0 0101 11rr rrrr 05rr DJZ R R-1 → R, skip if zero None
0 0110 00rr rrrr 06rr RRCA R
0 0110 01rr rrrr 06rr RRC R
0 0110 10rr rrrr 06rr RLCA R
0 0110 11rr rrrr 06rr RLC R
0 0111 00rr rrrr 07rr SWAPA R
R(n) → A(n-1),
R(0) → C, C → A(7)
R(n) → R(n-1),
R(0) → C, C → R(7)
R(n) → A(n+1),
R(7) → C, C → A(0)
R(n) → R(n+1),
R(7) → (C), C → (R(0)
R(0-3) → ( A(4-7),
R(4-7) → ( A(0-3)
0 0111 01rr rrrr 07rr SWAP R R(0-3) → ( R(4-7) None
0 0111 10rr rrrr 07rr JZA R R+1 → A, skip if zero None
0 0111 11rr rrrr 07rr JZ R R+1 → R, skip if zero None
0 100b bbrr rrrr 0xxx BC R, b 0→ ( R(b) None
0 101b bbrr rrrr 0xxx BS R, b 1→ ( R(b) None
0 110b bbrr rrrr 0xxx JBC R, b if R(b)=0, skip None
0 111b bbrr rrrr 0xxx JBS R, b if R(b)=1, skip None
1 00kk kkkk kkkk 1kkk CALL k
PC+1 → [SP],
(Page, k) → (PC)
1 01kk kkkk kkkk 1kkk JMP k (Page, k) → (PC) None
1 1000 kkkk kkkk 18kk MOV A, k k → A None
1 1001 kkkk kkkk 19kk OR A, k A v k → A Z
1 1010 kkkk kkkk 1Akk AND A, k A & k → A Z
1 1011 kkkk kkkk 1Bkk XOR A, k A ⊕ k → A Z
1 1100 kkkk kkkk 1Ckk RETL k
k → A, [Top of Stack] →
PC
1 1101 kkkk kkkk 1Dkk SUB A, k k-A → A Z,C,DC
1 1111 kkkk kkkk 1Fkk ADD A, k k+A → A Z,C,DC
1 1110 1000 kkkk 1E8k PAGE k K->R5(6:4) None
1 1110 1001 kkkk 1E9k BANK k K->R4(7:6) None
1
Note:
This instruction is applicable to IOC6~IOCA, IMR1, IMR2 only.
Status
Affected
C
C
C
C
None
None
None
Product Specification
(This specification is subject to change without further notice)
(V1.0) 10 . 03.2006• 57
EM78P312N
8-Bit Microcontroller
6 Absolute Maximum Ratings
6.1 Absolute Maximum Ratings
Items Rating
Temperature under bias -40°C to 85°C
Storage temperature -65°C to 150°C
Input voltage -0.3V to +6.0V
Output voltage -0.3V to +6.0V
Operating Frequency (2clk) DC to 10MHz
6.2 Recommended Operating Conditions
Vss = 0V
Symbol Parameter Condition Min. Typ. Max. Unit
VDD Supply Voltage
Fc
Crystal: VDD 4.5 to 5.5V 1 − 10
Crystal: VDD 2.5 to 5.5V
Fc = 10MHz 4.0 −
Fc = 4MHz 2.5 −
Two cycles with two clocks
5.5 V
1 − 4
MHz
• Product Specification (V1.0) 10.03.2006
58
(This specification is subject to change without further notice)
EM78P312N
8-Bit Microcontroller
7 Electrical Characteristics
7.1 DC Electrical Characteristics
Ta= 25 °C, VDD= 5.0V ± 5%, VSS= 0V
Symbol Parameter Condition Min. Typ. Max. Unit
Fc Crystal: 4.5V to VDD Two cycles with two clocks 1 − 10 MHz
IRC1 Sink current VI from low to high , VI=5V 7 9.5 12 μA
VILRC
IRC2 Sink current VI from high to low , VI=2V 6 8.5 11 μA
IIL
VIH1
VIL1
VIHT2
VILT2
VIHX1 Clock Input High Voltage LOSCI, OSCI in crystal mode 0.7 VDD− VDD +0.3V V
VILX1 Clock Input Low Voltage LOSCI, OSCI in crystal mode -0.3V − 0.3 VDD V
IOH1
IOL1
IOL2
IPH Pull-high current Pull-high active, input pin at VSS -15 -23 -31 μA
IPL Pull-low current Pull-low active, input pin at VDD 15 23 30 μA
ISB1
ISB2
ICC3
ICC4
Note:* Data in the Minimum, Typical, Maximum (“Min”, “Typ”, ”Max”) columns are based on characterization results at 25°C.
Input High Threshold
Voltage (Schmitt Trigger)
Input Low Threshold
Voltage (Schmitt Trigger)
Input Leakage Current for
input pins
Input High Voltage
(Schmitt Trigger)
Input Low Voltage
(Schmitt Trigger)
Input High Threshold
Voltage (Schmitt Trigger)
Input Low Threshold
Voltage (Schmitt Trigger)
Output High Voltage
(Ports 6, 7, 8, 9)
Output Low Voltage
(Port 9)
Output Low Voltage
(Ports 6,Port7, Port8)
Sleep mode
Power down current
Sleep mode
Power down current
Idle mode
Operating supply current
at two clocks
Normal mode
Operating supply current
at two clocks
°C, VDD= 3.0V ± 5%, VSS= 0V
OSCI in RC mode 1.6 2.3 2.8 V
OSCI in RC mode 0.7 1 1.3 V
VIN = VDD, VSS -1 0 1 μA
Ports 6,7,8,9,A 0.7VDD− VDD+0.3V V
Ports 6,7,8,9,A -0.3V − 0.3VDD V
/RESET, TCC 0.7 VDD− VDD +0.3V V
/RESET, TCC -0.3V − 0.3 VDD V
VOH = VDD-0.4V -2 -3.5 -5 mA
VOL = VSS+0.4V 2 3.5 5 mA
VOL = VSS+0.4V 10 13 16 mA
All input and I/O
pins at VDD,
output pin floating
VDD=3V, /RESET= 'High',
Fc=4MHz, CLKS="0", output pin
floating, WDT enabled
WDT disabled− 0.4 0.8 μA
WDT enabled− 1.5 3 μA
− 0.3 0.5 mA
− 1.1 1.5 mA
• Product Specification (V1.0) 10.03.2006
60
(This specification is subject to change without further notice)
EM78P312N
8-Bit Microcontroller
A/D Converter Characteristic (Vdd =2.5V to 5.5V, Vss=0V, Ta = -40 to 85°C)