IBM EM78P259N-260N User Manual

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EM78P259N/260N

8-Bit Microprocessor

with OTP ROM

Product

Specification

DOC. VERSION 1.2

ELAN MICROELECTRONICS CORP.

May 2007

Trademark Acknowledgments:

IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation.

ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation.

Copyright © 2005~2007 by ELAN Microelectronics Corporation

All Rights Reserved

Printed in Taiwan

The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order.

In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material.

The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement.

ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited.

NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.

ELAN MICROELECTRONICS CORPORATION

Headquarters:

Hong Kong:

USA:

No. 12, Innovation Road 1

Elan (HK) Microelectronics

Elan Information Technology

Hsinchu Science Park

Corporation, Ltd.

Group (USA)

Hsinchu, Taiwan 30077

Flat A, 19F., World Tech Centre 95

1821 Saratoga Ave., Suite 250

Tel: +886 3 563-9977

How Ming Street, Kwun Tong

Saratoga, CA 95070

Fax: +886 3 563-9966

Kowloon, HONG KONG

USA

http://www.emc.com.tw

Tel: +852 2723-3376

Tel: +1 408 366-8225

 

Fax: +852 2723-7780

 

Fax: +1 408 366-8220

 

elanhk@emc.com.hk

 

 

 

Shenzhen:

Shanghai:

 

Elan Microelectronics

Elan Microelectronics

 

Shenzhen, Ltd.

Shanghai, Ltd.

 

3F, SSMEC Bldg., Gaoxin S. Ave. I

#23, Zone 115, Lane 572, Bibo Rd.

 

Shenzhen Hi-tech Industrial Park

Zhangjiang Hi-Tech Park

 

(South Area) Shenzhen

Shanghai, CHINA 201203

 

CHINA 518057

Tel: +86 21 5080-3866

 

Tel: +86 755 2601-0565

Fax: +86 21 5080-4600

 

Fax: +86 755 2601-0500

 

 

 

 

 

 

 

 

Contents

Contents

 

1

General Description ..................................................................................................

1

2

Features .....................................................................................................................

 

1

3

Pin Assignment .........................................................................................................

2

4

Block Diagram ...........................................................................................................

2

5

Pin Description..........................................................................................................

3

 

5.1

EM78P259NP/M.................................................................................................

3

 

5.2

EM78P260NP/M/KM .........................................................................................

4

6

Function Description ................................................................................................

5

 

6.1

Operational Registers.........................................................................................

5

 

 

6.1.1

R0 (Indirect Address Register) .........................................................................

5

 

 

6.1.2

R1 (Time Clock /Counter)..................................................................................

5

 

 

6.1.3

R2 (Program Counter) and Stack ......................................................................

5

 

 

 

6.1.3.1 Data Memory Configuration................................................................

7

 

 

6.1.4

R3 (Status Register) ..........................................................................................

8

 

 

6.1.5

R4 (RAM Select Register) .................................................................................

8

 

 

6.1.6

R5 ~ R6 (Port 5 ~ Port 6) ..................................................................................

9

 

 

6.1.7

R7 (Port 7).........................................................................................................

9

 

 

6.1.8

R8 (AISR: ADC Input Select Register).............................................................

10

 

 

6.1.9

R9 (ADCON: ADC Control Register) ...............................................................

11

 

 

6.1.10

RA (ADOC: ADC Offset Calibration Register)..................................................

12

 

 

6.1.11

RB (ADDATA: Converted Value of ADC) .........................................................

12

 

 

6.1.12

RC (ADDATA1H: Converted Value of ADC).....................................................

13

 

 

6.1.13

RD (ADDATA1L: Converted Value of ADC) .....................................................

13

 

 

6.1.14

RE (Interrupt Status 2 & Wake-up Control Register)........................................

13

 

 

6.1.15

RF (Interrupt Status 2 Register).......................................................................

14

 

 

6.1.16

R10 ~ R3F.......................................................................................................

14

 

6.2

Special Purpose Registers ...............................................................................

15

 

 

6.2.1

A (Accumulator)...............................................................................................

15

 

 

6.2.2

CONT (Control Register) .................................................................................

15

 

 

6.2.3

IOC50 ~ IOC70 (I/O Port Control Register) .....................................................

16

 

 

6.2.4

IOC80 (Comparator and TCCA Control Register)............................................

16

 

 

6.2.5

IOC90 (TCCB and TCCC Control Register) ....................................................

17

 

 

6.2.6

IOCA0 (IR and TCCC Scale Control Register) ................................................

18

 

 

6.2.7

IOCB0 (Pull-down Control Register)................................................................

20

 

 

6.2.8

IOCC0 (Open-Drain Control Register).............................................................

20

 

 

6.2.9

IOCD0 (Pull-high Control Register) .................................................................

21

 

 

6.2.10

IOCE0 (WDT Control & Interrupt Mask Registers 2)........................................

21

 

 

6.2.11

IOCF0 (Interrupt Mask Register) .....................................................................

22

 

 

6.2.12

IOC51 (TCCA Counter) ...................................................................................

23

 

 

Product Specification (V1.2) 05.18.2007

iii

Contents

 

6.2.13

IOC61 (TCCB Counter) ...................................................................................

23

 

6.2.14

IOC71 (TCCBH/MSB Counter)........................................................................

24

 

6.2.15

IOC81 (TCCC Counter)...................................................................................

24

 

6.2.16

IOC91 (Low Time Register).............................................................................

25

 

6.2.17

IOCA1 (High Time Register)............................................................................

25

 

6.2.18

IOCB1 High/Low Time Scale Control Register) ...............................................

25

 

6.2.19

IOCC1 (TCC Prescaler Counter).....................................................................

26

6.3

TCC/WDT and Prescaler..................................................................................

27

6.4

I/O Ports ...........................................................................................................

 

28

 

6.4.1

Usage of Port 5 Input Change Wake-up/Interrupt Function .............................

31

6.5

Reset and Wake-up..........................................................................................

31

 

6.5.1

Reset and Wake-up Operation ........................................................................

31

 

 

6.5.1.1 Wake-Up and Interrupt Modes Operation Summary .........................

34

 

 

6.5.1.2 Register Initial Values after Reset.....................................................

36

 

 

6.5.1.3 Controller Reset Block Diagram........................................................

40

 

6.5.2

The T and P Status under STATUS (R3) Register ...........................................

41

6.6

Interrupt ............................................................................................................

 

41

6.7

Analog-To-Digital Converter (ADC) ..................................................................

44

 

6.7.1

ADC Control Register (AISR/R8, ADCON/R9, ADOC/RA)...............................

44

 

 

6.7.1.1 R8 (AISR: ADC Input Select Register)..............................................

44

 

 

6.7.1.2 R9 (ADCON: AD Control Register) ...................................................

45

 

 

6.7.1.3 RA (ADOC: AD Offset Calibration Register)......................................

46

 

6.7.2

ADC Data Register (ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD)..............

47

 

6.7.3

ADC Sampling Time........................................................................................

47

 

6.7.4

AD Conversion Time .......................................................................................

47

 

6.7.5

ADC Operation during Sleep Mode .................................................................

47

 

6.7.6

Programming Process/Considerations ............................................................

48

 

 

6.7.6.1

Programming Process ......................................................................

48

 

 

6.7.6.2

Sample Demo Programs ..................................................................

49

6.8 Infrared Remote Control Application/PWM Waveform Generation...................

51

 

6.8.1

Overview .........................................................................................................

51

 

6.8.2

Function Description........................................................................................

52

 

6.8.3

Programming the Related Registers................................................................

54

6.9

Timer/Counter...................................................................................................

 

55

 

6.9.1

Overview .........................................................................................................

55

 

6.9.2

Function Description........................................................................................

55

 

6.9.3

Programming the Related Registers................................................................

57

6.10

Comparator .....................................................................................................

 

57

 

6.10.1

External Reference Signal...............................................................................

58

 

6.10.2

Comparator Output..........................................................................................

58

 

6.10.3 Using a Comparator as an Operation Amplifier ...............................................

59

 

6.10.4

Comparator Interrupt .......................................................................................

59

 

6.10.5

Wake-up from Sleep Mode..............................................................................

59

iv

Product Specification (V1.2) 05.18.2007

 

 

 

 

Contents

 

6.11

Oscillator .........................................................................................................

60

 

 

6.11.1

Oscillator Modes .............................................................................................

60

 

 

6.11.2

Crystal Oscillator/Ceramic Resonators (Crystal) .............................................

61

 

 

6.11.3

External RC Oscillator Mode ...........................................................................

62

 

 

6.11.4

Internal RC Oscillator Mode ............................................................................

63

 

6.12

Power-on Considerations ................................................................................

64

 

 

6.12.1

Programmable WDT Time-out Period..............................................................

64

 

 

6.12.2 External Power-on Reset Circuit .....................................................................

64

 

 

6.12.3

Residual Voltage Protection ............................................................................

65

 

6.13

Code Option ....................................................................................................

66

 

 

6.13.1

Code Option Register (Word 0) .......................................................................

66

 

 

6.13.2

Code Option Register (Word 1) .......................................................................

67

 

 

6.13.3

Customer ID Register (Word 2) .......................................................................

68

 

6.14

Instruction Set .................................................................................................

68

7

Absolute Maximum Ratings ...................................................................................

70

8

DC Electrical Characteristics .................................................................................

71

 

8.1

AD Converter Characteristics...........................................................................

73

 

8.2

Comparator (OP) Characteristics .....................................................................

74

 

8.3

Device Characteristics......................................................................................

74

9

AC Electrical Characteristic ...................................................................................

75

10

Timing Diagrams .....................................................................................................

76

APPENDIX

A

Package Types Summary .......................................................................................

77

B

Packaging Configurations......................................................................................

77

 

B.1

18-Lead Plastic Dual in line (PDIP) — 300 mil.................................................

77

 

B.2

18-Lead Plastic Small Outline (SOP) — 300 mil ..............................................

78

 

B.3

20-Lead Plastic Shrink Small Outline (SSOP) — 209 mil ................................

79

 

B.4

20-Lead Plastic Dual-in-line (PDIP) — 300 mil ................................................

80

 

B.5

20-Lead Plastic Small Outline (SOP) — 300 mil ..............................................

81

C

Quality Assurance and Reliability .........................................................................

82

 

C.1

Address Trap Detect.........................................................................................

82

Product Specification (V1.2) 05.18.2007

v

Contents

Specification Revision History

Doc. Version

 

 

Revision Description

 

Date

1.0

 

Initial official version

2005/06/16

 

 

 

 

1.1

 

Added the IRC drift rate in the feature

2006/05/29

 

 

 

 

 

 

 

 

1.

Improved the contents and format of the Features

 

 

 

 

 

section, Fig.4-1 EM78P259N/260N Functional Block

 

 

 

 

 

Diagram, Fig.6-2 TCC and WDT Block Diagram and

 

 

 

 

 

Fig.6-11 IR/PWM System Block Diagram.

 

 

 

 

2.

Modified Section 6.7 Analog-to-Digital Converter( ADC)

 

 

1.2

 

3.

Modified Section 6.13.1 Code Option Register (Word 0)

2007/05/18

 

 

 

and Section 6.13.2 Code Option Register (Word 1)

 

 

 

 

4.

Added Internal RC Electrical Characteristics

 

 

 

 

5.

Modified Section 8.1 AD Converter Characteristics,

 

 

 

 

 

Section 8.2 Comparator (OP) Characteristics and

 

 

 

 

 

Appendix A. Package Type.

 

 

 

 

 

 

 

 

vi

Product Specification (V1.2) 05.18.2007

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

1 General Description

The EM78P259N and EM78P260N are 8-bit microprocessors designed and developed with low-power and high-speed CMOS technology. The series has an on-chip 2K×13-bit Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides a protection bit to prevent intrusion of user’s code. Three Code option words are also available to meet user’s requirements.

With its enhanced OTP-ROM feature, the EM78P259N and EM78P260N provide a convenient way of developing and verifying user’s programs. Moreover, this OTP device offers the advantages of easy and effective program updates, using development and programming tools. User can avail of the ELAN Writer to easily program his development code.

2Features

CPU configuration

2K×13 bits on-chip ROM

80×8 bits on-chip registers (SRAM)

8-level stacks for subroutine nesting

Less than 1.9 mA at 5V/4MHz

Typically 15 μA, at 3V/32kHz

Typically 1 μA, during Sleep mode

I/O port configuration

3 bidirectional I/O ports : P5, P6, P7

17 I/O pins

Wake-up port : P5

8 Programmable pull-down I/O pins

8 programmable pull-high I/O pins

8 programmable open-drain I/O pins

External interrupt : P60

Operating voltage range

Operating voltage: 2.3V~5.5V (Commercial)

Operating voltage: 2.5V~5.5V (Industrial)

Operating temperature range

Operating temperature: 0°C ~70°C (Commercial)

Operating temperature: -40°C ~85°C (Industrial)

Operating frequency range

Crystal mode:

DC~20MHz/2clks @ 5V, DC~100ns inst. cycle @ 5V DC~8MHz/2clks @ 3V, DC~250ns inst. cycle @ 3V

ERC mode:

DC~16MHz/2clks @ 5V, DC~125ns inst. cycle @ 5V DC~8MHz/2clks @ 3V, DC~250ns inst. cycle @ 3V

IRC mode:

Oscillation mode : 4MHz, 8MHz, 1MHz, 455kHz

Internal RC

 

 

 

Drift Rate

 

 

 

 

 

Temperature

 

Voltage

 

 

 

 

Frequency

 

 

 

Process

 

Total

 

 

(-40°C+85°C)

 

(2.3V~5.5V)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4MHz

 

±10%

 

±5%

 

±4%

 

±19%

8MHz

 

±10%

 

±6%

 

±4%

 

±20%

1MHz

 

±10%

 

±5%

 

±4%

 

±19%

455MHz

 

±10%

 

±5%

 

±4%

 

±19%

All these four main frequencies can be trimmed by programming with four calibrated bits in the ICE259N Simulator. OTP is auto trimmed by ELAN Writer.

Peripheral configuration

8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt

8-bit real time clock/counter (TCCA, TCCC) and

16-bit real time clock/counter (TCCB) with selective signal sources, trigger edges, and overflow interrupt

4-bit channel Analog-to-Digital Converter with 12-bit resolution in Vref mode

Easily implemented IR (Infrared remote control) application circuit

One pair of comparators or OP

Six available interrupts:

TCC, TCCA, TCCB, TCCC overflow interrupt

Input-port status changed interrupt (wake-up from sleep mode)

External interrupt

ADC completion interrupt

Comparators status change interrupt

IR/PWM interrupt

Special features

Programmable free running watchdog timer (4.5ms:18ms)

Power saving Sleep mode

Selectable Oscillation mode

Power-on voltage detector (2.0V ± 0.1V)

Package type:

18-pin DIP 300mil : EM78P259NPS/NPJ

18-pin SOP 300mil : EM78P259NMS/NMJ

20-pin SOP 300mil : EM78P260NPS/NPJ

20-pin SOP 300mil : EM78P260NMS/NMJ

20-pin SSOP 209mil : EM78P260NKMS/NKMJ

Product Specification (V1.2) 05.18.2007

1

(This specification is subject to change without further notice)

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

3Pin Assignment

(1)18-Pin DIP/SOP

P52/ADC2

 

1

 

 

18

 

 

P51/ADC1

 

 

 

 

P53/ADC3

 

2

 

 

17

 

 

P50/ADC0

 

 

 

 

P54/TCC/VREF

 

3

EM78P259NM

EM78P259NP

16

 

 

P55/OSCI

 

 

/RESET

 

4

15

 

 

P70/OSCO

 

 

 

 

 

Vss

 

5

 

 

14

 

 

VDD

 

 

 

 

P60//INT

 

6

 

 

13

 

 

P67/IR OUT

 

 

 

 

P61/TCCA

 

7

 

 

12

 

 

P66/CIN-

 

 

 

 

P62/TCCB

 

8

 

 

11

 

 

P65/CIN+

 

 

 

 

P63/TCCC

 

9

 

 

10

 

 

P64/CO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Fig. 3-1 EM78P259NP/M

4 Block Diagram

(2) 20-Pin DIP/SOP/SSOP

P56

 

1

 

20

 

P57

 

 

 

P52/ADC2

 

2

 

19

 

P51/ADC1

 

 

 

P53/ADC3

 

3

 

18

 

P50/ADC0

 

 

 

P54/TCC/VREF

 

4

EM78P260N

17

 

P55/OSCI

 

 

/RESET

 

5

16

 

P70/OSCO

 

 

Vss

 

6

 

15

 

VDD

 

 

 

P60//INT

 

7

 

14

 

P67/IR OUT

 

 

 

P61/TCCA

 

8

 

13

 

P66/CIN-

 

 

 

 

 

9

 

12

 

 

P62/TCCB

 

 

 

P65/CIN+

P63/TCCC

 

10

 

11

 

P64/CO

 

 

 

 

 

 

 

 

 

 

Fig. 3-2 EM78P260NP/M/KM

 

 

PC

Ext.

Int.

Ext.

Start-up

 

 

ROM

timer

 

 

OSC.

RC

RC

 

 

 

 

 

 

 

 

 

 

 

 

WDT

 

 

 

 

Oscillation

TCCA

TCCA

 

Instruction

8-level stack

 

 

Generation

 

TCCB

P7

Register

(13 bit)

TCCB

 

 

 

 

P70

 

 

 

 

 

TCCC

TCCC

 

 

 

 

Reset

 

 

 

Instruction

 

 

 

Infrared

 

 

 

 

 

 

IR out

 

Decoder

 

 

 

 

remote

 

 

 

 

 

 

control

 

P6

 

 

 

 

 

circuit

 

 

 

 

 

 

 

TCC

P60

 

 

Mux

 

TCC

 

 

 

 

 

 

 

 

 

 

P61

 

 

 

 

ALU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P62

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P63

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P64

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P65

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R4

 

 

 

 

 

 

 

 

 

 

 

 

 

P66

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P67

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P5

 

 

 

 

 

R3 (Status

 

Interrupt

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ACC

 

 

control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reg.)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P50

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P51

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P52

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P53

 

 

 

 

 

 

 

 

 

 

 

Interrupt

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P54

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

circuit

 

 

 

 

 

 

 

 

 

 

ADC

 

Comparator

 

P55

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(CO) or OP

 

P56

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P57

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ext INT Ain0~3 Cin+ CinCO

 

Fig. 4-1 EM78P259N/260N Functional Block Diagram

 

 

2

Product Specification (V1.2) 05.18.2007

 

(This specification is subject to change without further notice)

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

5Pin Description

5.1EM78P259NP/M

Symbol

Pin No.

Type

Function

 

 

 

 

 

 

 

 

P70

15

I/O

General purpose input/output pin

Default value after a power-on reset

 

 

 

 

 

 

 

P60~P67

6~13

I/O

General purpose input/output pin

Open-drain

 

 

 

Default value after a power-on reset

 

 

 

General purpose input/output pin

P50~P55

1~3

I/O

Pull-high/pull-down

16~18

Default value after a power-on reset

 

 

 

 

 

Wake up from sleep mode when the status of the pin changes

 

 

 

“-“ : the input pin of Vinof the comparator

CIN-, CIN+

12, 11

I

“+” : the input pin of Vin+ of the comparator

CO

10

O

Pin CO is the comparator output

 

 

 

Defined by IOC80 <4:3>

 

 

 

 

OSCI

16

I

Crystal type: Crystal input terminal or external clock input pin

RC type: RC oscillator input pin

 

 

 

OSCO

15

I/O

Crystal type: Crystal input terminal or external clock input pin.

RC type: clock output with a duration of one instruction cycle

 

 

 

External clock signal input

 

 

 

If set as /RESET and remains at logic low, the device will be

/RESET

4

I

reset

Voltage on /RESET/Vpp must not exceed Vdd during normal

 

 

 

 

 

 

mode

 

 

 

 

 

 

 

External Counter input

TCC, TCCA,

3, 7,

I

TCC is defined by CONT <5>

TCCA is defined by IOC80 <1>

TCCB, TCCC

8, 9

 

TCCB is defined by IOC90 <5>

 

 

 

 

 

 

TCCC is defined by IOC90 <1>

ADC0~ADC3

1, 2,

I

Analog to Digital Converter

17, 18

Defined by ADCON (R9) <1:0>

 

 

IR OUT

13

O

IR mode output pin, capable of driving and sinking

current=20mA when the output voltage drops to 0.7Vdd and

 

 

 

rise to0.3Vdd at Vdd=5V.

VREF

3

I

External reference voltage for ADC

Defined by ADCON (R9) <7>

 

 

 

/INT

6

I

External interrupt pin triggered by a falling or rising edge

Defined by CONT <7>

 

 

 

VDD

14

Power supply

VSS

5

Ground

Product Specification (V1.2) 05.18.2007

3

(This specification is subject to change without further notice)

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

5.2 EM78P260NP/M/KM

Symbol

Pin No.

Type

Function

 

 

 

 

 

 

 

 

P70

16

I/O

General purpose input/output pin

Default value after a power-on reset

 

 

 

 

 

 

 

P60~P67

7~14

I/O

General purpose input/output pin

Open-drain

 

 

 

Default value after a power-on reset

 

 

 

General purpose input/output pin

P50~P57

1~4

I/O

Pull-high/pull-down

17~20

Default value after a power-on reset

 

 

 

 

 

Wake up from sleep mode when the status of the pin changes

 

 

 

“-“ : the input pin of Vinof the comparator

CIN-, CIN+

13, 12

I

“+” : the input pin of Vin+ of the comparator

CO

11

O

Pin CO is the comparator output

 

 

 

Defined by IOC80 <4:3>

 

 

 

 

OSCI

17

I

Crystal type: Crystal input terminal or external clock input pin

RC type: RC oscillator input pin

 

 

 

OSCO

16

I/O

Crystal type: Crystal input terminal or external clock input pin.

RC type: clock output with a duration of one instruction cycle

 

 

 

External clock signal input

 

 

 

If set as /RESET and remains at logic low, the device will be

/RESET

5

I

reset

Voltage on /RESET/Vpp must not exceed Vdd during normal

 

 

 

 

 

 

mode

 

 

 

 

 

 

 

External Timer/Counter input

TCC, TCCA,

4, 8,

I

TCC is defined by CONT <5>

TCCA is defined by IOC80 <1>

TCCB, TCCC

9, 10

 

TCCB is defined by IOC90 <5>

 

 

 

 

 

 

TCCC is defined by IOC90 <1>

ADC0~ADC3

2, 3,

I

Analog to Digital Converter

18, 19

Defined by ADCON (R9) <1:0>

 

 

IR OUT

14

O

IR mode output pin, capable of driving and sinking

current=20mA when the output voltage drops to 0.7Vdd and

 

 

 

rise to0.3Vdd at Vdd=5V.

VREF

4

I

External reference voltage for ADC

Defined by ADCON (R9) <7>

 

 

 

/INT

7

I

External interrupt pin triggered by a falling or rising edge

Defined by CONT <7>

 

 

 

VDD

15

Power supply

VSS

6

Ground

4

Product Specification (V1.2) 05.18.2007

 

(This specification is subject to change without further notice)

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

6Function Description

6.1Operational Registers

6.1.1 R0 (Indirect Address Register)

R0 is not a physically implemented register. Its major function is to perform as an indirect address pointer. Any instruction using R0 as a pointer, actually accesses the data pointed by the RAM Select Register (R4).

6.1.2 R1 (Time Clock /Counter)

Increased by an external signal edge which is defined by the TE bit (CONT-4) through the TCC pin, or by the instruction cycle clock.

Writable and readable as any other registers

The TCC prescaler counter (IOCC1) is assigned to TCC

The contents of the IOCC1 register is cleared –

when a value is written to the TCC register.

when a value is written to the TCC prescaler bits (Bits 3, 2, 1, 0 of the CONT register)

during power-on reset, /RESET, or WDT time out reset.

6.1.3 R2 (Program Counter) and Stack

R3

 

 

 

 

 

 

 

A10

A9 A8

A7

~

A0

Reset Vector

000H

 

 

003H

 

 

 

CALL

 

 

Hardware Interrupt Vector

~

 

 

 

 

 

 

01EH

 

 

 

RET

 

 

 

User

 

 

 

 

 

 

 

 

RETL

 

 

 

 

 

 

RETI

 

 

 

 

Memory

00 PAGE0 0000~03FF

Stack Level 1

On-chip Program

3FEH

01 PAGE1 0400~07FF

Stack Level 2

Memory

 

Space

 

 

 

Stack Level 3

 

 

 

 

 

 

 

 

 

Stack Level 4

 

 

 

 

 

 

 

 

 

 

 

Stack Level 5

 

 

 

 

 

 

Stack Level 6

 

 

 

 

 

 

Stack Level 7

 

 

 

 

 

 

Stack Level 8

 

7FFH

 

Fig. 6-1 Program Counter Organization

R2 and hardware stacks are 12-bit wide. The structure is depicted in the table under Section 6.1.3.1, Data Memory Configuration (subsequent page).

Generates 2K×13 bits on-chip ROM addresses to the relative programming instruction codes. One program page is 1024 words long.

The contents of R2 are all set to "0"s when a reset condition occurs.

Product Specification (V1.2) 05.18.2007

5

(This specification is subject to change without further notice)

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to jump to any location within a page.

"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page.

"RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top of stack.

"ADD R2, A" allows a relative address to be added to the current PC, and the ninth and above bits of the PC will increase progressively.

"MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits of the PC, and the ninth and tenth bits (A8 ~ A9) of the PC will remain unchanged.

Any instruction (except “ADD R2,A”) that is written to R2 (e.g., "MOV R2, A", "BC R2, 6", etc.) will cause the ninth bit and the tenth bit (A8 ~ A9) of the PC to remain unchanged.

In the case of EM78P259N/260N, the most significant bit (A10) will be loaded with the content of PS0 in the status register (R3) upon execution of a "JMP", "CALL", or any other instructions set which write to R2.

All instructions are single instruction cycle (fclk/2 or fclk/4) except for the instructions that are written to R2. Note that these instructions need one or two instructions cycle as determined by Code Option Register CYES bit.

6

Product Specification (V1.2) 05.18.2007

 

(This specification is subject to change without further notice)

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

6.1.3.1Data Memory Configuration

Address

 

R PAGE registers

IOCX0 PAGE registers

IOCX1 PAGE registers

00

R0

(Indirect Addressing Register)

 

Reserve

 

Reserve

01

R1

(Time Clock Counter)

CONT

(Control Register)

 

Reserve

02

R2

(Program Counter)

 

Reserve

 

Reserve

03

R3

(Status Register)

 

Reserve

 

Reserve

04

R4

(RAM Select Register)

 

Reserve

 

Reserve

05

R5

(Port 5)

 

IOC50 (I/O Port Control Register)

IOC51

(TCCA Counter)

06

R6

(Port 6)

 

IOC60 (I/O Port Control Register)

IOC61

(TCCB LSB Counter)

07

R7

(Port 7)

 

IOC70 (I/O Port Control Register)

IOC71

(TCCB HSB Counter)

08

R8

(ADC Input Select Register

IOC80

(Comparator and TCCA

IOC81

(TCCC Counter)

 

 

 

 

 

Control Register)

 

 

09

R9

(ADC Control Register)

IOC90

(TCCB and TCCC

IOC91

(Low Time Register)

 

 

 

 

 

Control Register)

 

 

0A

RA

(ADC Offset Calibration

IOCA0

(IR and TCCC Scale

IOCA1

(High Time Register)

Register)

 

Control Register)

0B

RB

(The converted value

IOCB0

(Pull-down Control

IOCB1

(High Time and Low Time

 

 

AD11~AD4 of ADC)

 

Register)

 

Scale control Register)

0C

RC

(The converted value

IOCC0

(Open-drain Control

IOCC1

(TCC Prescaler Control)

AD11~AD8 of ADC)

Register)

 

0D

RD

(The converted value

IOCD0 (Pull-high Control Register)

 

Reserve

AD7~AD0 of ADC)

 

 

 

 

(WDT Control Register and

 

 

0E

RE

(Interrupt Status 2 and

IOCE0

 

Reserve

 

 

Wake-up Control Register

 

Interrupt Mask Register 2)

 

 

0F

RF (Interrupt Status Register 1)

IOCF0 (Interrupt Mask Register 1)

 

Reserve

10

 

 

 

 

 

 

 

 

 

General

Registers

 

 

 

 

1F

 

 

 

 

 

 

 

20

 

Bank 0

Bank 1

 

 

 

 

 

 

 

 

 

 

3F

 

 

 

 

 

 

 

Product Specification (V1.2) 05.18.2007

7

(This specification is subject to change without further notice)

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

6.1.4 R3 (Status Register)

Bit 7

 

Bit 6

 

 

Bit 5

Bit 4

 

Bit 3

 

Bit 2

 

Bit 1

Bit 0

 

 

 

 

 

 

RST

 

IOCS

 

 

PS0

T

 

P

 

Z

 

DC

C

Bit 7 (RST): Bit of reset type

 

 

 

 

 

 

 

 

 

 

 

 

Set to “1” if wake-up from sleep on pin change, comparator status

 

 

 

change, or AD conversion completed. Set to “0” if wake-up from other

 

 

 

reset types

 

 

 

 

 

 

 

 

 

Bit 6 (IOCS): Select the Segment of IO control register

 

 

 

 

 

 

 

 

0 = Segment 0 (IOC50 ~ IOCF0) selected

 

 

 

 

 

 

 

 

1 = Segment 1 (IOC51 ~ IOCC1) selected

 

 

 

 

 

Bit 5 (PS0): Page select bits. PS0 is used to select a program memory page. When

 

 

 

executing a "JMP," "CALL," or other instructions which cause the

 

 

 

program counter to change (e.g., MOV R2, A), PS0 is loaded into the

 

 

 

11th bit of the program counter where it selects one of the available

 

 

 

program memory pages. Note that RET (RETL, RETI) instruction does

 

 

 

not change the PS0 bit. That is, the return address will always be back

 

 

 

to the page from where the subroutine was called, regardless of the

 

 

 

current PS0 bit setting.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PS0

 

 

Program Memory Page [Address]

 

 

 

 

 

 

0

 

 

 

 

Page 0 [000-3FF]

 

 

 

 

 

 

 

 

1

 

 

 

 

Page 1 [400-7FF]

 

 

 

 

 

Bit 4 (T):

 

Time-out bit. Set to “1” by the "SLEP" and "WDTC" commands or during

 

 

 

power on; and reset to “0” by WDT time-out (see Section 6.5.2, The T

 

 

 

and P Status under STATUS Register for more details).

 

Bit 3 (P):

 

Power-down bit. Set to “1” during power-on or by a "WDTC" command

 

 

 

and reset to “0” by a "SLEP" command (see Section 6.5.2, The T and P

 

 

 

Status under STATUS Register for more details).

 

 

 

Bit 2 (Z):

 

Zero flag. Set to "1" if the result of an arithmetic or logic operation is

 

 

 

zero.

 

 

 

 

 

 

 

 

 

 

Bit 1 (DC):

 

Auxiliary carry flag

 

 

 

 

 

 

 

 

Bit 0 (C):

 

Carry flag

 

 

 

 

 

 

 

 

 

 

6.1.5 R4 (RAM Select Register)

Bit 7:

Set to “0” all the time

Bit 6:

Used to select Bank 0 or Bank 1 of the register

Bits 5~0:

Used to select a register (Address: 00~0F, 10~3F) in indirect addressing

 

mode

See the table under Section 6.1.3.1, Data Memory Configuration for data memory

configuration.

 

 

 

8

Product Specification (V1.2) 05.18.2007

 

(This specification is subject to change without further notice)

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

6.1.6 R5 ~ R6 (Port 5 ~ Port 6)

R5 & R6 are I/O registers

The upper 2 bits of R5 are fixed to “0” (if EM78P259N is selected).

Only the lower 6 bits of R5 are available (this applies to EM78P259N only as EM78P260N can use all the bits)

6.1.7 R7 (Port 7)

Bit

7

6

5

4

 

3

2

1

0

EM78P259N/260N

‘0’

‘0’

‘0’

‘0’

 

‘0’

‘0’

‘0’

I/O

 

 

 

 

 

 

 

 

 

 

ICE259N

C3

C2

C1

C0

 

RCM1

RCM0

‘0’

I/O

 

 

 

 

 

 

 

 

 

 

Note: R7 is an I/O register

For EM78P259N/260N, only the lower 1 bit of R7 is available.

Bit 7 ~ Bit 2:

[With EM78P259N/260N]: Unimplemented, read as ‘0’.

[With Simulator (C3~C0, RCM1, & RCM0)]: are IRC calibration bits in IRC oscillator mode. Under IRC oscillator mode of ICE259N simulator, these are the IRC mode selection bits and IRC calibration bits.

Bit 7 ~ Bit 4 (C3 ~ C0): Calibrator of internal RC mode

C3

C2

C1

C0

Frequency (MHz)

 

 

 

 

 

0

0

0

0

(1-36%) x F

0

0

0

1

(1-31.5%) x F

0

0

1

0

(1-27%) x F

0

0

1

1

(1-22.5%) x F

0

1

0

0

(1-18%) x F

0

1

0

1

(1-13.5%) x F

0

1

1

0

(1-9%) x F

0

1

1

1

(1-4.5%) x F

1

1

1

1

F (default)

1

1

1

0

(1+4.5%) x F

1

1

0

1

(1+9%) x F

1

1

0

0

(1+135%) x F

1

0

1

1

(1+18%) x F

1

0

1

0

(1+22.5%) x F

1

0

0

1

(1+27%) x F

1

0

0

0

(1+31.5%) x F

1.Frequency values shown are theoretical and taken at an instance of a high frequency mode. Hence, frequency values are shown for reference only. Definite values depend on the actual process.

2.Similar way of calculation is also applicable to low frequency mode.

Product Specification (V1.2) 05.18.2007

9

(This specification is subject to change without further notice)

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

Bit 3 & Bit 2 (RCM1, RCM0): IRC mode selection bits

RCM 1

 

RCM 0

 

Frequency (MHz)

 

 

 

 

 

 

 

1

1

 

4 (default)

1

0

8

0

1

1

0

0

 

455kHz

6.1.8 R8 (AISR: ADC Input Select Register)

The AISR register individually defines the pins of Port 5 as analog input or as digital I/O.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

 

 

 

 

 

 

 

 

 

 

 

 

ADE3

ADE2

ADE1

ADE0

 

 

 

 

 

 

 

 

 

Bit 7 ~ Bit 4:

Not used

 

 

 

 

 

Bit 3 (ADE3): AD converter enable bit of P53 pin

 

 

 

 

 

0

= Disable ADC3, P53 functions as I/O pin

 

 

 

 

1

= Enable ADC3 to function as analog input pin

 

 

Bit 2 (ADE2): AD converter enable bit of P52 pin

 

 

 

 

 

0

= Disable ADC2, P52 functions as I/O pin

 

 

 

 

1

= Enable ADC2 to function as analog input pin

 

 

Bit 1 (ADE1): AD converter enable bit of P51 pin

 

 

 

 

 

0

= Disable ADC1, P51 functions as I/O pin

 

 

 

 

1

= Enable ADC1 to function as analog input pin

 

 

Bit 0 (ADE0): AD converter enable bit of P50 pin.

 

 

 

 

 

0

= Disable ADC0, P50 functions as I/O pin

 

 

 

 

1

= Enable ADC0 to function as analog input pin

 

 

10

Product Specification (V1.2) 05.18.2007

 

(This specification is subject to change without further notice)

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

6.1.9 R9 (ADCON: ADC Control Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit

2

Bit 1

Bit 0

VREFS

CKR1

CKR0

ADRUN

ADPD

 

ADIS1

ADIS0

 

 

 

 

 

 

 

 

 

Bit 7 (VREFS): Input source of the Vref of the ADC

0 = The Vref of the ADC is connected to Vdd (default value), and the P54/VREF pin carries out the function of P54

1 = The Vref of the ADC is connected to P54/VREF

NOTE

The P54/TCC/VREF pin cannot be applied to TCC and VREF at the same time. If P54/TCC/VREF functions as VREF analog input pin, then CONT Bit 5 “TS” must be “0.”

The P54/TCC/VREF pin priority is as follows:

P53/TCC/VREF Pin Priority

High

 

Medium

 

Low

VREF

 

TCC

 

P54

 

 

 

 

 

Bit 6 & Bit 5 (CKR1 & CKR0): Prescaler of oscillator clock rate of ADC 00 = 1: 16 (default value)

01 = 1: 4

10 = 1: 64

11 = 1: WDT ring oscillator frequency

CKR1:CKR0

 

Operation Mode

 

Max. Operation Frequency

00

 

Fosc/16

 

4 MHz

 

 

 

 

 

01

 

Fosc/4

 

1 MHz

 

 

 

 

 

10

 

Fosc/64

 

16 MHz

 

 

 

 

 

11

 

Internal RC

 

 

 

 

 

 

Bit 4 (ADRUN): ADC starts to RUN.

 

 

0

= Reset upon completion of the conversion. This bit cannot be

 

 

 

reset through software

 

 

1

= AD conversion is started. This bit can be set by software.

 

Bit 3 (ADPD):

ADC Power-down mode

 

 

0 = Switch off the resistor reference to conserve power even while the

 

 

CPU is operating

 

 

1

= ADC is operating

 

Bit 2:

Not used

 

 

 

Product Specification (V1.2) 05.18.2007

11

(This specification is subject to change without further notice)

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

Bit 1 ~ Bit 0 (ADIS1 ~ADIS0): Analog Input Select

00 = ADIN0/P50

01 = ADIN1/P51

10= ADIN2/P52

11= ADIN3/P53

These bits can only be changed when the ADIF bit (see Section 6.1.14, RE (Interrupt Status 2 & Wake-up Control Register)) and the ADRUN bit are both LOW.

6.1.10 RA (ADOC: ADC Offset Calibration Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CALI

SIGN

VOF[2]

VOF[1]

VOF[0]

“0”

“0”

“0”

Bit 7 (CALI): Calibration enable bit for ADC offset 0 = Calibration disable

1 = Calibration enable

Bit 6 (SIGN): Polarity bit of offset voltage 0 = Negative voltage

1 = Positive voltage

Bit 5 ~ Bit 3 (VOF[2] ~ VOF[0]): Offset voltage bits

VOF[2]

VOF[1]

VOF[0]

EM78P259N/260N

ICE259N

 

 

 

 

 

0

0

0

0LSB

0LSB

0

0

1

2LSB

1LSB

0

1

0

4LSB

2LSB

0

1

1

6LSB

3LSB

1

0

0

8LSB

4LSB

1

0

1

10LSB

5LSB

1

1

0

12LSB

6LSB

1

1

1

14LSB

7LSB

Bit 2 ~ Bit 0: Unimplemented, read as ‘0’

6.1.11 RB (ADDATA: Converted Value of ADC)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

AD11

AD10

AD9

AD8

AD7

AD6

AD5

AD4

 

 

 

 

 

 

 

 

When AD conversion is completed, the result is loaded into the ADDATA. The ADRUN bit is cleared, and the ADIF (see Section 6.1.14, RE (Interrupt Status 2 & Wake-up Control Register)) is set.

RB is read only.

12

Product Specification (V1.2) 05.18.2007

 

(This specification is subject to change without further notice)

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

6.1.12 RC (ADDATA1H: Converted Value of ADC)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

“0”

“0”

“0”

“0”

AD11

AD10

AD9

AD8

 

 

 

 

 

 

 

 

When AD conversion is completed, the result is loaded into the ADDATA1H. The ADRUN bit is cleared, and the ADIF (see Section 6.1.14, RE (Interrupt Status 2 & Wake-up Control Register)) is set.

RC is read only

6.1.13 RD (ADDATA1L: Converted Value of ADC)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

 

 

 

 

 

 

 

 

When AD conversion is completed, the result is loaded into the ADDATA1L. The ADRUN bit is cleared, and the ADIF (see Section 6.1.14, RE (Interrupt Status 2 & Wake-up Control Register)) is set.

RD is read only

6.1.14 RE (Interrupt Status 2 & Wake-up Control Register)

Bit 7

 

Bit 6

Bit 5

 

Bit 4

Bit 3

Bit 2

Bit 1

 

Bit 0

 

 

 

 

ADIF

 

CMPIF

ADWE

CMPWE

ICWE

 

-

 

 

 

 

 

 

 

 

 

Note: RE <5, 4> can be cleared by instruction but cannot be set

 

 

 

 

 

IOCE0 is the interrupt mask register

 

 

 

 

 

 

 

Reading RE will result to "logic AND" of RE and IOCE0

 

 

 

 

Bit 7

& Bit 6:

Not used

 

 

 

 

 

 

Bit 5

(ADIF):

Interrupt flag for analog to digital conversion. Set when AD

 

 

 

 

conversion is completed. Reset by software

 

 

 

0 = no interrupt occurs

1 = with interrupt request

Bit 4 (CMPIF): Comparator interrupt flag. Set when a change occurs in the output of Comparator. Reset by software.

0 = no interrupt occurs

1 = with interrupt request Bit 3 (ADWE): ADC wake-up enable bit 0 = Disable ADC wake-up 1 = Enable ADC wake-up

When AD Conversion enters sleep mode, this bit must be set to “Enable“.

Product Specification (V1.2) 05.18.2007

13

(This specification is subject to change without further notice)

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

Bit 2 (CMPWE): Comparator wake-up enable bit 0 = Disable Comparator wake-up 1 = Enable Comparator wake-up

When Comparator enters sleep mode, this bit must be set to “Enable.“

Bit 1 (ICWE): Port 5 input change to wake-up status enable bit 0 = Disable Port 5 input change to wake-up status 1 = Enable Port 5 input change to wake-up status

When Port 5 change enters sleep mode, this bit must be set to “Enable“.

Bit 0: Not implemented, read as ‘0’

6.1.15 RF (Interrupt Status 2 Register)

Bit 7

Bit 6

Bit 5

 

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

 

LPWTIF

HPWTIF

TCCCIF

 

TCCBIF

TCCAIF

EXIF

ICIF

TCIF

 

 

 

 

 

 

 

 

 

Note: “ 1 ” means with interrupt request

 

“ 0 ” means no interrupt occurs

 

RF can be cleared by instruction but cannot be set.

 

 

 

IOCF0 is the relative interrupt mask register.

 

 

 

 

Reading RF will result to "logic AND" of RF and IOCF0.

 

 

 

Bit 7 (LPWTIF): Internal low-pulse width timer underflow interrupt flag for IR/PWM function. Reset by software.

Bit 6 (HPWTIF): Internal high-pulse width timer underflow interrupt flag for IR/PWM function. Reset by software.

Bit 5 (TCCCIF): TCCC overflow interrupt flag. Set when TCCC overflows. Reset by software.

Bit 4 (TCCBIF): TCCB overflow interrupt flag. Set when TCCC overflows. Reset by software.

Bit 3 (TCCAIF): TCCA overflow interrupt flag. Set when TCCC overflows. Reset by software.

Bit 2 (EXIF): External interrupt flag. Set by falling edge on /INT pin. Reset by software.

Bit 1 (ICIF): Port 5 input status change interrupt flag. Set when Port 5 input changes. Reset by software.

Bit 0 (TCIF): TCC overflow interrupt flag. Set when TCC overflows. Reset by software.

6.1.16 R10 ~ R3F

All of these are 8-bit general-purpose registers.

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Product Specification (V1.2) 05.18.2007

 

(This specification is subject to change without further notice)

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

6.2 Special Purpose Registers

6.2.1 A (Accumulator)

Internal data transfer operation, or instruction operand holding usually involves the temporary storage function of the Accumulator, which is not an addressable register.

6.2.2 CONT (Control Register)

Bit 7

 

Bit 6

 

Bit 5

 

Bit 4

 

Bit 3

 

Bit 2

 

Bit 1

 

Bit 0

 

 

 

 

 

 

 

INTE

 

INT

 

TS

 

TE

 

PSTE

 

PST2

 

PST1

 

PST0

 

 

 

 

 

 

 

 

 

 

 

 

Note: The CONT register is both readable and writable

 

 

 

 

 

 

 

Bit 6 is read only.

 

 

 

 

 

 

 

 

 

 

 

Bit 7 (INTE): INT signal edge

 

 

 

 

 

 

 

 

 

 

 

0

= interrupt occurs at the rising edge on the INT pin

 

 

 

 

 

1

= interrupt occurs at the falling edge on the INT pin

 

Bit 6 (INT):

Interrupt enable flag

 

 

 

 

 

 

 

 

 

 

 

0

= masked by DISI or hardware interrupt

 

 

 

 

 

 

 

1

= enabled by the ENI/RETI instructions

 

 

 

 

 

 

 

This bit is readable only.

 

 

 

 

 

 

 

Bit 5 (TS):

TCC signal source

 

 

 

 

 

 

 

 

 

 

 

0

= internal instruction cycle clock. P54 is bi-directional I/O pin.

 

 

 

1

= transition on the TCC pin

 

 

 

 

 

 

 

Bit 4 (TE):

TCC signal edge

 

 

 

 

 

 

 

 

 

 

 

0

= increment if the transition from low to high takes place on the TCC

 

 

 

pin

 

 

 

 

 

 

 

 

 

 

 

 

 

1

= increment if the transition from high to low takes place on the TCC

 

 

 

pin.

 

 

 

 

 

 

 

 

 

 

 

Bit 3 (PSTE): Prescaler enable bit for TCC

 

 

 

 

 

 

 

 

 

0

= prescaler disable bit. TCC rate is 1:1.

 

 

 

 

 

 

 

1

= prescaler enable bit. TCC rate is set as Bit 2 ~ Bit 0.

 

Product Specification (V1.2) 05.18.2007

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(This specification is subject to change without further notice)

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

Bit 2 ~ Bit 0 (PST2 ~ PST0): TCC prescaler bits

PST2

 

PST1

 

PST0

TCC Rate

0

 

0

 

0

1:2

0

 

0

 

1

1:4

0

 

1

 

0

1:8

0

 

1

 

1

1:16

1

 

0

 

0

1:32

1

 

0

 

1

1:64

1

 

1

 

0

1:128

1

 

1

 

1

1:256

 

 

 

 

 

 

Note: Tcc time-out period [1/Fosc x prescaler x 256 (Tcc cnt) x 1 (CLK=2)]

Tcc time-out period [1/Fosc x prescaler x 256 (Tcc cnt) x 2 (CLK=4)]

6.2.3 IOC50 ~ IOC70 (I/O Port Control Register)

"1" puts the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output.

Only the lower 6 bits of IOC50 can be defined (this applies to EM78P259N only, since EM78P260N can use all the bits).

Only the lower 1 bit of IOC70 can be defined, the other bits are not available.

IOC50, IOC60, and IOC70 registers are all readable and writable

6.2.4 IOC80 (Comparator and TCCA Control Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CMPOUT

COS1

COS0

TCCAEN

TCCATS

TCCATE

 

 

 

 

 

 

 

 

Note: Bits 4~0 of the IOC80 register are both readable and writable

Bit 5 of the IOC80 register is read only.

Bit 7 & Bit 6: Not used

Bit 5 (CMPOUT): Result of the comparator output

 

 

 

 

This bit is read only.

 

Bit 4 & Bit 3 (COS1 & COS0): Comparator/OP Select bits

 

 

 

 

 

 

 

 

COS1

 

COS0

 

Function Description

 

 

0

 

0

 

Comparator and OP are not used. P64, P65, and P66 function as

 

 

 

 

normal I/O pins.

 

 

 

 

 

 

 

 

0

 

1

 

Acts as Comparator and P64 functions as normal I/O pin

 

 

1

 

0

 

Acts as Comparator and P64 functions as Comparator output pin (CO)

 

 

1

 

1

 

Acts as OP and P64 functions as OP output pin (CO)

 

 

Bit 2 (TCCAEN):

TCCA enable bit

 

 

 

 

0 = disable TCCA

 

 

 

 

1 = enable TCCA as a counter

 

 

 

 

 

 

 

16

 

 

Product Specification (V1.2) 05.18.2007

 

 

 

 

 

(This specification is subject to change without further notice)

 

 

 

 

 

 

 

 

EM78P259N/260N

 

 

 

 

 

 

8-Bit Microprocessor with OTP ROM

Bit 1 (TCCATS):

TCCA signal source

 

 

 

 

 

 

 

0 =: internal instruction cycle clock. P61 is a bi-directional I/O pin.

 

 

1

= transit through the TCCA pin

 

 

 

 

Bit 0 (TCCATE):

TCCA signal edge

 

 

 

 

 

 

 

0

= increment if transition from low to high takes place on the

 

 

 

 

TCCA pin

 

 

 

 

 

 

 

1

= increment if transition from high to low takes place on the

 

 

 

 

TCCA pin

 

 

 

 

 

6.2.5 IOC90 (TCCB and TCCC Control Register)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit 7

Bit 6

 

 

Bit 5

Bit 4

Bit 3

Bit 2

 

Bit 1

Bit 0

TCCBHE

TCCBEN

 

 

TCCBTS

TCCBTE

TCCCEN

 

TCCCTS

TCCCTE

 

 

 

 

 

 

 

 

 

 

 

Bit 7 (TCCBHE): Control bit is used to enable the most significant byte of counter

0 = Disable the most significant byte of TCCBH (default value) TCCB is an 8-bit counter

1 = Enable the most significant byte of TCCBH TCCB is a 16-bit counter

Bit 6 (TCCBEN): TCCB enable bit

0 = disable TCCB

1 = enable TCCB as a counter

Bit 5 (TCCBTS) TCCB signal source

0 = internal instruction cycle clock. P62 is a bi-directional I/O pin. 1 = transit through the TCCB pin

Bit 4 (TCCBTE): TCCB signal edge

0 = increment if the transition from low to high takes place on the TCCB pin

1 = increment if the transition from high to low takes place on the TCCB pin

Bit 3:

Not used.

Bit 2

(TCCCEN): TCCC enable bit

 

 

0

= disable TCCC

 

 

1

= enable TCCC as a counter

Bit 1

(TCCCTS)

TCCC signal source

 

 

0

= internal instruction cycle clock. P63 is a bi-directional I/O pin.

 

 

1

= transit through the TCCC pin

Bit 0 (TCCCTE): TCCC signal edge

Product Specification (V1.2) 05.18.2007

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(This specification is subject to change without further notice)

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

0 = increment if the transition from low to high takes place on the TCCC pin

1 = increment if the transition from high to low takes place on the TCCC pin

6.2.6 IOCA0 (IR and TCCC Scale Control Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TCCCSE

TCCCS2

TCCCS1

TCCCS0

IRE

HF

LGP

IROUTE

 

 

 

 

 

 

 

 

Bit 7 (TCCCSE): Scale enable bit for TCCC

An 8-bit counter is provided as scaler for TCCC and IR-Mode. When in IR-Mode, TCCC counter scale uses the low time segments of the pulse generated by Fcarrier frequency modulation (see Fig. 6-11 in Section 6.8.2, Function Description).

0 = scale disable bit, TCCC rate is 1:1

1 = scale enable bit, TCCC rate is set as Bit 6 ~ Bit 4

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Product Specification (V1.2) 05.18.2007

 

(This specification is subject to change without further notice)

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

Bit 6 ~ Bit 4 (TCCCS2 ~ TCCCS0): TCCC scale bits

The TCCCS2 ~ TCCCS0 bits of the IOCA0 register are used to determine the scale ratio of TCCC as shown below:

TCCCS2

TCCCS1

TCCCS0

TCCC Rate

 

 

 

 

0

0

0

1:2

0

0

1

1:4

0

1

0

1:8

0

1

1

1:16

1

0

0

1:32

1

0

1

1:64

1

1

0

1:128

1

1

1

1:256

Bit 3 (IRE):

Infrared Remote Enable bit

 

0

= Disable IRE, i.e., disable H/W Modulator Function. IROUT pin

 

 

fixed to high level and the TCCC is an Up Counter.

 

1

= Enable IRE, i.e., enable H/W Modulator Function. Pin 67 is

 

 

defined as IROUT. If HP=1, the TCCC counter scale uses the

 

 

low time segments of the pulse generated by Fcarrier frequency

 

 

modulation (see Fig. 6-11 in Section 6.8.2, Function

 

 

Description). When HP=0, the TCCC is an Up Counter.

Bit 2 (HF):

High Frequency bit

 

0

= PWM application. IROUT waveform is achieved according to

 

 

high-pulse width timer and low-pulse width timer which

 

 

determines the high time width and low time width respectively

 

1

= IR application mode. The low time segments of the pulse

 

 

generated by Fcarrier frequency modulation (see Fig. 6-11 in

 

 

Section 6.8.2, Function Description)

Bit 1 (LGP):

Long Pulse.

 

0

= high time register and low time register is valid

 

1

= high time register is ignored. A single pulse is generated.

Bit 0 (IROUTE):

Control bit to define the P67 (IROUT) pin function

 

0

= P67 is defined as bi-directional I/O pin

 

1

= P67 is defined as IROUT. Under this condition, the I/O control

 

 

bit of P67 (Bit 7 of IOC60) must be set to “0”

Product Specification (V1.2) 05.18.2007

19

(This specification is subject to change without further notice)

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

6.2.7 IOCB0 (Pull-down Control Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

/PD57

/PD56

/PD55

/PD54

/PD53

/PD52

/PD51

/PD50

 

 

 

 

 

 

 

 

Note: The IOCB0 register is both readable and writable

Bit 7 (/PD57): Control bit used to enable the pull-down function of the P57 pin (applicable to EM78P260N only)

0= Enable internal pull-down

1= Disable internal pull-down

Bit 6 (/PD56): Control bit used to enable the pull-down function of the P56 pin (applicable to EM78P260N only)

Bit 5 (/PD55): Control bit used to enable the pull-down function of the P55 pin Bit 4 (/PD54): Control bit used to enable the pull-down function of the P54 pin Bit 3 (/PD53): Control bit used to enable the pull-down function of the P53 pin Bit 2 (/PD52): Control bit used to enable the pull-down function of the P52 pin Bit 1 (/PD51): Control bit used to enable the pull-down function of the P51 pin

Bit 0 (/PD50): Control bit used to enable the pull-down function of the P50 pin.

6.2.8 IOCC0 (Open-Drain Control Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

/OD67

/OD66

/OD65

/OD64

/OD63

/OD62

/OD61

/OD60

 

 

 

 

 

 

 

 

Note: The IOCC0 register is both readable and writable

Bit 7 (/OD67): Control bit used to enable the open-drain output of the P67 pin 0 = Enable open-drain output

1 = Disable open-drain output

Bit 6 (/OD66): Control bit used to enable the open-drain output of the P66 pin Bit 5 (/OD65): Control bit used to enable the open-drain output of the P65 pin Bit 4 (/OD64): Control bit used to enable the open-drain output of the P64 pin

Bit 3 (/OD63): Control bit used to enable the open-drain output of the P63 pin

Bit 2 (/OD62): Control bit used to enable the open-drain output of the P62 pin

Bit 1 (/OD61): Control bit used to enable the open-drain output of the P61 pin

Bit 0 (/OD60): Control bit used to enable the open-drain output of the P60 pin

20

Product Specification (V1.2) 05.18.2007

 

(This specification is subject to change without further notice)

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

6.2.9 IOCD0 (Pull-high Control Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

/PH57

/PH56

/PH55

/PH54

/PH53

/PH52

/PH51

/PH50

 

 

 

 

 

 

 

 

Note: The IOCD0 register is both readable and writable

Bit 7 (/PH57): Control bit is used to enable the pull-high of the P57 pin (applicable to EM78P260N only).

0= Enable internal pull-high;

1= Disable internal pull-high.

Bit 6 (/PH56): Control bit used to enable the pull-high function of the P56 pin (applicable to EM78P260N only).

Bit 5 (/PH55): Control bit used to enable the pull-high function of the P55 pin. Bit 4 (/PH54): Control bit used to enable the pull-high function of the P54 pin. Bit 3 (/PH53): Control bit used to enable the pull-high function of the P53 pin. Bit 2 (/PH52): Control bit used to enable the pull-high function of the P52 pin. Bit 1 (/PH51): Control bit used to enable the pull-high function of the P51 pin.

Bit 0 (/PH50): Control bit used to enable the pull-high function of the P50 pin.

6.2.10 IOCE0 (WDT Control & Interrupt Mask Registers 2)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WDTE

EIS

ADIE

CMPIE

PSWE

PSW2

PSW1

PSW0

 

 

 

 

 

 

 

 

Bit 7 (WDTE): Control bit used to enable Watchdog Timer 0 = Disable WDT

1 = Enable WDT

WDTE is both readable and writable

Bit 6 (EIS): Control bit used to define the function of the P60 (/INT) pin 0 = P60, bi-directional I/O pin

1 = /INT, external interrupt pin. In this case, the I/O control bit of P60 (Bit 0 of IOC60) must be set to "1"

NOTE

When EIS is "0," the path of /INT is masked. When EIS is "1," the status of /INT pin can also be read by way of reading Port 6 (R6). Refer to Fig. 6-4 (I/O Port and I/O Control Register Circuit for P60 (/INT)) under Section 6.4 (I/O Ports).

EIS is both readable and writable.

Product Specification (V1.2) 05.18.2007

21

(This specification is subject to change without further notice)

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