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Such information and material may change to conform to each confirm ed order.
In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or
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NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY
ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
(This specification is subject to change without further notice)
Contents
Specification Revision History
Doc. Version Revision Description Date
0.9 Preliminary version 2007/03/20
1.0 Initial released version 2007/10/19
vi •
Product Specification (V1.0) 10.19.2007
(This specification is subject to change without further notice)
EM78P221/2N
8-Bit Microcontroller with OTP ROM
Read Me First !
Comparison between V-Package and U-Package version
This series of microcontrollers comprise of the older V-package version and the newer
U-package version. In the newer U-package version, a Code Option NRM is added
and various features such as Crystal mode Operating frequency range, IRC mode
wake-up time, WDT Time-out time, Comparator function and Pins function have been
modified to favorably meet users’ requirements. The following table is provided for
quick comparison between the two package version and for user convenience in the
choice of the most suitable product for their application.
EM78P221/222N-VEM78P221/222N-U
Crystal mode Operating
frequency range at 0°C~ 70°C
IRC mode wake-up time
Sleep mode → Normal mode
Condition: 5V, 4MHz
P52, P53 Function Output only Input / Output
Comparator Function Comparator only Comparator / OPA
WDT Time-out time
(Prescaler = 1 : 1)
Condition: VDD = 5V
Code Option
DC ~ 12MHz, 4.0V
DC ~ 8MHz, 3.0V
DC ~ 4MHz, 2.1V
64μs 10μs
16.5 ms ± 30 % 15.2 ms ± 30 %
×
DC ~ 16MHz, 4.5V
DC ~ 8MHz, 3.0V
DC ~ 4MHz, 2.1V
Added a Code Option NRM
EM78P221/2N-V Package version EM78P221/2N-U Package version
Product Specification (V1.0) 10.19.2007 • 1
(This specification is subject to change without further notice)
EM78P221/2N
8-Bit Microcontroller with OTP ROM
1 General Description
EM78P221N and EM78P222N are 8-bit microprocessors designed and developed with low-power and high-speed CMOS
technology. Each device in the series has as an on-chip 4K×13-bit Electrical One Time Programmable Read Only Memory
(OTP-ROM). Each provides a protection bit to prevent intrusion of user’s OTP memory code. Two Code option bits are
also available to meet user’s requirements.
With its enhanced OTP-ROM features, each device provides a convenient way of developing and verifying user’s
programs. Moreover, this OTP devices offer the advantages of easy and effective program updates, using development
and programming tools. User can avail of the ELAN Writer to easily program his development code.
Crystal type: Output terminal for crystal oscillator.
RC type: Clock output with a duration of one instruction cycle
time.
External clock signal input.
If it remains at a logic low, the device will be reset
Wake-up from sleep mode when pin status changes
Voltage on /RESET must not exceed Vdd during normal mode
External interrupt pin
Power supply
Ground
Product Specification (V1.0) 10.19.2007
4 •
(This specification is subject to change without further notice)
4.2 EM78P221N
Symbol Pin No. Type Function
P50~P57
P60~P67
P70~P73
P77
P81
CINCIN+
CO
OSCI
OSCO
/RESET
INT0~INT1
VDD
VSS
1~2
11~14
22~23
6 ~ 10
15~17
5
21 ~ 18
24 I/O
18
19
20
23 I
22 O
24 I
5, 20 I
3 -
4 -
I/O
I/O
I/O
I
I
O
EM78P221/2N
8-Bit Microcontroller with OTP ROM
8-bit General purpose input/output pins
Default value at power-on reset.
8-bit General purpose input/output pins
Default value at power-on reset
5-bit General purpose input/output pins
Default value at power-on reset
P72 and P73 are open drain pins when used as output pins of
the ICE220N simulator.
1-bit General purpose input or output open-drain pin
Default value at power-on reset
“-“ : input pin of Vin- of the comparator
“+” : input pin of Vin+ of the comparator
Pin CO is the comparator output
Defined by CMPCON (Bank 1-RA) <3 : 4>
Crystal type: Output terminal for crystal oscillator
RC type: Clock output with a duration of one instruction cycle
time.
External clock signal input.
If it remains at logic low, the device will be reset
Wake-up from sleep mode when pin status changes
Voltage on /RESET must not exceed Vdd during normal mode
External interrupt pin
Power supply
Ground
Product Specification (V1.0) 10.19.2007 • 5
(This specification is subject to change without further notice)
EM78P221/2N
8-Bit Microcontroller with OTP ROM
5 Block Diagram
P8
P80
P81
P70
P71
P72
P73
P74
P75
P76
P77
P60
P61
P62
P63
P64
P65
P66
P67
P50
P51
P52
P53
P54
P55
P56
P57
P7
P6
P5
ACC
ROM
Instruction
Register
Instruction
Decoder
ALU
R3 (Status
Reg.)
PC
8-level stack
(13 bit)
Interrupt
Control
Register
Interrupt
Circuit
R4
Ext.
OSC.
Int.
RC
Oscillation
Generation
Reset
Mux
.
RAM
Ext.
RC
WDT
TCC
Port
change
LVR
Comparator
TCC
Port 6
Ext INT
Cin+ Cin- CO
Fig. 5-1 EM78P221/2N Functional Block Diagram
6 •
(This specification is subject to change without further notice)
Product Specification (V1.0) 10.19.2007
EM78P221/2N
8-Bit Microcontroller with OTP ROM
6 Function Description
6.1 Register Configuration
Address Bank 0 Registers Bank 1 Registers Bank 2 Registers Bank 3 Registers
2. When using ICE, some registers code options are set. Refer to Section 6.2 for detailed Registers Description.
3. Registers with * can only be used in ICE220N simulator.
Product Specification (V1.0) 10.19.2007 • 7
(This specification is subject to change without further notice)
EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.2 Registers Description
6.2.1 A (Accumulator)
Internal data transfer operation, or instruction operand holding usually involves the
temporary storage function of the Accumulator. The Accumulator is not an
addressable register.
6.2.2 CONT (Control Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTE INT TS TE PSTE PST2 PST1 PST0
Bit 7 (INTE): INT signal edge
0 = interrupt occurs at the rising edge on the INT0 and INT1 pin
1 = interrupt occurs at the falling edge on the INT0 and INT1 pin
Bit 6 (INT): Interrupt enable flag
0 = masked by DISI or hardware interrupt
1 = enabled by the ENI/RETI instructions
This bit is readable only.
Bit 5 (TS): TCC signal source
0 = internal instruction cycle clock. If P56 is used as I/O pin, TS must be 0.
1 = transition on the TCC pin
Bit 4 (TE): TCC signal edge
0 = increment if the transition from low to high takes place on the TCC pin
1 = increment if the transition from high to low takes place on the TCC pin.
Bit 3 (PSTE): Prescaler enable bit for TCC
0 = prescaler disable bit. TCC rate is 1:1
1 = prescaler enable bit. TCC rate is set as Bit 2 ~ Bit 0.
When the Comparator output status change is used to enter interrupt
vector or to wake-up from sleep, the CMPWE bit must be set to
“Enable“.
Bit 0 (CMPIF): Comparator interrupt flag. Set when a change occurs in the output of
Comparator. Reset by software.
0 = no interrupt occurs
1 = with interrupt request
NOTE
■ Bank 0-RE <7, 0> can be cleared by instruction but cannot be set.
■ Bank1-RE <0> is an interrupt mask register.
■ Interrupt results from "logic AND" of Bank 0-RE <7, 0> and Bank 1-RE <0>, with
instruction “ENI”.
6.2.14 Bank 0-RF (Interrupt Status Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 0 0 0 0 EX0IF ICIF TCIF
Bits 7~3: not used bits, fixed to 0 all the time
Bit 2 (EX0IF): External interrupt flag. Set by INT0 pin. Reset by software.
0 = no interrupt occurs
1 = with interrupt request
Product Specification (V1.0) 10.19.2007
12 •
(This specification is subject to change without further notice)
EM78P221/2N
8-Bit Microcontroller with OTP ROM
Bit 1 (ICIF): Port 6 input status change interrupt flag. Set when Port 6 input changes.
Reset by software.
0 = no interrupt occurs
1 = with interrupt request
Bit 0 (TCIF): TCC overflow interrupt flag. Set when TCC overflows. Reset by software.
0 = no interrupt occurs
1 = with interrupt request
NOTE
■ Bank 0-RF <2, 1, 0> can be cleared by instruction but cannot be set.
■ Bank1-RF <2, 1, 0> is an interrupt mask register.
■ Interrupt results from "logic AND" of Bank 0-RF <2, 1, 0> and Bank 1-RF <2, 1, 0>
with instruction “ENI”.
6.2.15 Bank 1-R5 ~R7 (I/O Port Control Register)
Bits 7~0: 0 = defines the relative I/O pin as output
1 = puts the relative I/O pin into high impedance
Bank 1-R5, R6 and R7 registers are all readable and writable.
6.2.16 Bank 1-R8 (I/O Port Control Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 0 0 0 0 0 C81 C80
Bits 7~2: not used, fixed to 0 all the time
Bits 1~0 (C81~C80): 0 = defines the relative I/O pin as output 1 = puts the relative I/O pin into high impedance
With Simulator]: P80 and P81 are General I/O pins
[With EM78P221/2N]: P80 is General input or output, but P81 is input or open-drain
output pin.
Product Specification (V1.0) 10.19.2007 • 13
(This specification is subject to change without further notice)
EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.2.17 Bank 1-R9 (Reserve)
Bits 7~0: not used, fixed to 0 all the time
6.2.18 Bank 1-RA (CMPCON: Comparator Control Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
EIS1 EIS0 CMPOUT CMPCOS1 CMPCOS00 0 0
Bit 7 (EIS1): Control bit used to define the function of the P71 (/INT1) pin
0 = P71, normal I/O pin 1 = /INT1, external interrupt pin. In this case, the I/O control bit of P71
(Bit 1 of Bank 1-R7) must be set to "1"
Bit 6 (EIS0): Control bit used to define the function of the P77 (/INT0) pin
0 = P77, normal I/O pin 1 = /INT0, external interrupt pin. In this case, the I/O control bit of P77
(Bit 7 of Bank 1-R7) must be set to "1"
NOTE
When EIS is "0," the path of /INT is masked. When EIS is "1," the status of /INT
pin can also be read by way of reading Port 7 (Bank 0-R7). Refer to Fig. 6-4 (I/O
Port and I/O Control Register Circuit for P77 (/INT0) and P71 (/INT1) under
Section 6.4 (I/O Ports).
EIS0 and EIS1 are both readable and writable.
The highest priority of P71/INT1/CO2 is INT1. When EIS1=0, the working type
of P71/INT1/CO is determined by CMPCOS1 and CMPCOS0.
Bit 5 (CMPOUT): The result of the comparator output
Bit 4 ~ Bit 3 (CMPCOS1 ~ CMPCOS0): Comparator Select bits
CMPCOS1 CMPCOS0 Function Description
0 0
0 1
1 0
1 1 Used as OP and P71 is OP output pin (CO)
Comparator is not used. P72, P73 and P71 are
normal I/O pins
P72 and P73 are Comparator input pins and P71
is normal I/O pin
P72 and P73 are Comparator input pins and P71
is Comparator output pin (CO)
Bits 2~0: not used, fixed to 0 all the time
Product Specification (V1.0) 10.19.2007
14 •
(This specification is subject to change without further notice)
EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.2.19 Bank 1-RB (Pull-down Control Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
/PD7 /PD6 /PD5 /PD4 /PD3 /PD2 /PD1 /PD0
Bank 1-RB register is both readable and writable
Bit 7 (/PD7): Control bit used to enable the pull-down function of the P67 pin
0 = Enable internal pull-down function
1 = Disable internal pull-down function
Bit 6 (/PD6): Control bit used to enable the pull-down function of the P66 pin.
Bit 5 (/PD5): Control bit used to enable the pull-down function of the P65 pin.
Bit 4 (/PD4): Control bit used to enable the pull-down function of the P64 pin.
Bit 3 (/PD3): Control bit used to enable the pull-down function of the P63 pin.
Bit 2 (/PD2): Control bit used to enable the pull-down function of the P62 pin.
Bit 1 (/PD1): Control bit used to enable the pull-down function of the P61 pin.
Bit 0 (/PD0): Control bit used to enable the pull-down function of the P60 pin.
6.2.20 Bank 1-RC (Open-Drain Control Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
/OD7 /OD6 /OD3 /OD2 /OD5 /OD4 /OD1 /OD0
Bank 1-RC register is both readable and writable.
Bit 7 (OD7): Control bit used to enable the open-drain output of the P57 pin.
0 = Enable open-drain output
1 = Disable open-drain output
Bit 6 (OD6): Control bit used to enable the open-drain output of the P56 pin.
Bit 5 (OD5): Control bit used to enable the open-drain output of the P55 pin.
Bit 4 (OD4): Control bit used to enable the open-drain output of the P54 pin.
Bit 3 (OD3): Control bit used to enable the open-drain output of the P53 pin.
Bit 2 (OD2): Control bit used to enable the open-drain output of the P52 pin.
Bit 1 (OD1): Control bit used to enable the open-drain output of the P51 pin.
Bit 0 (OD0): Control bit used to enable the open-drain output of the P50 pin.
Product Specification (V1.0) 10.19.2007 • 15
(This specification is subject to change without further notice)
EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.2.21 Bank 1-RD (Pull-high Control Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
/PH7 /PH6 /PH5 /PH4 /PH3 /PH2 /PH1 /PH0
Bank 1-RD register is both readable and writable.
Bit 7 (/PH7): Control bit used to enable the pull-high function of the P67 pin.
Bit 6 (/PH6): Control bit used to enable the pull-high function of the P66 pin.
Bit 5 (/PH5): Control bit used to enable the pull-high function of the P65 pin.
Bit 4 (/PH4): Control bit used to enable the pull-high function of the P64 pin.
Bit 3 (/PH3): Control bit used to enable the pull-high function of the P53 pin.
Bit 2 (/PH2): Control bit used to enable the pull-high function of the P52 pin.
Bit 1 (/PH1): Control bit used to enable the pull-high function of the P51 pin.
Bit 0 (/PH0): Control bit used to enable the pull-high function of the P50 pin.
6.2.22 Bank 1-RE (WDT Control Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WDTE 0 PSWE PSW2 PSW1 PSW0 0 CMPIE
NOTE
Bank 1-RE <0> register is both readable and writable
Individual interrupt is enabled by setting its associated control bit in the
Bank 1-RF <0 > to "1."
Global interrupt is enabled by the ENI instruction and is disabled by the DISI
instruction. Refer to Fig. 6-8 (Interrupt Input Circuit) under Section 6.6
(Interrupt).
Bit 7 (WDTE): Control bit is used to enable Watchdog Timer
0 = Disable WDT
1 = Enable WDT
WDTE is both readable and writable.
Bits 6, 1: not used, fixed to 0 all the time
Bit 5 (PSWE): Prescaler enable bit for WDT
0 = prescaler disable bit. WDT rate is 1:1
1 = prescaler enable bit. WDT rate is set as Bit 4~Bit 2
Product Specification (V1.0) 10.19.2007
16 •
(This specification is subject to change without further notice)
When the Comparator output status change is used to enter an
interrupt vector or to enter next instruction, the CMPIE bit must be set
to “Enable“. But actually the output of the comparator must be read to
latch the status first. Then the output of the comparator is compared
to this latch to produce the information of output status change.
EM78P221/2N
6.2.23 Bank 1-RF (Interrupt Mask Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 0 0 0 0 EXIE ICIE TCIE
NOTE
RF register is both readable and writable.
Individual interrupt is enabled by setting its associated control bit in the RF to "1."
Global interrupt is enabled by the ENI instruction and is disabled by the DISI
instruction. Refer to Fig. 6-8 (Interrupt Input Circuit) under Section 6.6 (Interrupt).
Bits 7~3: not used bits, fixed to 0 all the time
Bit 2 (EXIE): EX0IF and EX1IF interrupts enable bit
0 = Disable EX0IF and EX1IF interrupts
1 = Enable EX0IF and EX1IF interrupts
Bit 1 (ICIE):ICIF interrupt enable bit 0 = Disable ICIF interrupt
1 = Enable ICIF interrupt
If Port 6 Input Status Change Interrupt is used to enter an interrupt
vector or to enter next instruction, the ICIE bit must be set to
“Enable“.
Bit 0 (TCIE):TCIF interrupt enable bit 0 = Disable TCIF interrupt
1 = Enable TCIF interrupt
Product Specification (V1.0) 10.19.2007 • 17
(This specification is subject to change without further notice)
EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.2.24 Bank 2-R5 (HDCR: High Drive Control Register for Port 6)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
HD67 HD66 HD65 HD64 HD63 HD62 HD61 HD60
[With Simulator]: function nonexistent
[With EM78P221/2N]: General I/O pins
Bit 7 (HD67): Output High Drive Current Select for P67
Bit 6 (HD66): Output High Drive Current Select for P66
Bit 5 (HD65): Output High Drive Current Select for P65
Bit 4 (HD64): Output High Drive Current Select for P64
Bit 3 (HD63): Output High Drive Current Select for P63
Bit 2 (HD62): Output High Drive Current Select for P62
Bit 1 (HD61): Output High Drive Current Select for P61
Bit 0 (HD60): Output High Drive Current Select for P60
HDxx VDD = 5V, Drive Current
0 9mA (in 0.9VDD)
1 27mA (in 0.7VDD)
6.2.25 Bank 2-R6 (HSCR1: High Sink Control Register for Port 5)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
HS57 HS56 HS55 HS54 HS53 HS52 HS51 HS50
[With Simulator]: function nonexistent
[With EM78P221/2N]: General I/O pins
Bit 7 (HS57): Output High Sink Current Select for P57
Bit 6 (HS56): Output High Sink Current Select for P56
Bit 5 (HS55): Output High Sink Current Select for P55
Bit 4 (HS54): Output High Sink Current Select for P54
Bit 3 (HS53): Output High Sink Current Select for P53
Bit 2 (HS52): Output High Sink Current Select for P52
Bit 1 (HS51): Output High Sink Current Select for P51
Bit 0 (HS50): Output High Sink Current Select for P50
HDxx VDD = 5V, Sink Current
0 18mA (in 0.1VDD)
1 75mA (in 0.3VDD)
Product Specification (V1.0) 10.19.2007
18 •
(This specification is subject to change without further notice)
EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.2.26 Bank 2-R7 (HSCR2: High Sink Control Register for Port 6)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
HS67 HS66 HS65 HS64 HS63 HS62 HS61 HS60
[With Simulator]: function nonexistent
[With EM78P221/2N]: General I/O pins.
Bit 7 (HS67): Output High Sink Current Select for P67
Bit 6 (HS66): Output High Sink Current Select for P66
Bit 5 (HS65): Output High Sink Current Select for P65
Bit 4 (HS64): Output High Sink Current Select for P64
Bit 3 (HS63): Output High Sink Current Select for P63
Bit 2 (HS62): Output High Sink Current Select for P62
Bit 1 (HS61): Output High Sink Current Select for P61
Bit 0 (HS60): Output High Sink Current Select for P60
HDxx VDD = 5V, Sink Current
0 18 mA (in 0.1VDD)
1 75 mA (in 0.3VDD)
6.2.27 Bank 2-R8 (Operating Mode Control Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
011000 0 0
Bits 7, 4~0: not used, fixed to "0" all the time.
Bits 6~5: not used, fixed to "1" all the time.
NOTE
■ If user wants the MCU to work normally, user must set Bit 6 and Bit 5 of the R8
register to “1” and clear Bit 4 of R8 register to “0”.
6.2.28 Bank 2-R9~RF (Reserve)
Bits 7~0: not used, fixed to "0" all the time
6.2.29 Bank 3-R5 (Timer Clock/Counter)
Incremented by an external signal edge through the TCC pin, or by the instruction
cycle clock.
External signal of TCC trigger pulse width must be greater than one instruction.
The signals to increase the counter are determined by Bit 4 and Bit 5 of the CONT
register.
Writable and readable as any other registers.
Product Specification (V1.0) 10.19.2007 • 19
(This specification is subject to change without further notice)
[With EM78P221/2N]: Unimplemented, read as ‘0’.
Bits 7 ~ 4 (C3 ~ C0): Calibrator of internal RC mode
In IRC oscillator mode of ICE220N simulator, these are the
IRC mode selection bits and IRC calibration bits.
C3 C2 C1 C0 Frequency (MHz)
0 0 0 0 (1-36%) × F
0 0 0 1 (1-31.5%) × F
0 0 1 0 (1-27%) × F
0 0 1 1 (1-22.5%) × F
0 1 0 0 (1-18%) × F
0 1 0 1 (1-13.5%) × F
0 1 1 0 (1-9%) × F
0 1 1 1 (1-4.5%) × F
1 1 1 1 F (default)
1 1 1 0 (1+4.5%) × F
1 1 0 1 (1+9%) × F
1 1 0 0 (1+135%) × F
1 0 1 1 (1+18%) × F
1 0 1 0 (1+22.5%) × F
1 0 0 1 (1+27%) × F
1 0 0 0 (1+31.5%) × F
1. Frequency values shown are theoretical and taken at an instance of
a high frequency mode. Hence, frequency values are shown for
reference only. Definite values depend on the actual process.
2. Similar way of calculation is also applicable to low frequency mode.
Bits 3 ~ 2 (RCM1 ~ RCM0): IRC mode selection bits
RCM 1 RCM 0 Frequency (MHz)
1 1 4 (default)
1 0 16
0 1 1
0 0 455kHz
Bits 1 ~ 0: are not used, fixed to "0" all the time.
Product Specification (V1.0) 10.19.2007
20 •
(This specification is subject to change without further notice)
EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.2.31 Bank 3-R7 (Noise and LVR Control) - only for ICE
Bit 7 6 5 4 3 2 1 0
EM78P221/2N ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
ICE220N “0” “0” “0” “0” NRHL NRE LVR1 LVR0
Bits 7 ~ 4: not used, fixed to "0" all the time.
Bits 3 ~ 0:
[With EM78P221/2N]: Unimplemented, read as ‘0’.
[With Simulator]:
Bit 3 (NRHL): Noise rejection high/low pulses define bit. The INT pin is a falling
edge trigger
0 = Pulses equal to 8/fc [s] are regarded as signal.
1 = Pulses equal to 32/fc [s] are regarded as signal (default)
NOTE
The noise rejection function is turned off in the LXT2 and sleep mode.
oscillator (LXT) mode, the noise rejection circuit is always
disabled.
Bits 1 ~ 0 (LVR1 ~ LVR0): Low Voltage Reset enable bits. If Vdd has crossover at
Vdd reset level as Vdd changes, the system will be reset.
LVR1, LVR0 VDD Reset Level VDD Release Level
11 NA (Power-on Reset) (default)
10 2.5V 2.7V
01 3.0V 3.2V
00 4.0V 4.2V
6.2.32 Bank 3-R8~RF (Reserve)
Bits 7~0: not used, fixed to "0" all the time.
6.2.33 R10 ~ R1F
All of these are 8-bit general-purpose registers.
6.2.34 Banks 0~3 - R20 ~ R3F
All of these are 8-bit general-purpose registers.
Product Specification (V1.0) 10.19.2007 • 21
(This specification is subject to change without further notice)
EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.3 TCC/WDT and Prescaler
There are two 8-bit counters available as prescalers for the TCC and WDT. The
PST0~PST2 bits of the CONT register are used to determine the ratio of the TCC
prescaler, and the PWR0~PWR2 bits of the Bank 1-RE register are used to determine
the WDT prescaler. The prescaler counter is cleared by the instructions each time
such instructions are written into TCC. The WDT and prescaler are cleared by the
“WDTC” and “SLEP” instructions. Fig. 6-2 depicts the block diagram of TCC/WDT.
TCC (Bank 3-R5) is an 8-bit timer/counter. The TCC clock source can be internal clock
(Fosc) or external signal input (edge selectable from the TCC pin). If the TCC signal
source is from an external clock input, TCC will be incremented by 1 at every falling
edge or rising edge of the TCC pin. The TCC pin input time length (kept at High or Low
level) must be greater than 1CLK. 1 CLK is always Fosc/2..Refer to Fig. 6-2.
The internal TCC will stop running when in sleep mode.
NOTE
The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on
running even when the oscillator driver has been turned off (i.e., in sleep mode).
During normal operation or sleep mode, a WDT time-out (if enabled) will cause the
device to reset. The WDT can be enabled or disabled at any time during normal mode
through software programming. Refer to WDTE bit of Bank 1-RE register (Section
6.2.10 Bank 1-RE (WDT Control Register). With no prescaler, the WDT time-out
duration is approximately 18ms.
1
1
VDD=5V, WDT Time-out period = 15.2ms ± 30%.
VDD=3V, WDT Time-out period = 18ms ± 30%.
Product Specification (V1.0) 10.19.2007
22 •
(This specification is subject to change without further notice)
EM78P221/2N
8-Bit Microcontroller with OTP ROM
CLK (Fosc)
TCC Pin
TE (CONT)
WDTE (Bank 1-RE)
6.4 I/O Ports
The I/O registers (Port 5, Port 6, Port 7, and Port 8) are bidirectional tri-state I/O ports.
The Pull-high, Pull-down, and Open-drain functions can be set internally by Bank 1-RB,
Bank 1-RC, and Bank 1-RD respectively. The High Drive, and High Sink functions can
be set internally by Bank 2-R5, Bank 2-R6, and Bank 2-R7 respectively. Port 6 features
an input status change interrupt (or wake-up) function. Most I/O pin can be defined as
"input" or "output" pin by the I/O control registers (P52, P53 are only used as output
pins). The I/O registers and I/O control registers are both readable and writable.
However, the initial states of these I/O ports (Port 5, Port 6, Port 7 and Port 8) are
unknown input (high impedance). Then, if the I/O pin is pulled to a level at external
circuit, the pin must induce a voltage. Hence, user must take into consideration
whether the induced voltage causes a wrong action in the system. The I/O interface
circuits for Port 5, Port 6, Port 7, and Port 8 are illustrated in Figures 6-3, 6-4, & 6-5
respectively. Port 6 with Input Change Interrupt/Wake-up is shown in Fig. 6-6.
0
MUX
1
TS (CONT)
8-bit CounterWDT
WDT Time out
8-bit Counter
8 to 1 MUX
Prescaler
PSR2~0
(CONT)
Prescaler8 to 1 MUX
PSW2~0
(Bank 1-RE)
Fig. 6-2 TCC and WDT Block Diagram
Data Bus
TCC (R1)
TCC overflow
Interrupt
PCRD
P
R
DDQ
CLK
PCWR
C
L
P
R
CLK
PDWR
C
L
PDRD
IOD
PORT
_
Q
Q
_
Q
M
0
U
X
1
Note: Pull-high and Open-drain are not shown in the figure.
Fig. 6-3 I/O Port and I/O Control Register Circuit for Port 5 , Port 7 and Port 8
Product Specification (V1.0) 10.19.2007 • 23
(This specification is subject to change without further notice)
EM78P221/2N
8-Bit Microcontroller with OTP ROM
P77, /INT0
P71, /INT1
PORT
EIS1,EIS0
P
DQ
R
CLK
_
C
Q
L
PCRD
P
R
DQ
CLK
_
Q
_
Q
M
0
U
X
1
PCWR
C
L
P
R
DQ
CLK
PDWR
C
L
IOD
PDRD
INT
Note: CO2, Pull-high and Open-drain are not shown in the figure.
Fig. 6-4 I/O Port and I/O Control Register Circuit for P77 (/INT0) and P71 (/INT1)
PCRD
P
R
DQ
CLK
PCW R
C
L
P
R
DQ
CLK
PDW R
C
L
PDRD
_
Q
IOD
TI n
P60 ~ P67
PORT
_
Q
_
Q
M
0
U
X
1
P
DQ
R
CLK
C
L
Note: Pull-high (down) and Open-drain are not shown in the figure.
Fig. 6-5 I/O Port and I/O Control Register Circuit for Port 6
Product Specification (V1.0) 10.19.2007
24 •
(This specification is subject to change without further notice)
EM78P221/2N
8-Bit Microcontroller with OTP ROM
ICIE
P
Q
D
R
T10
T11
T17
/SLEP
CLK
_
C
Q
L
D
CLK
RE.1
P
R
C
L
Q
_
Q
P
Q
R
CLK
_
C
Q
L
Interrupt
ENI Instruction
D
DISI Instruction
Interrupt
(Wake-up from
SLEEP)
ICWE
Next Instruction
(Wake-up from
SLEEP)
Fig. 6-6 Port 6 Block Diagram with Input Change Interrupt/Wake-up
6.4.1 Usage of Port 6 Input Change Wake-up/Interrupt Function
Usage of Port 6 Input Status Change Wake-up/Interrupt
(1) Wake-up (2) Wake-up and Interrupt
(a) Before Sleep (a) Before Sleep
1. Disable WDT 1. Disable WDT
2. Read I/O Port 6 (MOV R6,R6) 2. Read I/O Port 6 (MOV R6,R6)
3. Execute "ENI" or "DISI" 3. Execute "ENI" or "DISI"
4. Enable wake-up bit
(Set Bank 0-RE ICWE =1)
5. Execute "SLEP" instruction
(b) After wake-up 6. Execute "SLEP" instruction
→ Next instruction (b) After wake-up
1. IF "ENI" → Interrupt vector (008H)
2. IF "DISI" → Next instruction
(3) Interrupt
(a) Before Port 6 pin change
1. Read I/O Port 6 (MOV R6,R6)
2. Execute "ENI" or "DISI"
3. Enable interrupt (Set BANK1-RF ICIE =1)
(b) After Port 6 pin changed (interrupt)
1. IF "ENI" → Interrupt vector (008H)
2. IF "DISI" → Next instruction
4. Enable wake-up bit
(Set Bank 0-RE ICWE =1)
5. Enable interrupt (Set BANK1-RF ICIE
=1)
Product Specification (V1.0) 10.19.2007 • 25
(This specification is subject to change without further notice)
EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.5 Reset and Wake-up
6.5.1 Reset and Wake-up Operation
A reset is initiated by one of the following events:
1. Power-on reset
2. /RESET pin input "low"
3. WDT time-out (if enabled)
A device is kept in a reset condition for a duration of approximately 18ms
reset is detected. When in LXT mode, the reset time is 500ms. Once a reset occurs,
the following functions are performed (the initial address is 000h):
The oscillator continues running, or will be started (if in sleep mode)
The Program Counter (R2) is set to all "0"
All I/O port pins are configured as input mode (high-impedance state)
2
after the
The Watchdog Timer and prescaler are cleared
When power is switched On, the Memory switch register (R1) is set to 0
The CONT register bits are set to all "0" except for Bit 6 (INT flag)
The Bank 0-RF register bits are set to all "0"
The Bank 1-RB register bits are set to all "1"
The Bank 1-RC register bits are set to all "1"
The Bank 1-RD register bits are set to all "1"
The Bank 1-RE register bits are set to all "0"
The Bank 1-RF register bits are set to all "0"
Executing the “SLEP” instruction will assert the sleep (power down) mode. While
entering sleep mode, the Oscillator and TCC are stopped. The WDT (if enabled) is
cleared but keeps on running.
The controller can be awakened by:
Case 1 External reset input on /RESET pin
Case 2 WDT time-out (if enabled)
Case 3 Port 6 input status changes (if ICWE is enabled)
Case 4 Comparator output status changes (if CMPWE is enabled)
2
VDD=5V, Setup time period = 16.5ms ± 30%.
VDD=3V, Setup time period = 18ms ± 30%.
Product Specification (V1.0) 10.19.2007
26 •
(This specification is subject to change without further notice)
EM78P221/2N
8-Bit Microcontroller with OTP ROM
The first two cases (1 & 2) will cause the EM78P221/2N to reset. The T and P flags of
R3 can be used to determine the source of the reset (wake-up). Cases 3 & 4 are
considered the continuation of program execution and the global interrupt ("ENI" or
"DISI" being executed) decides whether or not the controller branches to the interrupt
vector following a wake-up. If ENI is executed before SLEP, the instruction will begin to
execute from Address 0x8 after wake-up. If DISI is executed before SLEP, the
execution will restart from the instruction next to SLEP after wake-up. All sleep mode
wake up time is dependent on the oscillator mode, no matter what the oscillator type or
mode is (except when it’s in LXT2 mode). In LXT2 mode, wake-up time is 2 ~ 3 sec.
Only one of Cases 1 to 4 can be enabled before entering into sleep mode. That is:
Case [a] If WDT is enabled before SLEP, all of the RE bit is disabled. Hence, the
EM78P221/2N can be awakened only with Case 1 or Case 2. Refer to the
section on Interrupt (Section 6.6) for further details.
Case [b] If Port 6 Input Status Change is used to wake -up EM78P221/2N and ICWE
bit of Bank 0-RE register is enabled before SLEP, WDT must be disabled.
Hence, the EM78P221/2N can be awakened only with Case 3. Wake-up
time is dependent on the oscillator mode. In RC mode (VDD: 5V, IRC:
4MHz), wake-up time is 10 μs (for stable oscillators). In HXT2 mode (VDD:
5V, Crystal: 4MHz, C1/C2: 30pF), wake-up time is 800μs (for stable
oscillators), and in LXT2 mode, wake-up time is 2 ~ 3 sec.
Case [c] If the Comparator output status change is used to wake-up the EM78P221/ 2N
and the CMPWE bit of the RE register is enabled before SLEP, WDT must be
disabled by software. Hence, the EM78P221/2N can be awakened only with
Case 4.
Wake-up time is dependent on the oscillator mode. In RC mode (VDD: 5V,
IRC: 4MHz), wake-up time is 10μs (for stable oscillators). In HXT2 mode
(VDD: 5V, Crystal: 4MHz, C1/C2: 30 pF), wake-up time is 800μs (for stable
oscillators), and in LXT2 mode, wake-up time is 2 ~ 3 sec.
Product Specification (V1.0) 10.19.2007 • 27
(This specification is subject to change without further notice)
EM78P221/2N
;
o
8-Bit Microcontroller with OTP ROM
If Port 6 Input Status Change Interrupt is used to wake up the EM78P221/2N (as in
Case b above), the following instructions must be executed before SLEP:
MOV A, @000110xxb ; Select WDT prescaler and disable WDT
BANK 1
MOV RE, A
WDTC ; Clear WDT and prescaler
BANK 0
MOV R6, R6 ; Read Port 6
ENI (or DISI) ; Enable (or disable) global interrupt
MOV A, @xxx1xxxxb ; Enable Port 6 input change wake-up bit
MOV RE
MOV A, @00000x1xb ; Enable Port 6 input change interrupt
BANK 1
MOV RF, A
SLEP ; Sleep
Similarly, if the Comparator Interrupt is used to wake up the EM78P221/2N (as in Case
[c] above), the following instructions must be executed before SLEP:
MOV A, @xxx01xxxb
BANK 1
MOV RA, A
MOV A, @000110xxb ; Select WDT prescaler and Disabl e WDT
MOV RE, A
WDTC ; Clear WDT and prescaler
ENI (or DISI) ; Enable (or disable) global interrupt
MOV A, @00000100b
BANK 0
MOV RE, A
BANK 1
MOV A, @0x00000001b
MOV RE, A
SLEP ; Sleep
; Select Comparator and P71 funct ions as
; general I/O pin
Enable comparator output status change
; wake-up bit
; Enable Comparator 1
; interrupt
utput status change
6.5.1.1 Wake-up and Interrupt Modes Operation Summary
All categories under Reset, Wake-up and Interrupt modes are summarized below.
Wake-up Signal Sleep Mode Normal Mode
External interrupt
Port 6 pin change
TCC overflow interrupt
Comparator interrupt
WDT Time out
28 •
(This specification is subject to change without further notice)
Low Voltage Reset
After wake up:
1. If interrupt enable → interrupt+ next instruction
2. If interrupt disable → next instruction
Product Specification (V1.0) 10.19.2007
If enable ICWE bit Wake-up
+ interrupt (if interrupt enable)+ next instruction
If enable CMPWE bit Wake-up
+ interrupt (if interrupt enable) + next instruction
Reset to Normal mode Reset to Normal mode
Reset to Normal mode Reset to Normal mode
x
x
Interrupt (if interrupt enable)
or next instruction
Interrupt (if interrupt enable)
or next instruction
Interrupt (if interrupt enable)
or next instruction
Interrupt (if interrupt enable)
or next instruction
EM78P221/2N
8-Bit Microcontroller with OTP ROM
The controller can be awakened from sleep mode and idle mode. The wake-up signals are listed as
follows:
Signal Sleep Mode Normal Mode
DISI + Bank 1-RF (EXIE) Bit 2 = 1
INT0
INT1
Bank 0-RE (ICWE) Bit 4 = 0,
Bank 1-RF (ICIE) Bit 1 = 0
Oscillator, TCC and TCC are stopped.
Port 6 input status changed wake-up is invalid.
Bank 0-RE (ICWE) Bit 4 = 0,
Bank 1-RF (ICIE) Bit 1 = 1
Set Bank 0-RF (ICIF) = 1,
Oscillator and TCC are stopped.
Port 6 input status changed wake-up is invalid.
Bank 0-RE (ICWE) Bit 4 = 1,
Port 6 Input Status Change
TCC Overflow N/A
Comparator
(Comparator Output Status
Change)
WDT Time-out
Bank 1-RE (WDTE) Bit 7=1
Low Voltage Reset
Bank 1-RF (ICIE) Bit 1 = 0
Wake-up+ Next Instruction
Oscillator and TCC are stopped.
Bank 0-RE (ICWE) Bit 4 = 1,
DISI + Bank 1-RF (ICIE) Bit 1 = 1
Wake-up+ Next Instruction+ Set Bank 0-RF
(ICIF) = 1
Oscillator and TCC are stopped.
Bank 0-RE (ICWE) Bit 4 = 1,
ENI + Bank 1-RF (ICIE) Bit 1 = 1
Wake-up+ Interrupt Vector (0x08)+ Set Bank
0-RF (ICIF) = 1
Oscillator, TCC and TIMERX are stopped.
Bank 0-RE (CMPWE) Bit 2 = 0
Bank 1-RE (CMPIE) Bit 0 = 0
Comparator output status changed wake-up is
invalid.
Oscillator and TCC are stopped.
Bank 0-RE (CMPWE) Bit 2 = 0, }
Bank 1-RE (CMPIE) Bit 0 = 1
Set Bank 0-RE (CMPIF) = 1,
Comparator output status changed wake-up is
invalid.
Oscillator and TCC are stopped.
Bank 0-RE (CMPWE) Bit 2 = 1,
Bank 1-RE (CMPIE) Bit 0 = 0
Wake-up+ Next Instruction,
Oscillator and TCC are stopped.
Bank 0-RE (CMPWE) Bit 2 = 1,
DISI + Bank 1-RE (CMPIE) Bit 0 =1
Wake-up+ Next Instruction+ Set Bank 0-RE
(CMPIF) Bit 0 =1,
Oscillator and TCC are stopped.
Bank 0-RE (CMPWE) Bit 2 = 1,
ENI + Bank 1-RE (CMPIE) Bit 0 = 1
Wake-up+ Interrupt Vector (0x08)+ Set Bank 0RE (CMPIF) Bit 0 = 1,
Oscillator and TCC are stopped.
(This specification is subject to change without further notice)
Next Instruction+ Set Bank 0-RF (EX0IF) = 1
or Set Bank 0-RE (EX1IF) = 1
ENI + Bank 1-RF (EXIE) Bit 2 = 1
Interrupt Vector (0x08)+ Set Bank 0-RF
(EX0IF) = 1
Bank 1-RF (ICIE) Bit 1 = 0
Port 6 input status change interrupt is invalid
N/A
N/A
N/A
N/A
DISI + Bank 1-RF (ICIE) Bit 1 = 1
Next Instruction+ Set Bank 0-RF (ICIF) = 1
ENI + Bank 1-RF (ICIE) Bit 1 = 1
Interrupt Vector (0x08)+ Set Bank 0-RF
(ICIF) = 1
DISI + Bank 1-RF (TCIE) Bit 0 = 1
Next Instruction+ Set Bank 0-RF (TCIF) = 1
ENI + Bank 1-RF (TCIE) Bit 0=1
Interrupt Vector (0x08)+ Set Bank 0-RF
(TCIF) = 1
Bank 1-RE (CMPIE) Bit 0 = 0
Comparator output status change interrupt is
invalid.
DISI + Bank 1-RE (CMPIE) Bit 0 = 1
Next Instruction+ Set Bank 0-RE (CMPIF)
Bit 0 = 1
ENI + Bank 1-RE (CMPIE) Bit 0 = 1
Interrupt Vector (0x08)+ Bank 0-RE (CMPIF)
Bit 0 = 1
EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.5.1.2 Register Initial Values af ter Reset
The following table summarizes the registers initialized values.
Address Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit Name INTE INT TS TE PSTE PST2 PST1 PST0
Power-on 0 0 0 0 0 0 0 0
N/A CONT
0x00 R0 (IAR)
0x01 R1 (MSR)
0x02 R2 (PC)
0x03 R3 (SR)
0x04 R4 (RSR)
0x05 Bank 0-R5
0x06 Bank 0-R6
/RESET & WDT 0 0 0 0 0 0 0 0
Wake-up from
Pin Change
Bit Name - - - - - - - -
Power-on U U U U U U U U
/RESET & WDT P P P P P P P P
Wake-up from
Pin Change
Bit Name - - - - - - BS1 BS
Power-on 0 0 0 0 0 0 0 0
/RESET & WDT 0 0 0 0 0 0 0 0
Wake-up from
Pin Change
Bit Name - - - - - - - -
Power-on 0 0 0 0 0 0 0 0
/RESET & WDT 0 0 0 0 0 0 0 0
Wake-up from
Pin Change
Bit Name - - - T P Z DC C
Power-on 0 0 0 1 1 U U U
/RESET & WDT 0 0 0 t t P P P
Wake-up from
Pin Change
Bit Name - - - - - - - -
Power-on 0 0 U U U U U U
/RESET & WDT 0 0 P P P P P P
Wake-up from
Pin Change
Bit Name P57 P56 P55 P54 P53 P52 P51 P50
Power-on U U U U U U U U
/RESET & WDT U U U U U U U U
Wake-up from
Pin Change
Bit Name P67 P66 P65 P64 P63 P62 P61 P60
Power-on U U U U U U U U
/RESET & WDT U U U U U U U U
Wake-up from
Pin Change
P P P P P P P P
P P P P P P P P
P P P P P P P P
Jump to Address 0x08 or continue to execute next instruction
P P P t t P P P
P P P P P P P P
P P P P P P P P
P P P P P P P P
Product Specification (V1.0) 10.19.2007
30 •
(This specification is subject to change without further notice)
Address Name
0x07 Bank 0-R7
0x8 Bank 0-R8
0x9
~
0XD
0xE
0xF
Bank 0R9~RD
(Reserve)
Bank 0-
RE
(WUCR)
Bank 0-
RF (ISR)
Reset Type
Bit Name
Power-on
/RESET & WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET & WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET & WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET & WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET & WDT
Wake-up from
Pin Change
Bit Name
EM78P221/2N
8-Bit Microcontroller with OTP ROM
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P77 P76 P75 P74 P73 P72 P71 P70
U U U U U U U U
U U U U U U U U
P P P P P P P P
- - NREN - - - P81 P80
0 0 0 0 0 0 U U
0 0 0 0 0 0 U U
P P P P P P P P
- - - - - - - -
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
P P P P P P P P
EX1IF - - ICWE - CMPWE - CMPIF
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
P P P P P P P P
- - - - - EX0IF ICIF TCIF
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
P P P P P P P P
C57 C56 C55 C54 C53 C52 C51 C50
Power-on
0x05 Bank 1-R5
0x06 Bank 1-R6
0x07 Bank 1-R7
Product Specification (V1.0) 10.19.2007 • 31
(This specification is subject to change without further notice)
/RESET & WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET & WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET & WDT
Wake-up from
Pin Change
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
P P P P P P P P
C67 C66 C65 C64 C63 C62 C61 C60
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
P P P P P P P P
C77 C76 C75 C74 C73 C72 C71 C70
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
P P P P P P P P
EM78P221/2N
8-Bit Microcontroller with OTP ROM
Address Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit Name
0x8 Bank 1-R8
Power-on
/RESET & WDT
Wake-up from
Pin Change
Bit Name
ICE
211N
ICE
211N
ICE
- - -
220N
212N
220N
212N
0 0 0 1 0 1 0 1 0 1 1
0 0 0 1 0 1 0 1 0 1 1
P P P P P P P P P P P
- - - - - - - -
220N
211N
C81 C80
212N
0x9
0xA
Bank 1-R9
(Reserve)
Bank 1-RA
(CMPCON)
0xB Bank 1-RB
0xC Bank 1-RC
Power-on
/RESET & WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET & WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET & WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET & WDT
Wake-up from
Pin Change
Bit Name
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
P P P P P P P P
EIS1EIS0
CMP
OUT
CMP
COS1
CMP
COS0
- - -
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
P P P P P P P P
/PD7 /PD6 /PD5 /PD4 /PD3 /PD2 /PD1 /PD0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
P P P P P P P P
/OD7 /OD6 /OD5 /OD4 /OD3 /OD2 /OD1 /OD0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
P P P P P P P P
/PH7 /PH6 /PH5 /PH4 /PH3
/PH2 /PH1 /PH0
0xD Bank 1-RD
0xE Bank 1-RE
Power-on
/RESET & WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET & WDT
Wake-up from
Pin Change
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
P P P P P P P P
WDTE- PSWEPSW2 PSW1 PSW0 - CMPIE
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
P P P P P P P P
Product Specification (V1.0) 10.19.2007
32 •
(This specification is subject to change without further notice)
Address Name
Reset Type
Bit Name
EM78P221/2N
8-Bit Microcontroller with OTP ROM
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
-
- - - - EXIE ICIE TCIE
0xF Bank 1-RF
~
Bank 2-R5
(HDCR)
Bank 2-R6
(HSCR1)
Bank 2-R7
(HSCR2)
Bank 2-R8
(OMCR)
Bank 2-R9
(RF)
Bank 3-R5
(TCC)
Bank 3-R6
(IRC)
(only for
ICE) Wake-up from
0x05
0x06
0x07
0x8
0x9
0xF
0x05
0x06
Power-on
/RESET & WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET & WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET & WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET & WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET & WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET & WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET & WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET & WDT
Pin Change
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
P P P P P P P P
HD67 HD66 HD65 HD64
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
P P P P P P P P
HS57 HS56 HS55 HS54
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
P P P P P P P P
HS67 HS66 HS65 HS64
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
P P P P P P P P
- - - -
U 1 1 1 U U U U
P 1 1 1 P P P P
P P P P P P P P
- - - -
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
P P P P P P P P
TCC7 TCC6 TCC5 TCC4 TCC3 TCC2 TCC1 TCC0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
P P P P P P P P
C3 C2 C1 C0 RCM1 RCM0 - -
1 1 1 1 1 1 U U
1 1 1 1 1 1 P P
P P P P P P P P
HD63 HD62 HD61 HD60
HS53 HS52 HS51 HS50
HS63 HS62 HS61 HS60
- - - -
- - - -
Product Specification (V1.0) 10.19.2007 • 33
(This specification is subject to change without further notice)
EM78P221/2N
8-Bit Microcontroller with OTP ROM
Address Name
Bank 3-R7
0x07
(only for
ICE)
0x10 ~
0x1F
0x20 ~
0x3F
Legend: “×” = not used “P” = previous value before reset “u” = unknown or don’t care “t” = check “Reset Type” Table in Section 6.5.2
R10 ~ R1F
Bank 0~3
R20 ~ R3F
Reset Type
Bit Name
Power-on
/RESET & WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET & WDT
Wake-up from
Pin Change
Bit Name
Power-on
/RESET & WDT
Wake-up from
Pin Change
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
- - - - NRHL NRE LVR1 LVR0-
U U U U 1 1 1 1
P P P P 1 1 1 1
P P P P P P P P
- - - - - - - -
U U U U U U U U
P P P P P P P P
P P P P P P P P
- - - - - - - -
U U U U U U U U
P P P P P P P P
P P P P P P P P
6.5.1.3 Controller Reset Block Diagram
VDD
Oscillator
Power-on Reset
Voltage Detector
WTE
WDT Timeout
WDT
/RESET
Fig. 6-7 Controller Reset Block Diagram
D Q
CLK
CLR
Setup time
CLK
Reset
Product Specification (V1.0) 10.19.2007
34 •
(This specification is subject to change without further notice)
EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.5.2 The T and P Status under Status Register
A reset condition is initiated by one of the following events:
1. Power-on reset
2. /RESET pin input "low"
3. WDT time-out (if enabled)
The values of T and P as listed in the table below, are used to check how the processor
wakes up.
Reset Type T P
Power-on 1 1
/RESET during Operating mode *P *P
/RESET wake-up during Sleep mode 1 0
LVR during Operating mode, *P *P
LVR wake-up during SLEEP mode 1 0
WDT during Operating mode 0 *P
WDT wake-up during Sleep mode 0 0
Wake-up on pin change during Sleep mode 1 0
* P: Previous status before reset
The following shows the events that may affect the status of T and P.
Event T P
Power-on 1 1
WDTC instruction 1 1
WDT time-out 0 *P
SLEP instruction 1 0
Wake-up on pin changed during Sleep mode 1 0
* P: Previous value before reset
Product Specification (V1.0) 10.19.2007 • 35
(This specification is subject to change without further notice)
EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.6 Interrupt
The EM78P221/2N has four interrupts as listed below:
1. TCC overflow interrupt
2. Port 6 Input Status Change Interrupt
3. External interrupt INT0, INT1
4. When the Comparator 1 output status changes
Before the Port 6 Input Status Change Interrupt is enabled, reading Port 6 (e.g., "MOV
R6, R6") is necessary. Each Port 6 pin will have this feature if its status changes. Port 6
Input Status Change Interrupt will wake up the EM78P221/2N from sleep mode if it is
enabled prior to going into sleep mode by executing SLEP. When wake-up occurs, the
controller will continue to execute the succeeding program if the global interrupt is
disabled. If enabled, it will branch out to the interrupt vector 008H.
The external interrupt has a built-in digital noise rejection circuit (if the input pulse is
less than 8-system clock time, it is eliminated as noise. Edge selection is possible with
/INT. Refer to Word 1 Bits 8~7 (Section 6.13.2, Code Option Register (Word 1)) for
digital noise rejection definition.
During a power source unstable situation, like during external power noise interference
or EMS test condition, it will cause the power to vibrate fiercely. While Vdd is still
unsettled, the supply voltage may be below working voltage. When the system supply
voltage Vdd is below the working voltage, the IC kernel must automatically keep all
register status.
Bank 0-RE and Bank 0-RF are the interrupt status register that records the interrupt
requests in the relative flags/bits. Bank 1-RE and Bank 1-RF are interrupt mask
registers. The global interrupt is enabled by the ENI instruction and is disabled by the
DISI instruction. When one of the interrupts (when enabled) occurs, the next instruction
will be fetched from Address 008H. Once in the interrupt service routine, the source of an
interrupt can be determined by polling the flag bits in Bank 0-RE and Bank 0-RF. The
interrupt flag bit must be cleared by instructions before leaving the interrupt service
routine to avoid recursive interrupts.
When interrupt mask bits is “Enable”, the flag in the Interrupt Status Register (RF) is set
regardless of the ENI execution. Note that the result of Bank 0-RE/RF will be the logic
AND of BANK 0-RE/RF and Bank 1-RE/RF (refer to Fig. 6-8). The RETI instruction
ends the interrupt routine and enables the global interrupt (the ENI execution).
When any interrupt occurs, the contents of ACC, R1 (Bits 5, 4, 1, 0), R3 (Bits 2 ~0), R4
registers are pushed to the corresponding stack (Fig 6-9). After the RETI instruction is
executed, the content of the corresponding stack are popped to ACC, R1 (Bits 5, 4, 1, 0),
R3 (Bits 2 ~0), R4 registers.
Product Specification (V1.0) 10.19.2007
36 •
(This specification is subject to change without further notice)
BANK0-RE/RF
BANK1-RE/RF
BANK1-RE/RF RD
BANK0-RE/RF RD
BANK1-RE/RF WR
EM78P221/2N
8-Bit Microcontroller with OTP ROM
Interrupt Sources
ENI/DISI
BANK0-RE/RF WR
Fig. 6-8 Interrupt Input Circuit
ACC
R1 (5, 4 ,1 ,0)
R3 (2 ~0)
R4
Fig. 6-9 Interrupt Backup Diagram
Interrupt
occurs
RETI
Stack ACC
Stack R1
Stack R3
Stack R4
Product Specification (V1.0) 10.19.2007 • 37
(This specification is subject to change without further notice)
EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.7 Comparator
The EM78P221/2N has one comparator comprising of two analog inputs and one
output. The comparator can be utilized to wake up the EM78P221/2N from sleep
mode. The comparator circuit diagram is depicted in the figure below.
ERC1 (External RC oscillator mode); P52/OSCO act as P52 0 0 0
ERC1 (External RC oscillator mode); P52/OSCO act as OSCO 0 0 1
IRC2 (Internal RC oscillator mode); P52/OSCO act as P52 0 1 0
IRC2 (Internal RC oscillator mode); P52/OSCO act as OSCO 0 1 1
LXT13 (Frequency range of XT mode is 1MHz~100kHz) 1 0 0
HXT13 (Frequency range of XT mode is 16MHz~6MHz) 1 0 1
LXT23 (Frequency range of XT mode is 32kHz) 1 1 0
HXT23 (Frequency range of XT mode is 6MHz~1MHz) (Default)1 1 1
1
In ERC mode, OSCI is used as oscillator pin. OSCO/P52 is defined by code option Word 0 Bit 6 ~ Bit 4.
2
In IRC mode, P53 is normal I/O pin. OSCO/P52 is defined by code option Word 0 Bit 6 ~ Bit 4.
3
In LXT1, LXT2, HXT1 and HXT2 modes; OSCI and OSCO are used as oscillator pins. These pins cannot
and should not be defined as normal I/O pins.
Bit 3: Not used (Reserved). This bit is set to 0 all the time
Bits 2 ~ 0 (PR2 ~ PR0): Protect Bits
PR2 ~ PR0 are protect bits. Each protect status is as follows:
PR2 PR1 PR0 Protect
0 0 0 Enable
1 1 1 Disable (Default)
Product Specification (V1.0) 10.19.2007
48 •
(This specification is subject to change without further notice)
EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.11.2 Code Option Register (Word 1)
Word 1
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
- -
RESET
Bit 12: Not used (reserved), fixed to “1” all the time.
Bit 11: Not used (reserved), fixed to “0” all the time.
Bit 10 (RESETENB): P81/RESET pin select bit
Bit 9 (RCOUT): System clock output enable bit in IRC or ERC mode
RCOUT NRHL NRE - C3 C2 C1 C0 RCM1 RCM0
ENB
0 = P81 set as /RESET pin
1 = P81 is general purpose input pin or open drain for output port
(Default)
0 = OSCO pin is open drain
1 = OSCO output instruction clock (Default)
Bit 8 (NRHL): Noise rejection high/low pulse define bit. INT pin has a falling edge
trigger.
0 = Pulses equal to 8/fc are regarded as signal
1 = Pulses equal to 32/fc are regarded as signal (Default)
Input High Threshold
Voltage (Schmitt Trigger)
Input Low Threshold Voltage
(Schmitt Trigger)
Input Leakage Current
for input pins
Input High Voltage
(Schmitt Trigger)
Input Low Voltage
(Schmitt Trigger)
Input High Threshold
Voltage (Schmitt Trigger)
Input Low Threshold Voltage
(Schmitt Trigger)
Input High Threshold
Voltage (Schmitt Trigger)
Input Low Threshold Voltage
(Schmitt Trigger)
Output High Voltage
(Ports 5, 6, 7, 8)
Output High Voltage
(Ports 6)
Output Low Voltage
(Ports 5, 6, 7, 8 )
Output Low Voltage
(Ports 5, 6)
OSCI in RC mode −
OSCI in RC mode −
VIN = VDD, VSS –1.0
Ports 5, 6, 7, 8 −
Ports 5, 6, 7, 8 −
/RESET −
/RESET −
TCC, INT −
TCC, INT −
VOH = 0.9VDD − -9 − mA
VOH = 0.7VDD − -27 − mA
VOL = 0.1VDD − 16.8 − mA
VOL = 0.3VDD − 67.2 − mA
3.75
1.25
0
3.75
1.25
1.9
1.2
3.75
1.25
3.75
1.25
− V
− V
1.0 μA
− V
− V
− V
− V
− V
− V
− V
− V
EM78P221/2N
8-Bit Microcontroller with OTP ROM
Symbol Parameter Condition Min. Typ. Max. Unit
IPH
IPL
ISB1 Power down current
ISB2 Power down current
ISB3 Power down current
ICC1
ICC2
ICC3
ICC4
Pull-high current
(Ports 50~53, 64~67)
Pull-low current
(Ports 60~67)
Operating supply current
at two clocks (VDD=3V)
Operating supply current
at two clocks (VDD=3V)
Operating supply current
at two clocks (VDD=5V)
Operating supply current
at two clocks (VDD=5V)
Pull-high active, input pin at VSS
Pull-low active, input pin at Vdd
All input and I/O pins at VDD,
Output pin floating, LVR disabled
WDT disabled,
All input and I/O pins at VDD,
Output pin floating, LVR Disabled
WDT enabled,
All input and I/O pins at VDD,
Output pin floating, LVR enabled
WDT disabled