IBM EM78P221, EM78P222N User Manual

EM78P221/2N

8-Bit Microcontroller

with OTP ROM

Product

Specification

DOC. VERSION 1.0

ELAN

MICROELECTRONICS CORP.

October 2007

T rademark Acknowledgments:

IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation.

ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation.

Printed in Taiwan

The contents of this specification are subject to change without further notice. ELAN Microelectronics assume s no responsibility concerning the accuracy , adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirm ed order.

In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the informat ion or material contai ned in this specifi cation. ELAN Mi croelectronics shall n ot be liable for direct, indirect, special incidental, or cons equenti al dama ges arising f rom the us e of such i nformat ion or material.

The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement.

ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohib ited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.

ELAN MICROELECTRONICS CORPORATION

Headquarters:

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Contents

EM78P221/2N-V Package version.................................................................................... 1

EM78P221/2N-U Package version ................................................................................... 1

1 General Description.................................................................................................. 2

2 Features ..................................................................................................................... 2

3 Pin Assignment......................................................................................................... 3

4 Pin Description.......................................................................................................... 4

4.1 EM78P222N ....................................................................................................... 4

4.2 EM78P221N ....................................................................................................... 5

5 Block Diagram........................................................................................................... 6

6 Function Description ................................................................................................ 7

6.1 Register Configuration........................................................................................ 7

6.2 Registers Description ......................................................................................... 8

6.2.1 A (Accumulator)...................................................................................................8

6.2.2 CONT (Control Register).....................................................................................8

6.2.3 R0 (Indirect Addressing Register) ......................................................................9

6.2.4 R1 (Memory Switch Register) .............................................................................9

6.2.5 R2 (Program Counter and Stack)........................................................................9

6.2.6 R3 (Status Register)..........................................................................................10

6.2.7 R4 (Select Indirect Address) ............................................................................. 11

6.2.8 Bank 0-R5 (Port 5) ............................................................................................11

6.2.9 Bank 0-R6 (Port 6) ............................................................................................11

6.2.10 Bank 0-R7 (Port 7) ............................................................................................11

6.2.11 Bank 0-R8 (Port 8) ............................................................................................11

6.2.12 Bank 0-R9~RD (Reserve) .................................................................................11

6.2.13 Bank 0-RE (WUCR: Wake-up Control Register)...............................................12

6.2.14 Bank 0-RF (Interrupt Status Register)...............................................................12

6.2.15 Bank 1-R5 ~R7 (I/O Port Control Register).......................................................13

6.2.16 Bank 1-R8 (I/O Port Control Register) ..............................................................13

6.2.17 Bank 1-R9 (Reserve).........................................................................................14

6.2.18 Bank 1-RA (CMPCON: Comparator Control Register) .....................................14

6.2.19 Bank 1-RB (Pull-down Control Register)...........................................................15

6.2.20 Bank 1-RC (Open-Drain Control Register) .......................................................15

6.2.21 Bank 1-RD (Pull-high Control Register) ............................................................16

6.2.22 Bank 1-RE (WDT Control Register) ..................................................................16

6.2.23 Bank 1-RF (Interrupt Mask Register) ................................................................17

6.2.24 Bank 2-R5 (HDCR: High Drive Control Register for Port 6)..............................18

6.2.25 Bank 2-R6 (HSCR1: High Sink Control Register for Port 5) .............................18

6.2.26 Bank 2-R7 (HSCR2: High Sink Control Register for Port 6) .............................19

Product Specification (V1.0) 10.19.2007 • iii

(This specification is subject to change without further notice)

Contents

6.2.27 Bank 2-R8 (Operating Mode Control Register).................................................19

6.2.28 Bank 2-R9~RF (Reserve)..................................................................................19

6.2.29 Bank 3-R5 (Timer Clock/Counter).....................................................................19

6.2.30 Bank 3-R6 (IRC Control)-only for ICE ...............................................................20

6.2.31 Bank 3-R7 (Noise and LVR Control) - only for ICE ...........................................21

6.2.32 Bank 3-R8~RF (Reserve)..................................................................................21

6.2.33 R10 ~ R1F .........................................................................................................21

6.2.34 Banks 0~3 - R20 ~ R3F ....................................................................................21

6.3 TCC/WDT and Prescaler.................................................................................. 22

6.4 I/O Ports ........................................................................................................... 23

6.4.1 Usage of Port 6 Input Change Wake-up/Interrupt Function..............................25

6.5 Reset and Wake-up.......................................................................................... 26

6.5.1 Reset and Wake-up Operation..........................................................................26

6.5.1.1 Wake-up and Interrupt Modes Operation Summary ..........................28

6.5.1.2 Register Initial Values after Reset ......................................................30

6.5.1.3 Controller Reset Block Diagram........................................................34

6.5.2 The T and P Status under Status Register........................................................35

6.6 Interrupt ............................................................................................................ 36

6.7 Comparator ...................................................................................................... 38

6.7.1 External Reference Signal ................................................................................38

6.7.2 Comparator Outputs..........................................................................................38

6.7.3 Using a Comparator as an Operation Amplifier.................................................39

6.7.3.1 Bank 0-RE (WUCR: Wake-up Control Register)................................39

6.7.3.2 Bank 1-RA (CMPCON: Comparator Control Register) ......................40

6.7.3.3 Bank 1-RE (WDT Control Register) ...................................................40

6.7.4 Comparator Interrupt.........................................................................................40

6.7.5 Wake-up from Sleep Mode................................................................................40

6.8 Oscillator .......................................................................................................... 41

6.8.1 Oscillator Modes................................................................................................41

6.8.2 Crystal Oscillator/Ceramic Resonators (Crystal)...............................................41

6.8.3 External RC Oscillator Mode.............................................................................44

6.8.4 Internal RC Oscillator Mode ..............................................................................45

6.9 Power-on Considerations ................................................................................. 45

6.9.1 External Power-on Reset Circuit .......................................................................45

6.9.2 Residual Voltage Protection ..............................................................................46

6.10 Low Voltage Reset ........................................................................................... 46

6.11 Code Option ..................................................................................................... 47

6.11.1 Code Option Register (Word 0).........................................................................47

6.11.2 Code Option Register (Word 1).........................................................................49

6.11.3 Customer ID Register (Word 2).........................................................................50

6.12 Instruction Set .................................................................................................. 50

iv •

Product Specification (V1.0) 10.19.2007

(This specification is subject to change without further notice)

Contents

7 Absolute Maximum Ratings................................................................................... 53

8 DC Electrical Characteristics................................................................................. 53

8.1 Comparator (OP) Characteristic....................................................................... 55

9 AC Electrical Characteristic................................................................................... 55

10 Timing Diagrams..................................................................................................... 56

APPENDIX

A Package Type........................................................................................................... 57

B Packaging Configuration........................................................................................ 58

B.1 24-Lead Plastic Skinny Dual in line (SDIP) — 300 mil ..................................... 58

B.2 24-Lead Plastic Small Outline (SOP) — 300 mil .............................................. 59

B.3 24-Lead Plastic Shrink Small Outline (SSOP) — 209 mil ................................ 60

B.4 28- Lead Plastic Skinny Dual in line (SDIP) — 300 mil .................................... 61

B.5 28-Lead Plastic Small Outline (SOP) — 300 mil .............................................. 62

B.6 28- Lead Plastic Shrink Small Outline (SSOP) — 209 mil ............................... 63

C Quality Assurance and Reliability ........................................................................ 64

C.1 Address Trap Detect......................................................................................... 64

Product Specification (V1.0) 10.19.2007 • v

(This specification is subject to change without further notice)

Contents

Specification Revision History

Doc. Version Revision Description Date

0.9 Preliminary version 2007/03/20

1.0 Initial released version 2007/10/19

vi •

Product Specification (V1.0) 10.19.2007

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

Read Me First !

Comparison between V-Package and U-Package version

This series of microcontrollers comprise of the older V-package version and the newer

U-package version. In the newer U-package version, a Code Option NRM is added

and various features such as Crystal mode Operating frequency range, IRC mode

wake-up time, WDT Time-out time, Comparator function and Pins function have been

modified to favorably meet users’ requirements. The following table is provided for

quick comparison between the two package version and for user convenience in the

choice of the most suitable product for their application.

EM78P221/222N-V EM78P221/222N-U

Crystal mode Operating

frequency range at 0°C~ 70°C

IRC mode wake-up time

Sleep mode → Normal mode

Condition: 5V, 4MHz

P52, P53 Function Output only Input / Output

Comparator Function Comparator only Comparator / OPA

WDT Time-out time

(Prescaler = 1 : 1)

Condition: VDD = 5V

Code Option

DC ~ 12MHz, 4.0V

DC ~ 8MHz, 3.0V

DC ~ 4MHz, 2.1V

64μs 10μs

16.5 ms ± 30 % 15.2 ms ± 30 %

DC ~ 16MHz, 4.5V

DC ~ 8MHz, 3.0V

DC ~ 4MHz, 2.1V

Added a Code Option NRM

EM78P221/2N-V Package version EM78P221/2N-U Package version

Product Specification (V1.0) 10.19.2007 • 1

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

1 General Description

EM78P221N and EM78P222N are 8-bit microprocessors designed and developed with low-power and high-speed CMOS technology. Each device in the series has as an on-chip 4K×13-bit Electrical One Time Programmable Read Only Memory (OTP-ROM). Each provides a protection bit to prevent intrusion of user’s OTP memory code. Two Code option bits are also available to meet user’s requirements.

With its enhanced OTP-ROM features, each device provides a convenient way of developing and verifying user’s programs. Moreover, this OTP devices offer the advantages of easy and effective program updates, using development and programming tools. User can avail of the ELAN Writer to easily program his development code.

2 Features

 CPU configuration

• 4K×13 bits on-chip OTP-ROM

• 144×8 bits on-chip registers (SRAM)

• 8-level stacks for subroutine nesting

• 3 programmable Level Voltage Reset

(LVR) : 4.0V, 3.0V, 2.5V

• Less than 1.5 mA at 5V/4MHz

• Typically 15 μA, at 3V/32kHz

• Typically 2 μA, during sleep mode

 I/O port configuration

• 4 bidirectional I/O ports: P5, P6, P7 and P8

• Wake-up port : P6

• 26 I/O pins

• 8 programmable pull-down I/O pins

• 8 programmable pull-high I/O pins

• 8 programmable open-drain I/O pins

• 16 Programmable high sink current I/O pins

• 8 Programmable high drive current I/O pins

• External interrupt : P77, P71

 Operating voltage range:

• OTP version:

Operating voltage range: 2.1V~5.5V (commercial)

Operating voltage range: 2.3V~5.5V (industrial)

 Operating temperature range:

Operating temperature range: 0°C~70°C

(commercial)

Operating temperature range: -40°C~85°C

(industrial)

 Operating frequency range

• Crystal mode:

DC~16MHz/2 clks @ 4.5V; DC~125ns inst. cycle @ 4.5V

DC ~ 8MHz/2 clks @ 3V; DC~250ns inst. Cycle @ 3V

• ERC mode:

DC ~ 16MHz/2 clks @ 4.5V; DC~125ns inst. cycle @ 5V

DC ~ 8MHz/2 clks @ 3V; DC ~ 250ns inst. Cycle @ 3V

• IRC mode:

Oscillation mode: 16MHz, 4 MHz, 1 MHz, 455kHz

Process deviation: Typ ± 3%, Max. ± 5%

Temperature deviation: ± 5% (-40°C~85°C)

Product Specification (V1.0) 10.19.2007

2 •

(This specification is subject to change without further notice)

Internal RC

Frequency

4MHz ±5% ±5% ±4% ±14%

16MHz ±5% ±5% ±4% ±14%

1MHz ±5% ±5% ±4% ±14%

455kHz ±5% ±5% ±4% ±14%

All these four main frequencies can be trimmed by

programming with four calibrated bits in the ICE220N

Simulator. OTP is auto trimmed by ELAN Writer

(DWTR).

 Fast set-up time requires only 800μs (VDD:5V,

Crystal: 4MHz, C1/C2: 30pF) in HXT2 mode and 10μs in IRC mode (VDD:5V IRC:4MHz)

 Peripheral configuration

• 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt

• One comparator (can act as an OP). (offset voltage is smaller than 10mV)

 Five available interrupts

• TCC overflow interrupt

• Input-port status changed interrupt (wake up from

sleep mode)

• Two External interrupts

• Comparator high/low interrupt

 Special Features

• Programmable free running Watchdog Timer

• Two clocks per instruction cycle

• Power-on voltage detector available (1.8 V± 0.1V)

• High EFT immunity (better performance at 4MHz or

below

• Power saving Sleep mode

• Selectable Oscillation mode

• Package Type:

• 24-pin skinny DIP 300mil : EM78P221NKJ/NKS

• 24 pin SOP 300mil : EM78P221NMJ/NMS

• 24 pin SSOP 209mil : EM78P221NAMJ/NAMS

• 28-pin skinny DIP 300mil : EM78P222NKJ/NKS

• 28 pin SOP 300mil : EM78P222NMJ/NMS

• 28 pin SSOP 209mil : EM78P222NAMJ/NAMS

Temperature

(-40°C+85°C)

Drift Rate

Voltage

(2.1V~5.5V)

Process Total

3 Pin Assignment

(1) 28-Pin DIP/SOP/SSOP

8-Bit Microcontroller with OTP ROM

(2) 24-Pin DIP/SOP/SSOP

EM78P221/2N

P55

P56/TCC

P77/INT0

VSS

P60 P61 P62

P63 P64 P50 P51

P80 P76

EM78P222N

Fig. 3-1 EM78P222NK/AK/M/AM

P81//RESET

P53/OSCI

P52/OSCOVDD

P70 P71/CO/INT1

P72/CIN+ P73/CIN-

P67

P66

P65

P57 P54

P74 P75

P55

VSS

P60

P61

P62 P63

P64

P50 P51

EM78P221N

P56/TCC

P77/INT0

P81//RESET P53/OSCI P52/OSCOVDD

P70 P71/CO/INT1 P72/CIN+

P73/CINP67

P66

P65

P57 P54

Fig. 3-2 EM78P221NK/M/AM

Product Specification (V1.0) 10.19.2007 • 3

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

4 Pin Description

4.1 EM78P222N

Symbol Pin No. Type Function

1~2

P50~P57

P60~P67

P70~ P77

P80, P81

CINCIN+ CO

OSCI

OSCO

/RESET

INT0~INT1

VDD

VSS

11~12 17~18 26~27

6 ~ 10

19 ~21

14 ~ 16

22~25

13, 28 I/O

22 23 24

27 I

26 O

28 I

5, 24 I

3 -

4 -

I/O

8-bit General purpose input/output pins Default value at power-on reset

8-bit General purpose input/output pins Default value at power-on reset.

P72 and P73 are open drain pins when used as output pins in ICE220N simulator.

2-bit General purpose input or output pin Default value at power-on reset

P81 is define as General purpose input or output open-drain pin.

“-“ : input pin of Vin- of the comparator

“+” : input pin of Vin+ of the comparator

Pin CO is the comparator output Defined by CMPCON (Bank 1-RA) <3 : 4>

Crystal type: Crystal input terminal RC type: RC oscillator input pin

Crystal type: Output terminal for crystal oscillator. RC type: Clock output with a duration of one instruction cycle

time.

External clock signal input.

If it remains at a logic low, the device will be reset Wake-up from sleep mode when pin status changes Voltage on /RESET must not exceed Vdd during normal mode

External interrupt pin

Power supply

Ground

Product Specification (V1.0) 10.19.2007

4 •

(This specification is subject to change without further notice)

4.2 EM78P221N

Symbol Pin No. Type Function

P50~P57

P60~P67

P70~P73 P77

P81

CINCIN+ CO

OSCI

OSCO

/RESET

INT0~INT1

VDD

VSS

1~2 11~14 22~23

6 ~ 10 15~17

21 ~ 18

24 I/O

18 19 20

23 I

22 O

24 I

5, 20 I

3 -

4 -

I/O

I I

EM78P221/2N

8-Bit Microcontroller with OTP ROM

8-bit General purpose input/output pins Default value at power-on reset.

8-bit General purpose input/output pins Default value at power-on reset

5-bit General purpose input/output pins Default value at power-on reset

P72 and P73 are open drain pins when used as output pins of the ICE220N simulator.

1-bit General purpose input or output open-drain pin Default value at power-on reset

“-“ : input pin of Vin- of the comparator “+” : input pin of Vin+ of the comparator Pin CO is the comparator output Defined by CMPCON (Bank 1-RA) <3 : 4>

Crystal type: Crystal input terminal RC type: RC oscillator input pin

Crystal type: Output terminal for crystal oscillator RC type: Clock output with a duration of one instruction cycle

time.

External clock signal input.

If it remains at logic low, the device will be reset Wake-up from sleep mode when pin status changes Voltage on /RESET must not exceed Vdd during normal mode

External interrupt pin

Power supply

Ground

Product Specification (V1.0) 10.19.2007 • 5

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

5 Block Diagram

P80 P81

P70 P71 P72 P73 P74

P75 P76 P77

P60 P61 P62 P63

P64 P65 P66 P67

P50 P51 P52 P53

P54 P55 P56

P57

ACC

ROM

Instruction

Decoder

ALU

R3 (Status

Reg.)

8-level stack

(13 bit)

Interrupt

Control

Interrupt

Circuit

Ext.

OSC.

Int. RC

Oscillation

Generation

Reset

Mux

RAM

Ext.

WDT

TCC

Port

change

LVR

Comparator

TCC

Port 6

Ext INT

Cin+ Cin- CO

Fig. 5-1 EM78P221/2N Functional Block Diagram

6 •

(This specification is subject to change without further notice)

Product Specification (V1.0) 10.19.2007

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6 Function Description

6.1 Register Configuration

Address Bank 0 Registers Bank 1 Registers Bank 2 Registers Bank 3 Registers

00 R0 (Indirect Addressing Register) 01 R1 (Memory switch register) 02 R2 (Program Counter) 03 R3 (Status Register) 04 R4 (Select Indirect Address)

05 R5 (Port 5)

06 R6 (Port 6)

07 R7 (Port 7)

08 R8 (Port 8)

09 Reserve Reserve Reserve Reserve

0A Reserve

0B Reserve

0C Reserve

0D Reserve

RE (Wake-up Control

RF (Interrupt Status

General Registers (16×8 bits)

General Registers

(32×8 bits)

R5 (I/O Port Control

R6 (I/O Port Control

R7 (I/O Port Control

R8 (I/O Port Control

RA (Comparator Control

RB (Pull-down Control

RC (Open-drain Control

RD (Pull-high Control

RE (WDT Control

RF (Interrupt Mask

General Registers

(32×8 bits)

R5 (High Drive Control

R6 (High Sink Control

R7 (High Sink Control

Reserve Reserve

General Registers

(32×8 bits)

R5 (Timer Clock /

Counter)

Reserve*

General Registers

(32×8 bits)

Note: 1. All registers are 8 bits.

2. When using ICE, some registers code options are set. Refer to Section 6.2 for detailed Registers Description.

3. Registers with * can only be used in ICE220N simulator.

Product Specification (V1.0) 10.19.2007 • 7

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.2 Registers Description

6.2.1 A (Accumulator)

Internal data transfer operation, or instruction operand holding usually involves the

temporary storage function of the Accumulator. The Accumulator is not an

addressable register.

6.2.2 CONT (Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTE INT TS TE PSTE PST2 PST1 PST0

Bit 7 (INTE): INT signal edge 0 = interrupt occurs at the rising edge on the INT0 and INT1 pin 1 = interrupt occurs at the falling edge on the INT0 and INT1 pin

Bit 6 (INT): Interrupt enable flag 0 = masked by DISI or hardware interrupt 1 = enabled by the ENI/RETI instructions

This bit is readable only. Bit 5 (TS): TCC signal source

0 = internal instruction cycle clock. If P56 is used as I/O pin, TS must be 0. 1 = transition on the TCC pin

Bit 4 (TE): TCC signal edge 0 = increment if the transition from low to high takes place on the TCC pin 1 = increment if the transition from high to low takes place on the TCC pin.

Bit 3 (PSTE): Prescaler enable bit for TCC 0 = prescaler disable bit. TCC rate is 1:1 1 = prescaler enable bit. TCC rate is set as Bit 2 ~ Bit 0.

Bit 2 ~ Bit 0 (PST2 ~ PST0): TCC prescaler bits

PST2 PST1 PST0 TCC Rate

0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256

Note: Tcc time-out period [1/Fosc x prescaler x (256 -Tcc cnt) x 1] Fosc: Oscillator (Crystal, ERC, IRC) frequency

Product Specification (V1.0) 10.19.2007

8 •

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.2.3 R0 (Indirect Addressing Register)

R0 is not a physically implemented register. Its major function is to perform as an

indirect address pointer. Any instruction using R0 as a pointer, actually accesses the

data pointed by the RAM Select Register (R4).

6.2.4 R1 (Memory Switch Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

“0” “0” “0” “0” “0” “0” BS1 BS0

Bits 7~2: not used bits, fixed to 0 all the time. Bits 1~0: used to select Banks 0 ~ 3 for R20~R3F and select Banks 0 ~ 3 for the

control register.

See the table under Section 6.2 Registers Description for the data memory

configuration.

6.2.5 R2 (Program Counter and Stack)

A11 A10

R1(5,4)

00 PAGE0 0000~03FF

01 PAGE1 0400~07FF

10 PAGE2 0800~0BFF

11 PAGE3 0C00~0FFF

A9 ~ A0

CALL RET RETL

RETI

Stack Level 1 Stack Level 2 Stack Level 3 Stack Level 4 Stack Level 5

Stack Level 6 Stack Level 7 Stack Level 8

Fig. 6-1 Program Counter Organization

Reset Vector

Interrupt Vector

On-chip Program

Memory

R2 and hardware stacks are 12-bit wide. The structure is depicted in the table under

Section

6.1 Register Configuration.

Generates 4K×13 bits on-chip ROM addresses to the relative programming instruction

codes. One program page is 1024 words long.

000H 008H

User Memory Space

FFFH

The contents of R2 are all set to "0"s when a reset condition occurs.

Product Specification (V1.0) 10.19.2007 • 9

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,

"JMP" allows PC to jump to any location within a Page (1K).

"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the

stack. Thus, the subroutine entry address can be located anywhere within a page (1K).

"LJMP" instruction allows direct loading of the lower 11 program counter bits.

Therefore, "LJMP" allows PC to jump to any location within 2K (2

"LCALL" instruction loads the lower 11 bits of the PC, and then PC+1 are pushed onto

the stack. Thus, the subroutine entry address can be located anywhere within 2K (2

"RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the

top of stack.

"ADD R2, A" allows a relative address to be added to the current PC, and the ninth and

above bits of the PC will increase progressively.

"MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits of the

PC, and the ninth and above bits of the PC will remain unchanged.

Any instruction (except “ADD R2,A”) that is written to R2 (e.g., "MOV R2, A", "BC R2, 6"

etc.) will cause the ninth bit and above bits of the PC to remain unchanged.

All instructions are single instruction cycle (fclk/2) except “LCALL” and “LJMP”

instructions. The “LCALL” and “LJMP” instructions need two instructions cycle.

6.2.6 R3 (Status Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

- - - T P Z DC C

Bits 7~5: not used, fixed to 0 all the time. Bit 4 (T): Time-out bit. Set to 1 by the "SLEP" and "WDTC" commands or during

power on and reset to 0 by WDT time-out.

Bit 3 (P): Power-down bit. Set to 1 during power on or by a "WDTC" command

and reset to 0 by a "SLEP" command.

NOTE

Bit 4 & Bit 3 (T & P) are read only.

Bit 2 (Z): Zero flag. Set to "1" if the result of an arithmetic or logic operation is

zero.

Bit 1 (DC): Auxiliary carry flag Bit 0 (C): Carry flag

Product Specification (V1.0) 10.19.2007

10 •

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.2.7 R4 (Select Indirect Address)

Bits 7~6: not used, fixed to 0 all the time. Bit 5 ~ Bit 0: used to select registers (Address: 00 ~ 3F) in indirect addressing mode.

6.2.8 Bank 0-R5 (Port 5)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

P57 P56 P55 P54 P53 P52 P51 P50

Bits 7 ~ 0 (P57 ~ P50): I/O data bits

6.2.9 Bank 0-R6 (Port 6)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

P67 P66 P65 P64 P63 P62 P61 P60

Bits 7 ~ 0 (P67 ~ P60): I/O data bits

6.2.10 Bank 0-R7 (Port 7)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

P77 P76 P75 P74 P73 P72 P71 P70

Bits 7 ~ 0 (P77 ~ P70): I/O data bits [With Simulator]: P73 ~ P72 are input or open-drain output pins. [With EM78P221/2N]: P73 ~ P72 are general input or output pins.

6.2.11 Bank 0-R8 (Port 8)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 0 NREN 0 0 0 P81 P80

Bits 7~6, 4~2, 0: not used, fixed to 0 all the time. Bit 5 (NREN): Noise rejection enable

0 = disable noise rejection (Default) 1 = enable noise rejection. However in crystal oscillator mode

(LXT2), the noise rejection circuit is always disabled.

Bits 1 ~0 (P81~P80): I/O data bit.

6.2.12 Bank 0-R9~RD (Reserve)

Bits 7~0: not used, fixed to "0" all the time.

Product Specification (V1.0) 10.19.2007 • 11

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.2.13 Bank 0-RE (WUCR: Wake-up Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

EX1IF 0 0 ICWE 0 CMPWE 0 CMPIF

Bit 7 (EX1IF): External interrupt flag. Set by INT1 pin, reset by software. 0 = no interrupt occurs 1 = with interrupt request

Bits 6~5, 3, 1: not used bits, fixed to 0 all the time Bit 4 (ICWE): Port 6 input change to wake-up status enable bit

0 = Disable Port 6 input change to wake-up status 1 = Enable Port 6 input change wake-up status

When the Port 6 Input Status Change is used to enter interrupt vector or

to wake-up EM78P221N//2N from sleep, the ICWE bit must be set to

“Enable“. Bit 2 (CMPWE): Comparator wake-up enable bit

0 = Disable Comparator wake-up 1 = Enable Comparator wake-up

When the Comparator output status change is used to enter interrupt

vector or to wake-up from sleep, the CMPWE bit must be set to

“Enable“.

Bit 0 (CMPIF): Comparator interrupt flag. Set when a change occurs in the output of

Comparator. Reset by software.

0 = no interrupt occurs 1 = with interrupt request

NOTE

■ Bank 0-RE <7, 0> can be cleared by instruction but cannot be set.

■ Bank1-RE <0> is an interrupt mask register.

■ Interrupt results from "logic AND" of Bank 0-RE <7, 0> and Bank 1-RE <0>, with

instruction “ENI”.

6.2.14 Bank 0-RF (Interrupt Status Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 0 0 0 0 EX0IF ICIF TCIF

Bits 7~3: not used bits, fixed to 0 all the time Bit 2 (EX0IF): External interrupt flag. Set by INT0 pin. Reset by software.

0 = no interrupt occurs 1 = with interrupt request

Product Specification (V1.0) 10.19.2007

12 •

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

Bit 1 (ICIF): Port 6 input status change interrupt flag. Set when Port 6 input changes.

Reset by software.

0 = no interrupt occurs 1 = with interrupt request

Bit 0 (TCIF): TCC overflow interrupt flag. Set when TCC overflows. Reset by software.

0 = no interrupt occurs 1 = with interrupt request

NOTE

■ Bank 0-RF <2, 1, 0> can be cleared by instruction but cannot be set.

■ Bank1-RF <2, 1, 0> is an interrupt mask register.

■ Interrupt results from "logic AND" of Bank 0-RF <2, 1, 0> and Bank 1-RF <2, 1, 0>

with instruction “ENI”.

6.2.15 Bank 1-R5 ~R7 (I/O Port Control Register)

Bits 7~0: 0 = defines the relative I/O pin as output 1 = puts the relative I/O pin into high impedance Bank 1-R5, R6 and R7 registers are all readable and writable.

6.2.16 Bank 1-R8 (I/O Port Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 0 0 0 0 0 C81 C80

Bits 7~2: not used, fixed to 0 all the time Bits 1~0 (C81~C80): 0 = defines the relative I/O pin as output 1 = puts the relative I/O pin into high impedance

With Simulator]: P80 and P81 are General I/O pins [With EM78P221/2N]: P80 is General input or output, but P81 is input or open-drain

output pin.

Product Specification (V1.0) 10.19.2007 • 13

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.2.17 Bank 1-R9 (Reserve)

Bits 7~0: not used, fixed to 0 all the time

6.2.18 Bank 1-RA (CMPCON: Comparator Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

EIS1 EIS0 CMPOUT CMPCOS1 CMPCOS0 0 0 0

Bit 7 (EIS1): Control bit used to define the function of the P71 (/INT1) pin

0 = P71, normal I/O pin 1 = /INT1, external interrupt pin. In this case, the I/O control bit of P71

(Bit 1 of Bank 1-R7) must be set to "1"

Bit 6 (EIS0): Control bit used to define the function of the P77 (/INT0) pin

0 = P77, normal I/O pin 1 = /INT0, external interrupt pin. In this case, the I/O control bit of P77

(Bit 7 of Bank 1-R7) must be set to "1"

NOTE

 When EIS is "0," the path of /INT is masked. When EIS is "1," the status of /INT

pin can also be read by way of reading Port 7 (Bank 0-R7). Refer to Fig. 6-4 (I/O Port and I/O Control Register Circuit for P77 (/INT0) and P71 (/INT1) under Section 6.4 (I/O Ports).

 EIS0 and EIS1 are both readable and writable.

 The highest priority of P71/INT1/CO2 is INT1. When EIS1=0, the working type

of P71/INT1/CO is determined by CMPCOS1 and CMPCOS0.

Bit 5 (CMPOUT): The result of the comparator output Bit 4 ~ Bit 3 (CMPCOS1 ~ CMPCOS0): Comparator Select bits

CMPCOS1 CMPCOS0 Function Description

0 0

0 1

1 0

1 1 Used as OP and P71 is OP output pin (CO)

Comparator is not used. P72, P73 and P71 are normal I/O pins

P72 and P73 are Comparator input pins and P71 is normal I/O pin

P72 and P73 are Comparator input pins and P71 is Comparator output pin (CO)

Bits 2~0: not used, fixed to 0 all the time

Product Specification (V1.0) 10.19.2007

14 •

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.2.19 Bank 1-RB (Pull-down Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

/PD7 /PD6 /PD5 /PD4 /PD3 /PD2 /PD1 /PD0

Bank 1-RB register is both readable and writable Bit 7 (/PD7): Control bit used to enable the pull-down function of the P67 pin

0 = Enable internal pull-down function 1 = Disable internal pull-down function

Bit 6 (/PD6): Control bit used to enable the pull-down function of the P66 pin. Bit 5 (/PD5): Control bit used to enable the pull-down function of the P65 pin. Bit 4 (/PD4): Control bit used to enable the pull-down function of the P64 pin. Bit 3 (/PD3): Control bit used to enable the pull-down function of the P63 pin. Bit 2 (/PD2): Control bit used to enable the pull-down function of the P62 pin. Bit 1 (/PD1): Control bit used to enable the pull-down function of the P61 pin. Bit 0 (/PD0): Control bit used to enable the pull-down function of the P60 pin.

6.2.20 Bank 1-RC (Open-Drain Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

/OD7 /OD6 /OD3 /OD2 /OD5 /OD4 /OD1 /OD0

Bank 1-RC register is both readable and writable. Bit 7 (OD7): Control bit used to enable the open-drain output of the P57 pin.

0 = Enable open-drain output

1 = Disable open-drain output

Bit 6 (OD6): Control bit used to enable the open-drain output of the P56 pin. Bit 5 (OD5): Control bit used to enable the open-drain output of the P55 pin. Bit 4 (OD4): Control bit used to enable the open-drain output of the P54 pin. Bit 3 (OD3): Control bit used to enable the open-drain output of the P53 pin. Bit 2 (OD2): Control bit used to enable the open-drain output of the P52 pin. Bit 1 (OD1): Control bit used to enable the open-drain output of the P51 pin. Bit 0 (OD0): Control bit used to enable the open-drain output of the P50 pin.

Product Specification (V1.0) 10.19.2007 • 15

(This specification is subject to change without further notice)

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