Cascadable Silicon Bipolar
MMIC␣ Amplifier
Technical Data
MSA-0100
Features
• Cascadable 50 Ω Gain Block
• 3 dB Bandwidth:
DC to 1.3 GHz
• High Gain:
18.5 dB Typical at 0.5 GHz
• Unconditionally Stable
(k>1)
Description
The MSA-0100 is a high performance
silicon bipolar Monolithic Microwave
Integrated Circuit (MMIC) chip. This
MMIC is designed for use as a general
purpose 50 Ω gain block. Typical
The MSA-series is fabricated using
HP’s 10 GHz f
bipolar MMIC process which uses
nitride self-alignment, ion implantation, and gold metallization to
achieve excellent performance,
uniformity and reliability. The use
of an external bias resistor for
temperature and current stability
also allows bias flexibility.
The recommended assembly
procedure is gold-eutectic die
attach at 400° C and either wedge or
ball bonding using 0.7 mil gold
wire.
“Chip Use”.
applications include narrow and
broad band IF and RF amplifiers in
commercial, industrial and military
applications.
Typical Biasing Configuration
R
bias
, 25␣ GHz f
T
[1]
See APPLICATIONS section,
V
> 7 V
CC
MAX
, silicon
Chip Outline
Note:
1. This chip contains additional biasing
options. The performance specified
applies only to the bias option whose
bond pads are indicated on the chip
outline. Refer to the APPLICATIONS
section “Silicon MMIC Chip Use” for
additional information.
[1]
RFC (Optional)
C
block
IN OUT
MSA
C
block
= 5 V
V
d
5965-9689E
6-242
MSA-0100 Absolute Maximum Ratings
Parameter Absolute Maximum
Device Current 40 mA
(TMS)
[2,3]
= 25°C.
200 mW
␣>␣191 °C.
MS
than do alternate methods. See MEASURE-
jc
Power Dissipation
RF Input Power +20 dBm
Junction Temperature 200°C
Storage Temperature –65 to 200° C
Notes:
1. Permanent damage may occur if any of these limits are exceeded.
2. T
Mounting Surface
3. Derate at 22.2 mW/° C for T
4. The small spot size of this technique results in a higher, though more
accurate determination of θ
MENTS section “Thermal Resistance” for more information.
[1]
Thermal Resistance
θjc = 45°C/W
[2,4]
:
Electrical Specifications
Symbol Parameters and Test Conditions
G
P
∆G
P
f
3 dB
VSWR
Power Gain (|S21|2) f = 0.1 GHz dB 19.0
Gain Flatness f = 0.1 to 0.7 GHz dB ±0.6
3 dB Bandwidth GHz 1.3
Input VSWR f = 0.1 to 3.0 GHz 1.3:1
Output VSWR f = 0.1 to 3.0 GHz 1.3:1
[1]
, T
A
= 25° C
[2]
: Id = 17 mA, Z
= 50 Ω Units Min. Typ. Max.
O
NF 50 Ω Noise Figure f = 0.5 GHz dB 5.5
P
IP
t
V
1 dB
3
D
d
Output Power at 1 dB Gain Compression f = 0.5 GHz dBm 1.5
Third Order Intercept Point f = 0.5 GHz dBm 14.0
Group Delay f = 0.5 GHz psec 150
Device Voltage V 4.5 5.0 5.5
dV/dT Device Voltage Temperature Coefficient mV/°C –9.0
Notes:
1. The recommended operating current range for this device is 13 to 25 mA. Typical performance as a function of current
is on the following page.
RF performance of the chip is determined by packaging and testing 10 devices per wafer in a dual ground configuration.
2.
Part Number Ordering Information
Part Number Devices Per Tray
MSA-0100-GP4 100
6-243