HP HP500 Schematics

1

2

3

4

5

6

7

8

PCB STACK UP

LAYER 1 : TOP
LAYER 2 : SGND1
LAYER 3 : IN1

A A

LAYER 4 : IN2
LAYER 5 : VCC
LAYER 6 : IN3
LAYER 7 : SGND2
LAYER 8 : BOT

DDR2-SODIMM1

533/667 MHZ DDR II

SW7 BLOCK DIAGRAM

CPU
Merom

479P (uPGA)/46W

PG 3,4

CPU THERMAL SENSOR
FAN

PG 5

CLK_CPU_BCLK,CLK_CPU_BCLK#
CLK_MCH_BCLK,CLK_MCH_BCLK#

DREFCLK,DREFCLK#
DREFSSCLK,DREFSSCLK#

LVDS

CLOCK GEN

ALPR365K05
64pins

Panel Connector

01

14.318MHz

PG 2

PG 22

PG 13,14

DDR2-SODIMM2

533/667 MHZ DDR II

PG 13,14

B B

SATA - HDD

SATA

PG 28

SYSTEM CHARGER(MAX8724)

SYSTEM POWER MAX8778

C C

DDR II SMDDR_VTERM

1.8V/1.8VSUS(TPS51116REGR)

PAG 41

PAG 42

PAG 46

VCCP +1.5V AND GMCH

1.05V(MAX8717)

VGACORE(1.025V)MAX1992

PAG 43

PAG 45

PATA - ODD

PG 28

Bluetooth

PG 19

AUDIO

PG 25,26

Audio
Jacks

IDE

USB2.0 (P5)

Azalia

MODEM

PG 27

32.768KHz

PG 25

CPU CORE MAX8771

PAG 44

NORTH BRIDGE

Crestline

PG 6~12

32.768KHz

DMI LINK

SOUTH BRIDGE

ICH-8M

PG 15~18

LPC

KBC

ene

KB3926

PG 33

VGA

S-Video

USB2.0 (P2)
USB2.0 (P0,P1)

LAN

33MHz PCI
PCIEx2
USB2.0 (P6,P7)
USB2.0 P3

USB CAMERA

25MHz

PG 32

CRT Connector

PG 21

I/O Board Connector

(EXT Left Side)
(EXT Right Side)

MARVELL
8055/8039

PG 29

1394/Card Reader

PCI7402
PG 23,24

24.576MHz

SD/MMC/MS

CARD READER

PG 24

PG 20

NBSRCCLK, NBSRCCLK#

USB

PG 32

RJ45/Magnetics

PG 30

1394 P0

1394
CONNECTOR

PG 23

D D

Flash

PG 33

1

2

3

Keyboard
S/W&Led

PG 20

4

PS/2

Touchpad

PG 19

EXPRESS-CARD

MINI-CARD

WLAN
PG 31

5

6

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

7

BLOCK DIAGRAM

BLOCK DIAGRAM

BLOCK DIAGRAM

PROJECT : SW7

PROJECT : SW7

Quanta Computer Inc.

Quanta Computer Inc.

of

of

of

144Friday, September 28, 2007

144Friday, September 28, 2007

144Friday, September 28, 2007

8

1A

1A

1A

1

+3V +3V

L37

L37

1 2

BLM21PG600SN1D

BLM21PG600SN1D

120 ohms@100Mhz

C448

C448

4.7uF/6.3V_6

4.7uF/6.3V_6

C447

C447

4.7uF/6.3V_6

4.7uF/6.3V_6

2

12

C483

C483

0.1uF/10V

0.1uF/10V

12

C482

C482

0.1uF/10V

0.1uF/10V

12

C451

C451

0.1uF/10V

0.1uF/10V

3

+CK_VDD_MAIN

12

C466

C466

0.1uF/10V

0.1uF/10V

12

C485

C485

0.1uF/10V

0.1uF/10V

4

12

CLK_XTAL_IN

C474

C474
22pF/50V

22pF/50V

Y9

Y9

1 2

14.318MHZ

14.318MHZ

12

5

CLK_XTAL_OUT

C475

C475
22pF/50V

22pF/50V

6

CLK_3GPLLREQ#
NEW-CARD_CLK_REQ#

7

R282 10K/FR282 10K/F
R276 10K/FR276 10K/F

12
12

8

02

14.318MHz

A A

L36

L36

1 2

BLM21PG600SN1D

BLM21PG600SN1D

C449

C449

4.7uF/6.3V_6

4.7uF/6.3V_6

L39

L39

1 2

BLM21PG600SN1D

BLM21PG600SN1D

120 ohms@100Mhz

B B

0=overclocking
of CPU and
SRC Allowed

1 = overclocking
of CPU and SRC
not Allowed

C C

0=UMA
1 = External VGA

D D

C455

C455

4.7uF/6.3V_6

4.7uF/6.3V_6

+3V

R292

R292
10K/F

10K/F

1 2

TME

R285

R285
*4.7K

*4.7K

PCI_DBP

R301

R301
10K/F

10K/F

1 2

ITP_EN

12

10K/F

10K/F
R302

R302

Disable ITP

1

C450

C450

4.7uF/6.3V_6

4.7uF/6.3V_6

C453

C453

4.7uF/6.3V_6

4.7uF/6.3V_6

ICH_SMBDATA17,31

ICH_SMBCLK17,31

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

VDDCPU

12

C463

C463

0.1uF/10V

0.1uF/10V

12

12

C487 *33pF/50VC487 *33pF/50V
C503 *33pF/50VC503 *33pF/50V
C489 10pF/50VC489 10pF/50V
C488 *33pF/50VC488 *33pF/50V
C459 *33pF/50VC459 *33pF/50V

C245

C245

0.1uF/10V

0.1uF/10V

Q24

Q24
2N7002E

2N7002E

3

Q25

Q25
2N7002E

2N7002E

3

C486

C486

0.1uF/10V

0.1uF/10V

12

+3V

2

+3V

2

CLK_PCI_EC
CLK_PCI_PCCARD
CLK_PCI_ICH
CLK_PCI_DBP
CLK_ICH_14M

C484

C484

0.1uF/10V

0.1uF/10V

2

1

1

1

4

RP37

RP37
4P2R-S-2.2K

4P2R-S-2.2K

3

CLK_SDATA

CLK_SCLK

12

C464

C464

0.1uF/10V

0.1uF/10V

CK_PWG17

12

C465

C465

0.1uF/10V

0.1uF/10V

+CK_VDD_MAIN2

12

C467

C467

0.1uF/10V

0.1uF/10V

CPU_MCH_BSEL1

CLK_SCLK14,31
CLK_SDATA14,31

+CK_VDD_MAIN

VDDCPU

+CK_VDD_MAIN2

R280 4.7K/FR280 4.7K/F

CLK_SCLK
CLK_SDATA

CLK_XTAL_IN
CLK_XTAL_OUT

FSB

for EMI

CPU Clock select

CPU_MCH_BSEL03

CPU_MCH_BSEL13 MCH_BSEL1 7

CPU_MCH_BSEL23 MCH_BSEL2 7

2

R308 *56R308 *56
R306 1K/FR306 1K/F

R274 *0R274 *0
R273 1K/FR273 1K/F

R271 *0R271 *0
R270 1K/FR270 1K/F

3

R304 0R304 0

R279 0R279 0

R272 0R272 0

<FAE>
1K to NB only when
XDP is implement.No
XDP can use 0 ohm

4

U24

U24

16

VDDPLL3

9

VDD48

2

VDDPCI

61

VDDREF

39

VDDSRC

55

VDDCPU

12

VDD96I/O

20

VDDPLL3I/O

26

VDDSRCI/O

45

VDDSRCI/O

36

VDDSRCI/O

49

VDDCPU_IO

48

NC

60

X1

59

X2

56

CK_PWRGD/PD#

57

FSLB/TEST_MODE

64

SCLK

63

SDATA

15

GND

19

GND

11

GND48

52

GNDCPU

8

GNDPCI

58

GNDREF

23

GNDSRC

29

GNDSRC

42

GNDSRC

ICS9LPRS365AGLFT

ICS9LPRS365AGLFT

MCH_BSEL0 7

54

CPUCLKT0

53

CK505

CK505

27MHz_Nonss/SRCCLK1/SE1

FSC FSB
1330
0
0

1
1

0
00
1

033
1

1
1

1

5

CPUCLKC0

51

CPUCLKT1

50

CPUCLKC1

SRCCLKT4
SRCCLKC4

PCI_STOP#

SRCCLKT6
SRCCLKC6

SRCCLKT9
SRCCLKC9

PCICLK3

47
46

13
14

17
18

21
22

24
25

27
28

38
37

41
40

44
43

30
31

34
35

33
32

1
3
4
5
6

7
10
62

CPUT2_ITP/SRCT8
CPUT2_ITP/SRCC8

DOTT_96/SRCT0

DOTC_96/SRCC0

27Mhz_ss/SRCCLC1/SE2

SRCCLKT2/SATACL
SRCCLKC2/SATACL

SRCCLKT3/CR#_C
SRCCLKC3/CR#_D

CPU_STOP#

SRCCLKT7/CR#_F

SRCCLKC7/CR#_E

SRCCLKT10

SRCCLKC10

SRCCLKT11/CR#_H
SRCCLKC11/CR#_G

PCICLK0/CR#_A
PCICLK1/CR#_B

PCICLK2/TME

PCICLK4/27_SELECT

PCI_F5/ITP_EN

USB_48MHZ/FSLA

FSLC/TST_SL/REF

FSA CPU SRC PCI

133
166
200
266
333
400

RSVD

100
100
100
100
100
100
100
100

33
33
33
33

33
33

1 100
10
1
0
0
0
0
1

T18T18

T17T17

NEW-CARD_CLK_REQ#_R
CLK_3GPLLREQ#_R

PCI_EC
PCI_PCCARD

TME

PCI_DBP

ITP_EN

6

CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3

CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6

MCH_DREFCLK 7
MCH_DREFCLK# 7

DREF_SSCLK 7
DREF_SSCLK# 7

CLK_PCIE_SATA 15
CLK_PCIE_SATA# 15

CLK_PCIE_LAN 29
CLK_PCIE_LAN# 29

CLK_PCIE_ICH 16
CLK_PCIE_ICH# 16

CLK_PCIE_MINI 31
CLK_PCIE_MINI# 31

CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7

CLK_PCIE_EXPCARD 31
CLK_PCIE_EXPCARD# 31

R281 475/FR281 475/F
R283 475/FR283 475/F

R284 33R284 33
R291 33R291 33

R286 33R286 33
R287 33R287 33

R290 22R290 22

FSA
FSC

R293 22R293 22
R298 4.7K/FR298 4.7K/F
R277 4.7K/FR277 4.7K/F
R278 33R278 33

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

7

H_STP_PCI# 17
H_STP_CPU# 17

NEW-CARD_CLK_REQ#
CLK_3GPLLREQ#

CLK_PCI_EC 33
CLK_PCI_PCCARD 23

CLK_PCI_DBP 31

CLK_PCI_ICH 16

CPU_MCH_BSEL0
CPU_MCH_BSEL2

PROJECT : SW7

PROJECT : SW7

Quanta Computer Inc.

Quanta Computer Inc.

CLOCK GENERATOR

CLOCK GENERATOR

CLOCK GENERATOR

NEW-CARD_CLK_REQ# 31
CLK_3GPLLREQ# 7

CLK_7402_48M 24
CLK_ICH_48M 17

CLK_ICH_14M 17

244Friday, September 28, 2007

244Friday, September 28, 2007

244Friday, September 28, 2007

of

of

of

8

1A

1A

1A

1

2

3

4

5

6

7

8

H_A#[3..16]6

A A

H_ADSTB#06
H_REQ#[0..4]6

H_A#[17..35]6

B B

H_ADSTB#16
H_A20M#15

H_FERR#15

H_IGNNE#15
H_STPCLK#15

H_INTR15
H_NMI15
H_SMI#15

C C

Populate ITP700Flex for bringup

ITP_TDI
ITP_TMS
ITP_TDO
BPM#5

H_RESET#

D D

H_A#[3..16]

H_REQ#[0..4]

H_A#[17..35]

+1.05V_VCCP

Layout Note:
Place R4,R361,R346 & R7 close to CPU.

12

12

R97

R97

R106

R106

54.9/F

54.9/F

*54.9/F

*54.9/F

Layout Note:
Place R8 close ITP.

R104 27.4/FR104 27.4/F

12
12

R108 649/FR108 649/F

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

12

R10739R107
39

12

R111

R111
150/F

150/F

ITP_TCK
ITP_TRST#

U22A

U22A

J4

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07]

D22

RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

Merom Ball-out Rev 1a

Merom Ball-out Rev 1a

12

R105

R105

54.9/F

54.9/F

ADDR GROUP 0

ADDR GROUP 0

CONTROLXDP/ITP SIGNALS

CONTROLXDP/ITP SIGNALS

ADDR GROUP 1

ADDR GROUP 1

THERMAL

THERMAL

PROCHOT#

THERMDA
THERMDC

ICH

ICH

THERMTRIP#

H CLK

H CLK

RESERVED

RESERVED

H1

ADS#

E2

BNR#

G5

BPRI#

H5

DEFER#

F21

DRDY#

E1

DBSY#

F1

BR0#

IERR#

LOCK#

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TRST#

DBR#

BCLK[0]
BCLK[1]

H_IERR#

D20
B3

INIT#

H4
C1

F3
F4
G3
G2

G6

HIT#

E4
AD4

AD3
AD1
AC4
AC2

BPM#5

AC1

ITP_TCK

AC5

TCK

ITP_TDI

AA6

TDI

ITP_TDO

AB3

TDO

ITP_TMS

AB5

TMS

ITP_TRST#

AB6

ITP_DBRESET#

C20

H_PROCHOT#

D21

H_THERMDA

A24

H_THERMDC

B25

PM_THRMTRIP#

C7

A22
A21

Merom CPU Socket PN:
FOX: DGT^000021
TYC: DGT^000012
MLX: DGT^000004

ITP debug signals

R60 56R60 56

1 2

R55 75/FR55 75/F

R288 56R288 56

1 2

12

H_ADS# 6
H_BNR# 6
H_BPRI# 6

H_DEFER# 6
H_DRDY# 6
H_DBSY# 6

H_BR0# 6

+1.05V_VCCP

H_INIT# 15

H_LOCK# 6

H_RS#0 6

H_RS#1 6

RV7

RV7

H_RS#2 6

H_TRDY# 6
H_HIT# 6

H_HITM# 6

ITP_DBRESET# 17

+1.05V_VCCP

H_THERMDA 5

H_THERMDC 5
PM_THRMTRIP# 7,15

+1.05V_VCCP

CLK_CPU_BCLK 2
CLK_CPU_BCLK# 2

R91 0R91 0

12

*VZ0603M260APT

*VZ0603M260APT

H_RESET# 6

Add for ESD

Layout Note:
Place voltage
divider within

0.5" of GTLREF
pin

+1.05V_VCCP

R57

R57
1K/F

1K/F

1 2

R56

R56
2K/F

2K/F

1 2

R253 *1K/FR253 *1K/F

1 2

R260 *1K/FR260 *1K/F

1 2

C154 *0.1uF/10VC154 *0.1uF/10V

R261 *0R261 *0

1 2

Place C close to the
CPU_TEST4 pin. Make sure
CPU_TEST4 routing is
reference to GND and away
from other noisy signal.

CPU_TEST1
CPU_TEST2

CPU_TEST4

12

CPU_TEST6

H_D#[0..63]6

H_DSTBN#06
H_DSTBP#06
H_DINV#06

H_DSTBN#16
H_DSTBP#16
H_DINV#16

CPU_MCH_BSEL02
CPU_MCH_BSEL12
CPU_MCH_BSEL22

ITP disable guidelines

Signal Resistor Value Connect To Resistor Placement

150 ohm +/- 5%

TDI

39 ohm +/- 1%

TMS

500-680ohm +/- 5%

TRST#

27 ohm +/- 1%

TCK

150 ohm +/- 5%

TDO

Within 2.0" of the ITPVTT
Within 2.0" of the ITP

VTT

Within 2.0" of the ITP

GND

Within 2.0" of the ITP

GND

Within 2.0" of the ITP

VTT

Note: Populate R5, R8, C372 & R430 when ITP connector is populated.

1

2

3

4

PM_THRMTRIP#

H_D#[0..63]

H_D#[0..63]

FANLESS#33

+1.05V_VCCP

R295

R295

*1K

*1K

1 3

Q26

Q26
*MMBT3904

*MMBT3904

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

V_CPU_GTLREF
CPU_TEST1
CPU_TEST2
CPU_TEST3
CPU_TEST4
CPU_TEST5
CPU_TEST6

3VPCU

R289

R289
10K/F

10K/F

2

5

2

U22B

U22B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Merom Ball-out Rev 1a

Merom Ball-out Rev 1a

+5V

12

R47

R47
100K/F

100K/F

Q13

Q13
DTC144EUA

DTC144EUA

1 3

FSB
533 0 0 1133
667
800

BCLK

166
200

DATA GRP 0 DATA GRP 1

DATA GRP 0 DATA GRP 1

MISC

MISC

DATA GRP 2DATA GRP 3

DATA GRP 2DATA GRP 3

DSTBN[2]#
DSTBP[2]#

DSTBN[3]#
DSTBP[3]#

DPRSTP#

PWRGOOD

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#

DINV[2]#

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#

DINV[3]#
COMP[0]

COMP[1]
COMP[2]
COMP[3]

DPSLP#

DPWR#

SLP#

THERM_CPUDIE# 33

PSI#

2

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

V23

H_D#37

T22

H_D#38

U25

H_D#39

U23

H_D#40

Y25

H_D#41

W22

H_D#42

Y23

H_D#43

W24

H_D#44

W25

H_D#45

AA23

H_D#46

AA24

H_D#47

AB25
Y26
AA26
U22

H_D#48

AE24

H_D#49

AD24

H_D#50

AA21

H_D#51

AB22

H_D#52

AB21

H_D#53

AC26

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AC25

H_D#58

AE21

H_D#59

AD21

H_D#60

AC22

H_D#61

AD23

H_D#62

AF22

H_D#63

AC23
AE25
AF24
AC20

COMP0

R26

COMP1

U26

COMP2

AA1

COMP3

Y1
E5

B5
D24
D6
D7
AE6

H_PROCHOT#

3

Q16

Q16
2N7002E

2N7002E

1

H_D#32

Y22

BSEL2 BSEL1 BSEL0

0

1

0011

6

H_D#[0..63]

03

H_DSTBN#2 6
H_DSTBP#2 6

H_D#[0..63]

Note:
H_DPRTSTP need to daisy chain
from ICH8 to IMVP6 to CPU.

H_DINV#2 6

H_DSTBN#3 6
H_DSTBP#3 6
H_DINV#3 6

H_DPRSTP# 7,15,38
H_DPSLP# 15
H_DPWR# 6
H_PWRGOOD 15
H_CPUSLP# 6
PM_PSI# 38

CPU_TEST3

T8

*PADT8*PAD

T21*PADT21*PAD

For the purpose of testability, route these signals
through a ground referenced Z0 = 55ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

CPU_TEST5

Comp0,2 connect with Zo=27.4ohm,Comp1,3
connect with Zo=55ohm, make those traces
length shorter than 0.5".Trace should be
at least 25 mils away from any other
toggling signal.

Merom (HOST BUS)

Merom (HOST BUS)

Merom (HOST BUS)

7

Reserved for EMI.

+1.05V_VCCP

+1.5V_RUN

COMP0
COMP1
COMP2
COMP3

R109

R109

R110

R110

54.9/F

54.9/F

1 2

PROJECT : SW7

PROJECT : SW7

Quanta Computer Inc.

Quanta Computer Inc.

R58

R58

27.4/F

27.4/F

54.9/F

54.9/F

1 2

1 2

12

C418

C418

0.1uF/10V

0.1uF/10V

1 2

344Friday, September 28, 2007

344Friday, September 28, 2007

344Friday, September 28, 2007

8

R59

R59

27.4/F

27.4/F

1A

1A

1A

of

of

of

1

VCC_CORE

A A

VCC_CORE

All use 10U 4V(+-20%,X6S,0805)Pb-Free.

12

12

C452

C452
10U/6.3V_8

10U/6.3V_8

C445

C445
10U/6.3V_8

10U/6.3V_8

12

C461

C461
10U/6.3V_8

10U/6.3V_8

12

C202

C202
10U/6.3V_8

10U/6.3V_8

8 inside cavity, north side, secondary layer.

VCC_CORE

12

B B

VCC_CORE

12

C173

C173
10U/6.3V_8

10U/6.3V_8

C204

C204
10U/6.3V_8

10U/6.3V_8

12

C462

C462
10U/6.3V_8

10U/6.3V_8

12

C197

C197
10U/6.3V_8

10U/6.3V_8

8 inside cavity, south side, secondary layer.

VCC_CORE

12

C228

C228
10U/6.3V_8

10U/6.3V_8

12

C222

C222
10U/6.3V_8

10U/6.3V_8

6 inside cavity, north side, primary layer.

VCC_CORE

C C

12

C234

C234
10U/6.3V_8

10U/6.3V_8

12

C437

C437
10U/6.3V_8

10U/6.3V_8

6 inside cavity, south side, primary layer.

+1.05V_VCCP

C213

C213

0.1uF/10V

0.1uF/10V

12

C211

C211

0.1uF/10V

0.1uF/10V

12

2

12

C456

C456
10U/6.3V_8

10U/6.3V_8

12

C438

C438
10U/6.3V_8

10U/6.3V_8

12

C201

C201
10U/6.3V_8

10U/6.3V_8

12

C457

C457
10U/6.3V_8

10U/6.3V_8

12

C214

C214
10U/6.3V_8

10U/6.3V_8

12

C235

C235
10U/6.3V_8

10U/6.3V_8

12

C227

C227

0.1uF/10V

0.1uF/10V

12

C219

C219
10U/6.3V_8

10U/6.3V_8

12

C212

C212
10U/6.3V_8

10U/6.3V_8

12

C192

C192
10U/6.3V_8

10U/6.3V_8

12

C174

C174
10U/6.3V_8

10U/6.3V_8

12

C216

C216
10U/6.3V_8

10U/6.3V_8

12

C215

C215
10U/6.3V_8

10U/6.3V_8

12

C183

C183

0.1uF/10V

0.1uF/10V

12

C188

C188
10U/6.3V_8

10U/6.3V_8

12

C203

C203
10U/6.3V_8

10U/6.3V_8

12

C225

C225

0.1uF/10V

0.1uF/10V

3

12

C226

C226
10U/6.3V_8

10U/6.3V_8

12

C446

C446
10U/6.3V_8

10U/6.3V_8

12

C182

C182
10U/6.3V_8

10U/6.3V_8

12

C181

C181
10U/6.3V_8

10U/6.3V_8

12

C444

C444
10U/6.3V_8

10U/6.3V_8

12

C233

C233
10U/6.3V_8

10U/6.3V_8

12

C184

C184

0.1uF/10V

0.1uF/10V

4

VCC_CORE VCC_CORE

U22C

U22C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

Merom Ball-out Rev 1a

Merom Ball-out Rev 1a

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

5

TP_VCCSENSE

TP_VSSSENSE

ICCODE:
for Merom processors
recommended design
target is 44A

ICCP:
1before vccore stable
peak current is 4.5A

+1.05V_VCCP

2.after vccore stable
continue current is

2.5A

+

C252

+

C252
*330u/2.5V/12m

*330u/2.5V/12m

ICCA 130mA

CPU_VID0 38
CPU_VID1 38
CPU_VID2 38
CPU_VID3 38
CPU_VID4 38
CPU_VID5 38
CPU_VID6 38

TP_VCCSENSE 38

TP_VSSSENSE 38

12

Layout Note:
Place C105 near PIN
B26.

6

C420

C420

0.01uF/25V

0.01uF/25V

+1.5V_RUN

12

C417

C417
10U/6.3V_8

10U/6.3V_8

7

U22D

U22D

A4
A8

A11
A14
A16
A19
A23
AF2

B6
B8

B11
B13
B16
B19
B21
B24

C5
C8

C11
C14
C16
C19

C2

C22
C25

D1
D4
D8

D11
D13
D16
D19
D23
D26

E3
E6
E8

E11
E14
E16
E19
E21
E24

F5
F8

F11
F13
F16
F19

F2

F22
F25

G4
G1

G23
G26

H3
H6

H21
H24

J2

J5
J22
J25

K1

K4
K23
K26

L3

L6
L21
L24

M2

M5
M22
M25

N1

N4
N23
N26

Merom Ball-out Rev 1a

Merom Ball-out Rev 1a

VSS[082]

VSS[001]
VSS[002]

VSS[083]

VSS[003]

VSS[084]

VSS[004]

VSS[085]

VSS[005]

VSS[086]

VSS[006]

VSS[087]

VSS[007]

VSS[088]

VSS[008]

VSS[089]

VSS[009]

VSS[090]

VSS[010]

VSS[091]

VSS[011]

VSS[092]

VSS[012]

VSS[093]

VSS[013]

VSS[094]

VSS[014]

VSS[095]

VSS[015]

VSS[096]

VSS[016]

VSS[097]

VSS[017]

VSS[098]

VSS[018]

VSS[099]

VSS[019]

VSS[100]

VSS[020]

VSS[101]

VSS[021]

VSS[102]

VSS[022]

VSS[103]

VSS[023]

VSS[104]

VSS[024]

VSS[105]

VSS[025]

VSS[106]

VSS[026]

VSS[107]

VSS[027]

VSS[108]

VSS[028]

VSS[109]

VSS[029]

VSS[110]

VSS[030]

VSS[111]

VSS[031]

VSS[112]

VSS[032]

VSS[113]

VSS[033]

VSS[114]

VSS[034]

VSS[115]

VSS[035]

VSS[116]

VSS[036]

VSS[117]

VSS[037]

VSS[118]

VSS[038]

VSS[119]

VSS[039]

VSS[120]

VSS[040]

VSS[121]

VSS[041]

VSS[122]

VSS[042]

VSS[123]

VSS[043]

VSS[124]

VSS[044]

VSS[125]

VSS[045]

VSS[126]

VSS[046]

VSS[127]

VSS[047]

VSS[128]

VSS[048]

VSS[129]

VSS[049]

VSS[130]

VSS[050]

VSS[131]

VSS[051]

VSS[132]

VSS[052]

VSS[133]

VSS[053]

VSS[134]

VSS[054]

VSS[135]

VSS[055]

VSS[136]

VSS[056]

VSS[137]

VSS[057]

VSS[138]

VSS[058]

VSS[139]

VSS[059]

VSS[140]

VSS[060]

VSS[141]

VSS[061]

VSS[142]

VSS[062]

VSS[143]

VSS[063]

VSS[144]

VSS[064]

VSS[145]

VSS[065]

VSS[146]

VSS[066]

VSS[147]
VSS[148]

VSS[067]
VSS[068]

VSS[149]

VSS[069]

VSS[150]

VSS[070]

VSS[151]

VSS[071]

VSS[152]

VSS[072]

VSS[153]

VSS[073]

VSS[154]

VSS[074]

VSS[155]

VSS[075]

VSS[156]

VSS[076]

VSS[157]

VSS[077]

VSS[158]

VSS[078]

VSS[159]

VSS[079]

VSS[160]

VSS[080]

VSS[161]

VSS[081]P3VSS[162]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

8

04

Layout out:
Place these inside socket cavity on North side secondary.

D D

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

1

2

3

4

5

6

Date: Sheet

Merom Processor (POWER)

Merom Processor (POWER)

Merom Processor (POWER)

7

PROJECT : SW7

PROJECT : SW7

Quanta Computer Inc.

Quanta Computer Inc.

444Friday, September 28, 2007

444Friday, September 28, 2007

444Friday, September 28, 2007

of

of

of

8

1A

1A

1A

5

4

3

2

1

+3V

5V_AL

05

R427

R427
100

D D

R50

R50

R49

R49

10K/F

10K/F

10K/F

10K/F

THCLK_SMB

THDAT_SMB

THERM_ALERT#17

THERM_ALERT#

1 2

R54 *0R54 *0

R52

R52
10K/F

10K/F

R61

R61

8
7
6
4

*100

*100

close to ICH

C C

+3V

Q12

Q12

2

2N7002E

2N7002E

MBDATA33,35

B B

MBCLK33,35

3

Q11

Q11
2N7002E

2N7002E

3

+3V

2

THDAT_SMB

1

THCLK_SMB

1

+5V

12

C413

C413
10U/6.3V_8

10U/6.3V_8

100

U10

U10

VCC

SCLK

DXP

SDA

DXN

ALERT#

GND

OVERT#

GMT-781

GMT-781

ADDRESS: 98H

2nd:AL006648004

R252 0_6R252 0_6

C414

C414

1 2

0.1uF/10V

0.1uF/10V

25mils

LM86VCC

C153

C153

0.1uF/10V

0.1uF/10V

1
2
3
5

H_THERMDA

C156

C156
2200pF/50V

2200pF/50V

H_THERMDC

SYS_SHDN-1#

10/20mils

H_THERMDA 3

H_THERMDC 3

1st FAN OUT CONNECTOR

VFAN_133

+5V_FAN

12

C415

C415
1000pF/50V

1000pF/50V

+3V

R51 *0R51 *0

+3V

R53

R53
1M/F

1M/F

3

C149

C149

0.1uF/10V

2

Q14

Q14
2N7002E

2N7002E

0.1uF/10V

1

add hardware protect

J8

1
2
3
4

FANJ8FAN

FAN Con.
1st PN: DFHD04MR663(MLX)
2nd PN: DFWF04MS079(PTI)

SYS_SHDN# 36

3

2

Q15

Q15
2N7002E

2N7002E

1

R256

R256
10K/F

10K/F

FANSIG_133

A A

5

4

3

12

C416

C416
1000pF/50V

1000pF/50V

PROJECT : SW7

PROJECT : SW7

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

THERMAL LM86 & FAN

THERMAL LM86 & FAN

THERMAL LM86 & FAN

Quanta Computer Inc.

of

of

of

544Friday, September 28, 2007

544Friday, September 28, 2007

544Friday, September 28, 2007

1

1A

1A

1A

1

2

3

4

5

6

7

8

06

U23A

M10

N12

P13

W10

AD12

AE3
AD9
AC9
AC7

AC14
AD11
AC11

AB2
AD7

AB1
AC6

AE2
AC5
AG3

AH8

AJ14

AE9

AE11
AH12

AH5

AE7

AE5
AH2

AH13

E2

G2
G7
M6
H7
H3
G4

F3
N8
H2

N9
H5

K9
M2

Y8

V4
M3

J1
N5
N3
W6
W9
N2

Y7
Y9

P4
W3
N1

Y3

AJ9

AJ5
AJ6
AJ7

AJ2
AJ3

B3
C2

W1
W2

B6

E5

B9

A9

U23A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

H_CPURST#
H_CPUSLP#

H_AVREF
H_DVREF

CRESTLINE_1p0

CRESTLINE_1p0

H_ADSTB#_0
H_ADSTB#_1

HOST

HOST

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#
H_HITM#

H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_REQ#_0
H_REQ#_1

H_REQ#_2
H_REQ#_3

H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

K5
L2
AD13
AE13

M7
K3
AD2
AH11

L7
K2
AC2
AJ10

M14
E13
A11
H13
B12

E12
D7
D8

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_D#[0..63]3

A A

+1.05V_VCCP

12

R303

R303
221/F

221/F

H_SWING

12

R297

R297
100

100

B B

+1.05V_VCCP

C495

C495

0.1uF/10V

0.1uF/10V

1 2

impedance 55 ohm

12

12

R275

R275

R269

R269

54.9/F

54.9/F

54.9/F

54.9/F

H_SCOMP
H_SCOMP#

12

R89

R89

24.9/F

24.9/F

C C

H_RESET#3

RV8

RV8

H_RCOMP

Layout Note:
H_RCOMP trace should be
10-mil wide with 20-mil
spacing.

R2940R294
0

12

*VZ0603M260APT

*VZ0603M260APT

+1.05V_VCCP

H_D#[0..63]

H_CPUSLP#3

H_REF

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

Add for ESD

R299

R299
1K/F

1K/F

1 2

D D

12

1

2

R300

R300
2K/F

2K/F

12

C493

C493

0.1uF/10V

0.1uF/10V

Layout Note:
Place the 0.1 uF
decoupling capacitor
within 100 mils from
GMCH pins.

3

H_REF

4

5

H_A#[3..35]

H_ADS# 3
H_ADSTB#0 3
H_ADSTB#1 3
H_BNR# 3
H_BPRI# 3
H_BR0# 3
H_DEFER# 3
H_DBSY# 3
CLK_MCH_BCLK 2
CLK_MCH_BCLK# 2
H_DPWR# 3
H_DRDY# 3
H_HIT# 3
H_HITM# 3
H_LOCK# 3
H_TRDY# 3

H_DINV#0 3
H_DINV#1 3
H_DINV#2 3
H_DINV#3 3

H_DSTBN#0 3
H_DSTBN#1 3
H_DSTBN#2 3
H_DSTBN#3 3

H_DSTBP#0 3
H_DSTBP#1 3
H_DSTBP#2 3
H_DSTBP#3 3

H_REQ#0 3
H_REQ#1 3
H_REQ#2 3
H_REQ#3 3
H_REQ#4 3

H_RS#0 3
H_RS#1 3
H_RS#2 3

6

H_A#[3..35] 3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Crestline (HOST)

Crestline (HOST)

Crestline (HOST)

7

PROJECT : SW7

PROJECT : SW7

Quanta Computer Inc.

Quanta Computer Inc.

644Friday, September 28, 2007

644Friday, September 28, 2007

644Friday, September 28, 2007

8

1A

1A

1A

of

of

of

1

A A

WW22 update

--- MA14 needs
to be routed if
customers are
planning on
using 2Gb
technology and
width=8 (by 8)
DIMMs

DDR_A_MA1413,14
DDR_B_MA1413,14

MCH_BSEL02
MCH_BSEL12
MCH_BSEL22

R78 0R78 0
R77 0R77 0

PM_EXTTS#1

R63 100R63 100
R67 0R67 0
R118 0R118 0

1 2
1 2

T20 *PADT20 *PAD
T19 *PADT19 *PAD

CRESTLINE
new pin
define

Layout Note:

B B

DELAY_VR_PWRGOOD17,38

C C

GMCH pwrok is 3.3v
tolerant

D D

Location of all MCH_CFG strap
resistors needs to be close to
minmize stub.

CFG512

CFG1212
CFG1312

CFG1612

CFG2012

PM_BMBUSY#17
H_DPRSTP#3,15,38
PM_EXTTS#014

PLT_RST-R#16,31

PM_THRMTRIP#3,15

PM_DPRSLPVR17,38

+3V

R74 10K/FR74 10K/F
R84 10K/FR84 10K/F

1

2

CFG5

CFG12
CFG13

CFG16

CFG20

PM_BMBUSY#_R
ICH_DPRSTP#_R

R80 0R80 0

PLTRST_MCH#
PM_THRMTRIP#_GMCH
PM_DPRSLPVR_GMCH

PM_EXTTS#0
PM_EXTTS#1

2

P36

P37
R35
N35

AR12
AR13
AM12
AN13

J12

AR37
AM36

AL36

AM37

D20

H10

B51

BJ20
BK22
BF19
BH20
BK18

BJ18
BF23
BG23
BC23
BD24

BJ29
BE24
BH39

AW20

BK20

C48
D47

B44

C44

A35
B37
B36
B34

C34

P27
N27
N24
C21
C23

F23
N23
G23

J20
C20
R24

L23

J23

E23

E20

K23
M20
M24

L32
N33

L35

G41

L39

L36

J36

AW49

AV20

N20
G36

BJ51
BK51
BK50

BL50

BL49

BL3
BL2

BK1

BJ1

E1
A5

C51

B50
A50
A49

BK2

CRESTLINE_1p0

CRESTLINE_1p0

U23B

U23B

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14

RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
SA-MA14
SB_MA14
RSVD34
RSVD35
RSVD36
LVDSA_DATA#_3
LVDSA_DATA_3
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16

SM_RCOMP_VOH

12

C429

C429

0.01uF/25V

0.01uF/25V

SM_RCOMP_VOL

12

C428

C428

0.01uF/25V

0.01uF/25V

CFGRSVD

CFGRSVD

PM

PM

NC

NC

12

C424

C424

2.2uF/6.3V_6

2.2uF/6.3V_6

12

C423

C423

2.2uF/6.3V_6

2.2uF/6.3V_6

3

SM_CK#_0
SM_CK#_1
SM_CK#_3

SM_CK#_4
SM_CKE_0

SM_CKE_1
SM_CKE_3
SM_CKE_4

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

SM_RCOMP

DDR MUXINGCLKDMI

DDR MUXINGCLKDMI

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF_0
SM_VREF_1

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3

GFX_VR_EN

GRAPHICS VIDME

GRAPHICS VIDME

CL_PWROK

SDVO_CTRL_CLK

SDVO_CTRL_DATA

CLK_REQ#

ICH_SYNC#

MISC

MISC

+1.8VSUS

12

R257

R257
1K/F

1K/F

12

R259

R259

3.01K/F

3.01K/F

12

R258

R258
1K/F

1K/F

3

SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4

PEG_CLK

CL_CLK

CL_DATA
CL_RST#

CL_VREF

TEST_1
TEST_2

AV29
BB23
BA25
AV23

AW30
BA23
AW25
AW23

BE29
AY32
BD39
BG37

BG20
BK16
BG16
BE13

BH18
BJ15
BJ14
BE16

BL15
BK14

BK31
BL31

AR49
AW4

B42
C42
H48
H47

K44
K45

AN47
AJ38
AN42
AN46

AM47
AJ39
AN41
AN45

AJ46
AJ41
AM40
AM44

AJ47
AJ42
AM39
AM43

E35
A39
C38
B39
E36

AM49
AK50
AT43
AN49
AM50

H35
K36
G39
G40

A37
R32

4

M_CLK_DDR0 14
M_CLK_DDR1 14
M_CLK_DDR2 14
M_CLK_DDR3 14

M_CLK_DDR#0 14
M_CLK_DDR#1 14
M_CLK_DDR#2 14
M_CLK_DDR#3 14

DDR_CKE0_DIMMA 13,14
DDR_CKE1_DIMMA 13,14
DDR_CKE2_DIMMB 13,14
DDR_CKE3_DIMMB 13,14

DDR_CS0_DIMMA# 13,14
DDR_CS1_DIMMA# 13,14
DDR_CS2_DIMMB# 13,14
DDR_CS3_DIMMB# 13,14

M_ODT0 13,14
M_ODT1 13,14
M_ODT2 13,14
M_ODT3 13,14

SMRCOMPP
SMRCOMPN

SM_RCOMP_VOH
SM_RCOMP_VOL

SMDDR_VREF_MCH

DMI_MRX_ITX_N0 16
DMI_MRX_ITX_N1 16
DMI_MRX_ITX_N2 16
DMI_MRX_ITX_N3 16

DMI_MRX_ITX_P0 16
DMI_MRX_ITX_P1 16
DMI_MRX_ITX_P2 16
DMI_MRX_ITX_P3 16

DMI_MTX_IRX_N0 16
DMI_MTX_IRX_N1 16
DMI_MTX_IRX_N2 16
DMI_MTX_IRX_N3 16

DMI_MTX_IRX_P0 16
DMI_MTX_IRX_P1 16
DMI_MTX_IRX_P2 16
DMI_MTX_IRX_P3 16

C178 0.1uF/10VC178 0.1uF/10V
C179 0.1uF/10VC179 0.1uF/10V
R62 0R62 0

MCH_DREFCLK 2
MCH_DREFCLK# 2
DREF_SSCLK 2
DREF_SSCLK# 2

CLK_MCH_3GPLL 2
CLK_MCH_3GPLL# 2

R92 1.3K_6R92 1.3K_6

IV&EV Dis/Enable setting

CL_CLK0 17

CL_DATA0 17
ECPWROK 17,33
CL_RST#0 17

MCH_CLVREF

CLK_3GPLLREQ# 2
MCH_ICH_SYNC# 17

R65

R65

R1120R112

20K/F

20K/F

0

1 2

1 2

+1.25V +1.8VSUS

12

R268

R268
1K/F

1K/F

MCH_CLVREF

12

R267

C439

C439

0.1uF/10V

0.1uF/10V

1 2

R267
392/F

392/F

4

+3V

V_DDR_MCH_REF 14,40

+3V

VGADDCCLK21
VGADDCDAT21

VGAHSYNC21
VGAVSYNC21

In Crestline EDS
Rev.1.0, Render
Standby Voltage is
not finalized
yet(TBD), 1.05V for
Graphic Voltage
range(VCC_AXG) is
between 0.9975V(min.)
and 1.1025V(max.).
Vgfx max at 1.1025V @
8A (estimated)

only resever AT3/5 not
support IAMT,but design
line suggest to connection
these pin ,do not NC

12

R264

R264
20/F

20/F

SMRCOMPP
SMRCOMPN

R265

R265
20/F

20/F

12

BIA_PWM22

PANEL_BKEN22

LCD_DDCCLK22
LCD_DDCDAT22

5

ENVDD22

5

R72 2.4KR72 2.4K

LCD_ACLK-22
LCD_ACLK+22

LCD_A0-22
LCD_A1-22
LCD_A2-22

LCD_A0+22
LCD_A1+22
LCD_A2+22

TV_CVBS20
TV_Y20
TV_C20

R68 2.2KR68 2.2K
R66 2.2KR66 2.2K

R93 39R93 39
R94 39R94 39

VGA_BLU_S21
VGA_GRN_S21
VGA_RED_S21

R85 10K/FR85 10K/F
R87 10K/FR87 10K/F

VGA_BLU
VGA_GRN
VGA_RED

R86 150/FR86 150/F
R79 150/FR79 150/F
R76 150/FR76 150/F

LVDS_IBG

TV_DCONSEL_0
TV_DCONSEL_1

HSYNC11
CRTIREF
VSYNC11

1 2
1 2
1 2

*18pF/50V

*18pF/50V

C260

C260

6

U23C

U23C

J40
H39
E39
E40
C37
D35
K40

L41

L43
N41
N40
D46
C45
D44
E42

G51
E51
F49

G50
E50
F48

G44
B47
B45

E44
A47
A45

E27
G27
K27

F27

J27

L27
M35

P33

H32
G32
K29

J29
F29
E29

K33
G35
F33
C32
E33

CRESTLINE_1p0

CRESTLINE_1p0

*18pF/50V

*18pF/50V

6

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN

LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2

TVA_DAC
TVB_DAC
TVC_DAC

TVA_RTN
TVB_RTN
TVC_RTN

TV_DCONSEL_0
TV_DCONSEL_1

CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC

TV_CVBS
TV_Y
TV_C

R119 0R119 0
R95 0R95 0
R115 0R115 0

C261

C261

C249

C249

*18pF/50V

*18pF/50V

7

VCC3G_PCIE_R

N43

PEG_COMPI

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

C251

C251

*18pF/50V

*18pF/50V

Crestline (VGA,DMI)

Crestline (VGA,DMI)

Crestline (VGA,DMI)

7

M43

J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41

J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42

N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44

M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43

LCD_DDCCLK
LCD_DDCDAT

R114

R114

150/F

150/F

1 2

PEG_COMPO

LVDS

LVDS

TV VGA

TV VGA

+3V

PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PCI-EXPRESS GRAPHICS

PCI-EXPRESS GRAPHICS

R90 2.2KR90 2.2K
R96 2.2KR96 2.2K

C242

C242

C258

C258

*18pF/50V

*18pF/50V

*18pF/50V

*18pF/50V

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet of

R69 24.9/FR69 24.9/F

1 2

VGA_BLU
VGA_GRN
VGA_RED

R113

R113

R88

R88

150/F

150/F

150/F

150/F

1 2

1 2

PROJECT : SW7

PROJECT : SW7

Quanta Computer Inc.

Quanta Computer Inc.

8

+VCC_PEG

07

744Friday, September 28, 2007

744Friday, September 28, 2007

744Friday, September 28, 2007

8

1A

1A

1A

of

of

1

2

3

4

5

6

7

8

08

DDR_A_D[63:0]14 DDR_B_D[63:0]14

A A

B B

C C

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AR43

AW44

BA45
AY46
AR41
AR45
AT42

AW47

BB45
BF48
BG47

BJ45
BB47
BG50
BH49
BE45

AW43

BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40

AW40

AT39

AW36
AW41

AY41
AV38
AT38
AV13
AT13

AW11

AV11
AU15
AT11
BA13
BA11
BE10
BD10

BG10

AW9

AM8

AN10

AN9
AM9

AN11

BD8
AY9

BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3

AT9

U23D

U23D

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

CRESTLINE_1p0

CRESTLINE_1p0

BB19

SA_BS_0

BK19

SA_BS_1

BF29

SA_BS_2

BL17

SA_CAS#
SA_DM_0

SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_RAS#

SA_RCVEN#

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_WE#

AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6

AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2

BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16

BE18
AY20

BA19

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

TP_SA_RCVEN#

DDR_A_BS0 13,14
DDR_A_BS1 13,14
DDR_A_BS2 13,14
DDR_A_CAS# 13,14

DDR_A_DM[0..7] 14

DDR_A_DQS[7:0] 14

DDR_A_DQS#[7:0] 14

DDR_A_MA[13:0] 13,14

DDR_A_RAS# 13,14

T9T9

DDR_A_WE# 13,14

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AP49

AR51
AW50
AW51

AN51

AN50

AV50

AV49

BA50

BB50

BA49

BE50

BA51

AY49

BF50

BF49

BJ50
BJ44
BJ43

BL43
BK47
BK49
BK43
BK42

BJ41

BL41

BJ37

BJ36
BK41

BJ40

BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12

BG12

BJ10

BK10

BH5

BG1

BC2
BK3
BE4
BD3

BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

BL9
BK5
BL5
BK9

BJ8
BJ6
BF4

BJ2

U23E

U23E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

CRESTLINE_1p0

CRESTLINE_1p0

AY17

SB_BS_0

BG18

SB_BS_1

BG36

SB_BS_2

BE17

SB_CAS#
SB_DM_0

SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SB_RAS#

SB_RCVEN#

SB_WE#

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2

AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3

BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13

AV16
AY18

BC17

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

TP_SB_RCVEN#

DDR_B_BS0 13,14
DDR_B_BS1 13,14
DDR_B_BS2 13,14

DDR_B_CAS# 13,14
DDR_B_DM[0..7] 14

DDR_B_DQS[7:0] 14

DDR_B_DQS#[7:0] 14

DDR_B_MA[13:0] 13,14

DDR_B_RAS# 13,14

T10 *PADT10 *PAD

DDR_B_WE# 13,14

D D

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

1

2

3

4

5

6

Date: Sheet

Crestline (DDR)

Crestline (DDR)

Crestline (DDR)

7

PROJECT : SW7

PROJECT : SW7

Quanta Computer Inc.

Quanta Computer Inc.

844Friday, September 28, 2007

844Friday, September 28, 2007

844Friday, September 28, 2007

of

of

of

8

1A

1A

1A

AT35
AT34

AH28

AC32
AC31
AK32
AJ31
AJ28
AH32
AH31
AH29
AF32

R30

AU32

AU33
AU35
AV33

AW33
AW35

AY35

BA32

BA33

BA35

BB33

BC32

BC33

BC35

BD32

BD35

BE32

BE33

BE35

BF33

BF34
BG32
BG33
BG35
BH32
BH34
BH35

BJ32

BJ33

BJ34
BK32
BK33
BK34
BK35

BL33
AU30

R20

T14
W13
W14

Y12

AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28

AF21

AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31

AJ20
AN14

5

5

U23G

U23G

VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

CRESTLINE_1p0

CRESTLINE_1p0

VCC CORE

VCC CORE

POWER

POWER

VCC SMVCC GFX

VCC SMVCC GFX

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55

VCC GFX NCTF

VCC GFX NCTF

VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

VCC SM LF

+1.05V_VCCP

D D

IVCCSM supply
current 1
channel

1.615A 2
channel

3.318A

C C

B B

A A

+1.8VSUS

+1.05V_VCCP

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

AW45
BC39
BE39
BD17
BD4
AW8
AT6

4

Ivcc_AXG Graphics core supply
current 7.7A

12

+

+

C436

C436

330UF_2.0V_ESR9

330UF_2.0V_ESR9

Layout Note:
Inside GMCH cavity for VCC_AXG.

12

12

GMCH 1.05V

VCC Core

VCC_AXG

VCC_AXD

VTT

VCC_PEG

VCC_AXM

VCCR_RX_DMI

C218

C218

0.1uF/10V

0.1uF/10V

C200

C200

0.1uF/10V

0.1uF/10V

current(A)

1.573

7.7

0.2

0.85

1.2

0.54

0.25

12.313SUM

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

4

12

C186

C186

0.1uF/10V

0.1uF/10V

12

3

Layout Note:
370 mils from edge.

Ivcc (External GFX 1.310 A,
integrate 1.572 A)

12

+

+

C480

C480
330UF_2.0V_ESR9

330UF_2.0V_ESR9

12

C469

C469

0.47uF/10V_6

0.47uF/10V_6

+1.05V_VCCP

12

C221

C221
1uF/6.3V

1uF/6.3V

Remark

( 1.3A for
external
GFX )

for integrated
Gfx

C190

C190

10U/6.3V_8

10U/6.3V_8

Layout Note:
370 mils from edge.

12

C472

C472
10U/6.3V_8

10U/6.3V_8

+1.05V_VCCP

Ivcc_AXM
Controller
supply
current
540mA

FSB VCCP

for PCIEG

for IAMT
function

DMI

12

C176

C176

0.1uF/10V

0.1uF/10V

12

C166

C166

0.47uF/10V_6

0.47uF/10V_6

C167

C167

0.47uF/10V_6

0.47uF/10V_6

12

C165

C165

0.47uF/10V_6

0.47uF/10V_6

3

+3V

R309 10R309 10

1 2

C207

C207

10U/6.3V_8

10U/6.3V_8

Layout Note:
Inside GMCH cavity.

C470

C470

10U/6.3V_8

10U/6.3V_8

C237

C237

10U/6.3V_8

10U/6.3V_8

12

C169

C169
1uF/6.3V

1uF/6.3V

+VCC_GMCH_L

12

C196

C196

0.22uF/10V_6

0.22uF/10V_6

C210

C210

10U/6.3V_8

10U/6.3V_8

12

C208

C208

0.1uF/10V

0.1uF/10V

C230

C230

10U/6.3V_8

10U/6.3V_8

Layout Note:
Place close to GMCH edge.

12

C177

C177
1uF/6.3V

1uF/6.3V

D27

D27

21

CH501H-40PT

CH501H-40PT

C224

C224

0.22uF/10V_6

0.22uF/10V_6

12

C220

C220

0.1uF/10V

0.1uF/10V

12

C223

C223

0.22uF/10V_6

0.22uF/10V_6

12

C209

C209

0.1uF/10V

0.1uF/10V

12

C205

C205

0.1uF/10V

0.1uF/10V

12

C471

C471

0.22uF/10V_6

0.22uF/10V_6

+1.8VSUS

12

C175

C175

0.1uF/10V

0.1uF/10V

Layout Note:
Place C901 where LVDS
and DDR2 taps.

12

+1.05V_VCCP

for IAMT power if not
support need to
connection to S0 power

Layout Note:
Inside GMCH
cavity.

2

U23F

U23F

AB33

VCC_NCTF_1

AB36

VCC_NCTF_2

AB37

VCC_NCTF_3

AC33

VCC_NCTF_4

AC35

VCC_NCTF_5

AC36

VCC_NCTF_6

AD35

VCC_NCTF_7

AD36

VCC_NCTF_8

AF33

VCC_NCTF_9

AF36

VCC_NCTF_10

AH33

VCC_NCTF_11

AH35

VCC_NCTF_12

AH36

VCC_NCTF_13

AH37

VCC_NCTF_14

AJ33

VCC_NCTF_15

AJ35

VCC_NCTF_16

AK33

VCC_NCTF_17

AK35

VCC_NCTF_18

AK36

VCC_NCTF_19

AK37

VCC_NCTF_20

AD33

VCC_NCTF_21

AJ36

VCC_NCTF_22

AM35

VCC_NCTF_23

AL33

VCC_NCTF_24

AL35

VCC_NCTF_25

AA33

VCC_NCTF_26

AA35

VCC_NCTF_27

AA36

VCC_NCTF_28

AP35

VCC_NCTF_29

AP36

VCC_NCTF_30

AR35

VCC_NCTF_31

AR36

VCC_NCTF_32

Y32

VCC_NCTF_33

Y33

VCC_NCTF_34

Y35

VCC_NCTF_35

Y36

VCC_NCTF_36

Y37

VCC_NCTF_37

T30

VCC_NCTF_38

T34

VCC_NCTF_39

T35

VCC_NCTF_40

U29

VCC_NCTF_41

U31

VCC_NCTF_42

U32

VCC_NCTF_43

U33

VCC_NCTF_44

U35

VCC_NCTF_45

U36

VCC_NCTF_46

V32

VCC_NCTF_47

V33

VCC_NCTF_48

V36

VCC_NCTF_49

V37

VCC_NCTF_50

AL24

VCC_AXM_NCTF_1

AL26

VCC_AXM_NCTF_2

AL28

VCC_AXM_NCTF_3

AM26

VCC_AXM_NCTF_4

AM28

VCC_AXM_NCTF_5

AM29

VCC_AXM_NCTF_6

AM31

VCC_AXM_NCTF_7

AM32

VCC_AXM_NCTF_8

AM33

VCC_AXM_NCTF_9

AP29

VCC_AXM_NCTF_10

AP31

VCC_AXM_NCTF_11

AP32

VCC_AXM_NCTF_12

AP33

VCC_AXM_NCTF_13

AL29

VCC_AXM_NCTF_14

AL31

VCC_AXM_NCTF_15

AL32

VCC_AXM_NCTF_16

AR31

VCC_AXM_NCTF_17

AR32

VCC_AXM_NCTF_18

AR33

VCC_AXM_NCTF_19

CRESTLINE_1p0

CRESTLINE_1p0

12

+

+

C431

C431
330UF_2.0V_ESR9

330UF_2.0V_ESR9

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

VCC NCTF

VCC NCTF

POWER

POWER

VCC AXM NCTF

VCC AXM NCTF

C172

C172

10U/6.3V_8

10U/6.3V_8

Layout Note:
Place on the edge.

PROJECT : SW7

PROJECT : SW7

Quanta Computer Inc.

Quanta Computer Inc.

Crestline (VCC, NCTF)

Crestline (VCC, NCTF)

Crestline (VCC, NCTF)

1

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16

VSS NCTF

VSS NCTF

VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

VSS SCBVCC AXM

VSS SCBVCC AXM

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7

C427

C427

10U/6.3V_8

10U/6.3V_8

1

09

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

A3
B2
C1
BL1
BL51
A51

+1.05V_VCCP

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

C132

C132

10U/6.3V_8

10U/6.3V_8

944Friday, September 28, 2007

944Friday, September 28, 2007

944Friday, September 28, 2007

C422

C422

10U/6.3V_8

10U/6.3V_8

of

of

of

1A

1A

1A

5

IV&EV Dis/Enable setting

+3V

D D

L42

L42

+3V

1 2

BLM18PG181SN1

C435

C435

0.1uF/10V

0.1uF/10V

L21

L21

1 2

100_6

100_6

BLM18PG181SN1

R307 0.03/FR307 0.03/F

12

12

FB_180ohm+-25%_100mHz_1500mA_0.09ohm DC

+3V_TV_DAC

FB_120ohm+-25%_100mHz
_200mA_0.2ohm DC

+1.25V

L35

L35
BLM18PG121SN

BLM18PG121SN

C443

C443

10U/6.3V_8

C C

B B

10U/6.3V_8

L34

L34
BLM18PG121SN

BLM18PG121SN

R266

R266

0.5/F_6

0.5/F_6

1 2

+VCCA_MPLL_L

C432

C432

10U/6.3V_8

10U/6.3V_8

12

12

C433

C433

10U/6.3V_8

10U/6.3V_8

50mA

+1.25V_VCCA_HPLL+1.25V_VCCA_HPLL

C441

C441

10U/6.3V_8

10U/6.3V_8

150mA

+1.25V_VCCA_MPLL

+VCCA_MPLL_L

12

C440

C440

0.1uF/10V

0.1uF/10V

12

+1.5V_RUN

FB_180ohm+-25%_
100mHz_1500mA_

0.09ohm DC

FB_180ohm+-25%_100mHz_1500mA_0.09ohm DC

+3V

R305 0_6R305 0_6

+3.3S_TVDAC_LDO

+3.3S_TVDAC_LDO

C504

C504

*10U/6.3V_8

*10U/6.3V_8

A A

For TV-OUT

U25

U25

5
4

BYP

*AAT3218

*AAT3218

C494

C494

*0.01uF/25V

*0.01uF/25V

+5V

IN1OUT

2

GND

3

EN

C498

C498
*1uF/6.3V

*1uF/6.3V

L41

L41

1 2

BLM18PG181SN1

BLM18PG181SN1

C501

C501

10U/6.3V_8

10U/6.3V_8

22nF & 0.1uF for
VCC_TVDACA:C_R should
be placed with in 250
mils from Crestline.

+VCC_TVBG

12

+1.25V

R73 0_6R73 0_6

C265

C265

0.1uF/10V

0.1uF/10V

C266

C266

0.1uF/10V

0.1uF/10V

12

C239

C239

0.1uF/10V

0.1uF/10V

12

C506

C506

0.1uF/10V

0.1uF/10V

+1.5V_VCCD_TVDAC

C262

C262

4.7uF/6.3V_6

4.7uF/6.3V_6

+3V_TV_DAC

12

C505

C505

0.1uF/10V

0.1uF/10V

+1.25V

L20

L20
10uH/100MA_8

10uH/100MA_8

10uH+-20%_100mA

L17

L17
10uH/100MA_8

10uH/100MA_8

0.1Caps should be
placed 200 mils
with in its pins.

+1.25V

12

C458

C458

+

+

220U/2.5V_B

220U/2.5V_B

+1.5V_VCCD_TVDAC

12

C499

C499

0.1uF/10V

0.1uF/10V

12

C497

C497

0.1uF/10V

0.1uF/10V

12

C500

C500

0.1uF/10V

0.1uF/10V

4

12

12

C155

C155

10U/6.3V_8

10U/6.3V_8

+3V_VCCA_CRT_DAC

+1.25V_VCCA_DPLLA

+

+

C507

C507
330UF_2.0V_ESR9

330UF_2.0V_ESR9

+1.25V_VCCA_DPLLB

+

+

C238

C238
330UF_2.0V_ESR9

330UF_2.0V_ESR9

C198

C198

4.7uF/6.3V_6

4.7uF/6.3V_6

1 2

C151

C151

10U/6.3V_8

10U/6.3V_8

+1.8VSUS

80mA

80mA

C187

C187

10U/6.3V_8

10U/6.3V_8

12

+VCCA_MPLL_L

250mA

+1.8VSUS_VCC_TX_LVDS

12

C244

C244

0.1uF/10V

0.1uF/10V

+3V

C240

C240

12

0.1uF/10V

0.1uF/10V

C195

C195

10U/6.3V_8

10U/6.3V_8

12

C171

C171

C170

C170

1uF/6.3V

1uF/6.3V

1uF/6.3V

1uF/6.3V

12

C434

C434

0.1uF/10V

0.1uF/10V

C168

C168
1uF/6.3V

1uF/6.3V

+1.25V

FB_220ohm+-25%_100MHz
_2A_0.1ohm DC

10mA

12

C502

C502

0.1uF/10V

0.1uF/10V

Ivcca_PEG_BG
supply current
100mA

C191

C191

10U/6.3V_8

10U/6.3V_8

12

12

C473

C473

0.1uF/10V

0.1uF/10V

C161

C161
10U/6.3V_8

10U/6.3V_8

L16

L16

1 2

BLM21PG221SN1D

BLM21PG221SN1D

+1.25V_VCCD_PEG_PLL

C189

C189

10U/6.3V_8

10U/6.3V_8

C157

C157

0.1uF/10V

0.1uF/10V

+1.5V_VCCD_TVDAC
+1.5V_VCCD_QDAC
+VCCA_MPLL_L
+1.25V_VCCD_PEG_PLL

3

CRT/TV Disable/Enable guideline

External VGA with EV@part,Internal VGA with IV@ part

Ball

Enable

Ball

3.3V

1.5V

1.5V

3.3V

3.3V

U23H

U23H

J32

VCCSYNC

A33

VCCA_CRT_DAC_1

B33

VCCA_CRT_DAC_2

A30

VCCA_DAC_BG

B32

VSSA_DAC_BG

B49

VCCA_DPLLA

H49

VCCA_DPLLB

AL2

VCCA_HPLL

AM2

VCCA_MPLL

A41

VCCA_LVDS

B41

VSSA_LVDS

K50

VCCA_PEG_BG

K49

VSSA_PEG_BG

U51

VCCA_PEG_PLL

AW18

VCCA_SM_1

AV19

VCCA_SM_2

AU19

VCCA_SM_3

AU18

VCCA_SM_4

AU17

VCCA_SM_5

AT22

VCCA_SM_7

AT21

VCCA_SM_8

AT19

VCCA_SM_9

AT18

VCCA_SM_10

AT17

VCCA_SM_11

AR17

VCCA_SM_NCTF_1

AR16

VCCA_SM_NCTF_2

BC29

VCCA_SM_CK_1

BB29

VCCA_SM_CK_2

C25

VCCA_TVA_DAC_1

B25

VCCA_TVA_DAC_2

C27

VCCA_TVB_DAC_1

B27

VCCA_TVB_DAC_2

B28

VCCA_TVC_DAC_1

A28

VCCA_TVC_DAC_2

M32

VCCD_CRT

L29

VCCD_TVDAC

N28

VCCD_QDAC

AN2

VCCD_HPLL

U48

VCCD_PEG_PLL

J41

VCCD_LVDS_1

H42

VCCD_LVDS_2

+1.25V_VCCD_PEG_PLL

12

C468

C468

0.1uF/10V

0.1uF/10V

Disable

GND VCCA_C_TVO

GND

VCCD_TVO

GND VCCABG_DAC

GND

VSSABG_DAC

GND

VCC_SYNC

CRTPLLA PEGA SMTV

CRTPLLA PEGA SMTV

POWER

POWER

A CK A LVDS

A CK A LVDS

D TV/CRTLVDS

D TV/CRTLVDS

+VTTLF1
+VTTLF2
+VTTLF3

12

C454

C454

0.47uF/10V_6

0.47uF/10V_6

+1.25V_VCCA_DPLLA
+1.25V_VCCA_DPLLB
+1.25V_VCCA_HPLL
+1.25V_VCCA_MPLL

C490

C490
1000pF/50V

1000pF/50V

100mA

12

C180

C180
1uF/6.3V

1uF/6.3V

+3V_TV_DAC
+3V_TV_DAC
+3V_TV_DAC

150mA

12

R64

R64
1/F_6

1/F_6

12

C232

C232
10U/6.3V_8

10U/6.3V_8

VCCA_CRT

VCCD_CRT

100mA

Enable

3.3V

1.5V

3.3VVCCDQ_CRT

GNDVCCA_A_TVO

3.3VVCCA_B_TVO

VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6

AXD

AXD

VCC_AXD_NCTF

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

AXF

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

SM CK

VCC_TX_LVDS

VCC_HV_1
VCC_HV_2

HV

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

PEG

PEG

VCC_RXR_DMI_1
VCC_RXR_DMI_2

DMI

DMI

CRESTLINE_1p0

CRESTLINE_1p0

12

C241

C241

0.47uF/10V_6

0.47uF/10V_6

Disable

GND

1.5V

GND

GND

GND

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14

VTT

VTT

VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22

VCC_DMI

VTTLF1
VTTLF2
VTTLF3

VTTLF

VTTLF

U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1

AT23
AU28
AU24
AT29
AT25
AT30

AR29

B23
B21
A21

AJ50

BK24
BK23
BJ24
BJ23

A43

C40
B40

AD51
W50
W51
V49
V50

AH50
AH51

A7
F2
AH1

12

C496

C496

0.47uF/10V_6

0.47uF/10V_6

2

LVDS Disable/Enable guideline

External VGA with EV@part,Internal VGA with IV@ part

If SDVO Disable
LVDS Disable

Signal

GND

VCCD_LVDS

VCCA_LVDS

GND

VCCTX_LVDS

GND

12

12

C229

C229

C231

C231

2.2uF/6.3V_6

2.2uF/6.3V_6

4.7uF/6.3V_6

4.7uF/6.3V_6

Place on the edge.

12

12

C236

C236

C217

C217

4.7uF/6.3V_6

4.7uF/6.3V_6

0.47uF/10V_6

0.47uF/10V_6

Place on the edge.

+1.25V_AXD

12

C193

C193
1uF/6.3V

1uF/6.3V

10U/6.3V_8

10U/6.3V_8

+1.8VSUS_VCC_SM_CK

200mA

+1.8VSUS_VCC_TX_LVDS

+3V_VCC_HV

12

C492

C492

0.1uF/10V

0.1uF/10V

+VCC_RXR_DMI

+VTTLF1
+VTTLF2
+VTTLF3

C194

C194

10U/6.3V_8

10U/6.3V_8

12

+

+

C426

C426

C160

C160

10U/6.3V_8

10U/6.3V_8

+VCC_PEG

C199

C199
220U/2.5V_B

220U/2.5V_B

10U/6.3V_8

10U/6.3V_8

1 2

12

+1.8VSUS_VCC_SM_CK

C421

C421

Ivcc_VTT FSB
supply
current

0.85A

+1.05V_VCCP

L12 0L12 0

Reserved L81 pad for
inductor.

Place caps close
to VCC_AXD.

+1.25V

Ivcc_DMI supply

C442

C442

current 100mA

0.1uF/10V

0.1uF/10V

+1.8VSUS_VCC_TX_LVDS

100mA

12

12

+

+

C491

C491
1000pF/50V

1000pF/50V

L40

L40

BLM21PG220SN1D

BLM21PG220SN1D

12

C460

C460

4.7uF/6.3V_6

4.7uF/6.3V_6

L38

L38

0_8

0_8

12

C430

C430

0.1uF/10V

0.1uF/10V

If SDVO enable
LVDS Disable

1.8V

GND

GND

L19 1uH/300mA_8L19 1uH/300mA_8

1uH+-20%_300mA

C508

C508
220U/2.5V_B

220U/2.5V_B

+1.05V_VCCP

+VCC_PEG

L33

L33
1uH/300mA_8

1uH/300mA_8

12

1uH+-20%_300mA

R254

R254
1/F_6

1/F_6

+VCC_SM_CK_L

12

C419

C419
10U/6.3V_8

10U/6.3V_8

If SDVO enable
LVDS enable

1.8V

1.8V

1.8V

+3V_VCC_HV

+1.25V

+1.8VSUS

12

Ivcc_PEG
supply current

1.2A

Ivcc_RX_DMI
supply current
250mA

12

D28

D28
CH501H-40PT

CH501H-40PT

+3V_VCC_HV

R296 0R296 0

12

+1.05V_VCCP

21

40 mil
wide

+3V_VCC_HV_L

12

R31010R310
10

+3V

+1.25V

12

C243

C243
1uF/6.3V

1uF/6.3V

Place caps close
to VCC_AXF

+1.8VSUS

C248

C248

4.7uF/6.3V_6

4.7uF/6.3V_6

1

10

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

PROJECT : SW7

PROJECT : SW7

Quanta Computer Inc.

Quanta Computer Inc.

Crestline (POWER)

Crestline (POWER)

Crestline (POWER)

1

1A

1A

1A

of

of

of

10 44Friday, September 28, 2007

10 44Friday, September 28, 2007

10 44Friday, September 28, 2007

5

U23I

U23I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

D D

C C

B B

A A

5

AB20
AB23
AB26
AB28

AB31
AC10
AC13

AC39
AC43
AC47

AD21
AD26
AD29

AD41
AD45
AD49

AD50

AE10

AE14

AF20

AF23

AF24

AF31
AG38

AG43
AG47
AG50

AH40
AH41

AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45

AJ49
AK20
AK21
AK26
AK28
AK31
AK51

AM11
AM13

AM41
AM45

AN38
AN39
AN43

AP48
AP50

AR11
AR39

AR44
AR47

AT10
AT14
AT41
AT49

AU23
AU29

AU36
AU49
AU51

AV39
AV48

AW1

AW12
AW16

AC3

AD1

AD3

AD5
AD8

AE6

AG2

AH3

AH7
AH9

AM3
AM4

AN1

AN5
AN7
AP4

AR2

AR7

AU1

AU3

AL1

VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

CRESTLINE_1p0

CRESTLINE_1p0

VSS

VSS

4

4

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

3

U23J

U23J

C46

VSS_199

C50

VSS_200

C7

VSS_201

D13

VSS_202

D24

VSS_203

D3

VSS_204

D32

VSS_205

D39

VSS_206

D45

VSS_207

D49

VSS_208

E10

VSS_209

E16

VSS_210

E24

VSS_211

E28

VSS_212

E32

VSS_213

E47

VSS_214

F19

VSS_215

F36

VSS_216

F4

VSS_217

F40

VSS_218

F50

VSS_219

G1

VSS_220

G13

VSS_221

G16

VSS_222

G19

VSS_223

G24

VSS_224

G28

VSS_225

G29

VSS_226

G33

VSS_227

G42

VSS_228

G45

VSS_229

G48

VSS_230

G8

VSS_231

H24

VSS_232

H28

VSS_233

H4

VSS_234

H45

VSS_235

J11

VSS_236

J16

VSS_237

J2

VSS_238

J24

VSS_239

J28

VSS_240

J33

VSS_241

J35

VSS_242

J39

VSS_243

K12

VSS_245

K47

VSS_246

K8

VSS_247

L1

VSS_248

L17

VSS_249

L20

VSS_250

L24

VSS_251

L28

VSS_252

L3

VSS_253

L33

VSS_254

L49

VSS_255

M28

VSS_256

M42

VSS_257

M46

VSS_258

M49

VSS_259

M5

VSS_260

M50

VSS_261

M9

VSS_262

N11

VSS_263

N14

VSS_264

N17

VSS_265

N29

VSS_266

N32

VSS_267

N36

VSS_268

N39

VSS_269

N44

VSS_270

N49

VSS_271

N7

VSS_272

P19

VSS_273

P2

VSS_274

P23

VSS_275

P3

VSS_276

P50

VSS_277

R49

VSS_278

T39

VSS_279

T43

VSS_280

T47

VSS_281

U41

VSS_282

U45

VSS_283

U50

VSS_284

V2

VSS_285

V3

VSS_286

CRESTLINE_1p0

CRESTLINE_1p0

3

VSS

VSS

VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305

VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313

2

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Crestline (VSS)

Crestline (VSS)

Crestline (VSS)

PROJECT : SW7

PROJECT : SW7

Quanta Computer Inc.

Quanta Computer Inc.

1

11

1

1A

1A

11 44Friday, September 28, 2007

11 44Friday, September 28, 2007

11 44Friday, September 28, 2007

1A

of

of

of

Strap table

5

All strap are sampled with respect to the leading edge of the GMCH Power OK(PWROK) Signal
CFG[17:3] Have internal Pull-up

CFG[18:19] Have internal Pull-down
Any CFG signal strapping option not list below should be left NC Pin

Pin Name Strap description

D D

CFG[2:0]

CFG[4:3]

CFG5

CFG6

CFG7

CFG8

CFG9

CFG[11:10]

C C

CFG[13:12]

CFG[15:14]

CFG16

CFG[18:17]

SDVO_CTRLDATA

CFG19

CFG20

B B

DMI X2 Select

MCH_CFG_5 Low = DMIX2

CFG57

High = IDMIX4(Default)

R81

R81
*4.02K/F

*4.02K/F

FSB Frequency Select

Reserved

DMI X2 Select

Reserved

CPU Strap

Low power PCI Express

PCI Express Graphics Lane Reversal

Reserved

XOR/ALLZ

Reserved

FSB Dynamic ODT

Reserved

SDVO Present

DMI Lane Reversal

SDVO/PCIe concurrent

DMI Lane Reversal

MCH_CFG_19 Low = Normal operation(Default)

4

High = Reverse Lane

3

2

Configuration

010 = FSB 800MHz
011 = FSB 667MHz

0 = DMI X2
1 = DMI X4(Default)

0 = Reserved
1 = Mobile CPU(Default)

0 = Normal mode
1 = Low Power mode

0 = Reverse Lanes
1 = Normal operation(Default)

00 = Reserved
01 = XOR Mode Enable
10 = All-Z Mode Enabled
11 = Normal operation(Default)

0 = Dynamic ODT disable
1 = Dynamic ODT Enable(Default)

0 = No SDVO Card present(Default)
1 = SDVO Card Present

0 = Normal operation(Default)
1 = Reverse Lanes

0 = Only SDVO or PCIE x1 is operation(Default)
1 = SDVO and PCIE x1 are operating simultaneously via the PEG port

XOR /ALLz /Clock Un-gating

MCH_CFG_12MCH_CFG_13 Configuration

0

0

1

1

0

1

0

1

Clock gating disable

XOR Mode Enable

ALL-z Mode Enable

Normal operation(Default)

PCI Express Graphics

MCH_CFG_9 Low = Reverse Lane

High = Normal operation(Default)

1

SDVO Present

Strap define at External
DVI control page

12

FSB Dynamic ODT

MCH_CFG_16 Low = ODT Disable

A A

CFG167

High = ODT Enable(Default)

R70

R70
*4.02K/F

*4.02K/F

5

SDVO/PCIE Concurrent operation

MCH_CFG_20

CFG207

Low = Only SDVO or PCIE X1 is
operational(Default)
High = SDVO andPCIE X1 are operating
simultaneously via the PEG port

+3V

R71

R71
*4.02K/F

*4.02K/F

4

CFG127
CFG137

R75

R75

R82

R82

*4.02K/F

*4.02K/F

*4.02K/F

*4.02K/F

3

2

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

GMCH STRAP

GMCH STRAP

GMCH STRAP

PROJECT : SW7

PROJECT : SW7

Quanta Computer Inc.

Quanta Computer Inc.

12 44Friday, September 28, 2007

12 44Friday, September 28, 2007

12 44Friday, September 28, 2007

of

of

1

of

1A

1A

1A

1

m

m

2

3

4

5

6

7

8

0.1uF/10V

0.1uF/10V

13 44Friday, September 28, 2007

13 44Friday, September 28, 2007

13 44Friday, September 28, 2007

C37

C37

8

13

C122

C122

0.1uF/10V

0.1uF/10V

of

of

of

1A

1A

1A

DDRII DUAL CHANNEL A,B.

A A

DDRII A CHANNEL

DDR_A_MA[13..0]
+0.9V_DDR_VTT

+0.9V_DDR_VTT

C40

C39

C38

C38

C39

0.1uF/10V

0.1uF/10V

DDR_A_MA7
DDR_A_MA11

DDR_A_MA6
DDR_A_MA4

DDR_A_BS1
DDR_A_RAS#

DDR_A_MA13
M_ODT0

DDR_A_MA12
DDR_A_BS2

DDR_A_MA8
DDR_A_MA9

DDR_A_MA5
DDR_A_MA3

DDR_A_BS0
DDR_A_MA10

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA2
DDR_A_MA0

DDR_A_MA1

2

0.1uF/10V

0.1uF/10V

C102

C102

0.1uF/10V

0.1uF/10V

0.1uF/10V

0.1uF/10V

B B

DDR_A_BS18,14
DDR_A_RAS#8,14

M_ODT07,14

C C

Please these resistor
closely DIMMA,all
trace length<750 mil.

D D

DDR_A_BS28,14

DDR_A_BS08,14

DDR_A_WE#8,14
DDR_A_CAS#8,14

DDR_B_MA147,14 DDR_A_MA14 7,14

M_ODT17,14

DDR_CS0_DIMMA#7,14

DDR_CS1_DIMMA#7,14
DDR_CKE0_DIMMA7,14
DDR_CKE1_DIMMA7,14

1

C40

C59

C59

0.1uF/10V

0.1uF/10V

RP23

RP23

2
4

4P2R-S-56

4P2R-S-56
RP22

RP22

2
4

4P2R-S-56

4P2R-S-56
RP20

RP20

2
4

4P2R-S-56

4P2R-S-56
RP19

RP19

2
4

4P2R-S-56

4P2R-S-56
RP25

RP25

2
4

4P2R-S-56

4P2R-S-56
RP24

RP24

2
4

4P2R-S-56

4P2R-S-56
RP28

RP28

2
4

4P2R-S-56

4P2R-S-56
RP27

RP27

2
4

4P2R-S-56

4P2R-S-56
RP26

RP26

2
4

4P2R-S-56

4P2R-S-56
RP21

RP21

2
4

4P2R-S-56

4P2R-S-56

R8 56R8 56
R32 56R32 56

1 2

R34 56R34 56

1 2

R24 56R24 56

1 2

R33 56R33 56

1 2

R31 56R31 56

1 2

R26 56R26 56

1 2

C100

C100

0.1uF/10V

0.1uF/10V

1
3

1
3

1
3

1
3

1
3

1
3

1
3

1
3

1
3

1
3

12

DDR_A_MA[13..0] 8,14
+0.9V_DDR_VTT 40

C103

C103

C60

C60

0.1uF/10V

0.1uF/10V

0.1uF/10V

0.1uF/10V

+0.9V_DDR_VTT

R25 56R25 56
R12 56R12 56
R14 56R14 56
R10 56R10 56
R13 56R13 56
R15 56R15 56
R9 56R9 56

3

C58

C58

0.1uF/10V

0.1uF/10V

RP13

RP13

1
3

4P2R-S-56

4P2R-S-56
RP12

RP12

1
3

4P2R-S-56

4P2R-S-56
RP10

RP10

1
3

4P2R-S-56

4P2R-S-56
RP9

RP9

1
3

4P2R-S-56

4P2R-S-56
RP16

RP16

1
3

4P2R-S-56

4P2R-S-56
RP18

RP18

1
3

4P2R-S-56

4P2R-S-56
RP17

RP17

1
3

4P2R-S-56

4P2R-S-56
RP15

RP15

1
3

4P2R-S-56

4P2R-S-56
RP14

RP14

1
3

4P2R-S-56

4P2R-S-56
RP11

RP11

1
3

4P2R-S-56

4P2R-S-56

C101

C101

0.1uF/10V

0.1uF/10V

2
4

2
4

2
4

2
4

2
4

2
4

2
4

2
4

2
4

2
4

12
12
12
12
12
12
12

C99

C99

0.1uF/10V

0.1uF/10V

DDR_B_MA7
DDR_B_MA11

DDR_B_MA6
DDR_B_MA4

DDR_B_BS1
DDR_B_RAS#

DDR_B_MA13
M_ODT2

DDR_B_MA3
DDR_B_MA1

DDR_B_MA9
DDR_B_MA12

DDR_B_MA5
DDR_B_MA8

DDR_B_MA10
DDR_B_BS0

DDR_B_CAS#

DDR_B_WE#

DDR_B_MA2
DDR_B_MA0

4

C61

C61

0.1uF/10V

0.1uF/10V

C125

C125

0.1uF/10V

0.1uF/10V

DDR_B_BS1 8,14
DDR_B_RAS# 8,14

M_ODT2 7,14

Please these resistor
closely DIMMB,all
trace length<750 mil.

DDR_B_BS0 8,14

DDR_B_CAS# 8,14
DDR_B_WE# 8,14

M_ODT3 7,14

DDR_B_BS2 8,14
DDR_CS2_DIMMB# 7,14
DDR_CS3_DIMMB# 7,14
DDR_CKE2_DIMMB 7,14
DDR_CKE3_DIMMB 7,14

DDRII B CHANNEL

DDR_B_MA[13..0]

+0.9V_DDR_VTT

C121

C121

C98

C98

0.1uF/10V

0.1uF/10V

0.1uF/10V

0.1uF/10V

C131

C131

0.1uF/10V

0.1uF/10V

Layout note: Place one cap close to every 2 pullup resistors terminated to SMDDR_VTERM

5

DDR_B_MA[13..0] 8,14

C130

C130

0.1uF/10V

0.1uF/10V

6

C129

C129

0.1uF/10V

0.1uF/10V

C36

C36

0.1uF/10V

0.1uF/10V

0.1uF/10V

0.1uF/10V

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

C62

C62

0.1uF/10V

0.1uF/10V

C124

C124

0.1uF/10V

0.1uF/10V

Quanta Computer Inc.

Quanta Computer Inc.

DDRII RES.ARRAY

DDRII RES.ARRAY

DDRII RES.ARRAY

7

C123

C123

C120

C120

0.1uF/10V

0.1uF/10V

PROJECT : SW7

PROJECT : SW7

C57

C57

0.1uF/10V

0.1uF/10V

PROJECT :

PROJECT :

Quanta Co

Quanta Co