HP HDMP-1526 Datasheet

Fibre Channel Transceiver Chip

Technical Data

HDMP-1526 Transceiver

Features

• ANSI X3.230-1994 Fibre
Channel Compatible (FC-0)

• Supports Full Speed
(1062.5 MBd) Fibre Channel

• Conforms to “Fibre Channel
10-Bit Interface”
Specification

• Transmitter and Receiver
Functions Incorporated onto
a Single IC

• 10-Bit Wide Parallel TTL
Compatible I/Os

• Single +5.0 V Power Supply

Applications

• 1062.5 MBd Fibre Channel
Interface

• Mass Storage System I/O
Channel

• Work Station/Server I/O
Channel

• High Speed Proprietary
Interface

Description

The HDMP-1526 transceiver is a
single silicon bipolar integrated
circuit packaged in an EDQuad
package. It provides a low-cost,
low-power physical layer solution
for 1062.5 MBd Fibre Channel or
proprietary link interfaces. It
provides complete FC-0 func­tionality for copper transmission,
incorporating both the Fibre
Channel FC-0 transmit and

receive functions into a single
device.

This chip is used to build a high­speed interface (as shown in
Figure 1) while minimizing board
space, power and cost. It is
compatible with both the ANSI
X3.230-1994 document and the
“Fibre Channel 10-bit Interface”
specification.

The transmitter section accepts
10-bit wide parallel TTL data and
multiplexes this data into a high­speed serial data stream. The
parallel data is expected to be
8B/10B encoded data, or
equivalent. This parallel data is
latched into the input register of
the transmitter section on the
rising edge of the 106.25 MHz
reference clock (used as the
transmit byte clock).

The transmitter section’s PLL
locks to this user supplied 106.25
MHz byte clock. This clock is
multiplied by 10, to generate the

1062.5 MHz serial signal clock
used to generate the high-speed
output. The high-speed outputs
are capable of interfacing directly
to copper cables for electrical
transmission or to a separate
fiber-optic module for optical
transmission.

The receiver section accepts a
serial electrical data stream at

1062.5 MBd and recovers the
original 10-bit wide parallel data.
The receiver PLL locks onto the
incoming serial signal and
recovers the high-speed serial
clock and data. The serial data is
converted back into 10-bit
parallel data, recognizing the
8B/10B comma character to
establish byte alignment.

The recovered parallel data is
presented to the user at TTL
compatible outputs. The receiver
section also recovers two 53.125
MHz receiver byte clocks that are
180 degrees out of phase with
each other. The parallel data is
aligned with the rising edge of
alternating clocks.

The transceiver provides for on­chip local loop-back functionality,
controlled through an external
input pin. Additionally, the byte
synchronization feature may be
disabled. This may be useful in
proprietary applications that use
alternative methods to align the
parallel data.

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5964-6897E (5/96)

HDMP-1526

TRANSMITTER SECTION

PLL

PROTOCOL DEVICE

BYTSYNC

REFCLK

ENBYTSYNC

-LCKREF

Figure 1. Typical Application Using the HDMP-1526.

TX

FRAME

MUX

DATA BYTE

TX[0-9]

TXCAP0
TXCAP1

REFCLK

-LCKREF
RXCAP0
RXCAP1

RBC0
RBC1

INPUT

LATCH

PLL/CLOCK

GENERATOR

RECEIVER SECTION

INTERNAL
Tx CLOCKS

PLL/CLOCK
RECOVERY

RX

PLL

OUTPUT
SELECT

INTERNAL

LOOPBACK

SELECT

INPUT

SERIAL DATA OUT

SERIAL DATA IN

± DOUT

LOOPEN

± DIN

HDMP-1526 Block Diagram

The HDMP-1526 was designed to
transmit and receive 10-bit wide
parallel data over a single high­speed line, as specified for the FC-0
layer of the Fibre Channel standard.
The parallel data applied to the
transmitter is expected to be
encoded per the Fibre Channel
specification, which uses an 8B/10B
encoding scheme with special
reserve characters for link
management purposes. In order to
accomplish this task, the HDMP­1526 incorporates the following:

• TTL Parallel I/Os

• High-Speed Phase Lock Loops

• Clock Generation/Recovery
Circuitry

• Parallel-to-Serial Converter

• High-Speed Serial Clock-and-Data
Recovery Circuitry

• Comma Character Recognition
Circuitry

• Byte Alignment Circuitry

• Serial-to-Parallel Converter

INPUT LATCH

The transmitter accepts 10-bit wide
TTL parallel data at inputs TX[0..9].
The user-provided reference clock
signal, REFCLK, is also used as the
transmit byte clock. The TX[0..9]
and REFCLK signals must be
properly aligned, as shown in
Figure 3.

DATA BYTE

RX[0-9]

Figure 2. HDMP-1526 Transceiver Block Diagram.

DRIVER

OUTPUT

FRAME
DEMUX

AND

BYTE SYNC

BYTSYNC ENBYTSYNC

INPUT

SAMPLER

INTERNAL

Rx CLOCKS

TX PLL/CLOCK GENERATOR

The transmitter Phase Lock Loop
and Clock Generator (TX PLL/
CLOCK GENERATOR) block is
responsible for generating all
internal clocks needed by the
transmitter section to perform its
functions. These clocks are based on
the supplied reference byte clock
(REFCLK). REFCLK is used as both
the frequency reference clock for
the PLL and the transmit byte clock
for the incoming data latches. It is
expected to be 106.25 MHz and
properly aligned to the incoming

683

parallel data (see Figure 3). This
clock is multiplied by 10 to
generate the 1062.5 MHz clock
necessary for the high-speed
serial outputs.

FRAME MUX

The FRAME MUX accepts the 10­bit wide parallel data from the
INPUT LATCH. Using internally
generated high-speed clocks, this
parallel data is multiplexed into
the 1062.5 MBd serial data
stream. The data bits are
transmitted sequentially, from the
least significant bit (TX[0]) to the
most significant bit (TX[9]).

OUTPUT SELECT

The OUTPUT SELECT block
provides for an optional internal
loopback of the high-speed serial
signal, for testing purposes.

In normal operation, LOOPEN is
set low and the serial data stream
is placed at ± DOUT. When wrap­mode is activated by setting
LOOPEN high, the ± DOUT pins
are held static and the serial
output signal is internally
wrapped to the INPUT SELECT
box of the receiver section.

INPUT SELECT

The INPUT SELECT block
determines whether the signal at
± DIN or the internal loop-back
serial signal is used. In normal
operation, LOOPEN is set low
and the serial data is accepted at
± DIN. When LOOPEN is set
high, the high-speed serial signal
is internally looped-back from the
transmitter section to the receiver
section. This feature allows for
loop-back testing exclusive of the
transmission medium.

RX PLL/CLOCK RECOVERY

The RX PLL/CLOCK RECOVERY
block is responsible for frequency
and phase locking onto incoming
serial data stream and recovering
the bit and byte clocks.

In order to accomplish this, upon
startup, the user should set

-LCKREF low for a period of at
least 500 µsec. This allows the
PLL to first frequency lock onto
the 106.25 MHz reference clock
provided at the REFCLK input.
The RX PLL/CLOCK RECOVERY
circuitry multiplies this reference
clock by 10 to generate an
internal 1062.5 MHz clock. After
500 µsec, the user should set

-LCKREF high. This will allow the
receiver to frequency and phase
lock the internal 1062.5 MHz
clock onto the incoming serial
data stream. Once locked, the
receiver will recover the two

53.125 MHz receiver byte clocks
(RBC1/RBC0). These byte clocks
are approximately 180° out of
phase with each other and are
alternately used to clock the
10-bit parallel output data.

INPUT SAMPLER

The INPUT SAMPLER is
responsible for converting the
serial input signal into a retimed
serial bit stream. In order to
accomplish this, it uses the high
speed serial clock recovered from
the RX PLL/CLOCK RECOVERY
block. This serial bit stream is
sent to the FRAME DEMUX and
BYTE SYNC block.

FRAME DEMUX AND BYTE SYNC

The FRAME DEMUX AND BYTE
SYNC block is responsible for
restoring the 10-bit parallel data
from the high speed serial bit
stream. This block is also
responsible for recognizing the
comma character (or a K28.5
character) of positive disparity
(0011111xxx). When recognized,
the FRAME DEMUX AND BYTE
SYNC block works with the RX
PLL/CLOCK RECOVERY block to
properly align the receive byte
clocks to the parallel data. When
a comma character is detected
and realignment of the receiver
byte clocks (RBC1/RBC0) is
necessary, these clocks are
stretched, not slivered, to the
next possible correct alignment
position. These clocks will be
fully aligned by the start of the
second 4-byte ordered set. The
second comma character received
shall be aligned with the rising
edge of RBC1. Comma characters
should not be transmitted in
consecutive succession to allow
the receiver byte clocks to
maintain their proper recovered
frequencies.

OUTPUT DRIVERS

The OUTPUT DRIVERS present
the 10-bit parallel recovered data
byte properly aligned to the
receive byte clocks (RBC1/
RBC0), as shown in Figure 4.
These output data buffers provide
TTL compatible signals.

684

HDMP-1526 (Transmitter Section)

Timing Characteristics

TC = 0°C to +85°C, VCC = 4.5 V to 5.25 V

Symbol Parameter Units Min. Typ. Max.

t

setup

t

hold

[1]

t_txlat

Note:

1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered
by the rising edge of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by the
rising edge of the first bit transmitted).

Setup Time nsec 2
Hold Time nsec 1.5
Transmitter Latency nsec 6.25 12.2

bits 6.64 13.0

REFCLK

TX[0]-TX[9]

DATA

t-SETUP

Figure 3. Transmitter Section Timing.

± DOUT

TX[0]-TX[9]

T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5

DATA DATA

t-HOLD

DATA BYTE A

t_TXLAT

DATA BYTE B DATA BYTE C

DATA DATA

1.4 V

2.0 V

0.8 V

DATA BYTE B

REFCLK

Figure 4. Transmitter Latency.

1.4 V

685

HDMP-1526 (Receiver Section)

,

Timing Characteristics

TC = 0°C to +85°C, VCC = 4.5 V to 5.25 V

Symbol Parameter Units Min. Typ. Max.

b_sync

f_lock_rate

t

Notes:

1. This is the recovery time for input phase jumps, per the FC-PH specification Ref 4.1, Sec 5.3.

2. Tested using C

3. The RBC clock skew is calculated as t

4. The receiver latency, as shown in Figure 5, is defined as the time between receiving the first serial bit of a parallel data word (as
defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive
byte clock, either RBC1 or RBC0).

[1,2]

[2]

f_lock

valid_before

t

valid_after

t

duty

[3]

t

A-B

[4]

t_rxlat

t-VALID BEFORE

[2]

= 0.01 µF.

PLL

Bit Sync Time bits 2500
Frequency Lock Time µsec 500

(from Time of Setting -LCKREF = 0)
Frequency Lock Rate (when -LCKREF = 0) kHz/µsec 200
Time Data Valid Before Rising Edge of RBC nsec 3 5.8
Time Data Valid After Rising Edge of RBC nsec 1.5 3.3
RBC Duty Cycle % 40 60
Rising Edge Time Difference nsec 8.9 9.4 9.9
Receiver Latency nsec 25.0 33.9

bits 26.6 36

- t

A-B(max)

t-VALID AFTER

A-B(min)

.

RBC1

RX[0]-RX[9]

BYTSYNC

RBC0

Figure 5. Receiver Section.

DATA BYTE C

R5 R6 R7 R8 R9 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R2 R3 R4 R5

± DIN

RX[0]-RX[9]

K28.5

DATA DATA

DATA BYTE D

t_RXLAT

DATA BYTE A DATA BYTE D

DATA DATA

1.4 V

2.0 V

0.8 V

2.0 V

0.8 V

1.4 V

Figure 6. Receiver Latency.

686

RBC1/0

1.4 V