HP HDMP-1514, HDMP-1512 Datasheet

Fibre Channel Transmitter and
Receiver Chipset

Technical Data

HDMP-1512 Transmitter
HDMP-1514 Receiver

Features

• ANSI X3.230-1994 Fibre
Channel Standard
Compatible (FC-0)

• Selectable 531.25 Mbaud or

1062.5 Mbaud Data Rates

• Selectable On Chip Laser
Driver and 50 Ω Cable
Driver

• TTL Compatible I/Os

• Single +5.0 V Power Supply

Applications

• Mass Storage System I/O
Channel

• Work Station/Server I/O
Channel

• High Speed Peripheral
Interface

Description

The HDMP-1512 transmitter and
the HDMP-1514 receiver are
bipolar integrated circuits,
separately packaged, in 80 pin M­Quad packages. They are used to
build a high speed Fibre Channel
link for point to point data com­munications. Shown in Figure 1 is
a typical full duplex point-to­point Fibre Channel link. The
sending system provides parallel,
8B/10B, encoded data and a
transmit byte clock to the HDMP­1512 transmitter. Using the trans­mit byte clock, the transmitter

converts the data to a serial
stream and sends it over a copper
cable or fiber-optic link. The
receiver converts the serial data
stream back to parallel encoded
data and presents it, along with
the recovered transmit byte
clock, to the receiving system.
The sending system has the
option to electrically wrap the
transmitted data back to the local
receiver. It is possible to transmit
over the cable driver, or laser
driver when data is being
wrapped back to the local
receiver.

The two-chip set (transmitter
chip and receiver chip) is
compatible with the FC-0 layer of
the American National Standards
Institute (ANSI), Fibre Channel
specification, X3.230-1994. This
specification defines four
standard rates of operation for
Fibre Channel links. The HDMP­1512 and HDMP-1514 chip-set
will operate at the two highest
defined serial rates of 531.25
Mbaud and 1062.5 Mbaud. These
serial baud rates correspond to
8B/10B encoded byte rates of 50
Mbytes/sec and 100 Mbytes/sec
respectively. The proper setting
of a single pin on each chip
selects the desired rate of
operation.

Several features, exclusive to this
chip-set, make it ideal for use in
Fibre Channel links. In addition,
the laser driver on the transmitter
chip, the dual loss of light
detectors on the receiver chip,
and the power supervisor and
power reset features make this
chip-set ideal for use with laser
optics. The serial cable driver
(transmitter chip), and the cable
equalizer (on the receiver chip),
can be operated in conjunction
with, or as an alternative to, the
laser driver. The laser driver can
also be driven directly with an
external high speed serial input.

Altogether, the various features,
input/output options, and
flexibility of this chip-set make
several unique link configurations
possible. In particular, it is ideally
suited for use in applications
where conformance to the FCSI
specification # 301-Rev 1.0,
Gbaud Link Module Specification,
is desired.

656

5964-6637E (4/96)

REF CLOCK

CLOCK

ENCODED DATA

ENCODED DATA

CLOCK

REF CLOCK

Figure 1. Point-to-Point Data Link.

DATA BYTE 0

Tx [00:09]

DATA BYTE 1

Tx [10:19]

Tx

Rx

10

10

SERIAL LINK

SERIAL LINK

-COMGEN

TTL INTERFACE

AND

INPUT LATCH

20

Rx

Tx

FRAME

MULTIPLEXER

± SI

SELECT

CLOCK

ENCODED DATA

ENCODED DATA

CLOCK

TS2

TS1

EWRAP

I/O

CABLE

DRIVERS

2

± LOUT

2

± SO

TBC

Figure 2. HDMP-1512 (Tx) Block Diagram.

Transmitter Operation

The block diagram of the HDMP­1512 transmitter is shown in
Figure 2. The basic functions of
the transmitter chip are the TTL
Interface and Input Latch, Frame
Multiplexing, Input/Output
selection, cable drivers, Laser
Driver, and monolithic Phase
Locked loop clock generator. The
actual operation of each function
changes slightly, according to the
desired configuration and option
settings. Figures 18 and 19 show
schematically how to terminate
each pin on the HDMP-1512
when used in systems incorporat­ing either copper or fiber media.

PLL/CLOCK

GENERATOR

PPSEL

SPDSEL

INTERNAL
CLOCKS

There are two main modes of
operation for the transmitter
chip, both are based on the
selected baud rate. The baud rate
is controlled by the appropriate
setting of the SPDSEL pin, #67.
When this pin is set low, the
transmitter operates at a serial
rate of 531.25 Mbaud. When pin
#67 is set high the transmitter
operates at a serial rate of 1062.5
Mbaud. As such, the two main
modes of operation are the

531.25 Mbaud mode and the

1062.5 Mbaud mode.

The transmitter does not encode
the applied data. It assumes the

2

LASER

DRIVER

-LZON

FAULT

± LZOUT

LASER
CONTROLS

data is pre-encoded using the
8B/10B encoding scheme as
defined in ANSI X3.230-1994.
The TTL input interface receives
data at the standard TTL levels
specified in the dc Electrical
Specification table. The internal
phase locked loop (PLL) locks to
the transmit byte clock, TBC.
TBC is supplied to the transmitter
chip by the sending system. TBC
should be a 53.125 MHz clock
(± 100 ppm) as defined in
X3.230-1994. Once the PLL has
locked to TBC, all the clocks used
by the transmitter are generated
by the internal clock generator.

657

When operating in the 531.25
Mbaud mode, data byte 0,
Tx[00:09], is active and is
clocked into the input latch a
single byte (10 bits) on each
rising edge of TBC. In the 1062.5
Mbaud mode both data byte 0,
Tx[00:09], and data byte 1,
Tx[10:19], are active. In 1062.5
Mbaud mode, data byte 0 and
data byte 1 are clocked into the
transmitter on the rising edge of
every clock cycle, (TBC). There is
one minor variation possible in
the 1062.5 Mbaud mode, referred
to as “ping-pong” mode. Ping­pong mode is selected by setting
the PPSEL pin (#34) high. In this
mode the transmitter clocks data
into the input latch one byte per
half clock cycle. Data byte 0 is
transmitted on the rising edge of
TBC and data byte 1 is trans­mitted 1/2 clock cycle later. See
Figure 16 for timing information.

The input latch will stop sending
the data applied to the Tx[00:09]
data pins when a low is applied to
the -COMGEN pin (#32) and will
send the pre-set special Fibre
Channel character, K28.5 instead.
The 8B/10B coding scheme,
adopted by Fibre Channel, con­verts 8 bit data words into 10 bit
representations of the actual
data. Of all the possible combina-

tions of 10 bit binary words, the
8B/10B code reserves 256 of
them to represent the valid
combinations of 8 bit data. Some
of the remaining combinations
are reserved for special functions.
The character reserved for
defining the transmitted word
boundary has been defined as the
K28.5 character, also known as a
comma character. The receiver
will automatically reset registers
and clock when it receives a
comma character (this will be
discussed in more detail in the
receiver operation section). Every
valid 8 bit data word is actually
represented by one of two 10 bit
codes, indicating either positive
or negative running disparity.
The input latch only generates
the K28.5 character with positive
disparity (0011111010).

In Figure 2, the Frame
Multiplexer utilizes shift registers
and a multi-stage multiplexing
scheme to convert the 10 or 20
parallel data bits to a serial data
stream. This serial data stream is
then fed directly into the Input/
Output Select portion of the
transmitter.

The I/O Select function allows use
of both the internally serialized
Fibre Channel data stream and an

externally supplied Fibre Channel
data stream denoted as ± SI (pins
11 and 12). By using the proper
settings of TS1, TS2, and EWRAP
(pins 76, 75, and 71
respectively), the internal data
stream and the external data
stream can be directed to various
combinations of the cable driver
output, the laser driver output,
and the electrical loopback
output. The possible I/O
combinations are listed in the
Input Output Select Table and the
functionality is described in more
detail in the Transmitter Laser
Driver Operation section below.

The cable driver function
provides a 50 Ω differential cable
driver output at pins 5 and 6
(± SO). The simplified circuit is
the O-BLL section shown in
Figure 10. A similar output is
provided to allow electrical
loopback, or wrap of the local
data back to the local receiver for
diagnostics. This is denoted as
± LOUT on pin 8 and pin 9.

The final function on the
transmitter chip is the Laser
Driver block which provides a
high speed differential output,
± LZOUT, at pins 19 and 20.
There are several other laser
control I/Os which will be

HDMP-1512 Input Output Select Table

Data Source For: Active Outputs

Mode TS1 TS2 EWRAP ±SO ±LZOUT ±LOUT ±SO ±LZOUT ±LOUT

0 0 0 0 NA Internal NA no yes no
1 0 0 1 NA NA Internal no no yes
2 0 1 0 Internal Internal NA yes yes no
3 0 1 1 Internal NA Internal yes no yes
4 1 0 0 Internal NA NA yes no no
5 1 0 1 NA Internal Internal no yes yes
6 1 1 0 Internal ± SI NA yes yes no
7 1 1 1 Internal NA ± SI yes no yes

658

± SI

VCC_LZ1

VCC_LZ

GND_LZ

-LZON

LZPWRON

FAULT

INTERNAL

DATA

STREAM

11
12

16
23

24
25

26

30

36

29

INPUT

SELECT

MUX

LASER ON

ERROR

DETECTOR

AC AMP

DISABLE

WINDOW

DETECTOR

BANDGAP

REFERENCE

BANDGAP

DETECTOR

Tx CHIP BOUNDARY

+

AC AMP

–

LZDC
–
DC

OP-AMP
+

10 nF
10 nF

V

CC

17

+LZOUT

19

-LZOUT

20

LZCSE

14

21

_LZAC

0.1 µF

5 Ω

0.1 µF 0.1 µF

25 Ω TRANSMISSION LINE

POT 2
50 Ω

5 Ω

0.1 µF

0.1 µF

25 Ω

301 Ω

P1 (β >= 100)

8 Ω

25 Ω

V

CC

V

CC

P2

0.1 µF

2.2 Ω

EXTERNAL
CONTROL

-LZBG

V

CC

2715 28 22

LZTC

0.1 µF

POT 1 5 KΩ

Figure 3. Laser Driver Block Diagram and External Circuitry.

described in more detail in the
laser driver operation section
below.

± SI pins. The user selects
between these two data sources
through the proper settings of
pins TS1, TS2, and EWRAP (pins

Transmitter Laser Driver Operation

The block diagram of the HDMP­1512, Tx, laser driver circuitry is
shown in Figure 3. The laser
driver is enabled by setting

-LZON (pin 30) low and
LZPWRON (pin 36) high. The
circuitry in Figure 3, shown
outside the chip boundary (dotted
box), illustrates the external
components required to complete
a typical laser driver connection.

76, 75, and 71). The possible
combinations of active inputs and
outputs are shown in the Input/
Output Select Table. The chosen
high speed input is then modu­lated onto the laser by the ac
amplifier. The external poten­tiometer, Pot 2, shown connected
to pin LZCSE (# 14) is used to
adjust the laser modulation
depth. The laser driver output is
at pins 19 and 20, ± LZOUT.
Laser diode dc bias control is
provided through the LZDC

The input data source to the laser
driver is user selected from either
the internally generated data
stream, or an externally supplied
high speed data stream. The
externally supplied data stream is
applied to the high speed input

(# 21) pin. Adjustment of Pot 1
sets the nominal dc bias desired
for the laser diode. The
equivalent output circuit of LZDC
is shown in Figure 4. Laser diode
fault and safety control is imple­mented through the combination

LZMDFLZBTP

VCC_LZ

54

400

LZDC

Figure 4. LZDC Equivalent Output
Circuit (Tx pin # 21).

of the window detector, error
detector, Laser On pin # 30
(-LZON), laser monitor diode
feedback pin # 22 (LZMDF), and
the op-amp dc bias control
circuit. The window detector
monitors the voltage on pin
LZMDF. If this voltage goes out
of range by more than ± 10%
from the nominal setting, the

659

capacitor on pin LZTC (# 27) will
begin to discharge. After
approximately 2 msec, the
voltage on LZTC falls to the fault
value and the error detector will
bring the FAULT pin (# 29) high
to alert the system. The error
detector will also hold the voltage
on LZMDF low, until a reset is
initiated.

The -LZON pin is used to disable
the laser driver under system
control or in conjunction with an
external open-fiber control (OFC)
chip. This pin is also used to
reset the error detector and
recharge the capacitor on pin
LZTC.

The LZPWRON pin, # 36, is used
to hold off dc power to the laser
driver until proper dc bias is
applied to the laser diode. When
LZPWRON goes high, the laser
driver is enabled, when it is low,
it is disabled. If not used, this pin
should be tied low.

Receiver Operation

The block diagram of the HDMP­1514 receiver is shown in Figure

5. The functions included on the
receiver are a coaxial cable
equalizer, two independent loss
of light (LOL) detectors, an input
select function, monolithic phase
locked loop and clock recovery
circuits, a clock generator, frame
demultiplexer and comma
detector, power supply super­visor, and output latch with TTL
drivers. Figures 20 and 21 show
schematically how to terminate
each pin on the HDMP-1514
when used in systems incorporat­ing either copper or fiber media.

In the most basic sense, the
receiver accepts a serial electrical
data stream at 1062.5 Mbaud or

531.25 Mbaud and recovers the
8B/10B encoded parallel data and
clock that was applied to the
transmitter. Like the transmitter,
the receiver has several configu­ration options which interrelate

according to the desired mode of
operation.

The two main modes of operation
for the receiver are based on the
desired signalling rate. The
signalling rate is controlled by
the proper setting of the SPDSEL
pin # 71. When this pin is set
low, the receiver operates at a
serial rate of 531.25 Mbaud.
When pin # 71 is set high, the
receiver operates at a serial rate
of 1062.5 Mbaud.

In a typical configuration, the
serial electrical data stream will
be applied to the ± DI pins, # 19
and # 20 on the receiver. The
serial electrical data stream may
have been transmitted over a
fiber optic link or a copper cable
link (several variations of each
link type is possible). For use
with copper links, a selectable
cable equalizer is available at the
input. This equalizer can be
switched into or out of the data

LOLA

LOLB

EWRAP

DR_REF

± DI

-EQEN

± LIN

VCC_HS

Figure 5. HDMP-1514 (Receiver) Block Diagram.

CABLE

EQUALIZER

SUPERVISOR

SUPPLY

-POR

LOL

DETECTORS

INPUT

SELECT

PS_CT

660

L_UNUSE

PLL AND

CLOCK

SELECT

-LCK_REF

-TCLKSEL

FRAME
DEMUX

COMMA
DETECT

PPSEL

CLKIN

AND

INTERNAL

CLOCKS

EN_CDET

20

SPDSEL

CLOCK

GENERATOR

OUTPUT

LATCH AND

TTL

INTERFACE

10

10

RBC0

RBC1

COM_DET

DATA BYTE 0
Rx [00:09]

DATA BYTE 1
Rx [10:19]

path using the -EQEN pin, # 32.
Setting pin #32 high disables the
equalizer. Setting pin # 32 low
enables the equalizer. The typical
performance of the input
equalizer is shown in the
(frequency response) plot of
Figure 7. The impact of the
equalizer is improved BER
performance over long lengths of
cable (10 to 20 meters).

Connected to the ± DI input pins,
prior to the equalizer, are the loss
of light detectors, LOLA (pin 28)
and LOLB (pin 29). Actually,
since these detectors monitor the
incoming serial electrical data
stream, they can be thought of as
loss of “signal” detectors. These
signals can be used to determine
if the incoming signal line is
connected properly. In the case
of a fiber optic system they can
be used to shut down laser output
power for laser safety considera­tions. The LOL detectors measure
transitions in the incoming data
stream that exceed a pre-set
peak-to-peak differential signal or
threshold level. The default peak­to-peak differential threshold
voltage is 25 mV and can be
adjusted by connecting a resistive
divider to the DR_REF pin (#21)
as shown in Figure 6. The rela-

+5 V

2 KΩ

8 KΩ POTENTIOMETER

PIN #21,
DR_REF

2 KΩ

tionship of the DR_REF voltage
to the peak-to-peak differential
threshold voltage is shown in
Figure 8. When the input signal
level falls below the threshold
voltage for 4 clock cycles, or 80
bit times, the signals at pins 28
and 29 will go high.

Once the serial data stream
passes the cable equalizer
function it is directed to an Input
Select section. A second high
speed serial data input, denoted
± LIN, is applied at pins # 16 and
# 17 and is connected directly to
the Input Select section. This data
input is intended for diagnostic
purposes. It is not affected by the
cable equalizer and has no effect
on the loss of light detectors. The
± LIN input should mainly be
used when it is desired to directly
connect the local transmitter
serial output data stream to the
local receiver (local loopback).
The Input Select function uses
the EWRAP signal, pin # 34, to
determine which serial data
stream to pass on to the rest of
the receiver. If EWRAP is high,
then the ± LIN signal is used. If
EWRAP is low the ± DI signal is
used.

The PLL and Clock select
circuitry contains a monolithic,
tunable, oscillator. This oscillator
phase locks to the selected high
speed data input and recovers the
high speed serial clock. To keep
the internal oscillator tuned close
to the incoming signal frequency,
an external reference oscillator is
applied to the CLKIN input, pin
# 7. The signal on the -LCK_REF
input, pin # 36, controls whether
the receiver oscillator locks to the
reference oscillator or to the

incoming data stream. When

-LCK_REF is toggled low, the
receiver frequency locks to the
signal at CLKIN. When the

-LCK_REF pin is toggled high,
the receiver phase locks to the
selected high speed serial data
input. This process of locking to
a local reference oscillator, prior
to receiving incoming data,
improves (shortens) the overall
time required by the receiver to
acquire lock. The LUNUSE input,
pin 73 will cause the receiver to
frequency lock on the CLKIN
signal under faulty or no input
signal conditions. The LUNUSE
signal needs to be provided to the
receiver by an external open fiber
control circuit or other control
logic. Once the receiver has
locked to the incoming data
stream at ± DI (EWRAP = 0 and

-LCKREF = 1), if LUNUSE
toggles high then the receiver will
switch to frequency lock on
CLKIN. If, however, the receiver
is locked onto the local data
wrapped back to the ± LI input
(EWRAP = 1 and -LCKREF = 1)
then the receiver stays locked to
the incoming signal at ± LI even
when LUNUSE goes high. In
summary, when the LUNUSE
input is set low, the receiver
frequency locks to the CLKIN
signal when the input to

-LCKREF is low and phase locks
to either the ± DI or ± LI signal,
depending on which input is
selected, when -LCKREF toggles
high. LUNUSE then, is used to
cause the receiver to frequency
lock to the reference oscillator at
CLKIN after the receiver has
established phase lock to the
incoming data signal at ± DI, and
the system determines the link is
faulty and not in EWRAP mode.

Figure 6. Simple Circuit Used to
Adjust the Voltage on Rx pin # 21,
DR_REF.

661

-LCK_REF EWRAP LUNUSE Rx Lock

0 x x CLKIN
100DI
1 0 1 CLKIN
111LI
110LI

The table above llustrates these
various settings.

incoming data stream at the ± DI
input but the actual frame or

word boundary will be undeter­Normally, the recovered serial
clock is used by the clock gener­ator to generate the various
internal clocks the receiver uses
including the receive clock
outputs RBC0 (pin 69) and RBC1
(pin 67).

mined. The EN_CDET pin (# 38)

should be set high now. With the

EN_CDET pin set high, the

receiver will scan the incoming

data stream for a comma charac-

ter. Once a comma character is

received, the internal clocks and

registers are reset giving proper
The final receiver clocking
feature is included for test
purposes only. By applying a low
to the -TCLKSEL input, pin 5, the
internal phase locked loop is
bypassed and the receiver uses
the CLKIN signal as the high
speed serial clock. Under normal
operating conditions the

-TCLKSEL pin should be tied
high.

frame alignment. The receiver

will reset on every comma

character that is transmitted as

long as EN_CDET is held high.

When the internal clock genera-

tor is reset due to the detection of

a comma character, internal

circuitry prevents a clock “sliver”

from appearing at the receive

clock outputs (RBC0 and RBC1).

This antisliver circuit assures

each clock output high, or low,
In a Fibre Channel link, frame
alignment is accomplished
through the transmission and
detection of the special character
K28.5, also known as a comma
character. Prior to actual data
transmission the system will
transmit a comma character over
the physical link. To start, the
receiver should be frequency
locked to the local reference
oscillator (-LCKREF set low). To
ensure frequency lock is

will be held for at least one half

the frame rate time. When

EN_CDET is set low the receiver

ignores all incoming comma

characters and assumes the

current frame and bit alignment

is correct. EN_CDET is

automatically disabled when

-LCKREF is set low. The

COM_DET pin, #75, on the

receiver will go high when a

comma character is detected (see

Figure 15).
achieved, -LCKREF should be
held low for a minimum of 500
µsec (see Rx Timing Characteris­tics, t

). It then should be

flock

toggled high. At this point the
receiver will phase lock to the

Now that frame alignment has

been achieved, the receiver is

ready to receive full speed serial

data and demultiplex it back to

its original 10 bit or 20 bit

4

2

0

-2

-4

-6

RELATIVE GAIN – dB

-8

-10

1.00E

1.00E

+ 06

Figure 7. Typical Frequency Response
Plot of the Internal Input Equalizer.

1.00E

+ 07

+ 08

FREQUENCY – f – Hz

1.00E
+ 09

1.00E
+ 10

parallel word format. This data is
then placed into the output latch.
The data output is presented in
the standard TTL output levels
and characteristics specified in
the dc and ac Electrical Specifica­tion tables. When operating in
531 Mbaud mode the receiver
generates output data in a single
byte wide (10 bits) output format.
This is data byte 0 and is denoted
RX[00:09] on pins 53 through

62. In 1063 Mbaud mode the data
output is generated in a two byte
wide (20 bits) format, data byte 0
and data byte 1. Data byte 0 is
denoted RX[00:09] on pins 53
through 62 and data byte 1 is
denoted RX[10:19] on pins 43
through 52. In standard operation
data byte 0 and data byte 1 will
both be clocked into the output
latch at the same time, on the
falling edge of RBC0. An
alternate mode of operation is
ping-pong mode. In ping-pong
mode the data is clocked out 1
byte at a time with byte 0 clocked
out on the falling edge of RBC0
and byte 1 clocked out on the
falling edge of RBC1. To set the
receiver to operate in ping-pong
mode, the PPSEL pin, # 76,
should be set high (otherwise it
should be tied low).

662

Rx Power Supply Supervisor

A power supply supervisor feature
has been designed into the
receiver as a system aid during
power-up. The -POR (pin # 27)
output is held low until the power
supply voltage (VCC) crosses the
nominal threshold of 4.25 volts.
Then, following a delay time
determined by the capacitor value
connected to the PS_CT pin
(# 22), the -POR output goes high.
The typical delay time is 8 msec,
with a 0.47 µF capacitor attached
to PS_CT.

90
80
70
60
50

DEFAULT

40

THRESHOLD

30
20

p-p DIFFERENTIAL – mV

10

LOL THRESHOLD VOLTAGE –

0

0

0.5 2.5
DR_REF VOLTAGE – V

Figure 8. Typical Plot of Loss of Light
Threshold Voltage vs. DR_REF
Voltage.

1.0

1.5

2.0

Recommended Handling Precautions

Additional circuitry is built into the
various input and output pins on
these chips to protect them against
low level electrostatic discharge,
however, they are still ESD
sensitive and standard procedures
for static sensitive devices should
be used in the handling and
assembly of the HDMP-1512 and
the HDMP-1514. The packing
materials used for shipment of
these devices was selected to
provide ESD protection and to
prevent mechanical damage.

During test and use, under power­up conditions, extreme care should
be taken to prevent the high speed
I/Os from being connected to
ground as permanent damage to
the device is likely.

HDMP-1512 (Tx), HDMP-1514 (Rx)

Absolute Maximum Ratings

Operation in excess of any one of these conditions may result in permanent damage.

Symbol Parameter Units Min. Max.

V

V

IN,TTL

V

IN,H50

I

O,TTL

T

T

T

max

CC

stg

J

Supply Voltage V -0.5 6.0
TTL Input Voltage V -0.7 VCC + 0.7
I-H50 Input Voltage, Figure 9 V VCC - 2.0 VCC + 0.7
TTL Output Source Current mA 13
Storage Temperature °C -40 +130
Junction Operating Temperature °C 0 +130
Maximum Assembly Temperature (for 10 seconds °C 0 +260

maximum)

HDMP-1512 (Tx), HDMP-1514 (Rx)

Specified Operating Rates

TC = 0°C to +85°C, VCC = 4.5 V to 5.5 V

Transmit Byte Clock (TBC) Serial Baud Rate

(MHz) (MBaud/sec)

SPDSEL Min. Max. Min. Max.

0 52.0 54.0 520 540
1 52.0 54.0 1040 1080

663