HP Envy X360 13-Y023CL Schematics
5
4
3
2
1
01
PCB 10L STACK UP
D D
C C
B B
Keyboard
Touch Pad
A A
Pavlova Intel KABYLAKE ULT Platform Block Diagram
SATA - 1st NGFF SSD
Package : 9.5 (mm)
Power :
PAGE 26
System BIOS
SPI ROM
PAGE 27
PAGE 27
LPDDR3 1866MHz
16Gb x64 2PCS
PAGE 17
LPDDR3 1866MHz
16Gb x64 2PCS
PAGE 18
SATA0/PCIE 4XLANE
PAGE 10
PS2
SMBUS
LPDDR3L x1866MHz 1.2V
LPDDR3L x1866MHz 1.2V
SPI Interface
TPM
SLB9665 V2.0
PAGE 26
ITE 8987
Embedded Controller
Power :
Package : BGA128
Size : 7x 7 (mm)
PAGE 30
FAN
PAGE 24
Kabylake U
Processor
Processor : Daul Core
Power : 15 (Watt)
Package : BGA1356
Size : 40 X 24 (mm)
HP
CX7700
Power :
Package : MQFN
Size : 7 x 7 (mm)
PAGE 23
Speaker
Headphone amplifier
HPA0022642RTJR
PAGE 2~16
eDP X4
DP Port 1
USB3.0 Interface
USB2.0 Interface
PCIE Gen 1 x 1 Lane
Port2
Carde Reader
RTS5237
PAGE 23
PAGE 24
I2C0
PCIE Port1
PAGE 26
Combo Jack
iPHONE type
USB 3.0* Port 1,2 ,3
Camera
Port6
PAGE 20
Touch Screen
PAGE 20
PTN5150A
Package : QFN-12
PS8201A
Package : QFN-40
TP2546
Package : QFN-16 3x3
Halt Mini Card
Intel Rambo Peak
WLAN / BT Combo
PCIE Port3
USB20 Port7
PAGE 28
PAGE 25
ISH
EC
eDP
USB TYPEC
USB30 Port4,6
USB20 Port5
HDMI Conn
USB3.0 Port x 3
Port1,2,3
G-Sensor
HP2DC2TR
PAGE 20
PAGE 21
(total 3.5A)
PAGE 29
PAGE 25
PAGE 22
Accelerometer/Compass/Gryoscope
SM BUS
HP9DS1TR
LAYER 1 : TOP
LAYER 2 : SGND
LAYER 3 : IN1(High)
LAYER 4 : IN2(High)
LAYER 5 : SGND
LAYER 6 : SVCC
LAYER 7 : IN3(Low)
LAYER 8 : IN4(High)
LAYER 9 : SGND
LAYER 10 : BOT
Digital MIC
5
4
PAGE 20
NB5
NB5
3
2
NB5
PROJECT : Y0DP
PROJECT : Y0DP
PROJECT : Y0DP
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Block Diagram
Block Diagram
Block Diagram
Date: Sheet of
Date: Sheet of
Date: Sheet of
1 40Friday, July 01, 2016
1 40Friday, July 01, 2016
1 40Friday, July 01, 2016
1
1A
1A
1A
I'm from VIETNAM sualaptop365
5
+3V <4,10,11,12,13,14,15,20,22,23,26 ,27,29,30,31,37,38>
+1.0V <4,6,30,36>
+VCCSTPLL <5,6,9,36,38>
+VCCIO <6,16,36>
D D
DDPB_CTRLDATA/ GPP_E19
Display Port B Detected
This signal has a weak internal pull-down.
0 = Port B is not detected.
1 = Port B is detected.
This signal has a weak internal pull-down.
0 = Port C and D is not detected.
1 = Port C and D is detected.
DDPD_CTRLDATA
R51 10K_2
C C
+VCCSTPLL
R165 * 49.9/F_2
+1.0V
R29 *51_2
R30 51_2
R35 51_2
B B
R25 51_2 R61 49.9/F_2
Close to Chipset
CATERR#
JTAGX_PCH
JTAG_TMS_PCH
JTAG_TDI_PCH
JTAG_TDO_PCH
JTAG_TCK_PCH
SDVO_CLK
SDVO_DATA
HDMI
+3V
R11760 2.2K_2
R192 2 .2K_2
eDP_COMPIO and ICOMPO signals should be shorted near
balls and routed with typical impedance <25 mohms
H_PROCHOT#<30,32,38>
+VCCIO
R164 4 99/F_4
4
IN_D0#<22>
IN_D0<22>
IN_D1#<22>
IN_D1<22>
IN_D2#<22>
IN_D2<22>
IN_CLK#<22>
IN_CLK<22>
R47 24.9/F_2
IN_D0#
IN_D0
IN_D1#
IN_D1
IN_D2#
IN_D2
IN_CLK#
IN_CLK
SDVO_CLK
SDVO_DATA
DDPD_CTRLDATA
EDP_RCOMP
EC_PECI<30>
PM_THRMTRIP#<30>
R58 49.9/F_2
R48 49.9/F_2R23 51_2
R45 49.9/F_2
U11A
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22/DDPD_CTRLCLK
N12
GPP_E23/DDPD_CTRLDATA
E52
EDP_RCOMP
*SKL_ULT
REV = 1
CATERR#
EC_PECI
PROCHOT#
PM_THRMTRIP#
PROC_POPIRCOMP
PCH_OPI_RCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP
D63
A54
C65
C63
A65
C55
D55
B54
C56
A6
A7
BA5
AY5
AT16
AU16
H66
H65
3
SKL_ULT
DDI
DISPLAY SIDEBANDS
U11D
CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#
CPU MISC
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP
*SKL_ULT
REV = 1
?
Need apply PN
SKL_ULT
EDP
?
4 OF 20
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
Need apply PN
JTAG
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
JTAGX
PDC
?1 OF 20
C47
C46
D46
C45
A45
B45
A47
B47
E45
F45
B52
G50
F50
E48
F48
G46
F46
L9
L7
L6
N9
L10
R12
R11
U13
XDP_TCK0
B61
XDP_TDI_CPU
D60
XDP_TDO_CPU
A61
XDP_TMS_CPU
C60
XDP_TRST#_CPU
B59
JTAG_TCK_PCH
B56
JTAG_TDI_PCH
D59
JTAG_TDO_PCH
A56
JTAG_TMS_PCH
C59
XDP_TRST#_CPU
C61
JTAGX_PCH
A59
INT_EDP_TXN0
INT_EDP_TXP0
INT_EDP_TXN1
INT_EDP_TXP1
INT_EDP_TXN2
INT_EDP_TXP2
INT_EDP_TXN3
INT_EDP_TXP3
INT_EDP_AUXN
INT_EDP_AUXP
HDMI_HPD_CON
ULT_EDP_HPD
PCH_LVDS_BLON
PCH_DPST_PWM
PCH_DISP_ON
2
INT_EDP_TXN0 <20>
INT_EDP_TXP0 <20>
INT_EDP_TXN1 <20>
INT_EDP_TXP1 <20>
INT_EDP_TXN2 <20>
INT_EDP_TXP2 <20>
INT_EDP_TXN3 <20>
INT_EDP_TXP3 <20>
INT_EDP_AUXN <20>
INT_EDP_AUXP <20>
DDI1_AUX_DN <22>
DDI1_AUX_DP <22>
HDMI_HPD_CON <22>
ULT_EDP_HPD <20>
PCH_LVDS_BLON <20>
PCH_DPST_PWM <20>
PCH_DISP_ON <20>
XDP_TRST#_CPU <2>
XDP_TRST#_CPU <2>
1
Reserve EDP_HPD opposites circuit!
+3V
R188
*10K_2
ULT_EDP_HPD
R187
100K_2
Close to EC
PM_THRMTRIP#
R213 1K_4
Processor pull-up (CPU)
TO BE REPLACED WITH 1K OHMS FOR SKL .
470 OHM IS FOR I/P
PLACE NEAR CPU
XDP_TMS_CPU
R36 *51_2
XDP_TDI_CPU
R31 *51_2
XDP_TDO_CPU
R28 *51_2
H_PROCHOT#
R142 1K_2
XDP_TCK0
R177 51_2
XDP_TRST#_CPU
R27 51_2
02
+VCCSTPLL
+1.0V
+1.0V
A A
PROJECT : Y0DP
PROJECT : Y0DP
PROJECT : Y0DP
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KBLU (1/14)
KBLU (1/14)
NB5
NB5
5
4
3
2
NB5
KBLU (1/14)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
1A
1A
1A
2 40Friday, July 01, 2016
2 40Friday, July 01, 2016
2 40Friday, July 01, 2016
I'm from VIETNAM sualaptop365
5
M_A_DQSN[7:0]<17>
M_A_DQSP[7:0]<17>
M_B_DQSN[7:0]<18>
M_B_DQSP[7:0]<18>
M_A_DQ[63:0]<17>
M_B_DQ[63:0]<18>
D D
C C
B B
+1.2VSUS <6,17,18 ,22,34,36>
M_A_DQ0
AL71
M_A_DQ1
AL68
M_A_DQ2
AN68
M_A_DQ3
AN69
M_A_DQ4
AL70
M_A_DQ5
AL69
M_A_DQ6
AN70
M_A_DQ7
AN71
M_A_DQ8
AR70
M_A_DQ9
AR68
M_A_DQ10
AU71
M_A_DQ11
AU68
M_A_DQ12
AR71
M_A_DQ13
AR69
M_A_DQ14
AU70
M_A_DQ15
AU69
M_A_DQ16
AF65
M_A_DQ17
AF64
M_A_DQ18
AK65
M_A_DQ19
AK64
M_A_DQ20
AF66
M_A_DQ21
AF67
M_A_DQ22
AK67
M_A_DQ23
AK66
M_A_DQ24
AF70
M_A_DQ25
AF68
M_A_DQ26
AH71
M_A_DQ27
AH68
M_A_DQ28
AF71
M_A_DQ29
AF69
M_A_DQ30
AH70
M_A_DQ31
AH69
M_A_DQ32
BB65
M_A_DQ33
AW65
M_A_DQ34
AW63
M_A_DQ35
AY63
M_A_DQ36
BA65
M_A_DQ37
AY65
M_A_DQ38
BA63
M_A_DQ39
BB63
M_A_DQ40
BA61
M_A_DQ41
AW61
M_A_DQ42
BB59
M_A_DQ43
AW59
M_A_DQ44
BB61
M_A_DQ45
AY61
M_A_DQ46
BA59
M_A_DQ47
AY59
M_A_DQ48
AT66
M_A_DQ49
AU66
M_A_DQ50
AP65
M_A_DQ51
AN65
M_A_DQ52
AN66
M_A_DQ53
AP66
M_A_DQ54
AT65
M_A_DQ55
AU65
M_A_DQ56
AT61
M_A_DQ57
AU61
M_A_DQ58
AP60
M_A_DQ59
AN60
M_A_DQ60
AN61
M_A_DQ61
AP61
M_A_DQ62
AT60
M_A_DQ63
AU60
U11B
DDR0_DQ[0]
DDR0_DQ[1]
DDR0_DQ[2]
DDR0_DQ[3]
DDR0_DQ[4]
DDR0_DQ[5]
DDR0_DQ[6]
DDR0_DQ[7]
DDR0_DQ[8]
DDR0_DQ[9]
DDR0_DQ[10]
DDR0_DQ[11]
DDR0_DQ[12]
DDR0_DQ[13]
DDR0_DQ[14]
DDR0_DQ[15]
DDR1_DQ[0]/DDR0 _DQ[16]
DDR1_DQ[1]/DDR0 _DQ[17]
DDR1_DQ[2]/DDR0 _DQ[18]
DDR1_DQ[3]/DDR0 _DQ[19]
DDR1_DQ[4]/DDR0 _DQ[20]
DDR1_DQ[5]/DDR0 _DQ[21]
DDR1_DQ[6]/DDR0 _DQ[22]
DDR1_DQ[7]/DDR0 _DQ[23]
DDR1_DQ[8]/DDR0 _DQ[24]
DDR1_DQ[9]/DDR0 _DQ[25]
DDR1_DQ[10]/DD R0_DQ[26]
DDR1_DQ[11]/DD R0_DQ[27]
DDR1_DQ[12]/DD R0_DQ[28]
DDR1_DQ[13]/DD R0_DQ[29]
DDR1_DQ[14]/DD R0_DQ[30]
DDR1_DQ[15]/DD R0_DQ[31]
DDR0_DQ[16]/DD R0_DQ[32]
DDR0_DQ[17]/DD R0_DQ[33]
DDR0_DQ[18]/DD R0_DQ[34]
DDR0_DQ[19]/DD R0_DQ[35]
DDR0_DQ[20]/DD R0_DQ[36]
DDR0_DQ[21]/DD R0_DQ[37]
DDR0_DQ[22]/DD R0_DQ[38]
DDR0_DQ[23]/DD R0_DQ[39]
DDR0_DQ[24]/DD R0_DQ[40]
DDR0_DQ[25]/DD R0_DQ[41]
DDR0_DQ[26]/DD R0_DQ[42]
DDR0_DQ[27]/DD R0_DQ[43]
DDR0_DQ[28]/DD R0_DQ[44]
DDR0_DQ[29]/DD R0_DQ[45]
DDR0_DQ[30]/DD R0_DQ[46]
DDR0_DQ[31]/DD R0_DQ[47]
DDR1_DQ[16]/DD R0_DQ[48]
DDR1_DQ[17]/DD R0_DQ[49]
DDR1_DQ[18]/DD R0_DQ[50]
DDR1_DQ[19]/DD R0_DQ[51]
DDR1_DQ[20]/DD R0_DQ[52]
DDR1_DQ[21]/DD R0_DQ[53]
DDR1_DQ[22]/DD R0_DQ[54]
DDR1_DQ[23]/DD R0_DQ[55]
DDR1_DQ[24]/DD R0_DQ[56]
DDR1_DQ[25]/DD R0_DQ[57]
DDR1_DQ[26]/DD R0_DQ[58]
DDR1_DQ[27]/DD R0_DQ[59]
DDR1_DQ[28]/DD R0_DQ[60]
DDR1_DQ[29]/DD R0_DQ[61]
DDR1_DQ[30]/DD R0_DQ[62]
DDR1_DQ[31]/DD R0_DQ[63]
*SKL_ULT
REV = 1
Need apply PN
?
SKL_ULT
DDR0_MA[12]/DDR0 _CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0 _CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0 _CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0 _CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0 _CAB[0]/DDR0_MA[13 ]
DDR0_CAS#/DDR0_ CAB[1]/DDR0_MA[15]
DDR0_RAS#/DDR0_ CAB[3]/DDR0_MA[16]
DDR0_MA[10]/DDR0 _CAB[7]/DDR0_MA[10 ]
NIL-DDR CH A
4
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_MA[5]/DDR0_ CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_ CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_ CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_ CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_ CAA[4]/DDR0_MA[7]
DDR0_WE#/D DR0_CAB[2]/DDR0_ MA[14]
DDR0_MA[2]/DDR0_ CAB[5]/DDR0_MA[2]
DDR0_MA[1]/DDR0_ CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_ CAB[9]/DDR0_MA[0]
DDR0_ODT[1]
DDR0_BA[2]/DDR0_ CAA[5]/DDR0_BG[0]
DDR0_BA[0]/DDR0_ CAB[4]/DDR0_BA[0]
DDR0_BA[1]/DDR0_ CAB[6]/DDR0_BA[1]
DDR0_MA[3]
DDR0_MA[4]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]
DDR1_DQSN[0]/DDR0 _DQSN[2]
DDR1_DQSP[0]/DD R0_DQSP[2]
DDR1_DQSN[1]/DDR0 _DQSN[3]
DDR1_DQSP[1]/DD R0_DQSP[3]
DDR0_DQSN[2]/DDR0 _DQSN[4]
DDR0_DQSP[2]/DD R0_DQSP[4]
DDR0_DQSN[3]/DDR0 _DQSN[5]
DDR0_DQSP[3]/DD R0_DQSP[5]
DDR1_DQSN[2]/DDR0 _DQSN[6]
DDR1_DQSP[2]/DD R0_DQSP[6]
DDR1_DQSN[3]/DDR0 _DQSN[7]
DDR1_DQSP[3]/DD R0_DQSP[7]
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
2 OF 20
3
SkyLake ULT Processor (DDR3L)
AU53
AT53
AU55
AT55
BA56
BB56
AW56
AY56
AU45
AU43
AT45
AT43
BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54
AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52
AM70
AM69
AT69
AT70
AH66
AH65
AG69
AG70
BA64
AY64
AY60
BA60
AR66
AR65
AR61
AR60
AW50
AT52
AY67
AY68
BA67
AW67
M_A_CKE2
M_A_CKE3
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_B0
M_A_B1
M_A_B2
M_A_B3
M_A_B4
M_A_B5
M_A_B6
M_A_B7
M_A_B8
M_A_B9
M_A_DQSN0
M_A_DQSP0
M_A_DQSN1
M_A_DQSP1
M_A_DQSN2
M_A_DQSP2
M_A_DQSN3
M_A_DQSP3
M_A_DQSN4
M_A_DQSP4
M_A_DQSN5
M_A_DQSP5
M_A_DQSN6
M_A_DQSP6
M_A_DQSN7
M_A_DQSP7
DDR_VTT_CNTL
R597 *0_2
Place near CPU
M_A_CLKN0 <17,19>
M_A_CLKP0 <17,19>
M_A_CLKN1 <17,19>
M_A_CLKP1 <17,19>
M_A_CKE0 <17,19>
M_A_CKE1 <17,19>
M_A_CKE2 <17,19>
M_A_CKE3 <17,19>
M_A_CS#0 <17,19>
M_A_CS#1 <17,19>
M_A_ODT0 <17,19>
M_A_A0 <17,19>
M_A_A1 <17,19>
M_A_A2 <17,19>
M_A_A3 <17,19>
M_A_A4 <17,19>
M_A_A5 <17,19>
M_A_A6 <17,19>
M_A_A7 <17,19>
M_A_A8 <17,19>
M_A_A9 <17,19>
M_A_B0 <17,19>
M_A_B1 <17,19>
M_A_B2 <17,19>
M_A_B3 <17,19>
M_A_B4 <17,19>
M_A_B5 <17,19>
M_A_B6 <17,19>
M_A_B7 <17,19>
M_A_B8 <17,19>
M_A_B9 <17,19>
20mils width
SM_VREF_CA <17>
SM_VREF_DQ0 <17>
SM_VREF_DQ1 <18>
DDR_VTT_CNTL_R <4>
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
U11C
AY39
DDR0_DQ[32]/DD R1_DQ[0]
AW39
DDR0_DQ[33]/DD R1_DQ[1]
AY37
DDR0_DQ[34]/DD R1_DQ[2]
AW37
DDR0_DQ[35]/DD R1_DQ[3]
BB39
DDR0_DQ[36]/DD R1_DQ[4]
BA39
DDR0_DQ[37]/DD R1_DQ[5]
BA37
DDR0_DQ[38]/DD R1_DQ[6]
BB37
DDR0_DQ[39]/DD R1_DQ[7]
AY35
DDR0_DQ[40]/DD R1_DQ[8]
AW35
DDR0_DQ[41]/DD R1_DQ[9]
AY33
DDR0_DQ[42]/DD R1_DQ[10]
AW33
DDR0_DQ[43]/DD R1_DQ[11]
BB35
DDR0_DQ[44]/DD R1_DQ[12]
BA35
DDR0_DQ[45]/DD R1_DQ[13]
BA33
DDR0_DQ[46]/DD R1_DQ[14]
BB33
DDR0_DQ[47]/DD R1_DQ[15]
AU40
DDR1_DQ[32]/DD R1_DQ[16]
AT40
DDR1_DQ[33]/DD R1_DQ[17]
AT37
DDR1_DQ[34]/DD R1_DQ[18]
AU37
DDR1_DQ[35]/DD R1_DQ[19]
AR40
DDR1_DQ[36]/DD R1_DQ[20]
AP40
DDR1_DQ[37]/DD R1_DQ[21]
AP37
DDR1_DQ[38]/DD R1_DQ[22]
AR37
DDR1_DQ[39]/DD R1_DQ[23]
AT33
DDR1_DQ[40]/DD R1_DQ[24]
AU33
DDR1_DQ[41]/DD R1_DQ[25]
AU30
DDR1_DQ[42]/DD R1_DQ[26]
AT30
DDR1_DQ[43]/DD R1_DQ[27]
AR33
DDR1_DQ[44]/DD R1_DQ[28]
AP33
DDR1_DQ[45]/DD R1_DQ[29]
AR30
DDR1_DQ[46]/DD R1_DQ[30]
AP30
DDR1_DQ[47]/DD R1_DQ[31]
AY31
DDR0_DQ[48]/DD R1_DQ[32]
AW31
DDR0_DQ[49]/DD R1_DQ[33]
AY29
DDR0_DQ[50]/DD R1_DQ[34]
AW29
DDR0_DQ[51]/DD R1_DQ[35]
BB31
DDR0_DQ[52]/DD R1_DQ[36]
BA31
DDR0_DQ[53]/DD R1_DQ[37]
BA29
DDR0_DQ[54]/DD R1_DQ[38]
BB29
DDR0_DQ[55]/DD R1_DQ[39]
AY27
DDR0_DQ[56]/DD R1_DQ[40]
AW27
DDR0_DQ[57]/DD R1_DQ[41]
AY25
DDR0_DQ[58]/DD R1_DQ[42]
AW25
DDR0_DQ[59]/DD R1_DQ[43]
BB27
DDR0_DQ[60]/DD R1_DQ[44]
BA27
DDR0_DQ[61]/DD R1_DQ[45]
BA25
DDR0_DQ[62]/DD R1_DQ[46]
BB25
DDR0_DQ[63]/DD R1_DQ[47]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
*SKL_ULT
REV = 1
2
?
SKL_ULT
Need apply PN
DDR1_MA[5]/DDR1_ CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_ CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_ CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_ CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_ CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_ CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1 _CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1 _CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1 _CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1 _CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1 _CAB[0]/DDR1_MA[13 ]
DDR1_CAS#/DDR1_ CAB[1]/DDR1_MA[15]
DDR1_WE#/D DR1_CAB[2]/DDR1_ MA[14]
DDR1_RAS#/DDR1_ CAB[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_ CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_ CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_ CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1 _CAB[7]/DDR1_MA[10 ]
DDR1_MA[1]/DDR1_ CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_ CAB[9]/DDR1_MA[0]
DDR0_DQSN[4]/DDR1 _DQSN[0]
DDR0_DQSP[4]/DD R1_DQSP[0]
DDR0_DQSN[5]/DDR1 _DQSN[1]
DDR0_DQSP[5]/DD R1_DQSP[1]
DDR1_DQSN[4]/DDR1 _DQSN[2]
DDR1_DQSP[4]/DD R1_DQSP[2]
DDR1_DQSN[5]/DDR1 _DQSN[3]
DDR1_DQSP[5]/DD R1_DQSP[3]
DDR0_DQSN[6]/DDR1 _DQSN[4]
DDR0_DQSP[6]/DD R1_DQSP[4]
DDR0_DQSN[7]/DDR1 _DQSN[5]
DDR0_DQSP[7]/DD R1_DQSP[5]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
PDC
DDR_RCOMP[2]
NIL-DDR CH B
3 OF 20
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]
DDR1_MA[3]
DDR1_MA[4]
DDR1_PAR
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
BA38
AY38
AY34
BA34
AT38
AR38
AT32
AR32
BA30
AY30
AY26
BA26
AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18
M_B_CKE2
M_B_CKE3
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_B0
M_B_B1
M_B_B2
M_B_B3
M_B_B4
M_B_B5
M_B_B6
M_B_B7
M_B_B8
M_B_B9
M_B_DQSN0
M_B_DQSP0
M_B_DQSN1
M_B_DQSP1
M_B_DQSN2
M_B_DQSP2
M_B_DQSN3
M_B_DQSP3
M_B_DQSN4
M_B_DQSP4
M_B_DQSN5
M_B_DQSP5
M_B_DQSN6
M_B_DQSP6
M_B_DQSN7
M_B_DQSP7
SM_DRAMRST#
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
12mils width
M_B_CLKN0 <18,19>
M_B_CLKN1 <18,19>
M_B_CLKP0 <18,19>
M_B_CLKP1 <18,19>
M_B_CKE0 <18,19>
M_B_CKE1 <18,19>
M_B_CKE2 <18,19>
M_B_CKE3 <18,19>
M_B_CS#0 <18,19>
M_B_CS#1 <18,19>
M_B_ODT0 <18,19>
M_B_A0 <18,19>
M_B_A1 <18,19>
M_B_A2 <18,19>
M_B_A3 <18,19>
M_B_A4 <18,19>
M_B_A5 <18,19>
M_B_A6 <18,19>
M_B_A7 <18,19>
M_B_A8 <18,19>
M_B_A9 <18,19>
M_B_B0 <18,19>
M_B_B1 <18,19>
M_B_B2 <18,19>
M_B_B3 <18,19>
M_B_B4 <18,19>
M_B_B5 <18,19>
M_B_B6 <18,19>
M_B_B7 <18,19>
M_B_B8 <18,19>
M_B_B9 <18,19>
+1.2VSUS
R65 200/F_2
R66 80.6/F_ 2
R64 162/F_2
1
03
R69
*0_2
PV
A A
PROJECT : Y0DP
PROJECT : Y0DP
PROJECT : Y0DP
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KBL U (2/14)
KBL U (2/14)
NB5
NB5
5
4
3
2
NB5
KBL U (2/14)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
3 40Friday, July 01 , 2016
3 40Friday, July 01 , 2016
3 40Friday, July 01 , 2016
1A
1A
1A
I'm from VIETNAM sualaptop365
5
+3V_DEEP_SUS<10,11,12,14,15,27>
+3V<2,10,11,12,13,14,15,20,22,23,26 ,27,29,30,31,37,38>
+3VS5<15,21,28,30,31,33,35,36,37>
+VCCSTPLL<2,5,6,9,36,38>
+1.0V<2,6,30,36>
+3V_RTC<13,27,31,32>
D D
RSMRST#<30>
PV2
EC26
*220P/50V_4
EC_PWROK<30>
SUSWARN#_EC<30>
PCIE_WAKE#<26,28,30>
RF_OFF_PCH<28>
DDR_VTT_CNTL_R<3>
TP1138
R161 * 10K_2
C229 *0.1U/10V_2
R410 * 0_2/S
SI
4
PLTRST#
SYS_RESET#
RSMRST#
PROCPWRGD
H_VCCST_PWRGD
SYS_PWROK
PCH_PWROK
DSWROK_EC_R
SUSWARN#
SUSACK#SUSWARN#
PCIE_WAKE#
RF_OFF_PCH
DDR_VTT_CNTL_R
U11K
SYSTEM POWER MANAGEMENT
AN10
GPP_B13/PLTRST#
B5
SYS_RESET#
AY17
RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK
BA20
PCH_PWROK
BB20
DSW_PWROK
AR13
GPP_A13/SUSWARN#/SUSPWRDNACK
AP11
GPP_A15/SUSACK#
BB15
WAKE#
AM15
GPD2/LAN_WAKE#
AW17
GPD11/LANPHYPC
AT15
GPD7/RSVD
*SKL_ULT
REV = 1
SKL_ULT
?
11 OF 20
3
Need apply PN
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW#
GPP_A11/PME#
GPP_B11/EXT_PWR_GATE#
GPP_B2/VRALERT#
SLP_SUS#
SLP_LAN#
INTRUDER#
2
1
04
PCH_SLP_S0_N
AT11
AP15
BA16
SLP_S5#
AY16
SLP_SUS#_EC
AN15
AW15
PCH_SLP_WLAN#
BB17
AN16
BA15
DNBSWON#
AC_PRESENT_EC
AY15
AU13
BATLOW#
AU11
INTRUDER#_R
AP16
AM10
AM11
?
TP1143
TP1136
R621M_2
SUSB# <30>
SUSC# <30>
SLP_SUS#_EC <30>
PCH_SLP_WLAN# <30>
SLP_A# <30>
DNBSWON# <30>
AC_PRESENT_EC <30>
+3V_COIN
PCH Pull-high/low(CLG)
+3V_DEEP_SUS
SUSWARN#
SUSACK#
BATLOW#
PCIE_WAKE#
AC_PRESENT_EC
BATLOW#
SYS_RESET#
RSMRST#
DSWROK_EC_R
R409 * 10K_2
R413 * 10K_2
R59 10K_2
R391 1 K_2
R387 * 10K_2R412*0_4/S
R596 * 10K_2
R169 1 0K_2
R411 1 0K_2
R384 1 00K_2
+3VS5
+3V
C C
B B
A A
For DS3 Sequence
For DS3 -->Ra
Non-DS3 -->Rb
RSMRST#
DPWROK_EC<30>
PLTRST#(CLG)
Check Q2010 Rise/Fall time less than 100ns
System PWR_OK(CLG)
5
R60
100K_2
Rb
R382 *0_2
R376 *0_2/S
Ra
PLTRST# <26,28,30>
SI
C558
0.1U/16V_4
R170 * 0_2/S
DSWROK_EC_R
EC_PWROKSYS_PWROK
R156
10K/F_2
1211 Del
+VCCSTPLL and R134
+1.0V
R127
1K_2
D2 RB501V-40
HWPG<30,33,34,35 ,37>
R10479 close to CPU side
H_VCCST_PWRGD trace 0.3" - 1.5"
4
H_VCCST_PWRGD_R
21
C164
*10P/50V_4
3
R128 60.4_4
H_VCCST_PWRGD
+1.0V +3VS5+5VS5
R440
15K/F_4
+1.0V_PWRGD_G1
C458
0.1U/10V_2
R437
100K_2
2
R425
100K_2
+1.0V_PWRGD_G2
Q23
METR3904-G
1 3
R423
10K_2
3
Q24
2
2N7002K
1
1110 Add Citcuit for +1.0V Power Good
1118 Change Change Q7062 P/N from BA051440000 to
BA039040020, Del D7002,D7003, R10526, R10527
NB5
NB5
2
NB5
HWPG
R426
100K_4
PROJECT : Y0DP
PROJECT : Y0DP
PROJECT : Y0DP
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KBL U (3/14)
KBL U (3/14)
KBL U (3/14)
Date: Sheet of
Date: Sheet of
Date: Sheet of
4 40Friday, July 01, 2016
4 40Friday, July 01, 2016
4 40Friday, July 01, 2016
1
1A
1A
1A
I'm from VIETNAM sualaptop365
5
+VCC_CORE<39>
+1.0V<2,4,6,30,36>
+VCCSTG<6>
+VCCSTPLL<2,6,9,36,38>
22U/6.3V_6
10U/6.3V_4
C150
22U/6.3V_6
C152
22U/6.3V_6
C149
10U/6.3V_4
C134
22U/6.3V_6
C141
22U/6.3V_6
C221
10U/6.3V_4
C148
22U/6.3V_6
C160
22U/6.3V_6
D D
C224
10U/6.3V_4
C175
22U/6.3V_6
C C
B B
C174
22U/6.3V_6
C219
10U/6.3V_4
C172
22U/6.3V_6
C193
22U/6.3V_6
C158
10U/6.3V_4
C154
22U/6.3V_6
C187
22U/6.3V_6
C225
10U/6.3V_4
4
?
SKL_ULT
CPU POWER 1 OF 4
28A
C192
22U/6.3V_6
C222
10U/6.3V_4
Need apply PN
12 OF 20
C156
22U/6.3V_6
C217
10U/6.3V_4
VCCSTG_G20
C188
22U/6.3V_6
C171
10U/6.3V_4
U11L
+VCC_CORE +VCC_CORE
A30
VCC_A30
A34
VCC_A34
A39
VCC_A39
A44
VCC_A44
AK33
C151
22U/6.3V_6
AK35
AK37
AK38
AK40
AL33
AL37
AL40
AM32
AM33
AM35
AM37
AM38
G30
K32
AK32
AB62
P62
V62
H63
G61
AC63
AE63
AE62
AG62
AL63
AJ62
Close U11
+VCC_CORE
+VCC_CORE
VCC_AK33
VCC_AK35
VCC_AK37
VCC_AK38
VCC_AK40
VCC_AL33
VCC_AL37
VCC_AL40
VCC_AM32
VCC_AM33
VCC_AM35
VCC_AM37
VCC_AM38
VCC_G30
RSVD_K32
RSVD_AK32
VCCOPC_AB62
VCCOPC_P62
VCCOPC_V62
VCC_OPC_1P8_H63
VCC_OPC_1P8_G61
VCCOPC_SENSE
VSSOPC_SENSE
VCCEOPIO
VCCEOPIO
VCCEOPIO_SENSE
VSSEOPIO_SENSE
*SKL_ULT
REV = 1
C186
22U/6.3V_6
C223
10U/6.3V_4
VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42
VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
PDC
?
C153
22U/6.3V_6
C220
10U/6.3V_4
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
H_CPU_SVIDALRT#
B63
VR_SVID_CLK_R
A63
H_CPU_SVIDDAT
D64
G20
3
C133
22U/6.3V_6
C159
10U/6.3V_4
C64
1uF/6.3_2
C53
1uF/6.3_2
C162
22U/6.3V_6
C191
10U/6.3V_4
2
C65
C16
1uF/6.3_2
C18
1uF/6.3_2
R50 100/F_2
R49 100/F_2
+VCCSTG
1uF/6.3_2C143
C17
1uF/6.3_2
C55
1uF/6.3_2
C33
1uF/6.3_2
+VCC_CORE
VCC_SENSE <38 >
VSS_SENSE <38>
100- ±1%
pull-up to VCC
near processor.
C19
1uF/6.3_2
C13
1uF/6.3_2C218
C14
1uF/6.3_2
C39
1uF/6.3_2
C15
1uF/6.3_2
C63
1uF/6.3_2
C54
1uF/6.3_2
Layout note: need routing together and ALERT need between CLK and DATA.
+VCCSTPLL
R181
100/F_2
R167
56.2/F_4
C234
*0.1U/10V_2
+VCCSTPLL
R157
*54.9/F_4
R175 * 0_2/S
C163
22U/6.3V_6
C199
10U/6.3V_4
CLOSE TO CPU
PLACE THE PU RESISTORS
PLACE THE PU RESISTORS
CLOSE TO VR
PULL UP IS IN THE VR MODULE
CLOSE TO CPU
PLACE THE PU RESISTORS
H_CPU_SVIDALRT#
1119 Update R10372 P/N to
CS12202FB06
VR_SVID_CLK_R
H_CPU_SVIDDAT
R178 2 20/F_4
R174 * 0_2/S
+VCCSTPLL
1
SVID ALERT
VR_SVID_ALERT# <38>
1014 Change to empty
SVID CLK
VR_SVID_CLK <38>
SVID DATA
VR_SVID_DATA <38>
05
A A
PROJECT : Y0DP
PROJECT : Y0DP
PROJECT : Y0DP
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KBL U (4/14)
KBL U (4/14)
NB5
NB5
5
4
3
2
NB5
KBL U (4/14)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
1A
1A
1A
5 40Friday, July 01, 2016
5 40Friday, July 01, 2016
5 40Friday, July 01, 2016
I'm from VIETNAM sualaptop365
5
+VCCSTPLL <2,5,9,36,38>
+VCCSA <38,39>
+1.2VSUS <3,17,18,22,34,36>
+1.0V_DEEP_SUS <9,13,15,35,36>
+1.0V <2,4,30,36>
+3VPCU <13,15,27,28,30,31,32,33>
+1.2V_VCCPLL_OC <36>
+1.2VSUS
D D
+1.0V
C C
C422
10U/6.3V_4
+VCCSTPLL
+1.2V_VCCPLL_OC
C409
10U/6.3V_4
C416
10U/6.3V_4
C71
C74
1uF/6.3_2
C397
10U/6.3V_4
+VCCPLL_OC
C77
1uF/6.3_2
Under U11
1uF/6.3_2
C407
10U/6.3V_4 C195
+VCCSTG
Close U11
C428
10U/6.3V_4
R130*0_4/S
R129*0_4
C404
10U/6.3V_4
*120P/50V_4
Under U11 Close U11
+VCCSTG +VCCPLL_OC +VCCPLL
C10
1U/6.3V_2
B B
C72
1uF/6.3_2
+VCCSTPLL
C227
1U/6.3V_2
C194
1uF/6.3_2
C76
1uF/6.3_2
+VCCSTPLL
C73
1U/6.3V_2
+VCCSTG
+VCCPLL_OC
Close A18 Ball
+VCCSTPLL
+VCCPLL
C238
1U/6.3V_2
4
3
2
1
06
Need apply PN
120mA
C197
22U/6.3V_6
?
SKL_ULT
U11N
CPU POWER 3 OF 4
AU23
VDDQ_AU23
AU28
2A
VDDQ_AU28
AU35
VDDQ_AU35
AU42
VDDQ_AU42
BB23
VDDQ_BB23
BB32
VDDQ_BB32
BB41
VDDQ_BB41
BB47
VDDQ_BB47
BB51
VDDQ_BB51
AM40
VDDQC
A18
0.12A
VCCST
A22
0.04A
VCCSTG_A22
AL23
VCCPLL_OC
K20
0.12A
VCCPLL_K20
K21
VCCPLL_K21
+VCCPLL+VCCSTPLL
*SKL_ULT
REV = 1
14 OF 20
VCCIO
3.1A
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCSA
5A
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
AK28
AK30
AL30
AL42
AM28
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
C50
1uF/6.3_2
+VCCSA
C38
1uF/6.3_2
VCCIO_VCCSENSE
VCCIO_VSSSENSE
C51
1uF/6.3_2
C9
1uF/6.3_2
C212
10U/6.3V_4
C226
C52
10U/6.3V_4
1uF/6.3_2
C37
C27
1uF/6.3_2
1U/6.3V_2
C168
C170
10U/6.3V_4
10U/6.3V_4
VSSSA_SENSE <38>
VCCSA_SENSE <38>
C247
10U/6.3V_4
C66
1U/6.3V_2
C173
10U/6.3V_4
C239
10U/6.3V_4
C31
1U/6.3V_2
C213
10U/6.3V_4
C58
1uF/6.3_2
C21
1uF/6.3_2
C232
10U/6.3V_4
VCCIO_VCCSENSE
VCCIO_VSSSENSE
IO Thrm Protect
For 65 degree, 1.8v limit, (SW)
+3VPCU
PV
R137
20K/F_4
For 75 degree, 1.2v limit, (HW)
THER_CPU
R138
100K_4 NTC
1 2
C178
0.1U/16V_4
THRM_MOINTOR1 <30>
C49
1uF/6.3_2
C169
10U/6.3V_4
R57 100/F_2
R56 100/F_2
C48
1uF/6.3_2
C189
10U/6.3V_4
+VCCIO
C57
1uF/6.3_2
C196
10U/6.3V_4
+VCCIO
C190
10U/6.3V_4EC58
10U/6.3V_4
C157
10U/6.3V_4
C231
10U/6.3V_4
+1.2VSUS
C415
C421
10U/6.3V_6
A A
5
4
10U/6.3V_6
C406
C398
10U/6.3V_6
10U/6.3V_6
3
C429
C408
10U/6.3V_6
10U/6.3V_6
Close to CPU
C70
1uF/6.3_2
C69
1uF/6.3_2
C75
C67
1uF/6.3_2
1uF/6.3_2
PROJECT : Y0DP
PROJECT : Y0DP
PROJECT : Y0DP
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KBL U (5/14)
KBL U (5/14)
NB5
NB5
2
NB5
KBL U (5/14)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
1A
1A
1A
6 40Friday, July 01, 2016
6 40Friday, July 01, 2016
6 40Friday, July 01, 2016
I'm from VIETNAM sualaptop365
5
+VCCGT <38,40>
C400
D D
C C
B B
22U/6.3V_6
C419
10U/6.3V_4
C11
1uF/6.3_2
C401
22U/6.3V_6
C399
10U/6.3V_4
C20
1uF/6.3_2
C413
22U/6.3V_6
C347
10U/6.3V_4
C6
1uF/6.3_2
4
SKL_ULT
U11M
+VCCGT
C414
C402
22U/6.3V_6
22U/6.3V_6
C273
C430
10U/6.3V_4
10U/6.3V_4
C12
C7
1uF/6.3_2
1uF/6.3_2
VCCGT_SENSE<38>
VSSGT_SENSE<38>
A48
A53
A58
A62
A66
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
M62
N63
N64
N66
N67
N69
J70
J69
CPU POWER 2 OF 4
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT_SENSE
VSSGT_SENSE
*SKL_ULT
REV = 1
PDC
13 OF 20
?
Need apply PN
VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66
VCCGTX_SENSE
VSSGTX_SENSE
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
3
+VCCGT
N70
N71
R63
C364
R64
22U/6.3V_6
R65
R66
R67
R68
R69
R70
R71
T62
C403
U65
22U/6.3V_6
U68
U71
W63
W64
W65
W66
W67
W68
C288
W69
22U/6.3V_6
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
C411
22U/6.3V_6
C424
22U/6.3V_6
C384
22U/6.3V_6
C358
22U/6.3V_6
C309
22U/6.3V_6
C359
22U/6.3V_6
C363
22U/6.3V_6
C380
22U/6.3V_6
C425
22U/6.3V_6
2
C427
22U/6.3V_6
C426
22U/6.3V_6
Close U11
C389
22U/6.3V_6
C271
22U/6.3V_6
C412
22U/6.3V_6
C379
22U/6.3V_6
1
07
A A
PROJECT : Y0DP
PROJECT : Y0DP
PROJECT : Y0DP
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KBL U (6/14)
KBL U (6/14)
NB5
NB5
5
4
3
2
NB5
KBL U (6/14)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
1A
1A
1A
7 40Friday, July 01, 2016
7 40Friday, July 01, 2016
7 40Friday, July 01, 2016
I'm from VIETNAM sualaptop365
5
4
3
2
1
08
U11R
?
D D
C C
B B
SKL_ULT
GND 3 OF 3
F8
VSS
G10
VSS
G22
VSS
G43
VSS
G45
VSS
G48
VSS
G5
VSS
G52
VSS
G55
VSS
G58
VSS
G6
VSS
G60
VSS
G63
VSS
G66
VSS
H15
VSS
H18
VSS
H71
VSS
J11
VSS
J13
VSS
J25
VSS
J28
VSS
J32
VSS
J35
VSS
J38
VSS
J42
VSS
J8
VSS
K16
VSS
K18
VSS
K22
VSS
K61
VSS
K63
VSS
K64
VSS
K65
VSS
K66
VSS
K67
VSS
K68
VSS
K70
VSS
K71
VSS
L11
VSS
L16
VSS
L17
VSS
*SKL_ULT
REV = 1
18 OF 20
L18
VSS
L2
VSS
L20
VSS
L4
VSS
L8
VSS
N10
VSS
N13
VSS
N19
VSS
N21
VSS
N6
VSS
N65
VSS
N68
VSS
P17
VSS
P19
VSS
P20
VSS
P21
VSS
R13
VSS
R6
VSS
T15
VSS
T17
VSS
T18
VSS
T2
VSS
T21
VSS
T4
VSS
U10
VSS
U63
VSS
U64
VSS
U66
VSS
U67
VSS
U69
VSS
U70
VSS
V16
VSS
V17
VSS
V18
VSS
W13
VSS
W6
VSS
W9
VSS
Y17
VSS
Y19
VSS
Y20
VSS
Y21
VSS
?
U11P
Need apply PN
?
SKL_ULT
GND 1 OF 3
A5
VSS
A67
VSS
A70
VSS
AA2
VSS
AA4
VSS
AA65
VSS
AA68
VSS
AB15
VSS
AB16
VSS
AB18
VSS
AB21
VSS
AB8
VSS
AD13
VSS
AD16
VSS
AD19
VSS
AD20
VSS
AD21
VSS
AD62
VSS
AD8
VSS
AE64
VSS
AE65
VSS
AE66
VSS
AE67
VSS
AE68
VSS
AE69
VSS
AF1
VSS
AF10
VSS
AF15
VSS
AF17
VSS
AF2
VSS
AF4
VSS
AF63
VSS
AG16
VSS
AG17
VSS
AG18
VSS
AG19
VSS
AG20
VSS
AG21
VSS
AG71
VSS
AH13
VSS
AH6
VSS
AH63
VSS
AH64
VSS
AH67
VSS
AJ15
VSS
AJ18
VSS
AJ20
VSS
AJ4
VSS
AK11
VSS
AK16
VSS
AK18
VSS
AK21
VSS
AK22
VSS
AK27
VSS
AK63
VSS
AK68
VSS
AK69
VSS
AK8
VSS
AL2
VSS
AL28
VSS
AL32
VSS
AL35
VSS
AL38
VSS
AL4
VSS
AL45
VSS
AL48
VSS
AL52
VSS
AL55
VSS
AL58
VSS
AL64
VSS
*SKL_ULT
REV = 1
16 OF 20
AL65
VSS
AL66
VSS
AM13
VSS
AM21
VSS
AM25
VSS
AM27
VSS
AM43
VSS
AM45
VSS
AM46
VSS
AM55
VSS
AM60
VSS
AM61
VSS
AM68
VSS
AM71
VSS
AM8
VSS
AN20
VSS
AN23
VSS
AN28
VSS
AN30
VSS
AN32
VSS
AN33
VSS
AN35
VSS
AN37
VSS
AN38
VSS
AN40
VSS
AN42
VSS
AN58
VSS
AN63
VSS
AP10
VSS
AP18
VSS
AP20
VSS
AP23
VSS
AP28
VSS
AP32
VSS
AP35
VSS
AP38
VSS
AP42
VSS
AP58
VSS
AP63
VSS
AP68
VSS
AP70
VSS
AR11
VSS
AR15
VSS
AR16
VSS
AR20
VSS
AR23
VSS
AR28
VSS
AR35
VSS
AR42
VSS
AR43
VSS
AR45
VSS
AR46
VSS
AR48
VSS
AR5
VSS
AR50
VSS
AR52
VSS
AR53
VSS
AR55
VSS
AR58
VSS
AR63
VSS
AR8
VSS
AT2
VSS
AT20
VSS
AT23
VSS
AT28
VSS
AT35
VSS
AT4
VSS
AT42
VSS
AT56
VSS
AT58
VSS
?
U11Q
Need apply PNNeed apply PN
?
SKL_ULT
GND 2 OF 3
AT63
VSS
AT68
VSS
AT71
VSS
AU10
VSS
AU15
VSS
AU20
VSS
AU32
VSS
AU38
VSS
AV1
VSS
AV68
VSS
AV69
VSS
AV70
VSS
AV71
VSS
AW10
VSS
AW12
VSS
AW14
VSS
AW16
VSS
AW18
VSS
AW21
VSS
AW23
VSS
AW26
VSS
AW28
VSS
AW30
VSS
AW32
VSS
AW34
VSS
AW36
VSS
AW38
VSS
AW41
VSS
AW43
VSS
AW45
VSS
AW47
VSS
AW49
VSS
AW51
VSS
AW53
VSS
AW55
VSS
AW57
VSS
AW6
VSS
AW60
VSS
AW62
VSS
AW64
VSS
AW66
VSS
AW8
VSS
AY66
VSS
B10
VSS
B14
VSS
B18
VSS
B22
VSS
B30
VSS
B34
VSS
B39
VSS
B44
VSS
B48
VSS
B53
VSS
B58
VSS
B62
VSS
B66
VSS
B71
VSS
BA1
VSS
BA10
VSS
BA14
VSS
BA18
VSS
BA2
VSS
BA23
VSS
BA28
VSS
BA32
VSS
BA36
VSS
F68
VSS
BA45
VSS
*SKL_ULT
REV = 1
17 OF 20
PDC
BA49
VSS
BA53
VSS
BA57
VSS
BA6
VSS
BA62
VSS
BA66
VSS
BA71
VSS
BB18
VSS
BB26
VSS
BB30
VSS
BB34
VSS
BB38
VSS
BB43
VSS
BB55
VSS
BB6
VSS
BB60
VSS
BB64
VSS
BB67
VSS
BB70
VSS
C1
VSS
C25
VSS
C5
VSS
D10
VSS
D11
VSS
D14
VSS
D18
VSS
D22
VSS
D25
VSS
D26
VSS
D30
VSS
D34
VSS
D39
VSS
D44
VSS
D45
VSS
D47
VSS
D48
VSS
D53
VSS
D58
VSS
D6
VSS
D62
VSS
D66
VSS
D69
VSS
E11
VSS
E15
VSS
E18
VSS
E21
VSS
E46
VSS
E50
VSS
E53
VSS
E56
VSS
E6
VSS
E65
VSS
E71
VSS
F1
VSS
F13
VSS
F2
VSS
F22
VSS
F23
VSS
F27
VSS
F28
VSS
F32
VSS
F33
VSS
F35
VSS
F37
VSS
F38
VSS
F4
VSS
F40
VSS
F42
VSS
BA41
VSS
?
A A
PROJECT : Y0DP
PROJECT : Y0DP
PROJECT : Y0DP
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KBL U (7/14)
KBL U (7/14)
NB5
NB5
5
4
3
2
NB5
KBL U (7/14)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
1A
1A
1A
8 40Friday, July 01, 2016
8 40Friday, July 01, 2016
8 40Friday, July 01, 2016
I'm from VIETNAM sualaptop365
5
4
3
2
1
09
?
SKL_ULT
19 OF 20
Need apply PN
RSVD_TP_BB68
RSVD_TP_BB69
RSVD_TP_AK13
RSVD_TP_AK12
RSVD_BB2
RSVD_BA3
RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2
RSVD_B3
RSVD_A3
RSVD_AW1
RSVD_E1
RSVD_E2
RSVD_BA4
RSVD_BB4
RSVD_A4
RSVD_C4
RSVD_A69
RSVD_B69
RSVD_AY3
RSVD_D71
RSVD_C70
RSVD_C54
RSVD_D54
VSS_AY71
RSVD_TP_AW71
RSVD_TP_AW70
PROC_SELECT#
ZVM#
MSM#
TP5
TP6
TP4
TP1
TP2
?
BB68
BB69
AK13
AK12
BB2
BA3
AU5
AT5
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
A69
B69
AY3
D71
C70
C54
D54
AY4
BB3
AY71
AR56
AW71
AW70
AP56
C64
R375 *0_2/S
R385 *0_2/S
R159 * 100K_2
0112 unmount
SI
+VCCSTPLL
+1.8V_DEEP_SUS
R556 *0_2
C559
*1uF/6.3_2
Need apply PN
?
SKL_ULT
U11T
AW69
AW68
AU56
AW48
SPARE
RSVD_AW69
RSVD_AW68
RSVD_AU56
RSVD_AW48
C7
RSVD_C7
U12
RSVD_U12
U11
RSVD_U11
H11
RSVD_H11
20 OF 20
*SKL_ULT
REV = 1
RSVD_F6
RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52
F6
E3
C11
B11
A11
D12
C12
F52
?
U11S
RESERVED SIGNALS-1
E68
D D
C C
B B
1224
Del CFG0~CFG2 CFG5~CFG19
+1.0V_DEEP_SUS
R46 49.9/F_2
R183 *1K_2
CFG3
CFG4
CFG_RCOMP
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70
E63
F63
E66
F66
E60
AY2
AY1
K46
K45
AL25
AL27
C71
B70
F60
A52
BA70
BA68
F65
G65
F61
E61
E8
D1
D3
J71
J68
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG_RCOMP
ITP_PMODE
RSVD_AY2
RSVD_AY1
RSVD_D1
RSVD_D3
RSVD_K46
RSVD_K45
RSVD_AL25
RSVD_AL27
RSVD_C71
RSVD_B70
RSVD_F60
RSVD_A52
RSVD_TP_BA70
RSVD_TP_BA68
RSVD_J71
RSVD_J68
VSS_F65
VSS_G65
RSVD_F61
RSVD_E61
*SKL_ULT
REV = 1
PDC
Processor Strapping
CFG3
(Physcial Debug Enable)
DFX Privacy
CFG4
(DP Presence Strap)
A A
5
The CFG signals have a default value of '1' if not terminated on the board.
1 0
Disable: Enable: Set DFX Enable in DFX interface MSR
Disable; No physical DP attached to eDP
4
Enable; An ext DP device is connected to eDP
3
CFG3
CFG4
Circuit
R143 *1K_2
R42 1K_2
PROJECT : Y0DP
PROJECT : Y0DP
PROJECT : Y0DP
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KBL U (8/14)
KBL U (8/14)
NB5
NB5
2
NB5
KBL U (8/14)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
1A
1A
1A
9 40Friday, July 01, 2016
9 40Friday, July 01, 2016
9 40Friday, July 01, 2016
I'm from VIETNAM sualaptop365
5
+3V_DEEP_SUS <4,11,12,14,15,27>
+3V <2,4,11,12,13,14,15,20,22,23,26,27 ,29,30,31,37,38>
+5V <22,23,24,27,37>
+1.0V <2,4,6,30,36>
+3VS5 <4,15,21,28,30,31,33 ,35,36,37>
D D
C C
4
3
2
1
10
?
U11E
PCH_SPI1_CLK
PCH_SPI1_SO
PCH_SPI1_SI
PCH_SPI_IO2
PCH_SPI_IO3
PCH_SPI_CS0#
TP1137
GPP_D1
Support Vpro
EC_RCIN#<30>
SERIRQ<30 >
CL_RST#<28>
SIO_EXT_SMI#
PCI_SERR#
CL_CLK<28>
CL_DAT<28 >
SIO_EXT_SMI#<30>
PCI_SERR#<3 0>
AV2
AW3
AV3
AW2
AU4
AU3
AU2
AU1
M2
M3
J4
V1
V2
M1
G3
G2
G1
AW13
AY11
SPI - FLASH
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#
SPI - TOUCH
GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#
C LINK
CL_CLK
CL_DATA
CL_RST#
GPP_A0/RCIN#
GPP_A6/SERIRQ
*SKL_ULT
REV = 1
SKL_ULT
LPC
PDC
5 OF 20
Need apply PN
SMBUS, SMLINK
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
SMB_PCH_CLK
R7
SMB_PCH_DAT
R8
R10
SML0ALERT#
SMB_ME0_CLK
R9
SMB_ME0_DAT
W2
W1
SML1ALERT#
SMB_ME1_CLK
W3
SMB_ME1_DAT
V3
GPP_B23
AM7
AY13
BA13
BB13
AY12
BA12
BA11
CLK_PCI_EC_R
AW9
CLK_PCI_LPC_R
AY9
AW11
CLKRUN#
?
LAD0 <28,30>
LAD1 <28,30>
LAD2 <28,30>
LAD3 <28,30>
LFRAME# <28,30>
CLKRUN# <30>
SML0ALERT# <11>
SML1ALERT# <11>
TP15
R408 22/F_4
R404 2 2/F_4
EC25 18P/50V_4
EC24 18P/50V_4
CLK_24M_KBC <30>
CLK_24M_DEBUG <28>
EMI(near PCH)
GPIO Pull UP
+3V +3V_DEEP_SUS
SERIRQ
CLKRUN#
SIO_EXT_SMI#
EC_RCIN#
PCI_SERR#
B B
R377 10K_2
R380 8.2K/F_4
R205 10K_2
R202 10K_2
SMB_PCH_CLK<27>
SMB_PCH_DAT<27>
ACC_LED#<12>
SMB_ME0_CLK
SMB_ME0_DAT
SMB_ME1_CLK
SMB_ME1_DAT
SMBus/Pull-up(CLG)
A A
1230
Change net name from SMB_RUN_CLK to SMB_PCH_CLK
Change net name from SMB_RUN_DAT to SMB_PCH_DAT
5
4
Touch Pad
XDP
R360 2.2K_2
R366 2.2K_2
R232 499/F_4
R257 499/F_4
R341 1K_2
R333 1K_2R378 10K_2
R173 10K_2
SI
PCH SPI ROM(CLG)
Vender P/N
Size
EON
Winbond
8MB
GigaDevice
8MB
Socket
TP66-71 need place to TOP
R457/R453/R450/R451/R546/R548 close to U15 pin
C376 1U/10V_4
3
AKE3EZN0Q01 (EN25QH64-104HIP)8MB
AKE3EFP0N07 (W25Q64FVSSIQ)
AKE3EGN0Q01 (GD25B64BSIGR)
DFHS08FS023
U23&U24 footprint
PCH_SPI_CS0#_R
TP65
PCH_SPI1_CLK_R
TP68
PCH_SPI1_SI_R
TP71
PCH_SPI1_SO_R
TP67
BIOS_WP#
TP70
HOLD#
TP66
PCH_SPI_CS0#
R340 1 5/F_4
PCH_SPI1_CLK
R361 1 5/F_4
R367 1 5/F_4
R354 1 5/F_4
R359 1 K_4
+3VSPI
PCH_SPI_IO2
R365 1 5/F_4
PCH_SPI_CS0#_R<30>
PCH_SPI1_CLK_R<30>
PCH_SPI1_SI_R<30>
PCH_SPI1_SO_R<30>
PCH SPI ROM(CLG)
C373
22P/50V_4
2
U17
1
CE#
6
SCK
5
SI
2
SO
3
WP#
GD25B64BSIGR
AKE3EFP0N07
PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_RPCH_SPI1_SI
PCH_SPI1_SO_RPCH_SPI1_SO
4M SPI ROM Socket
PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_R
PCH_SPI1_SO_R
BIOS_WP#
+3V_M
8
+3VSPI
VDD
R343 1K_ 4
7
HOLD#
HOLD#
R342 15 /F_4
4
VSS
PCH_SPI_IO3BIOS_WP#
NB5
NB5
NB5
+3VSPI
SI
HOLD#
+3V_M<15>
C346
0.1U/16V_4
PROJECT : Y0DP
PROJECT : Y0DP
PROJECT : Y0DP
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KBL U (9/14)
KBL U (9/14)
KBL U (9/14)
Date: Sheet of
Date: Sheet of
Date: Sheet of
10 40Friday, July 01, 2016
10 40Friday, July 01, 2016
10 40Friday, July 01, 2016
1
1A
1A
1A
I'm from VIETNAM sualaptop365
5
4
3
2
1
11
D D
DESIGN NOTE:
WEAK PULL UP RESISTOR PRESENT ON THIS NET
ACZ_SPKR
ACZ_SPKR<1 4,23>
C C
1212 change R95 pull-high from
+3V to +3V_DEEP_SUS
B B
GSPI1_MOSI<14>
+3V_DEEP_SUS
SML0ALERT#
GSPI1_MOSI
Functional Strap Definitions
TOP SWAP OVERRIDE
HIGH - TOP SWAP ENABLE
R381
*20K/F_2
LOW-DISABLED
HIGH: LPC SELECTED FOR SYSTEM FLASH
WEAK INTERNAL PD
R231
1K_2
No Boot:
The signal has a weak internal pull-down.
0 = Disable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (no confidentiality).
1 = Enable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (with confidentiality). Must be
R233
*20K/F_2
pulled up to support Intel AMT with TLS and Intel
SBA (Small Business Advantage) with TLS.
No Boot:
The signal has a weak internal pull-down.
This field determines the destination of accesses to the
BIOS memory range. Also controllable using Boot BIOS
R63
Destination bit (Chipset Configuration Registers: Offset
*20K/F_2
3410h:Bit 10). This strap is used in conjunction with Boot
BIOS Destination Selection 0 strap.
Bit 10 Boot BIOS Destination
0 SPI
1 LPC
ACZ_SDOUT<14>
GPIO33_EC<3 0>
GPP_B18<14>SML0ALERT#<10>
SML1ALERT#<10>
ACZ_SDOUT
R401 1K_2
SML1ALERT#
GPP_B18
+3V_DEEP_SUS
R397
*4.7K_2
ACZ_SDOUT
+3V
R363
*4.7K_2
+3V_DEEP_SUS
R267
20K/F_2
No Boot:
The signal has a weak internal pull-down.
0 = Enable security measures defined in the Flash
Descriptor.
1 = Disable Flash Descriptor Security (override). This
strap should only be asserted high using external
pull-up in manufacturing/debug environments ONLY.
This function is useful when running ITP/XDP.
No Boot:
The signal has a weak internal pull-down.
0 = Disable No Reboot mode.
1 = Enable No Reboot mode
(PCH will disable the TCO
R362
Timer system reboot feature).
10K_2
This function is useful when running ITP/XDP.
R260
*10K_2
No Boot:
The signal has a weak internal pull-down.
0 = LPC Is selected for EC.
1 = eSPI Is selected for EC.
A A
PROJECT : Y0DP
PROJECT : Y0DP
PROJECT : Y0DP
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KBL U (10/14)
KBL U (10/14)
NB5
NB5
5
4
3
2
NB5
KBL U (10/14)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
1A
1A
1A
11 40Friday, July 01, 2016
11 40Friday, July 01, 2016
11 40Friday, July 01, 2016
I'm from VIETNAM sualaptop365
5
+3V <2,4,10,11,13,14,15,20,22,23,26,27 ,29,30,31,37,38>
+3VS5 <4,15,21,28,30,31,33 ,35,36,37>
+3V_DEEP_SUS <4,10,11,14,15,27>
PCIE_RXN5_CARD<26>
PCIE_RXP5_CARD<26 >
Type C
PCIE_TXN5_CARD<26>
PCIE_TXP5_CARD<26>
USB30_RX6-<21>
USB30_RX6+<21>
USB30_TX6+<21>
PCIE_RXN6_WLAN<28>
PCIE_RXP6_WLAN<28>
PCIE_TXN6_WLAN<28 >
PCIE_TXP6_WLAN<28>
SATA_RXN3<26>
SATA_RXP3<26>
SATA_TXN3<26>
SATA_TXP3<26>
SATA_RXN2<26>
SATA_RXP2<26>
SATA_TXN2<26>
SATA_TXP2<26>
SATA_RXN1<26>
SATA_RXP1<26>
SATA_TXN1<26>
SATA_TXP1<26>
SATA_RXN0<26>
SATA_RXP0<26>
SATA_TXN0<26>
SATA_TXP0<26>
+3V_DEEP_SUS
USB30_TX6-<21>
Cardreader
D D
WLAN
HDD
C C
B B
PCIE_TXN5_CARD_C
C176 0.1 U/16V_4
PCIE_TXP5_CARD_C
C177 0.1 U/16V_4
USB30_RX6USB30_RX6+
USB30_TX6USB30_TX6+
PCIE_TXN6_WLAN_C
C216 0.1 U/16V_4
PCIE_TXP6_WLAN_C
C215 0.1 U/16V_4
PCIE_RCOMPN/P 12mil
PCIE_RCOMPN
R44 100/F_2
PCIE_RCOMPP
R379 1 0K_2
PIRQA#
PCI-E Port Mapping Table
PCI-E Port
Port1
Port2
Port3
Port4
Port5
A A
5
Port6
Port7
Port8
Port9
Port10 Un-used
U11H
PCIE/USB3/SATA
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
*SKL_ULT
REV = 1
Function
CardReader
Un-used
WLAN
Un-used
SSD
SSD
SSD
Un-used
4
4
SKL_ULT
CLK RQ Port
Port0
Port1
Port2
Port3
Port4
Port5
?
PDC
8 OF 20
Function
Un-used
CardReader
WLAN
Un-used
Un-used
SSDSSD
Need apply PN
SSIC / USB3
USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP
USB2
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_E8/SATALED#
3
H8
USB3_1_RXN
G8
USB3_1_RXP
C13
USB3_1_TXN
D13
USB3_1_TXP
J6
H6
B13
A13
J10
H10
B15
A15
E10
USB3_4_RXN
F10
USB3_4_RXP
C15
USB3_4_TXN
D15
USB3_4_TXP
AB9
USB2N_1
AB10
USB2P_1
AD6
USB2N_2
AD7
USB2P_2
AH3
USB2N_3
AJ3
USB2P_3
AD9
USB2N_4
AD10
USB2P_4
AJ1
USB2N_5
AJ2
USB2P_5
AF6
USB2N_6
AF7
USB2P_6
AH1
USB2N_7
AH2
USB2P_7
AF8
USB2N_8
AF9
USB2P_8
AG1
USB2N_9
AG2
USB2P_9
AH7
USB2N_10
AH8
USB2P_10
USB2_COMP
AB6
USB2_COMP
AG3
USB2_ID
AG4
A9
TS_OFF
C9
TS_INT#
D9
TS_RST
B9
J1
GPP_E4/DEVSLP0
J2
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
DEVSLP1
J3
DEVSLP2
H2
SATAGP0
H3
SATAGP1
G4
SATAGP2
SATA_LED#
H1
?
USB3.0 Port Mapping Table
USB3.0 Function
PORT-1
PORT-2
PORT-3
PORT-4,6
3
USB30_RX1USB30_RX1+
USB30_TX1USB30_TX1+
USB30_RX2USB30_RX2+
USB30_TX2USB30_TX2+
USB30_RX3USB30_RX3+
USB30_TX3USB30_TX3+
USB30_RX4USB30_RX4+
USB30_TX4USB30_TX4+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBP8USBP8+
R326 113/F_4
USB3.0 MB-2
USB3.0 MB-3
USB3.0 MB-4
TYPEC
USB30_RX1- <25>
USB30_RX1+ <25>
USB30_TX1- <25>
USB30_TX1+ <25 >
USB30_RX2- <25>
USB30_RX2+ <25>
USB30_TX2- <25>
USB30_TX2+ <25 >
USB30_RX3- <25>
USB30_RX3+ <25>
USB30_TX3- <25>
USB30_TX3+ <25 >
USB30_RX4- <21>
USB30_RX4+ <21>
USB30_TX4- <21>
USB30_TX4+ <21 >
Type C
USBP1- <2 5>
USBP1+ <25>
USBP2- <2 5>
USBP2+ <25>
USBP3- <2 5>
USBP3+ <25>
USBP5- <2 1>
USBP5+ <21>
For Type C
USBP6- <2 0>
USBP6+ <20>
USBP7- <2 8>
USBP7+ <28>
USBP8- <2 0>
USBP8+ <20>
PLACE 'R10387' WITHIN 500 MILS
FROM USB2_COMP PIN WITH
TRACE IMPEDANCE LESS THAN 0.5 OHMS
ACC_LED# <10>
TS_OFF <20>
TS_INT# <20>
TS_RST <20>
TP53
DEVSLP1 <26>
TP52
SI
GPIO34 <26>
GPIO35 <26>
GPIO36 <26>
2
USB3.0 (M/B-1)
USB3.0 (M/B-2)
USB3.0 (M/B-3)
Combo USB3.0 MB-1
Combo USB3.0 MB-2
Combo USB3.0 MB-3
Camera
BT
TOUCH SCREEN
USB2.0 Port Mapping Table
2
TS_OFF
TS_INT#
TS_RST
SATA_LED#
SATAGP0
SATAGP1
SATAGP2
USB2.0 Function
USB3.0 MB-1
PORT-1
PORT-2
USB3.0 MB-2
PORT-3
USB3.0 MB-3
PORT-4
NC
PORT-5
TYPEC
PORT-6
Camera
PORT-7
WLAN
PORT-8
Touch Screen
PORT-9
NC
PORT-10
NC
NB5
NB5
NB5
1
12
KBL U (11/14)
KBL U (11/14)
KBL U (11/14)
1
+3V
12 40Friday, July 01, 2016
12 40Friday, July 01, 2016
12 40Friday, July 01, 2016
R171 10K_2
R148 10K_2
R172 10K_2
R194 *10K_2
R126 10K_2
R15 10K_2
R14 10K_2
R16 *10K_2
R17 *10K_2
R131 *10K_2
PROJECT : Y0DP
PROJECT : Y0DP
PROJECT : Y0DP
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
1A
1A
1A
I'm from VIETNAM sualaptop365
Loading...