HP E1459A User Manual
Contents
HP E1459A 64-Channel Isolated Inpu t Inter rupt Modu le
Edition 3
Warranty .......................................................................................................................5
Safety Symbols . ............................................................................................................6
WARNINGS.................................................................................................................6
Declaration of Conformity............................................................................................7
Reader Comment Sheet ................................................................................................9
Chapter 1
Installing and Configuring the HP E1459A ..............................................................11
Functional Description................................................................................................11
Watchdog Timer ..................................................................................................14
Input Level Selection ..........................................................................................14
Input Isolation .....................................................................................................14
Input Debounce Processing .................................................................................14
Input Edge Detection ...........................................................................................15
Input Data Capture ..............................................................................................17
Front Panel Markers ............................................................................................18
Interrupt Driven or Polled Mode Operations ......................................................18
Interrupt Parsing ..................................................................................................18
Configuring for Installation ........................................................................................19
Setting the Logical Address ................................................................................20
Setting the Interrupt Priority ...............................................................................20
Setting Input Threshold Levels ................................................... ......... ...............21
Setting the Reset Time on the Watchdog Timer .................................................21
Connecting User Inputs .......................................................................................22
Installing the HP E1459A in a VXIbus Mainframe ............................................24
Terminal Block ....................................................................................................25
Wiring a Terminal Block .....................................................................................26
Chapter 2
Using the HP E1459A Module ................................. ...................................................29
Power-on / Reset States ..............................................................................................30
Example 1: Reset, Self Test, and Module ID ......................................................30
Example 2: Digital Input .....................................................................................32
Edge Detected Event Detection..................................................................................34
Example 3: Edge Interrupt ..................................................................................37
Contents 1
Chapter 3
HP E1459A SCPI Command Reference ....................................................................39
DIAGnostic:SYSReset Subsystem.............................................................................41
DIAGnostic:SYSReset[:STATe]? .......................................................................41
DIAGnostic:SYSReset:ENABle <state> ............................................................41
DIAGnostic:SYSReset:ENABle? .......................................................................42
DISPlay:MONitor Subsystem.....................................................................................43
DISPlay:MONitor:PORT <port> ........................................................................43
DISPlay:MONitor:PORT? [MINimum | MAXimum | DEFault] ........................ 44
DISPlay:MONitor:PORT:AUTO <state> ...........................................................44
DISPlay:MONitor:PORT:AUTO? ...................................................................... 44
DISPlay:MONitor[:STATe] <state> ...................................................................45
DISPlay:MONitor[:STATe]? .............................................................................. 45
INPut Subsystem.........................................................................................................46
INPutn:CLOCk[:SOURce] <source> ..................................................................46
INPutn:CLOCk[:SOURce]? ................................................................................ 4 7
INPutn:DEBounce:TIME <time> | MINimum | MAXimum | DEFault ............. 47
INPutn:DEBounce:TIME? [M INimum | MAXimu m | DEFault] ....................... 48
MEASure Subsystem..................................................................................................49
MEASure:DIGital:DATAn[:type] [:VALue]? ....................................................49
MEASure:DIGital:DATAn[:type]:BITm? .......................................................... 50
MEMory Subsystem ...................................................................................................51
MEMory:DELete:MACRo <name> ...................................................................51
SENSe Subsystem.......................................................................................................52
[SENSe:]EVENt:PORTn:DAVailable? .............................................................. 52
[SENSe:]EVENt:PORTn:DAVailable:ENABle <state> ....................................53
[SENSe:]EVENt:PORTn:DAVailable:ENABle? ...............................................53
[SENSe:]EVENt:PORTn:EDGE? ....................................................................... 54
[SENSe:]EVENt:PORTn:EDGE:ENABle <state> .............................. ...............54
[SENSe:]EVENt:PORTn:EDGE:ENABle? ........................................................ 55
[SENSe:]EVENt:PORTn:NEDGe? .....................................................................55
[SENSe:]EVENt:PORTn:NEDGe:ENABle <mask> ..........................................56
[SENSe:]EVENt:PORTn:NEDGe:ENABle? ......................................................56
[SENSe:]EVENt:PORTn:PEDGe? .....................................................................57
[SENSe:]EVENt:PORTn:PEDGe:ENABle <mask> ..........................................57
[SENSe:]EVENt:PORTn:PEDGe:ENABle? ......................................................58
[SENSe:]EVENt:PSUMmary:DAVailable? .......................................................58
[SENSe:]EVENt:PSUMmary:EDGE? ................................................................ 59
STATus Subsystem.....................................................................................................60
STATus:OPERation:CONDition? ......................................................................62
STATus:OPERation:ENABle <mask> ...............................................................62
STATus:OPERation:ENABle? ...........................................................................63
STATus:OPERation[:EVENt]? ...........................................................................63
STATus:OPERation:PSUMmary:CONDition? .................................................. 63
STATus:OPERation:PSUMmary:ENABle <mask> ...........................................64
STATus:OPERation:PSUMmary:ENABle? ....................................................... 64
STATus:OPERation:PSUMmary[:EVENt]? ......................................................65
STATus:PRESet ..................................................................................................65
2 Contents
STATus:QUEStionable:CONDition? .................................................................66
STATus:QUEStionable:ENABle <mask> ..........................................................66
STATus:QUEStionable:ENABle? ......................................................................67
STATus:QUEStionable[:EVENt]? ......................................................................67
SYSTem Subsystem ...................................................................................................68
SYSTem:CDEScription? <number> ...................................................................68
SYSTem:CTYPe? <number> ..............................................................................68
SYSTem:ERRor? ................................................................................................69
SYSTem:VERSion? ............................................................................................ 69
IEEE 488.2 Common Commands...............................................................................70
Command Quick Reference........................................................................................71
Appendix A
HP E1459A Specifications ...........................................................................................73
Appendix B
HP E1459A Register Definitions ................................................................................75
Overview.....................................................................................................................75
Addressing the Registers ............................................................................................76
Register Access with Logical Address ................................................................76
Register Access with Memory Mapping .............................................................76
Register Definitions....................................................................................................77
Manufacturer ID Register ..................................................................... ......... ......78
Device Type Register ......................................................... ......... ......... ...............78
Status/Control Register .......................................................................................78
Edge Interrupt Status Register .......................... ......... ......... ......... ......... ...............80
Data Available Status Register ................ ............................................................80
Watchdog Timer Control/Status Regist er ...........................................................81
Command Register Port 0/2 ................................................................................81
Channel Data Register Port 0/2 ...........................................................................83
Positive Edge Detect Register Port 0/2 ...............................................................83
Negative Edge Detect Register Port 0/2 ..............................................................84
Positive Mask Register Port 0/2 ..........................................................................84
Negative Mask Register Port 0/2 ........................................................................84
Debounce Clock Register Port 0 and Port1/ Port 2 and Port 3 ...........................85
Command Register Port 1/3 ................................................................................86
Channel Data Register Port 1/3 ...........................................................................87
Positive Edge Detect Register Port 1/3 ...............................................................88
Negative Edge Detect Register Port 1/3 ..............................................................88
Positive Mask Register Port 1/3 ..........................................................................88
Negative Mask Register Port 1/3 ........................................................................89
Debounce Clock Register Port 0 and Port 1/ Port 2 and Port 3 ..........................89
Power On/Reset Conditions........................................................................................91
Programming Examples..............................................................................................91
Output and Edge Detection Examples ................................................................92
Appendix C
Error Messages ..........................................................................................................105
Contents 3
4 Contents
Certification
Hewlett-Packard Company certifies that this product met its published specifications at the time of shipment from the factory. HewlettPackard further certifies that its calibration measurements are traceable to the United Sta tes Nati onal Insti tute of Sta ndards and
Technology (formerly National Bureau of Standards), to the extent allowed by that org an izat ion 's calibration facility, and to the
calibration facilities of other International Standards Organization members.
Warranty
This Hewlett-Packard product is warranted against defects in materials and workmanship for a period of three years from date of shipment.
Duration and conditions of warrant y for th is product ma y be superseded when the product is integrated in to (becomes a part of) other HP
products. During the warranty period, Hewlett-Packard Company will, at its option, either repair or replace products which prove to be
defective.
For warranty service or repair, this product must be returned to a service facility designated by Hewlett-Packard (HP). Buyer s hall prep ay
shipping charges to HP and HP shall pay shipping charges to return the product to Buyer. However, Buyer shall pay all shipping charges,
duties, and taxes for products returned to HP from another country
HP warrants that its software and firmware designated by HP for use with a product will execute its programming instructions when
properly installed on that product. HP does not warrant that the operation of the product, or software, or firmware will be uninterrupted
or error free.
Limitation Of Warranty
The foregoing warranty shall not appl y to defects resulting fro m improper or inad equate maintenance b y Buyer, Buyer-suppl ied prod ucts
or interfacing, unauthorized modification or misuse, operation outside of the environmental specifications for the product, or improper
site preparation or maintenance.
The design and implementation of any circuit on this product is the sole responsibility of the Buyer. HP does not warrant the Buyer's
circuitry or malfunctions of HP products that result from the Buyer's circuitry. In addition, HP does not warrant any damage that occurs
as a result of the Buyer's circuit or any defects that result from Buyer-supplied products.
NO OTHER WARRANTY IS EXPRESSED OR IMPLIED. HP SPECIFICALLY DISCLAIMS THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
Exclusive Remedies
THE REMEDIES PROVIDED HEREIN ARE BUYER 'S SO LE AND EXC LUSIVE REM EDIES. HP SHALL NOT BE LIABLE FOR
ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WHETHER BASED ON CONTRACT,
TORT, OR ANY OTHER LEGAL THEORY.
Notice
The information contained in this document is subject to change without notice. HEWLETT-PACKARD (HP) MAKES NO
WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. HP shall not be liable for errors
contained herein or for incidental or consequenti al damages in connection with the furnish ing, performance or use of this material. This
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photocopied, repro duced , o r tran slated t o an oth er lan gu age with out the prior written consent o f He wlett-Packard Company. HP assumes
no responsibility for the use or reliability of its software on equipment that is not furnished by HP.
U.S. Government Restricted Rights
The Software and Documentation have been developed entirely at private expense. They are delivered and licensed as "commercial
computer software" as defined in DFARS 252.227- 7013 (Oct 1988), DFARS 252.211-7015 (May 1991) or DFARS 252.227-7014 (Jun
1995), as a "commercial item" as defined in FAR 2.101(a), or as "Restricted computer software" as defined in FAR 52.227-19 (Jun
1987)(or any equivalent agency regulation or contract clause), whichever is applicable. You have only those rights provided for such
Software and Documentation by the applicable FAR or DFARS clause or the HP standard software agreement for the product involved
HP E1459A / Z2404B 64-Channel Isolated Input / Interrupt Module User's Manual
Edition 3
Copyright © 1997 Hewlett-Packard Company. All Rights Reserved.
5
Documentation History
All Editions and Updates of this manual and their creation date are listed below. The first Edi tion of the manu al is Editi on 1. The Edition
number increments by 1 whenever the manual is revised. Updates, which are issued between Editions, contain replacement pages to
correct or add additional information to the current Edition of the manual. Whenever a new Edition is created, it will contain all of the
Update information for the p revious Edition . Each new Editi on or Update also includ es a revised copy of th is documentation histor y page.
Edition 1 (as HP Z2404-90000). . . . . . . . . . . . . . . . . . . . . . . . . . . . August 1991
Edition 2 (as HP Z2404-90001). . . . . . . . . . . . . . . . . . . . . . . . . . .February 1996
Edition 3 (HP E1459-90001). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 1997
Safety Symbols
Instruction manual s ymbol affi xed to
Instruction manual s ymbol affi xed to
product. Indicates that the user must refer to
product. Indicates that the user must refer to
the manual for specific WARNING or
the manual for specific WARNING or
CAUTION information to avoid personal
CAUTION information to avoid personal
injury or damage to the product.
injury or damage to the product.
Indicates the field wiring terminal that must
be connected to earth ground before
operating the equipment — protects against
electrical shock in case of fault.
WARNING
Alternating current (AC)
Direct current (DC).
Indicates hazardous voltages.
Calls attention to a procedure, practice, or
condition that could cause bodily injury or
death.
or
Frame or chassis ground terminal—typically
connects to the equipment's metal frame.
CAUTION
Calls attention to a procedure, practice, or
condition that could possibl y cause damage to
equipment or permanent loss of data.
WARNINGS
The following general safety precautions must be observed during all phases of operation, service, and repair of this product. Failure to
comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design, manufacture, and
intended use of the product. Hewlett-Pa ckard Company assumes no liability for th e customer's failure to comply with these require ments.
Ground the equipment: For Safety Class 1 equipment (equipment having a protective earth terminal), an uninterruptible safety earth
ground must be provided from the mains power source to the product input wiring terminals or supplied power cable.
DO NOT operate the product in an explosive atmosphere or in the presence of flammable gases or fumes.
For continued protection against fir e, replace th e lin e fuse(s) on l y with fuse(s) of the same volt age and curren t rating and type. DO NOT
use repaired fuses or short-circuited fuse holders.
Keep away from live circuits: Operating personnel must not remove equipment covers or shields. Procedu res in volving th e removal of
covers or shields are for use by service-trained personnel only. Under certain conditions, dangerous voltages may exist even with the
equipment switched off. To avoid dangerous electrical shock, DO NOT perform procedures involving cover or shield removal unless you
are qualified to do so.
DO NOT operate damaged equipment: Whenever it is possible that the safety protection features built into this product have been
impaired, either through physical damage, excessive moisture, or any other reason, REMOVE POWER and do not use the product until
safe operation can be verified by service-trained personnel. If necessary, return the product to a Hewlett-Packard Sales and Service Office
for service and repair to ensure that safety features are maintained.
DO NOT service or adjust alone: Do not attempt internal service or adjustment unless another person, capable of rendering first aid and
resuscitation, is present.
DO NOT substitute parts or modify equipment: Because of the danger of introd ucing ad ditional h azards, do not install subst itute parts
or perform any unauthorized modification to the product. Return the product to a Hewlett-Packard Sales and Service Office for service
and repair to ensure that safety features are maintained.
6
Declaration of Conformity
according to ISO/IEC Guide 22 and EN 45014
Manufacturer's Name: Hewlett-Packard Company
Loveland Manufacturing Center
declares, that the product:
Product Name: 64-Channel Isolated Digital Input / Interrupt Module
Model Number: HP E1459A (formerly HP Z2404B)
Product Options: All
conforms to the following Product Specifications:
Safety: IEC 1010-1 (1990) Incl. Amend 1 (1992)/EN61010-1/A2 (1995)
CSA C22.2 #1010.1 (1992)
UL 3111
EMC: CISPR 11:1990/EN55011 (1991): Group1 Class A
EN50082-1:1992
IEC 801-2:1991: 4kVCD, 8kVAD
IEC 801-3:1984: 3 V/m
IEC 801-4:1988 : 1kV Power Line
ENV50141:1993/prEN50 082-1 (1995): 3Vrms
ENV50142:1994/prEN50082-1 (1995): 1kV CM, 0.5kV DM
IEC1000-4-8:1993/prEN50082-1 (1995): 3A/m
EN61000-4-11:1994/prEN50082-1 (1995):30%, 10ms 60%, 100ms
Supplementary Information: The product herewith complies with the requirements of the Low Voltage Directive
73/23/EEC and the EMC Directive 89/336/EEC (inclusive 93/68/EEC) and carries the "CE" mark accordingly.
Tested in a typical configuration in an HP C-Size VXI mainframe.
April, 1996
Jim White, QA Manager
European contact: Your local Hewlett-Packard Sales and Service Office or Hewlett-Packard GmbH, Department HQ-TRE, Herrenberger Straße 130, D-71034 Böblingen, Germany (FAX +49-7031-14-3143)
7
Notes:
8
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Chapter 1
Installing and Configuring the HP E1459A
The HP E1459A 64-Channel Isolated Digital Input/Interrupt module
(formerly known as the HP Z2404B
channels configured as four 16-bit ports. The module is used for sensing
signals and detecting edge changes on digital inputs. The module is a C-Size
VXIbus register-based product that operates in a C-Size VXIbus mainframe.
Each isolated channel can withstand up to 115 Vac RMS or 115 Vdc
difference in ground potential between channels. The input threshold for
each channel is selectable with a jumper to allow for inputs with high logic
levels from 5 to 48 volts. Each channel can be individually masked to
generate an interrupt on a positive and/or negative edge transition. Channel
inputs are also "debounced" to help prevent erroneous transition detection
on noisy signals. Two programmable clock sources control the debounce
circuitry (one for ports 0 and 1, one for ports 2 and 3).
Functional Descriptio n
The HP E1459A simultaneously monitors each channel for the occurrence
of transitions, (i.e., edge events), or for level sensing signals which meet
preprogrammed parameters for magnitude and duty. Each channel is
electrically isolated from al l other channels, power, gr ound, and other
current paths within the limits of specification. Each channel may be
independently programmed to sense only positive transitions, only negative
transitions, or transitions of either polarity.
1
) provides 64 isolated digital input
Figure 1-1 shows the functional block diagram for the module.
1. The HP E1459A and Z2404B are functionally identical. The HP E1459A is provided with a downloadable
SCPI driver and a VXIplug&play driver; the HP Z2404B was not provided with a language driver.
Installing and Configuring the HP E1459A 11
To VXIbus
Transceivers
Figure 1-1. HP E1459A 64-Channel Isolated Digital Input/Interrupt Block Diagram
12 Installing and Configuring the HP E1459A
The HP E1459A can be pr ogrammed to mon it or ch annel o ccurren ces ei th er
internally with a 1.0 MHz sample clock, or externally, with a sourced
capture clock. Using either clocking technique, data channels may function
as edge detect inputs and/or data capture inputs.
Events at any channel may occur simultaneously or in overlap with events
on any other channel. Figure 1-2 is a block diagram of the hardware interrupt
resolver circuit. User software algorithms are also necessary to resolve
issues of overlap and to determine the occurring sequence of events.
Figure 1-2. Resolver Block Diagram
Installing and Configuring the HP E1459A 13
Wa tchdog Ti me r The HP E1459A prov ides a progr ammable timer f acilit y which, in the e vent
of time-out, will generate a "system wide" reset to all other card-cage
modules. This timer may be disabled by the SCPI command
DIAG:SYSR:ENAB OFF.
Input Level
Selection
Each channel is capable o f operation over an input rang e from 2.0 through
60.0 Vdc. Input voltages are grouped into vo ltage ranges which ar e selected
via a series of jumpers on the module. These jumpers are described in more
detail beginning on page 21.
Input Isolation Each channel is optically coupled and electrically isolated from all other
channels and current paths. Isolated channel inputs are polarized and require
that the user observe input signal polarity when connections are made.
Input Debounce
Processing
Programmable
Debounce Parameters
Each channel is debounced by a digital circuit specific to this function. Two
programmable clock sources establish reference parameters which
determine the debounce criteria for validating inputs. Channels are not
independently programmed for debounce period, but are instead grouped
together in blocks of 32 channels per clock source. Channels 00-31 (Ports 0
and 1) are collectively programmed via one clock sou rce and channels 32-63
(Ports 2 and 3) are programmed via a second clock source.
Debounce circuits require that a channel input remain in a stable state for 4
to 4.5 periods of the programmable clock before a channel transition is
declared. The debounce clocks may be programmed for frequencies ranging
from 250 KHz down t o 466 µHz. The 4 to 4.5 clock period requirements of
the debouncers translate into debounce periods which range from 16 µS
minimum to 9600 seconds (2.67 hours) maximum.
The debounce circuits can add considerable latency in the signal path and an
additional delay occurs within the Register FPGA. Normally the signals pass
though without significant delay. However, during a VXIbus transaction to
this port, the input signals are momentarily captured by a latch and are held
for the duration of the bus transaction plus 500 nS. This prevents data events
from being lost due to potential timing conflicts with VXIbus transactions.
The data signals are then synchronized with the system clock and
synchronously captured in either the data register, the positive edge event
register, or the negative edge event register. This can potentially add another
500 nS depending upon timing circumstances.
Thus the input data is delayed by the debounce circuits, possibly by the input
latches (equal to bus transaction time plus 500 nS), and a synchronizing
delay of 500 nS. The external clocks (front panel external trigger inputs) are
also delayed but by no more than 500 nS. Therefore, an external capture
clock concurrent with a data event will not capture the event unless
consideration is given for data latency.
14 Installing and Configuring the HP E1459A
Caution The user MUST ensure, based upon the programmed debounce
period and internal delays, that data to be captured has
propagated the debouncers and is fully setup prior to the
assertion of the externally generated capture clock.
The module has two primary modes of operation: the module can interrupt
your software when an event occurs or your software can periodically poll
the module to determine if an event has occurred. If the channel data
registers are serviced via a "polled mode" method (which is not keyed to the
posting of the "marker bits" or the occurrence of an interrupt), no timing
relationship will necessarily exist with the debounced event. As a result, a
small window of uncertainty exists between input latch timing and debounce
circuit timing.
Input Edge
Detection
Caution Edge Detect Markers are cleared by a read of the register
Each channel may be programmed to sense the occurrence of a qualified
edge transition of either polarity, or both concurrently. All channels are
preprocessed via the debounce circuits before presentation to the edge detect
logic. Edge detection is performed (by sampling methods) within each of the
four ports, in groups of 16 channels per port. If enabled, each port will post
an "Edge Interrupt Marker" to the control logic circuitry on the occurrence
of a qualified edge event for any active channel within its channel group.
(The static state of these markers may be tested via the "Edge Interrupt
Status Register." These markers are also accessible at the front panel.)
causing the marker to be posted. Since there is no high-level
method of determining whether a positive or negative edge
event is generating the marker, both edge detect registers
(positive and negative) within a channel group, MUST be read
during the service interval to identify ALL edge events which
may have potentially occurred.
Each marker bit is forced inactive for a two clock (16 MHz) periods each
time either edge detect register is read. (The edge detect register is then
cleared at the end of the cycle.) If the register that is not being read is inactive
and remains inactive, the marker will continue to remain inactive. If the
register that is not read is active or becomes active, the marker is again
posted to the "control" logic. The control logic detects this event and stores
this occurrence in a flip-flop which marks the pending need for service. If
this marking register, (now active), is then read and ultimately cleared, the
marker will become inactive and will remain inactive until the subsequent
occurrence of another qualified edge event. The control logic detects this
"cleared marker condition" and consequently clears the pending service
request flip-flop.
External edge events which occur concurrently with a register read/clear
cycle are queued and post-processed on completion of the cycle.
Installing and Configuring the HP E1459A 15
Edge Detection
Examples
Figure 1-3 demonstrates a typical example. A channel that has been
programmed to detect both positive and negative edge transitions posts a
marker at the occurrence of a positive edge. Before user software can service
this interrupt, a negative transition occurs and is detected. Because both are
detected and the events are marked, user software first reads the positive
edge detect register and then the negative edge detect register.
Figure 1-3. Positive and Negative Edge Transitions
In Figure 1-4, a channel that has been programmed for data capture posts a
marker on the occurrence of an external capture clock. During the
subsequent data register read cycle, another data capture clock occurs to
create a pending DAV (Data AVailable) situation. The second DAV is
retained (and valid) until a subsequent read of the corresponding data
register.
Figure 1-4. DAV Timing
16 Installing and Configuring the HP E1459A
Input Data Capture The state of any channel, within any channel group, may be captured for
subsequent processing (as data) by an externally sourced capture clock
(XTRIG0N - XTRIG3N, the external trigger inputs for each port). Data
channels may be interspersed among all 64 channel inputs, but the user is
cautioned to ensure that all setup criteria and clock sources coincide with
requirements for synchronization. (Each channel group shares a common
capture clock which may not necessarily be synchronous with an external
capture clock of some other channel group.)
If enabled, each register FPGA will post a "Data Available Marker" to the
control FPGA on the occurrence of a corresponding capture clock. Data
Available Markers are cleared by a read of the corresponding "Channel Data
Register." (The static state of these markers may be tested via the "Data
Available Register.") Capture clocks which occur concurrently with a
"register read/marker clear" cycle, are queued and post- processed on
completion of the present cycle. In that event, the marker bit is forced
inactive for a two clock (16 MHz) period before again being posted to the
control FPGA.
In the "Data Capture Mode", the HP E1459A may be programmed to
generate an interrupt on the occurrence of an external capture clock, or an
internal 1.0 MHz sample clock may be selected to allow the state of the data
channels to be tested in the absence of a capture clock. Capture clock
selection (internal/external) is controlled by bit 1 of the Command Register
Word.
Caution A potential hazard exists if software were to improperly
program the HP E1459A to post data-capture IRQ's with the
internally selected 1.0 MHz clock source. I n this situation, a
DAV interrupt would be posted each microsecond (if software
were able to service at that rat e), and would cause software to
continuously vector to interrupt service upon each "return from
service." Therefore, the HP E1459A should never be
programmed to generate DAV interrupts with the internal clock
source selected.
In the HP E1459A the Data Ready Marker is guaranteed to be
cleared when the clock source is switched from internal to
external. Therefore, any capture clock which occurs within the
internal/external clock selection interval will not post a marker
to the control FPGA and will be lost.
Installing and Configuring the HP E1459A 17
Front Panel Markers All "Data Available" and "Edge Detect" marker bits are physically available
via the HP E1459A front panel. These outputs are TTL/HC compatible and
may be used to trigger other system-wide events or to provide logging
information for statistical tracking or other performance analysis purposes.
Interrupt Driven or
Polled Mode
Interrupts may be programmatically disabled for both edge-detect and
data-capture events. All registers remain active and valid and may be
serviced on a polled mode basis.
Operations
Interrupt Parsing Since the command module interrupt handler must service multiple,
concurrently-occurring interrupts, (including those which may be sharing
the same IRQ line), some method is necessary to ensure that only a single
IRQ is posted by the HP E1459A during each service interval.
Individual interrupts must be serviced by a commander on a one-for-one
basis. The HP E1459A accomplishes this by inhibiting the generation of a
second IRQ each time an IRQ is posted. THE INHIBIT CONDITION IS
CLEARED BY THE REMOVAL AND REASSERTION OF EITHER
INTERRUPT ENABLE BIT, "DAV" OR "EDGE DETECT." (Refer to
Figure 1-2.)
For this one-for-one interrupt parsing, the HP E1459A REQUIRES that a
global interrupt enable, either DAV or Edge Detect, be disabled and
reasserted within the context of the interrupt service procedure. Normally,
you would simply shut off interrupts at the top of the service procedure, and
would then re-enable them before returning from service. This is the
suggested usage, although this specific sequence is not necessary for proper
HP E1459A hardware function.
18 Installing and Configuring the HP E1459A
Configuring for Installation
Before installing the module you should verify that the following jumpers
and switches are set correctly.
•Logical Address dip sw itch
•Interrupt priority jumper positions
•Input threshold leve ls
•Reset time of the Watchdog Timer
WARNING SHOCK HAZARD. Only qualified, service-trained personnel who
are aware of the hazards involved should install, configure, or
remove the module. Disconnect all power sources from the
mainframe, the terminal module and installed modules before
installing or removing a module.
WARNING SHOCK HAZARD. When handling user wiring connected to the
terminal module, consider the highest voltage present
accessible on any terminal.
WARNING SHOCK HAZARD. Use wire with an insulation rating greater
than the highest voltage which will be present on the terminal
module. Do not touch any circuit element connected to the
terminal module if any other connector to the terminal module
is energized to more than 30 Vac RMS or 60 Vdc.
Caution MAXIMUM VOLTAG E. Maximum all owable voltage per channel
for this module is 60 Vdc. Up to 115 Vdc or 115 Vac RMS can be
applied from one channel to another or from any channel to
chassis.
Caution STATIC-SENSITIVE DEVICE. Use anti-static procedures when
removing, configuring, and installing a module. The module is
susceptible to static discharges. Do not install the module
without its metal shield attached.
Installing and Configuring the HP E1459A 19
Setting the Logical
Address
Each module within the VXIbus mainframe must be set to a unique logical
address. The setting is contr olle d by an 8 pin dip switch. This allows for
values from 0 to 255. The factory setting of this switch is decimal 144. No
two modules in the same mainframe can have the same logical address. The
location is shown in Figure 1-5.
Setting the Interrupt
Priority
Note Consult your mainfram e manual to be sure that backplane jumpers are
At power on, after a SYSRESET, or after resetting the module via the
control register, all masks will be cleared, interrupts will be disabled, and
internal triggering will be enabled. With interrupts enabled, an interrupt will
be generated whenever an edge occurs on a channel that has been enabled
properly.
The interrupt priority jumper selects which priority level will be asserted.
As shipped from the factory, the interrupt priority jumper should be in
position 1. In most applications this should not be changed. When set to
level X interrupts are disabled. The interrupt priority jumpers are identified
on the sheet metal shield. A hole has been cut into the shield for access to
the jumpers. Interrupts can also be disabled using the Control Register.
The jumper locations ar e shown in Fi gure 1-5. T o change the s ettin g, move
the jumper or jumpers to the desired setting. If the card uses two 2-pin
jumpers versus a single 4 pin jumper, the jumpers must all be placed in the
same row for proper operation.
configured correctly. If you are using the HP E1401B Mainframe these
jumpers are automatically set when the card is installed.
Figure 1-5. HP E1459A Logical Address Switch and IRQ Jumper Locations
20 Installing and Configuring the HP E1459A
Setting Input
Threshold Levels
1
Ch 0 Ch 2
Ch 3
Ch 6
Ch
The threshold levels for each channel can be set independently. A six pin
plug with a two pin shorting jack is provided for each channel. The channel
can be identified from the silk-screen on the board. Each jumper is labeled
JXCC, where J indicates jumper, X is a number that can be ignored and CC
indicates channel number. The default factory setting is for 5 volts. Pin 1 can
be identified by the square pad on the bottom of the board.
Ch 5
Ch 8
Ch 57 Ch 59
Ch 63
Ch 60
.
Figure 1-6. Input Threshold Level Jumpers and Watchdog Reset Time Jumpers
Setting the Reset
Time on the
Wa tchdog Ti me r
Ch 61
48 Volt
Ch 62
JM202
JM203
PET Time
Jumpers
12 Volt
24 Volt
5 Volt Settings
(Factory Default)
There are 2 jumpers located on the PC board used to control the reset time
of the Watchdog Timer (see Figure 1-6). The reset time is the maximum
allowed time between accesses to keep the Watchdog from asserting
SYSRESET. The Watchdog timer is reset by reading the Watchdog
Control/Status register; use the DIAG:SYSR:STAT? command (see Chapter
3).
.
The following table shows the effect of the jumpers on the reset time. An X
means that the jumper is in place and O indicates the jumper is removed. The
factory default setting is 1.2 second.
Jumper Reset Time
600 ms 150 ms 1.2 sec Not Allowed JM202 O X O X JM203 O O X X
Installing and Configuring the HP E1459A 21
Connecting User
Inputs
Port Channels External Trigger Data Available Interrupt
The HP E1459A Isolated Digital Input/Interrupt module consists of a
component module and a terminal block. User inputs for each channel
consists of a low and a high connection for each channel. The inputs will
only detect signals of a positive polarity. A logical "1" will onl y be detected
if the high terminal is at a higher potential than the low terminal. It must also
meet the drive requirements for the voltage threshold selected.
For each block of 16 channels an additional active low input and two active
low outputs are available. The table below lists the signal names and the
associated channels.
0 0 through 15 XTRIG0N DAV0N INTR0N 1 16 through 31 XTRIG1N DAV1N INTR1N 2 32 through 47 XTRIG2N DAV2N INTR2N 3 48 through 63 XTRIG3N DAV3N INTR3N
Figure 1-7 shows the front panel terminals and pinouts for the module. The
cover to the terminal module is silk-screened to indicate the function of each
screw terminal.
22 Installing and Configuring the HP E1459A
A B C
32 CH 00 HI CH 00 LO
31 CH 01 HI CH 02 LO CH 01 LO
30 CH 02 HI CH 03 LO
29 CH 04 HI CH 03 HI CH 04 LO
28 CH 05 HI CH 05 LO
27 CH 06 HI CH 06 LO
26 CH 07 HI CH 07 LO
25 CH 08 HI CH 08 LO
24 CH 09 HI CH 09 LO
23 CH 10 HI CH 11 LO CH 10 LO
22 CH 11 HI CH 12 LO
21 CH 13 HI CH 12 HI CH 13 LO
20 CH 14 HI CH 14 LO
19 CH 15 HI CH 15 LO
18 CH 16 HI CH 16 LO
17 CH 17 HI CH 17 LO
16 CH 18 HI CH 18 LO
15 CH 19 HI CH 19 LO
14 CH 20 HI CH 20 LO
13 CH 21 HI CH 21 LO
12 CH 22 HI CH 23 LO CH 22 LO
11 CH 23 HI CH 24 LO
10 CH 25 HI CH 24 HI CH 25 LO
9 CH 26 HI CH 26 LO
8 CH 27 HI CH 27 LO
7 CH 28 HI CH 28 LO
6 CH 29 HI CH 29 LO
5 CH 30 HI CH 30 LO
4 CH 31 HI CH 31 LO
3 CH 32 HI CH 32 LO
2 CH 33 HI CH 33 LO
1 CH 34 HI CH 34 LO
A B C
32 CH 35 HI CH 35 LO
31 CH 36 HI CH 37 LO CH 36 LO
30 CH 37 HI CH 38 LO
29 CH 38 HI CH 39 HI CH 39 LO
28 CH 40 HI CH 40 LO
27 CH 41 HI CH 42 LO CH 41 LO
26 CH 42 HI CH 43 LO
25 CH 43 HI CH 44 HI CH 44 LO
24 CH 45 HI CH 45 LO
23 CH 46 HI CH 46 LO
22 CH 47 HI CH 47 LO
21 CH 48 HI CH 48 LO
20 CH 49 HI CH 49 LO
19 CH 50 HI CH 50 LO
18 CH 51 HI CH 51 LO
17 CH 52 HI CH 52 LO
16 CH 53 HI CH 53 LO
15 CH 54 HI CH 55 LO CH 54 LO
14 CH 55 HI CH 56 LO
13 CH 56 HI CH 57 HI CH 57 LO
12 CH 58 HI CH 58 LO
11 CH 59 HI CH 59 LO
10 CH 60 HI CH 61 LO CH 60 LO
9 CH 61 HI CH 62 LO
8 CH 62 HI CH 63 HI CH 63 LO
7
6
5 GND +5VTC GND
4 DAV3N INTR3N XTRIG3N
3 DAV2N INTR2N XTRIG2N
2 DAV1N INTR1N XTRIG1N
1 DAV0N INTR0N XTRIG0N
Figure 1-7. Front Panel Connections
Installing and Configuring the HP E1459A 23
Installing the HP
E1459A in a
VXIbus Mainframe
Set the extraction levers out.
1
Extraction
Levers
The HP E1459A may be installed in any C-size VXIbus mainframe slot
(except slot 0). Refer to Figure 1-8 to install the module in a mainframe.
Slide the into any slot
2
(except slot 0) until the backplane
connectors touch.
module
Tighten the top and bottom screws to
4
secure the module to the mainframe.
NOTE: The extraction levers will not
seat the backplane connectorson older
VXIbus mainframes. You must manually
seat the connectors by pushing in the
module until the module'sfront panelis
flush with the front of the mainframe.
The extraction lever s may be used to
guide or remove the .
To remov e the from the mainframe
reverse the procedure.
module
module
Seat the into the
3
mainframe by pushing in the
extraction levers
,
module
Figure 1-8. Installing the HP E1459A in a VXIbus Mainframe
WARNING To prevent electric shock, tighten faceplate screws when
installing module into mainframe.
24 Installing and Configuring the HP E1459A
Terminal Block The HP E1459A includes b oth the input / interrupt module and a scre w-type
standard terminal block. User inputs to the terminal block are to the High
and Low for each channel, +5Volt, Ground, Data Valid (DAV0 - DAV3),
External Trigger (XTRIG0 - XTRIG3), and Interrupt (INTR0 - INTR3) .
Figure 1-9 shows the HP E1459A’s standard screw-type terminal block
connectors and associated channel numbers. Use the guidelines below to
wire conn ections.
CH0 CH5
CH1
CH2
CH3
CH4
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH1 3
CH1 4
CH1 5
CH1 6
CH1 7
CH1 8
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
+5 G ND
CH29
CH30
CH31
CH32
CH33
CH34
+5 G ND
+5 G ND
+5 G ND
CH35
CH36
CH37
CH38
CH39
CH40
CH41
CH42
CH43
CH44
CH45
CH46
CH47
CH48
CH49
CH50
CH51
CH52
CH56
CH60
CH63
CH53
CH57
CH61
+5 GND
CH54
CH58
CH62
+5 G ND
CH55
CH59
GNDDAV INTREXT
NotUsed
GNDDAV INTREXT
GNDDAV INTREXT
Figure 1-9. HP E1459A Standard Screw-type Terminal Block
Wiring Guidelines •Be sure the wires make solid connections in the screw terminals.
•Maximum terminal wire size is No. 16 AWG. When wiring all
channels, a smaller gauge wire (No. 20 or 22 AWG) is recommended.
Wire ends should be stripped 5 to 6 mm (0.2 to 0.25 in.) and tinned to
prevent single strands from shorting to adjacent terminals.
WARNING To prevent the spread of fire in the case of a fault, use
flame-rated field wiring whenever the input voltage will exceed
30Vrms, 42Vpeak, or 60Vdc.
Installing and Configuring the HP E1459A 25
Wiring a Terminal
Block
The following illustrations show how to connect field wiring to the terminal
block.
Continued on Next Page
26 Installing and Configuring the HP E1459A
Replace Wiring Exit P anel
5
Replace Clear C ove r
6
A. Hook in the top cover tabs
onto the fixture
B. Pressdown and
tighten screws
Cut required
holes in panels
for wire exit
Install the Termi nal
7
Module
Keep wiring exit panel
hole as smallas
possible
Push in the Extract ion Lev ers t o Lock t he
8
Termin al M odule onto the HP E1 459A
Extraction
Levers
HP E1459A
Module
Installing and Configuring the HP E1459A 27
28 Installing and Configuring the HP E1459A
Chapter 2
Using the HP E1459A Module
This chapter provides examples of using and programming the HP E1459A
using the Standard Commands for Programmable Instrumentation (SCPI).
For detailed information on all the SCPI commands for this module, refer to
Chapter 3. Appendix B in this manual provides information on registers and
register-based programming.
Note If you are controlling the module by a high level language, such as the
downloaded SCPI driver or the VXIplug&play driver, do not do register
writes. This is because the high level driver will not know the instrument
state and an interrupt may occur causing the driver and/or command
module to fail.
The example programs in this chapter were developed with the ANSI C
language using the HP VISA extensions. For additional information, refer to
the HP VISA User ’s Guide. These programs were written and tested in
Microsoft Visual C++ but should compile under any standard ANSI C
compiler.
To run the programs you must have the HP SICL Library, the HP VISA
extensions, and an HP 82340 or 82341 HP-IB module installed and properly
configured in your PC. An HP E1406 Command Module provides direct
access to the VXI backplane.
Using the HP E1459A Module 29
Power-on / Reset States
At power-on or reset (*RST) the HP E1459A is set to the following
conditions:
•Watchdog timer is off (disabled).
•Clock Source is Internal
•Input Debounce Time is 18.0 µS.
•DAV (Data Available) Event interrupts are disabled for all ports.
•Edge Event interrupts are disabled for all ports.
Example 1:
Reset, Self Test,
and Module ID
Also, refer to the
STATus:PRESet command in Chapter 3.
This first example resets the HP E1459A, performs the module self test, and
reads the module ID and description.
/* Self Test
This program resets the HP E1459A, performs a Self Test,
and reads the ID string
Created in Microsoft Visual C++ */
#include <visa.h >
#include <stdio.h>
#include <stdlib.h>
#define INSTR_ADDR "GPIB0::9::3::INSTR"
int main()
{
ViStatus errStatus;
ViSession viRM;
ViSession E1459;
char id_string [256] = {0};
char selftst_string[256] = {0};
/* HP E1459A logical address */
/* status from VISA call */
/* Resource Mgr. session */
/* session for HP E1459A */
/* ID string buffer */
30 Using the HP E1459A Module
Open a default Resource Manager
/*
errStatus = viOpenDefaultRM (&viRM);
if (VI_SUCCESS > errStatus){
printf("ERROR: viOpen() returned 0x%x\n",errStatus);
return errStatus;}
Open the Instrument Session
/*
errStatus = viOpen (viRM, INSTR_ADDR,VI_NULL ,VI_ NULL , &E14 59);
if (VI_SUCCESS > errStatus){
printf("ERROR: viOpen() returned 0x%x\n",errStatus);
return errStatus;}
Reset the E1459A
/*
errStatus = viPrintf (E1459, "*RST;*CLS\n");
if (VI_SUCCESS > errStatus){
printf("ERROR: viPrintf() returned 0x%x\n",errStatus);
return errStatus;}
*/
*/
*/
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