HP DL585 Introduction Manual
The AMD processor roadmap for industrystandard servers
technology brief, 6th Edition
Abstract.............................................................................................................................................. 2
Introduction......................................................................................................................................... 2
X86 architecture .................................................................................................................................. 2
32-bit operations.............................................................................................................................. 2
AMD64 technology.......................................................................................................................... 3
Instruction set and registers............................................................................................................ 3
Operating modes ......................................................................................................................... 4
Memory addressability.................................................................................................................. 4
Naming conventions ............................................................................................................................ 4
Direct Connect I/O Architecture ............................................................................................................ 5
Integrated memory controller and dedicated memory banks.................................................................. 5
HyperTransport Technology............................................................................................................... 6
Multi-core technologies......................................................................................................................... 7
Dual-core Revision F processors ......................................................................................................... 8
Quad-Core AMD Opteron processors................................................................................................. 9
AMD Smart Fetch Technology ......................................................................................................10
Enhanced AMD PowerNow! Technology....................................................................................... 10
Rapid Virtualization Indexing....................................................................................................... 10
Average CPU Power metric ......................................................................................................... 11
Independent and combined memory channel modes....................................................................... 12
Six-Core AMD Opteron processors................................................................................................... 12
HT Assist ................................................................................................................................... 13
Future AMD Opteron processors.......................................................................................................... 14
Software licensing ............................................................................................................................. 14
Conclusion........................................................................................................................................ 14
For more information.......................................................................................................................... 15
Call to action .................................................................................................................................... 15
Abstract
Since 1996, HP and AMD have collaborated to provide high-performance, energy efficient
solutions that deliver quality, variety, and value in industry-standard servers. This collaboration
includes the adoption of the latest multi-core AMD Opteron™ processors. This technology brief
discusses current and near future AMD Opteron processors and the evolving AMD Opteron
processor microarchitecture.
Introduction
The AMD Opteron family of processors is AMD’s offering for the industry-standard server market.
HP is providing AMD processors in the ProLiant server product line to offer enterprise customers
expanded options for improved performance while maintaining cost-effective infrastructures.
AMD Opteron processors are based on the X86 architecture with AMD64 technology and feature
an integrated memory controller and the Direct Connect I/O Architecture, which uses
HyperTransport™ technology. In addition, AMD multi-core processors feature AMD Virtualization™
and AMD PowerNow!™ technologies.
X86 architecture
AMD Opteron processors adhere to the x86 instruction set architecture to be compatible with the
wealth of 32-bit software applications available. In other words, at the software/hardware
interface, the software interface of the AMD Opteron processor remains the same with regard to
the memory addressing size, the instruction sets, and the register designs for the x86 architecture.
32-bit operations
A 32-bit processor has general-purpose registers (GPRs) that are 32 bits wide and can operate on
an integer data stream that is 32 bits wide. In addition, a 32-bit processor can hold 32 bits of
memory address data in a single register, for a maximum of 4 GB of addressable memory.
The x86 architecture supports physical addressing extensions (PAE), which extend the address
space to allow addressing to 36 bits for a maximum of 64 GB of physical addressable memory.
However, this requires the OS and applications to take advantage of the additional memory
addressing.
As shown in Table 1, the x86, 32-bit instruction set of the AMD Opteron family of processors
includes the following:
• Standard x86 instructions, which are general-purpose arithmetic functions
• Single Input Multiple Data (SIMD) Instructions, which let one command work simultaneously on
multiple data items. This includes Streaming SIMD Extensions (SSE), SSE2, SSE3, and SSE4a
instructions.
• x87 floating point instructions
AMD Opteron processors support 32-bit addressing as well as the 36-bit PAE.
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Table 1. 32-bit x86 instructions common to AMD processors
Instruction
name
Standard
x86
MMX
x87 Instructions for floating point calculations FP 80-bit* 8
SSE, SSE2,
SSE3, and
SSE4a
* According to the article “An Introduction to 64-bit Computing and x86-64” by Jon Stokes1, the “x87 uses 80-bit registers
to do double-precision floating point. The floats themselves are 64-bit, but the processor converts them to an internal, 80-bit
format for increased precision when doing computations.”
Description Register
type
Instructions for logical and arithmetic operations, address
calculations, and has 16-bit index registers for memory
pointers
Multimedia instructions that allow the processor to do 64-bit
SIMD operations
SSE improved upon the MMX instructions and allowed
processors to do 128-bit SIMD floating-point operations.
SSE2 added 64-bit parallel floating point numeric support.
It also added new instructions to support 128-bit SIMD
integer operations.
SSE3 instructions include 13 instructions that accelerate
performance of SSE technology, SSE2 technology, and
x87-floating-point math capabilities.
SSE4a instructions include two new SSE instructions. SSE4a
instructions also add support for unaligned SSE loadoperation, which formerly required 16-byte alignment.
GPR 32-bit 8
MMX 64-bit 8
MMX 128-bit 8
Size of
registers
Number of
registers
AMD Opteron processors support the AMD 3Dnow!™ instruction set, AMD’s version of multimedia
instructions. The 3DNow! set added SIMD instructions to improve the vector-processing (floating
point) performance of graphic-intensive and multimedia applications.
AMD64 technology
Introduced in 2003, AMD64 technology is the AMD microarchitecture and instruction set that
provides full support for 64-bit operating systems and applications. The most important feature of
AMD64 is support for very large virtual and physical memory in a flat address space.
Instruction set and registers
AMD64 instruction
These registers are used by the applications only when running the processors in 64-bit long mode.
To support the AMD64 instructions, the registers expand to include the following:
• Eight new 64-bit GPRs
• Extensions of the eight original, 32-bit GPRs to 64 bits
• Eight new 128-bit registers for SSE, SSE2, and SSE3 instructions
can take advantage of the 64-bit wide registers in AMD Opteron processors.
s
1
Available at http://arstechnica.com/cpu/03q1/x86-64/x86-64-1.html
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Operating modes
AMD Opteron processors use three different operating modes: 64-bit long mode, 64-bit
compatibility mode, and 32-bit legacy mode. The 64-bit long mode requires a 64-bit OS and an
application recompiled to use the 64-bit registers. In other words, the full capabilities of the
expanded register set are available only when both the OS and the application support 64 bits.
The 64-bit compatibility mode requires a 64-bit OS, but can use a 32-bit application. The
additional registers are available to the OS, but not to the 32-bit application, because it cannot
make use of them. When running in legacy mode, the processor acts just like a 32-bit processor,
and the extra registers are not available (Table 2).
Table 2. Operating modes for AMD Opteron processors2
Mode OS required Application
recompile required?
64-bit long mode 64-bit OS Yes Yes 64
64-bit compatibility
mode
32-bit legacy mode 32-bit OS No No 32
64-bit OS No Yes – to OS
Register extensions
available?
No – to application
GPR width
(bits)
32
Memory addressability
The AM
D Opteron registers are at least 64-bits wide. When operating in 64-bit long mode, the
AMD Opteron processors support up to 48 bits (256 Terabytes) for physical memory and use 64
bits for virtual memory
Naming conventions
First-generation single-core AMD Opteron processors (Socket 940 and Socket 939) have three-digit
model numbers in the form XZZ, and third-generation Quad-Core AMD Opteron processors (Socket
F and Socket AM2) have four-digit model numbers XYZZ. AMD Opteron processor “generations”
are called Revisions.
For all AMD Opteron processors, the first digit “X” specifies the number of CPUs on the target
machine:
• 1000 Series - Single-processor systems
• 2000 Series - Dual-processor systems
• 8000 Series - Systems with up to 8 processors
The second digit, Y, indicates socket generation, where “2” indicates Socket AM2 or Socket F
(1207). Series 12ZZ processors are based on Socket AM2; Series 22ZZ and 82ZZ processors are
based on Socket F (1207). If the second digit is “3,” it stands for third-generation AMD Opteron
processors for Socket AM2 and Socket F (1207). If the second digit is “4,” it indicates Six-Core
AMD Opteron processors.
2
From the document titled “AMD64 Architecture Programmer’s Manual, Vol. 1: Application Programming,“
available at www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24592.pdf
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The last two digits, ZZ, indicate the relati
higher performance.
In addition, the model number can include a suffix designator to indicate a non-standard power
level. HE designates a lower power version, and SE a higher power version. For example, Model
2220, Model 2220 HE, and Model 2220 SE all offer equivalent performance, but differ in power
consumption.
The AMD website includes a quick reference guide
socket, revision (stepping), core frequency, manufacturing process (45 nm, 65 nm, or 90 nm),
HyperTransport frequency, and wattage.
ve performance within the series. Higher numbers indicate
3
that details each processor part number by
Direct Connect I/O Architecture
The AMD Direct Connect I/O Architecture replaces the traditional front side bus with point-to-point
HyperTransport Technology links and an integrated memory controller connected to dedicated
memory banks for each processor.
Integrated memory controller and dedicated memory banks
Each AMD Opteron processor contains an integrated dual-channel SDRAM memory controller that
is directly connected to dedicated memory banks. Integrating the controller into the processor
means that memory performance can scale linearly based on the number of processors in a multiprocessor system. For example, in a multi-processor system, the integrated memory controller allows
for multiple memory requests in parallel, thereby increasing the effective memory bandwidth and
decreasing average memory latency.
The memory controller operates at a frequency independent of—and usually slower than—the
processor core. It has a 128-bit interface that is capable of supporting up to eight DDR2 DIMMs.
With four DDR2-800 DIMMs per channel, the memory bandwidth is up to 12.8 GB/s. The 128-bit
interface can be divided into two independent 64-bit memory channels for memory controller
utilization and better memory performance.
3
http://www.amdcompare.com/us-en/AMD Opteron/
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