HP C300 IBL30 Schematics

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Yonah uFCPGA with Intel

3 3

4 4

A

Calistoga_GM/PM+ICH7-M core logic

2006-07-24

REV:1.0

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-3342P

1.0

of

140Thursday, July 27, 2006

E

A

Compal confidential

File Name : LA-3342P

ZZZ

B

C

D

E

PCB

1 1

LVDS Panel
Interface

2 2

CRT & TV OUT

page 16

page 17

Thermal Sensor
ADM1032

page 4

Fan Control

page 4

uFCBGA-479/uFCPGA-478 CPU

Intel Calistoga GMCH

RTC CKT.

page 19

PCI BUS

3.3V 33 MHz

Power On/Off CKT.

page 29

10/100 LAN

DC/DC Int erface CKT.

3 3

page 33

RealTek 8100CL

page 23

Mobile Yonah

page 4, 5, 6

H_A#(3..31)
H_D#(0..63)

FSB

533/667MHz

PCBGA 1466

page 7, 8, 9, 10,11,12

DMI

Intel ICH7-M

mBGA-652

page 18, 19, 20, 21

LPC BUS

DDR2 -400/533/667

Dual Channel

PCIE x3

USB2.0

AC-LINK

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

page 13,14

Mini-PCIE Card

USB conn X2

BT Conn

Audio CKT
AMOM

page 24

page 28

page 28

page 25

Clock Generator
ICS 954306

Reserved

MODEM
AMOM

AMP & Audio Jack

page 15

page 26

page 27

Power Circuit DC/DC

page 34~40

RJ45 CONN

page 23

Touch Pad

page 29

ENE KB910/L

page 34

Int.KBD

page 29

SATA HDD
Connector x2

page 22

PATA CDROM
Connector

page 22

SPR CONN.

*RJ45 CONN
*MIC IN JACK
*LINE OUT JACK

BIOS

page 32

*SPDIF CONN
*DC JACK
*TVOUT CONN
*USB CONN x1

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LA-3342P

E

1.0

of

240Thursday, July 27, 2006

Voltage Rails

A

power
plane

+B
LDO3
LDO5

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

O MEANS ON

X MEANS OFF

1 1

O

O
O
O

O

X

+5VALW
+3VALW

O

O
O
O

X

XX X

+1.8V
+5V

O

XX

X

+5VS
+3VS
+2.5VS
+1.5VS
+0.9VS
+CPU_CORE
+VCCP

OO

OO

X

X

PCI Devices

EXTERNAL

CARD BUS & 1394

IDSEL# REQ/GNT# PIRQ
AD22 2 C,D,E,G

AD24 A1RealTekK 8100CL

Load BOM check item

MV step from PIRQE change to PIRQA for LAN poor performance.

1.U31 GM/PM/GML part number

2.U6 ICH7 part number

BOM: 43144132L01 (GM)

43144132L02 (GML)

Jump-Short:

PJP4,PJP6,PJP7 ,P JP8 ,PJ P10,PJP12,PJP14,PJP18,PJP19,PJP20,PJP25

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

LA-3342P

340Thursday, July 27, 2006

of

1.0

5

H_A#[3..31]<7>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

D D

H_REQ#[0..4]<7>

H_ADSTB#0<7>

C C

R17

56_0402_5%

1 2

+VCCP

B B

H_PROCHOT#<39>

1 2

+VCCP

75_0402_5%

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

A A

H_PROCHOT# OCP#

H_ADSTB#1<7>

CLK_CPU_BCLK<15>

CLK_CPU_BCLK#<15>

H_BPRI#<7>

H_DEFER#<7>

H_DRDY#<7>

H_HITM#<7>

H_LOCK#<7>

H_RESET#<7>

H_RS#[0..2]<7>

H_TRDY#<7>

ITP_DBRESET#<20>

H_DBSY#<7>

H_DPSLP#<19>

H_DPRSTP#<19,39>

H_DPWR#<7>

R18

H_PWRGOOD<19>

H_CPUSLP#<7>

R456 1K_0402_5%@

1 2

R455 51_0402_5%

1 2

H_THERMTRIP#<7,19>

+VCCP

12

R457

56_0402_5%@

B

2

E

3 1

C

Q35

MMBT3904_SOT23@

5

H_ADS#<7>
H_BNR#<7>

H_BR0#<7>

H_HIT#<7>

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

ITP_DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
ITP_BPM#4
ITP_BPM#5
H_PROCHOT#

H_PWRGOOD
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2 H_INIT#
ITP_TMS
ITP_TRST#

H_THERMDA
H_THERMDC
H_THERMTRIP#

OCP# <20>

JP16A

J4

A3#

L4

A4#

M3

A5#

K5

A6#

M1

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L1

A13#

P4

A14#

P1

A15#

R1

A16#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U2

A23#

R4

A24#

T5

ADDR GROUP

A25#

T3

A26#

W3

A27#

W5

A28#

Y4

A29#

W2

A30#

Y1

A31#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L5

REQ4#

L2

ADSTB0#

V4

ADSTB1#

A22

BCLK0

A21

H1

E2

G5

F1

H5

F21

G6

E4

D20

H4

B1

F3

F4
G3
G2

AD4
AD3
AD1
AC4

C20

E1

B5

E5

D24
AC2
AC1
D21

D6
D7

AC5
AA6
AB3
C26
D25
AB5
AB6

A24
A25

C7

HOST CLK

BCLK1

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#

CONTROL

HITM#
IERR#
LOCK#
RESET#

RS0#
RS1#
RS2#
TRDY#

BPM0#
BPM1#
BPM2#
BPM3#

DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

THERMAL

THERMDA

DIODE

THERMDC
THERMTRIP#

FOX_PZ47903-2741-42_YONAH

H_DPSLP#

H_DPRSTP#

YONAH

MISC

R437

1 2

56_0402_5%@

R436

1 2

56_0402_5%@

4

DATA GROUP

LEGACY CPU

+VCCP

4

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

3

This shall place near CPU

H_D#[0..63] <7>

H_D#0

E22

D0#

H_D#1

F24

D1#

H_D#2

E26

D2#

H_D#3

H22

D3#

H_D#4

F23

D4#

H_D#5

G25

D5#

H_D#6

E25

D6#

H_D#7

E23

D7#

H_D#8

K24

D8#

H_D#9

G24

D9#

H_D#10

J24

H_D#11

J23
H26
F26
K22
H25
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26

J26
M26
V23
AC20

H23
M24
W24
AD23
G22
N25
Y25
AE24

A6
A5
C4
B3
C6
B4

D5
A3

H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_A20M#
H_FERR#
H_IGNNE#

H_INTR
H_NMI

H_STPCLK#
H_SMI#

H_DINV#0 <7>
H_DINV#1 <7>
H_DINV#2 <7>
H_DINV#3 <7>

H_DSTBN#[0..3] <7>

H_DSTBP#[0..3] <7>

H_A20M# <19>
H_FERR# <19>
H_IGNNE# <19>
H_INIT# <19>
H_INTR <19>
H_NMI <19>

H_STPCLK# <19>
H_SMI# <19>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

ITP_DBRESET#

R181 200_0402_5%@

1 2

2005/03/10 2006/03/10

ITP_TDI
ITP_TMS
ITP_TDO
ITP_BPM#5
ITP_TRST#
ITP_TCK

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4

Thermal Sensor ADM1032AR

2200P_0402_50V7K

+3VS

FAN control

Compal Secret Data

Deciphered Date

2

R6 56_0402_5%

1 2

R3 56_0402_5%

1 2

R2 56_0402_5%

1 2

R1 56_0402_5%

1 2

R4 56_0402_5%

1 2

R5 56_0402_5%

1 2

T27

PAD

T5

PAD

T4

PAD

T3

PAD

T1

PAD

T2

PAD

+3VS

2

C598

0.1U_0402_16V4Z

C592

1 2

R458

1 2

10K_0402_5%

BAS16_SOT23

EN_FAN1<31>

1

H_THERMDA
H_THERMDC

THERM#

+5VS

FAN1

FAN1

D22

3

2

+VCCP

U30

1

VDD

2

D+

3

D­THERM#4GND

ADM1032AR_SOP8

SCLK

SDATA

ALERT#

EC_SMC_2

8

EC_SMD_2

7
6
5

Address:100_1100

EC_SMC_2<31>

EC_SMD_2<31>

C765 10U_1206_16V4Z

1 2

U40

1

VEN

2

VIN

3

VO

4

VSET

G993P1UF_SOP8

+5VS +3VS

12

1SS355_SOD323
D28

1

2

FAN_SPEED1<31>

EC_SMC_2
EC_SMD_2

8

GND

7

GND

6

GND

5

GND

1

1

2

2

1000P_0402_50V7K

C761

C763 10U_0805_10V4Z

C762

1000P_0402_50V7K

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Yonah CPU in mFCPGA479

LA-3342P

R551
10K_0402_5%

1 2

ACES_85205-0300

1

2

JP30

1

1
2
3

0.1

of

440Thursday, July 27, 2006

1

5

4

3

2

1

D D

+VCCP

V_CPU_GTLREF

12

R454
1K_0402_1%

12

R451
2K_0402_1%

+1.5vs is a power source equired
by the PL clock generator on the
processorsilicon

Close to CPU pin AD26
within 500mils.

C C

+CPU_CORE

R442
100_0402_1%

1 2

R441
100_0402_1%

1 2

VCCSENSE

VSSSENSE

CPU_BSEL CPU_BSEL2 CPU_BSEL1

133

166

00

0

Close to CPU pin
within 500mils.

12

12

R452

R453

27.4_0402_1%

B B

54.9_0402_1%

R439

Length match within 25 mils
The trace width 18 mils space
7 mils

+1.5VS

1

C586

C587

2

0.01U_0402_16V7K

+VCCP is the FSB rail of the
processor and GMCH

CPU_BSEL0

1

1

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.

12

27.4_0402_1%

1

R438

12

54.9_0402_1%

1

2

10U_0805_10V4Z

VCCSENSE<39>
VSSSENSE<39>

H_PSI#<39>

CPU_VID0<39>
CPU_VID1<39>
CPU_VID2<39>
CPU_VID3<39>
CPU_VID4<39>
CPU_VID5<39>
CPU_VID6<39>

V_CPU_GTLREF

CPU_BSEL0<15>
CPU_BSEL1<15>
CPU_BSEL2<15>

+CPU_CORE

+VCCP

VCCSENSE
VSSSENSE

H_PSI#
CPU_VID0

CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

COMP0
COMP1
COMP2
COMP3

JP16B

AF7

VCCSENSE

AE7

VSSSENSE

B26

VCCA

K6

VCCP

J6

VCCP

M6

VCCP

N6

VCCP

YONAH

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

PSI#
VID0

VID1
VID2
VID3
VID4
VID5
VID6

GTLREF
BSEL0

BSEL1
BSEL2

COMP0
COMP1
COMP2
COMP3

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

FOX_PZ47903-2741-42_YONAH

W21

AD26

AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17

T6

R6

K21

J21
M21
N21
T21
R21
V21

V6

G21

AE6
AD6

AF5
AE5
AF4
AE3
AF2
AE2

B22
B23
C21

R26
U26

U1

V1

E7

D2

F6
D3
C1

AF1
D22
C23
C24
AA1
AA4
AB2
AA3

M4
N5

T2

V3

B2
C3

T22
B25

AB26

VSS

AA25

VSS

AD25

VSS

AE26

VSS

AB23

VSS

AC24

VSS

AF24

VSS

AE23

VSS

AA22

VSS

AD22

VSS

AC21

VSS

AF21

VSS

AB19

VSS

AA19

VSS

AD19

VSS

AC19

VSS

AF19

VSS

AE19

VSS

AB16

VSS

AA16

VSS

AD16

VSS

AC16

VSS

AF16

VSS

AE16

VSS

AB13

VSS

AA14

VSS

AD13

VSS

AC14

VSS

AF13

VSS

AE14

VSS

AB11

VSS

AA11

VSS

AD11

VSS

AC11

VSS

AF11

VSS

AE11

VSS

AB8

VSS

AA8

VSS

AD8

VSS

AC8

VSS

AF8

VSS

AE8

VSS

AA5

VSS

AD5

VSS

AC6

VSS

AF6

VSS

AB4

VSS

AC3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1

POWER, GROUNG, RESERVED SIGNALS AND NC

+CPU_CORE

JP16C

AE18

VCC

AE17

VCC

AB15

VCC

AA15

VCC

AD15

VCC

AC15

VCC

AF15

VCC

AE15

VCC

AB14

VCC

AA13

VCC

AD14

VCC

AC13

VCC

AF14

VCC

AE13

VCC

AB12

VCC

AA12

VCC

AD12
AC12
AF12
AE12
AB10

AB9

AA10

AA9

AD10

AD9

AC10

AC9

AF10

AF9

AE10

AE9
AB7
AA7
AD7
AC7
B20
A20
F20
E20
B18
B17
A18
A17
D18
D17
C18
C17
F18
F17
E18
E17
B15
A15
D15
C15
F15
E15
B14
A13
D14
C13
F14
E13
B12
A12
D12
C12
F12
E12
B10

A10
D10
C10
F10
E10

B9
A9
D9
C9

F9

E9
B7
A7

F7

YONAH

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

POWER, GROUND

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

FOX_PZ47903-2741-42_YONAH

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Yonah CPU in mFCPGA479

LA-3342P

540Thursday, July 27, 2006

1

0.1

of

5

4

3

2

1

D D

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

C C

Place these capacitors on L8
(Sorth side,Secondary Layer)

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

C13
10U_0805_6.3V6M

C33
10U_0805_6.3V6M

C40
10U_0805_6.3V6M

C26
10U_0805_6.3V6M

1

C14
10U_0805_6.3V6M

2

1

C39
10U_0805_6.3V6M

2

1

C32
10U_0805_6.3V6M

2

1

C21
10U_0805_6.3V6M

2

1

C28
10U_0805_6.3V6M

2

1

C42
10U_0805_6.3V6M

2

1

C27
10U_0805_6.3V6M

2

1

C15
10U_0805_6.3V6M

2

1

C23
10U_0805_6.3V6M

2

1

C35
10U_0805_6.3V6M

2

1

C22
10U_0805_6.3V6M

2

1

C10
10U_0805_6.3V6M

2

1

C34
10U_0805_6.3V6M

2

1

C38
10U_0805_6.3V6M

2

1

C16
10U_0805_6.3V6M

2

1

C1
10U_0805_6.3V6M

2

1

C18
10U_0805_6.3V6M

2

1

C41
10U_0805_6.3V6M

2

1

C11
10U_0805_6.3V6M

2

1

C6
10U_0805_6.3V6M

2

1

C19
10U_0805_6.3V6M

2

1

C2
10U_0805_6.3V6M

2

1

C36
10U_0805_6.3V6M

2

1

C24
10U_0805_6.3V6M

2

1

C30
10U_0805_6.3V6M

2

1

C48
10U_0805_6.3V6M

2

1

C31
10U_0805_6.3V6M

2

1

C12
10U_0805_6.3V6M

2

Mid Frequence Decoupling

<7/17> DFX SMT issue C584 -> @C584, @C585 -> C585

+CPU_CORE

1

1

+

C8

South Side Secondary

B B

<6/19> Remove C37 330u Cap

C47

2

330U_V_2.5VK_R9

330U_V_2.5VK_R9

1

+

C583

2

2

820U_E9_2_5V_M_R7

@

1

+

C576

+

2

330U_V_2.5VK_R9

<6/19> Remove C578 820u Cap

1

1

+

+

C585

C584

@

330U_V_2.5VK_R9

2

2

330U_V_2.5VK_R9

North Side Secondary

ESR <= 1.5m ohm
Capacitor > 1980uF

<6/23> Will populate 330U *4 for PV2

+VCCP

1

+

C591

220U_D2_4VM

A A

5

2

1

C43

0.1U_0402_16V4Z

2

1

C44

0.1U_0402_16V4Z

2

4

1

C45

0.1U_0402_16V4Z

2

1

C3

0.1U_0402_16V4Z

2

1

C4

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C5

0.1U_0402_16V4Z

2

3

Place these inside
socket cavity on L8
(North side
Secondary)

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

CPU Bypass capacitors

LA-3342P

1

of

640Thursday, July 27, 2006

0.1

5

4

3

2

1

H_D#[0..63]<4>

D D

C C

+VCCP

12

12

R462

R461

54.9_0402_1%

54.9_0402_1%

B B

12

R466

24.9_0402_1%

+VCCP

12

A A

R45

100_0402_1%

12

R42

200_0402_1%

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1

12

R464

24.9_0402_1%

Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.

H_VREF

1

C87

2

0.1U_0402_16V4Z

5

H1
H3
G1

G2

H4

K11

G4

T10

W11

U7

U9
U11
T11

W9

W7

U5

W6
AB7

AA9

W4

W3

W5
Y10
AB8

W2
AA4
AA7
AA2
AA6

AA10

AA1
AB4
AC9

AB11
AC11

AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5

AD10

AD4
AC8

J13
K13

U1

W1

U31A

F1

HD0#

J1

HD1#
HD2#

J6

HD3#
HD4#

K2

HD5#
HD6#
HD7#

K9

HD8#

K1

HD9#

K7

HD10#

J8

HD11#
HD12#

J3

HD13#
HD14#
HD15#
HD16#
HD17#

T3

HD18#
HD19#
HD20#
HD21#
HD22#
HD23#

T1

HD24#

T8

HD25#

T4

HD26#
HD27#
HD28#

T9

HD29#
HD30#

T5

HD31#
HD32#
HD33#
HD34#
HD35#

Y3

HD36#

Y7

HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#

Y8

HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HVREF0
HVREF1

E1

HXRCOMP

E2

HXSCOMP

Y1

HYRCOMP
HYSCOMP

E4

HXSWING
HYSWING

CALISTOGA_FCBGA1466~D

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#

HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

HADSTB#0
HADSTB#1

HOST

HCLKN
HCLKP

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

HDINV#0
HDINV#1
HDINV#2
HDINV#3

HCPURST#

HADS#

HTRDY#

HDPWR#

HDRDY#

HDEFER#

HHITM#

HHIT#

HLOCK#

HBREQ0#

HBNR#

HBPRI#

HDBSY#

HCPUSLP#

HRS0#
HRS1#
HRS2#

12

R38

221_0603_1%

12

R37

100_0402_1%

H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14

D8
G8
B8
F8
A8

B9
C13

AG1
AG2

K4
T7
Y5
AC4
K3
T6
AA5
AC5

J7
W8
U3
AB10

B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3

B4
E6
D6

H_SWNG0

1

2

4

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_MCH_BCLK#
CLK_MCH_BCLK

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

C82

0.1U_0402_16V4Z

+VCCP+VCCP

12

R463

12

R465

H_A#[3..31] <4>

H_REQ#[0..4] <4>

H_ADSTB#0 <4>
H_ADSTB#1 <4>

CLK_MCH_BCLK# <15>
CLK_MCH_BCLK <15>
H_DSTBN#[0..3] <4>

H_DSTBP#[0..3] <4>

H_DINV#0 <4>
H_DINV#1 <4>
H_DINV#2 <4>
H_DINV#3 <4>

H_RESET# <4>
H_ADS# <4>
H_TRDY# <4>
H_DPWR# <4>
H_DRDY# <4>
H_DEFER# <4>
H_HITM# <4>
H_HIT# <4>
H_LOCK# <4>
H_BR0# <4>
H_BNR# <4>
H_BPRI# <4>
H_DBSY# <4>
H_CPUSLP# <4>

H_RS#[0..2] <4>

221_0603_1%

H_SWNG1

1

C601

2

100_0402_1%

0.1U_0402_16V4Z

U31B

AE35
AF39
AG35
AH39

AC35
AE39
AF35
AG39

AE37
AF41
AG37
AH41

AC37
AE41
AF37
AG41

AY35

AR1

AW7

AW40
AW35

AT1
AY7

AY40
AU20

AT20
BA29
AY29

AW13
AW12

AY21

AW21

AL20
AF10

BA13
BA12
AY20
AU21

AV9
AT9

AK1

AK41

G28

F25

H26

G6
AH33
AH34

K28

CALISTOGA_FCBGA1466~D

Deciphered Date

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMITXP0
DMITXP1
DMITXP2
DMITXP3

SM_CK0
SM_CK1
SM_CK2
SM_CK3

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

SM_OCDCOMP0
SM_OCDCOMP1

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

SM_RCOMPN
SM_RCOMPP

SM_VREF0
SM_VREF1

PM_BMBUSY#
PM_EXTTS0#
PM_EXTTS1#
PM_THERMTRIP#
PWROK
RSTIN#

ICH_SYNC#

DMI

DDR MUXING

PM

2

PAD
PAD

1

2

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_OCDOCMP0
M_OCDOCMP1

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMPN
SMRCOMPP

PM_BMBUSY#
PM_EXTTS#0
DPRSLPVR
H_THERMTRIP#
ICH_POK
PLTRST_R#

12

+1.8V

12

R483

12

R481

Compal Secret Data

100_0402_1%

100_0402_1%

DMI_TXN0<20>
DMI_TXN1<20>
DMI_TXN2<20>
DMI_TXN3<20>

DMI_TXP0<20>
DMI_TXP1<20>
DMI_TXP2<20>
DMI_TXP3<20>

DMI_RXN0<20>
DMI_RXN1<20>
DMI_RXN2<20>
DMI_RXN3<20>

DMI_RXP0<20>
DMI_RXP1<20>
DMI_RXP2<20>
DMI_RXP3<20>

M_CLK_DDR0<13>
M_CLK_DDR1<13>
M_CLK_DDR2<14>
M_CLK_DDR3<14>

M_CLK_DDR#0<13>
M_CLK_DDR#1<13>
M_CLK_DDR#2<14>
M_CLK_DDR#3<14>

DDR_CKE0_DIMMA<13>
DDR_CKE1_DIMMA<13>
DDR_CKE2_DIMMB<14>
DDR_CKE3_DIMMB<14>

DDR_CS0_DIMMA#<13>
DDR_CS1_DIMMA#<13>
DDR_CS2_DIMMB#<14>
DDR_CS3_DIMMB#<14>

T17
T11

+1.8V

R40 80.6_0402_1%
R41 80.6_0402_1%

PLT_RST#<18,22,24>

V_DDR_MCH_REF<13,14>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

M_ODT0<13>
M_ODT1<13>
M_ODT2<14>
M_ODT3<14>

1 2
1 2

V_DDR_MCH_REF

PM_BMBUSY#<20>
PM_EXTTS#0<13,14>
DPRSLPVR<20,39>

H_THERMTRIP#<4,19>

ICH_POK<20,31>

R98 100_0402_1%

MCH_ICH_SYNC#<18>

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

V_DDR_MCH_REF

C663

0.1U_0402_16V4Z

2005/03/10 2006/03/10

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16

CFG

CFG17
CFG18
CFG19
CFG20

G_CLKP

G_CLKN

D_REF_CLKN

D_REF_CLKP

CLKNC

D_REF_SSCLKN
D_REF_SSCLKP

CLK_REQ#

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8

RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

RESERVED

Title

Size Document Number Rev

Custom

Date: Sheet

Description at page15.

MCH_CLKSEL0

K16

MCH_CLKSEL1

K18

MCH_CLKSEL2

J18

CFG3

F18

CFG4

E15

CFG5

F15

CFG6

E18

CFG7

D19

CFG8

D16

CFG9

G16

CFG10

E16

CFG11

D15

CFG12

G15

CFG13

K15

CFG14

C15

CFG15

H16

CFG16

G18

CFG17

H15

CFG18

J25

CFG19

K27

CFG20

J26

CLK_MCH_3GPLL

AG33

CLK_MCH_3GPLL#

AF33

CLK_MCH_DREFCLK#

A27

CLK_MCH_DREFCLK

A26

MCH_SSCDREFCLK#

C40

MCH_SSCDREFCLK

D41

CLKREQB#

H32

A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

PM_EXTTS#0

DPRSLPVR

PAD
PAD

PAD
PAD
PAD

PAD
PAD

PAD

R71

10K_0402_5%

R79

10K_0402_5%@

1 2

MCH_CLKSEL0 <15>
MCH_CLKSEL1 <15>

MCH_CLKSEL2 <15>

T6
T9

CFG5 <11>

T7

CFG7 <11>

T12

CFG9 <11>

T10

CFG11 <11>

CFG12 <11>

CFG13 <11>

T8

T16

CFG16 <11>

T14

CFG18 <11>

CFG19 <11>

CFG20 <11>

CLKREQB# <15>

12

Compal Electronics, Inc.

Calistoga (1/6)

LA-3342P

1

CLK_MCH_3GPLL <15>
CLK_MCH_3GPLL# <15>

CLK_MCH_DREFCLK# <15>
CLK_MCH_DREFCLK <15>

MCH_SSCDREFCLK# <15>
MCH_SSCDREFCLK <15>

+3VS

of

740Thursday, July 27, 2006

0.1

5

D D

4

3

2

1

DDR_A_BS#0<13>
DDR_A_BS#1<13>
DDR_A_BS#2<13>

DDR_A_DM[0..7]<13>

DDR_A_DQS[0..7]<13>

C C

DDR_A_DQS#[0..7]<13>

DDR_A_MA[0..13]<13>

B B

DDR_A_CAS#<13>
DDR_A_RAS#<13>

DDR_A_WE#<13>

T18 P AD
T19 P AD

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5

DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11 DDR_B_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#
SA_RCVENOUT#

U31D

AU12

SA_BS0

AV14

SA_BS1

BA20

SA_BS2

AJ33

SA_DM0

AM35

SA_DM1

AL26

SA_DM2

AN22

SA_DM3

AM14

SA_DM4

AL9

SA_DM5

AR3

SA_DM6

AH4

SA_DM7

AK33

SA_DQS0

AT33

SA_DQS1

AN28

SA_DQS2

AM22

SA_DQS3

AN12

SA_DQS4

AN8

SA_DQS5

AP3

SA_DQS6

AG5

SA_DQS7

AK32

SA_DQS0#

AU33

SA_DQS1#

AN27

SA_DQS2#

AM21

SA_DQS3#

AM12

SA_DQS4#

AL8

SA_DQS5#

AN3

SA_DQS6#

AH5

SA_DQS7#

AY16

SA_MA0

AU14

SA_MA1

AW16

SA_MA2

BA16

SA_MA3

BA17

SA_MA4

AU16

SA_MA5

AV17

SA_MA6

AU17

SA_MA7

AW17

SA_MA8

AT16

SA_MA9

AU13

SA_MA10

AT17

SA_MA11

AV20

SA_MA12

AV12

SA_MA13

AY13

SA_CAS#

AW14

SA_RAS#

AY14

SA_WE#

AK23

SA_RCVENIN#

AK24

SA_RCVENOUT#

CALISTOGA_FCBGA1466~D

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8

SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39

DDR SYS MEMORY A

SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D[0..63] <13> DDR_B_D[0..63] <14>

DDR_B_BS#0<14>
DDR_B_BS#1<14>
DDR_B_BS#2<14>

DDR_B_DM[0..7]<14>

DDR_B_DQS[0..7]<14>

DDR_B_DQS#[0..7]<14>

DDR_B_MA[0..13]<14>

DDR_B_CAS#<14>

DDR_B_RAS#<14>

DDR_B_WE#<14>

T13 PAD
T15 PAD

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6DDR_A_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10

DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#

U31E

AT24

SB_BS0

AV23

SB_BS1

AY28

SB_BS2

AK36

SB_DM0

AR38

SB_DM1

AT36

SB_DM2

BA31

SB_DM3

AL17

SB_DM4

AH8

SB_DM5

BA5

SB_DM6

AN4

SB_DM7

AM39

SB_DQS0

AT39

SB_DQS1

AU35

SB_DQS2

AR29

SB_DQS3

AR16

SB_DQS4

AR10

SB_DQS5

AR7

SB_DQS6

AN5

SB_DQS7

AM40

SB_DQS0#

AU39

SB_DQS1#

AT35

SB_DQS2#

AP29

SB_DQS3#

AP16

SB_DQS4#

AT10

SB_DQS5#

AT7

SB_DQS6#

AP5

SB_DQS7#

AY23

SB_MA0

AW24

SB_MA1

AY24

SB_MA2

AR28

SB_MA3

AT27

SB_MA4

AT28

SB_MA5

AU27

SB_MA6

AV28

SB_MA7

AV27

SB_MA8

AW27

SB_MA9

AV24

SB_MA10

BA27

SB_MA11

AY27

SB_MA12

AR23

SB_MA13

AR24

SB_CAS#

AU23

SB_RAS#

AR27

SB_WE#

AK16

SB_RCVENIN#

AK18

SB_RCVENOUT#

CALISTOGA_FCBGA1466~D

AK39

SB_DQ0

AJ37

SB_DQ1

AP39

SB_DQ2

AR41

SB_DQ3

AJ38

SB_DQ4

AK38

SB_DQ5

AN41

SB_DQ6

AP41

SB_DQ7

AT40

SB_DQ8

AV41

SB_DQ9

AU38

SB_DQ10

AV38

SB_DQ11

AP38

SB_DQ12

AR40

SB_DQ13

AW38

SB_DQ14

AY38

SB_DQ15

BA38

SB_DQ16

AV36

SB_DQ17

AR36

SB_DQ18

AP36

SB_DQ19

BA36

SB_DQ20

AU36

SB_DQ21

AP35

SB_DQ22

AP34

SB_DQ23

AY33

SB_DQ24

BA33

SB_DQ25

AT31

SB_DQ26

AU29

SB_DQ27

AU31

SB_DQ28

AW31

SB_DQ29

AV29

SB_DQ30

AW29

SB_DQ31

AM19

SB_DQ32

AL19

SB_DQ33

AP14

SB_DQ34

AN14

SB_DQ35

AN17

SB_DQ36

AM16

SB_DQ37

AP15

SB_DQ38

AL15

SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

DDR SYS MEMORY B

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (2/6)

LA-3342P

1

0.1

of

840Thursday, July 27, 2006

5

D D

LVDSA0+<16>
LVDSA1+<16>

LVDSA2+<16>
LVDSA0-<16>

LVDSA1-<16>

LVDSA2-<16>

LVDSB0+<16>
LVDSB1+<16>
LVDSB2+<16>

LVDSB0-<16>
LVDSB1-<16>
LVDSB2-<16>

LVDSAC+<16>

LVDSAC-<16>
LVDSBC+<16>
LVDSBC-<16>

C C

B B

GMCH_ENBKL<16>

EDID_CLK_LCD<16>
EDID_DAT_LCD<16>

GMCH_LVDDEN<16>

TV_COMPS<17>
TV_LUMA<17>
TV_CRMA<17>

3VDDCCL<17>

3VDDCDA<17>

CRT_VSYNC<17>
CRT_HSYNC<17>

CRT_B<17>
CRT_G<17>
CRT_R<17>

R482 1.5K_0402_1%

TV_COMPS
TV_LUMA
TV_CRMA

4

LVDSA0+
LVDSA1+
LVDSA2+

LVDSA0­LVDSA1­LVDSA2-

LVDSB0+
LVDSB1+
LVDSB2+

LVDSB0­LVDSB1­LVDSB2-

LVDSAC+
LVDSAC­LVDSBC+
LVDSBC-

GMCH_ENBKL

EDID_CLK_LCD
EDID_DAT_LCD

GMCH_LVDDEN

12

R58

12

4.99K_0402_1%

3VDDCCL
3VDDCDA

CRT_VSYNC
CRT_HSYNC
CRT_B

CRT_G
CRT_R

R65

12

255_0402_1%

U31C

H27

SDVOCTRL_DATA

H28

SDVOCTRL_CLK

B37

LA_DATA0

B34

LA_DATA1

A36

LA_DATA2

C37

LA_DATA#0

B35

LA_DATA#1

A37

LA_DATA#2

F30

LB_DATA0

D29

LB_DATA1

F28

LB_DATA2

G30

LB_DATA#0

D30

LB_DATA#1

F29

LB_DATA#2

A32

LA_CLK

A33

LA_CLK#

E26

LB_CLK

E27

LB_CLK#

D32

LBKLT_CTL

J30

LBKLT_EN

H30

LCTLA_CLK

H29

LCTLB_DATA

G26

LDDC_CLK

G25

LDDC_DATA

F32

LVDD_EN

B38

LIBG

C35

LVBG

C33

LVREFH

C32

LVREFL

A16

TVDAC_A

C18

TVDAC_B

A19

TVDAC_C

J20

TV_IREF

B16

TV_IRTNA

B18

TV_IRTNB

B19

TV_IRTNC

J29

TV_DCONSEL1

K30

TV_DCONSEL0

C26

DDCCLK

C25

DDCDATA

H23

VSYNC

G23

HSYNC

E23

BLUE

D23

BLUE#

C22

GREEN

B22

GREEN#

A21

RED

B21

RED#

J22

CRT_IREF

CALISTOGA_FCBGA1466~D

3

+1.5VS_PCIE

R89

PEGCOMP

D40

EXP_COMPI

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP0

EXP_RXP1

EXP_RXP2

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN0

EXP_TXN1

EXP_TXN2

EXP_TXN3

EXP_TXN4

EXP_TXN5

EXP_TXN6

EXP_TXN7

EXP_TXN8

EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0

EXP_TXP1

EXP_TXP2

EXP_TXP3

EXP_TXP4

EXP_TXP5

EXP_TXP6

EXP_TXP7

EXP_TXP8

EXP_TXP9

EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D38
F34

G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38

D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38

F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

EXP_COMPO

LVDS

TV CRT

PCI-EXPRESS GRAPHICS

24.9_0402_1%

1 2

2

1

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (3/6)

LA-3342P

1

0.1

of

940Thursday, July 27, 2006

5

+VCCP

21

D D

C C

B B

A A

D5

CH751H-40_SC76@

CH751H-40_SC76@

12

+2.5VS

R80

10_0402_5%@

+1.5VS

21

D19

12

+3VS

R520

10_0402_5%@

1

C612

C613

2

4.7U_0805_10V4Z

1

C81

2

1

0.22U_0603_10V7K

2

1

+

C610

220U_D2_4VM

2

1

2

2.2U_0805_16V4Z

MCH_A6

1

C607

2

MCH_D2

C597

0.22U_0603_10V7K

C596

+1.5VS

+VCCP

0.47U_0603_10V7K

MCH_AB1

1

2

0.47U_0603_10V7K

U31H

AC14

VTT0

AB14

VTT1

W14

VTT2

V14

VTT3

T14

VTT4

R14

VTT5

P14

VTT6

N14

VTT7

M14

VTT8

L14

VTT9

AD13

VTT10

AC13

VTT11

AB13

VTT12

AA13

VTT13

Y13

VTT14

W13

VTT15

V13

VTT16

U13

VTT17

T13

VTT18

R13

VTT19

N13

VTT20

M13

VTT21

L13

VTT22

AB12

VTT23

AA12

VTT24

Y12

VTT25

W12

VTT26

V12

VTT27

U12

VTT28

T12

VTT29

R12

VTT30

P12

VTT31

N12

VTT32

M12

VTT33

L12

VTT34

R11

VTT35

P11

VTT36

N11

VTT37

M11

VTT38

R10

VTT39

P10

VTT40

N10

VTT41

M10

VTT42

P9

VTT43

N9

VTT44

M9

VTT45

R8

VTT46

P8

VTT47

N8

VTT48

M8

VTT49

P7

VTT50

N7

VTT51

M7

VTT52

R6

VTT53

P6

VTT54

M6

VTT55

A6

VTT56

R5

VTT57

P5

VTT58

N5

VTT59

M5

VTT60

P4

VTT61

N4

VTT62

M4

VTT63

R3

VTT64

P3

VTT65

N3

VTT66

M3

VTT67

R2

VTT68

P2

VTT69

M2

VTT70

D2

VTT71

AB1

VTT72

R1

VTT73

P1

VTT74

N1

VTT75

M1

VTT76

AG14

VCCAUX32

AF14

VCCAUX33

AE14

VCCAUX34

Y14

VCCAUX35

AF13

VCCAUX36

AE13

VCCAUX37

AF12

VCCAUX38

AE12

VCCAUX39

AD12

VCCAUX40

CALISTOGA_FCBGA1466~D

P O W E R

4

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCD_HMPLL0
VCCD_HMPLL1

VCCDQ_TVDAC

VCC_SYNC

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GPLL

VCCA_3GBG
VSSA_3GBG

VCCA_DPLLA
VCCA_DPLLB

VCCA_HPLL

VCCA_LVDS

VSSA_LVDS

VCCA_MPLL
VCCA_TVBG

VSSA_TVBG

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCD_TVDAC

VCCHV0
VCCHV1
VCCHV2

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8

VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

H22

B30
C30
A30

AB41
AJ41
L41
N41
R41
V41
Y41

AC33
G41
H41

E21
F21
G21

B26
C39
AF1

A38
B39

AF2
H20

G20

E19
F19
C20
D20
E20
F20

AH1
AH2

A28
B28
C28

D21
H19

A23
B23
B25

AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

+2.5VS

1 2

C162

0.1U_0402_16V4Z

+2.5VS

W=40 mils

+1.5VS_3GPLL
+2.5VS

+2.5VS_CRTDAC

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL

+2.5VS

+1.5VS_MPLL
+3VS_TVBG

+3VS_TVDACA
+3VS_TVDACB
+3VS_TVDACC

+1.5VS

+1.5VS_TVDAC

1

2

C124

0.1U_0402_16V4Z

+1.5VS

1

C163

2

+1.5VS_PCIE

1

+

C682

2

1

2

C615

10U_1206_6.3V6M

0.1U_0402_16V4Z

220U_D2_4VM

1

2

+3VS

1

C666

2

C115

3

0_0805_5%

1

C665

2

10U_1206_6.3V6M

10U_1206_6.3V6M

L7 BLM11A601S_0603

1 2

1

C116

2

2200P_0402_50V7K

0.1U_0402_16V4Z

1

2

R490

12

+1.5VS

+2.5VS

CRTDAC: Route caps within
250mil of Alviso. Route FB
within 3" of Calistoga

+2.5VS

1

1

C160

C215

2

2

0.1U_0402_16V4Z

0.01U_0402_16V7K

close pin A38

R39

12

0_0805_5%

C117

0.1U_0402_16V4Z

C112

2200P_0402_50V7K

1

2

+2.5VS

1

C225

2

0.1U_0402_16V4Z

close pin G41

1

2

+3VS+3VS_TVBG

2

C110

2200P_0402_50V7K

1

2

0_0805_5%

C111

0.1U_0402_16V4Z

+1.5VS_DPLLA +1.5VS_DPLLB

0.1U_0402_16V4Z

C138

1

2

R52

12

MBK160808_0603

330U_V_2.5VK_R9

1

C616

+

2

1

C114

2

L28

1

2

2200P_0402_50V7K

12

R55

0_0805_5%

C109

0.1U_0402_16V4Z

PCI-E/MEM/PSB PLL decoupling

+1.5VS+1.5VS_3GPLL

R99
0_0603_5%

12

12

1

C280

2

0.1U_0402_16V4Z

@

1

1

C248

C174

2

2

0.1U_0402_16V4Z

10U_1206_6.3V6M

+1.5VS_MPLL

45mA Max. 45mA Max.

C604

1

2

0.1U_0402_16V4Z

R459
0_0603_5%

1

C593

2

10U_1206_6.3V6M

1

L29

MBK160808_0603

330U_V_2.5VK_R9

0.1U_0402_16V4Z

1

C645

C226

1

+

2

2

12

+1.5VS_TVDAC +1.5VS

C113

1

C614

2

0.1U_0402_16V4Z

+1.5VS_HPLL

1

2

1

2

2200P_0402_50V7K

1

C605

2

0.1U_0402_16V4Z

1

C107

2

2200P_0402_50V7K

R46
0_0603_5%

1

C594

2

C106

0.1U_0402_16V4Z

12

C105

R460
0_0603_5%

10U_1206_6.3V6M

0_0805_5%

@

12

R44

1

2

0.1U_0402_16V4Z

12

+1.5VS+1.5VS

+3VS+3VS_TVDACA+3VS+3VS_TVDACB+3VS+3VS_TVDACC

12

+1.5VS+1.5VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Docum ent Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (4/6)

LA-3342P

1

0.1

of

10 40Thursday, July 27, 2006

5

4

3

2

1

Strap Pin Table

CFG[3:17] have internal pull up

+VCCP

D D

1

1

C86

2

0.22U_0603_10V7K

1

C173

2

10U_1206_6.3V6M

C C

B B

C164

C600

C595

C606

1

C85

2

2

0.22U_0603_10V7K

0.22U_0603_10V7K

1

1

C139

2

2

1U_0603_10V4Z

10U_1206_6.3V6M

1

+

220U_D2_4VM

2

1

+

220U_D2_4VM

2

+VCCP

U31F

AD27

VCC_NCTF0

AC27

VCC_NCTF1

AB27

VCC_NCTF2

AA27

VCC_NCTF3

Y27

VCC_NCTF4

W27

VCC_NCTF5

V27

VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8

R27

VCC_NCTF9

AD26

VCC_NCTF10

AC26

VCC_NCTF11

AB26

VCC_NCTF12

AA26

VCC_NCTF13

Y26

VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16

U26

VCC_NCTF17

T26

VCC_NCTF18

R26

VCC_NCTF19

AD25

VCC_NCTF20

AC25

VCC_NCTF21

AB25

VCC_NCTF22

AA25

VCC_NCTF23

Y25

VCC_NCTF24

W25

VCC_NCTF25

V25

VCC_NCTF26

U25

VCC_NCTF27

T25

VCC_NCTF28

R25

VCC_NCTF29

AD24

VCC_NCTF30

AC24

VCC_NCTF31

AB24

VCC_NCTF32

AA24

VCC_NCTF33

Y24

VCC_NCTF34

W24

VCC_NCTF35

V24

VCC_NCTF36

U24

VCC_NCTF37

T24

VCC_NCTF38

R24

VCC_NCTF39

AD23

VCC_NCTF40

V23

VCC_NCTF41

U23

VCC_NCTF42

T23

VCC_NCTF43

R23

VCC_NCTF44

AD22

VCC_NCTF45

V22

VCC_NCTF46

U22

VCC_NCTF47

T22

VCC_NCTF48

R22

VCC_NCTF49

AD21

VCC_NCTF50

V21

VCC_NCTF51

U21

VCC_NCTF52

T21

VCC_NCTF53

R21

VCC_NCTF54

AD20

VCC_NCTF55

V20

VCC_NCTF56

U20

VCC_NCTF57

T20

VCC_NCTF58

R20

VCC_NCTF59

AD19

VCC_NCTF60

V19

VCC_NCTF61

U19

VCC_NCTF62

T19

VCC_NCTF63

AD18

VCC_NCTF64

AC18

VCC_NCTF65

AB18

VCC_NCTF66

AA18

VCC_NCTF67

Y18

VCC_NCTF68

W18

VCC_NCTF69

V18

VCC_NCTF70

U18

VCC_NCTF71

T18

VCC_NCTF72

M19

VCC100

L19

VCC101

N18

VCC102

M18

VCC103

L18

VCC104

P17

VCC105

N17

VCC106

M17

VCC107

N16

VCC108

M16

VCC109

L16

VCC110

CALISTOGA_FCBGA1466~D

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36

P O W E R

VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

VCC_SM100

VCC_SM101

VCC_SM102

VCC_SM103

VCC_SM104

VCC_SM105

VCC_SM106

VCC_SM107

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

+1.5VS

C603

+1.8V

0.47U_0603_10V7K

1

1

C602

2

2

0.47U_0603_10V7K

Place near pin AV1 & AJ1

A A

+VCCP

U31G

AA33

VCC0

W33

VCC1

P33

VCC2

N33

VCC3

L33

VCC4

J33

VCC5

AA32

VCC6

Y32

VCC7

W32

VCC8

V32

VCC9

P32

VCC10

N32

VCC11

M32

VCC12

L32

VCC13

J32

VCC14

AA31

VCC15

W31

VCC16

V31

VCC17

T31

VCC18

R31

VCC19

P31

VCC20

N31

VCC21

M31

VCC22

AA30

VCC23

Y30

VCC24

W30

VCC25

V30

VCC26

U30

VCC27

T30

VCC28

R30

VCC29

P30

VCC30

N30

VCC31

M30

VCC32

L30

VCC33

AA29

VCC34

Y29

VCC35

W29

VCC36

V29

VCC37

U29

VCC38

R29

VCC39

P29

VCC40

M29

VCC41

L29

VCC42

AB28

VCC43

AA28

VCC44

Y28

VCC45

V28

VCC46

U28

VCC47

T28

VCC48

R28

VCC49

P28

VCC50

N28

VCC51

M28

VCC52

L28

VCC53

P27

VCC54

N27

VCC55

M27

VCC56

L27

VCC57

P26

VCC58

N26

VCC59

L26

VCC60

N25

VCC61

M25

VCC62

L25

VCC63

P24

VCC64

N24

VCC65

M24

VCC66

AB23

VCC67

AA23

VCC68

Y23

VCC69

P23

VCC70

N23

VCC71

M23

VCC72

L23

VCC73

AC22

VCC74

AB22

VCC75

Y22

VCC76

W22

VCC77

P22

VCC78

N22

VCC79

M22

VCC80

L22

VCC81

AC21

VCC82

AA21

VCC83

W21

VCC84

N21

VCC85

M21

VCC86

L21

VCC87

AC20

VCC88

AB20

VCC89

Y20

VCC90

W20

VCC91

P20

VCC92

N20

VCC93

M20

VCC94

L20

VCC95

AB19

VCC96

AA19

VCC97

Y19

VCC98

N19

VCC99

CALISTOGA_FCBGA1466~D

P O W E R

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8

VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

+1.8V

MCH_AT41
MCH_AM41

C669

1

1

C668

2

2

0.47U_0603_10V7K

0.47U_0603_10V7K

Place near pin AT41 & AM41

1

1

C83

C222

2

2

0.1U_0402_16V4Z

1

C125

2

0.47U_0603_10V7K

Place near pin BA23

1

1

C641

C609

C104

2

2

10U_1206_6.3V6M

10U_1206_6.3V6M

1

2

0.47U_0603_10V7K

Place near pin BA15

CFG[2:0]

CFG5

CFG7

CFG9

CFG6

PSB 4X CLK Enable 1 = Calistoga

CFG[13:12]

CFG16

0.1U_0402_16V4Z

CFG10 CFG18

CFG19

SDVO_CTRLDATA

1

1

C84

C128

2

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

CFG20

(PCIE/SDVO select)

1

+

C599

2

470U_V_2.5VK_R9

<7/17> EMI iss ue , a dd ne w p art s C927,C928,C929,C930, C931,C932

+1.5VS

C927 0.1U_0402_16V4Z

1 2

C928 0.1U_0402_16V4Z

1 2

C929 0.1U_0402_16V4Z

1 2

C930 0.1U_0402_16V4Z

1 2

CFG[19:18] have internal pull down

011 = 667MT/s FSB
001 = 533MT/s FSB

0 = DMI x 2
1 = DMI x 4

0 = Reserved
1 = Mobile Yonah CPU

0 = Lane Reversal Enable
1 = Normal Operation

0 = Reserved

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default)

10 = 1.05V
01 = 1.5V

0 = Normal Operation
1 = DMI Lane Reversal Enable

0 = No SDVO Device Present

(Default)

1 = SDVO Device Present

0 = Only PCIE or SDVO is
operational.
1 = PCIE/SDVO are operating
simu.

R48 2.2K_0402_5%@

CFG5<7>

R54 2.2K_0402_5%@

CFG7<7>

R51 2.2K_0402_5%@

CFG9<7>
CFG11<7>
CFG12<7>
CFG13<7>
CFG16<7>

CFG18<7>
CFG19<7>
CFG20<7>

＠

＠

＠

＠

R47 2.2K_0402_5%@
R49 2.2K_0402_5%@
R50 2.2K_0402_5%@
R53 2.2K_0402_5%@

R74 1K_0402_5%@
R82 1K_0402_5%@
R87 1K_0402_5%@

+1.8V +1.8V

(Default)

*

*

(Default)

*

(Default)

*

1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2

C931 0.1U_0402_16V4Z

＠

1 2

C932 0.1U_0402_16V4Z

＠

1 2

(Default)

*

(Default)

(Default)

*

*

(Default)

*

*

*

+3VS

+VCCP

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (5/6)

LA-3342P

1

1.0

of

11 40Thursday, July 27, 2006

5

4

3

2

1

U31I

AC41

VSS0

AA41

VSS1

W41

VSS2

T41

VSS3

P41

VSS4

M41

D D

C C

B B

A A

VSS5

J41

VSS6

F41

VSS7

AV40

VSS8

AP40

VSS9

AN40

VSS10

AK40

VSS11

AJ40

VSS12

AH40

VSS13

AG40

VSS14

AF40

VSS15

AE40

VSS16

B40

VSS17

AY39

VSS18

AW39

VSS19

AV39

VSS20

AR39

VSS21

AN39

VSS22

AJ39

VSS23

AC39

VSS24

AB39

VSS25

AA39

VSS26

Y39

VSS27

W39

VSS28

V39

VSS29

T39

VSS30

R39

VSS31

P39

VSS32

N39

VSS33

M39

VSS34

L39

VSS35

J39

VSS36

H39

VSS37

G39

VSS38

F39

VSS39

D39

VSS40

AT38

VSS41

AM38

VSS42

AH38

VSS43

AG38

VSS44

AF38

VSS45

AE38

VSS46

C38

VSS47

AK37

VSS48

AH37

VSS49

AB37

VSS50

AA37

VSS51

Y37

VSS52

W37

VSS53

V37

VSS54

T37

VSS55

R37

VSS56

P37

VSS57

N37

VSS58

M37

VSS59

L37

VSS60

J37

VSS61

H37

VSS62

G37

VSS63

F37

VSS64

D37

VSS65

AY36

VSS66

AW36

VSS67

AN36

VSS68

AH36

VSS69

AG36

VSS70

AF36

VSS71

AE36

VSS72

AC36

VSS73

C36

VSS74

B36

VSS75

BA35

VSS76

AV35

VSS77

AR35

VSS78

AH35

VSS79

AB35

VSS80

AA35

VSS81

Y35

VSS82

W35

VSS83

V35

VSS84

T35

VSS85

R35

VSS86

P35

VSS87

N35

VSS88

M35

VSS89

L35

VSS90

J35

VSS91

H35

VSS92

G35

VSS93

F35

VSS94

D35

VSS95

AN34

VSS96

AK34

VSS97

AG34

VSS98

AF34

VSS99

CALISTOGA_FCBGA1466~D

P O W E R

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

U31J

AN21

VSS200

AL21

VSS201

AB21

VSS202

Y21

VSS203

P21

VSS204

K21

VSS205

J21

VSS206

H21

VSS207

C21

VSS208

AW20

VSS209

AR20

VSS210

AM20

VSS211

AA20

VSS212

K20

VSS213

B20

VSS214

A20

VSS215

AN19

VSS216

AC19

VSS217

W19

VSS218

K19

VSS219

G19

VSS220

C19

VSS221

AH18

VSS222

P18

VSS223

H18

VSS224

D18

VSS225

A18

VSS226

AY17

VSS227

AR17

VSS228

AP17

VSS229

AM17

VSS230

AK17

VSS231

AV16

VSS232

AN16

VSS233

AL16

VSS234

J16

VSS235

F16

VSS236

C16

VSS237

AN15

VSS238

AM15

VSS239

AK15

VSS240

N15

VSS241

M15

VSS242

L15

VSS243

B15

VSS244

A15

VSS245

BA14

VSS246

AT14

VSS247

AK14

VSS248

AD14

VSS249

AA14

VSS250

U14

VSS251

K14

VSS252

H14

VSS253

E14

VSS254

AV13

VSS255

AR13

VSS256

AN13

VSS257

AM13

VSS258

AL13

VSS259

AG13

VSS260

P13

VSS261

F13

VSS262

D13

VSS265

B13

VSS264

AY12

VSS263

AC12

VSS266

K12

VSS267

H12

VSS268

E12

VSS269

AD11

VSS270

AA11

VSS271

Y11

VSS272

J11

VSS273

D11

VSS274

B11

VSS275

AV10

VSS276

AP10

VSS277

AL10

VSS278

AJ10

VSS279

CALISTOGA_FCBGA1466~D

P O W E R

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (6/6)

LA-3342P

1

0.1

of

12 40Thursday, July 27, 2006

5

DDR_A_DQS#[0..7]<8>

DDR_A_D[0..63]<8>

DDR_A_DM[0..7]<8>
DDR_A_DQS[0..7]<8>
DDR_A_MA[0..13]<8>

D D

Layout Note:
Place near JP41

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z
C131

1

2

0.1U_0402_16V4Z

1

1

2

2

C640

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

2.2U_0805_16V4Z
C204

1

2

0.1U_0402_16V4Z

1

2

C192

C639

+0.9VS

RP27 56_0404_4P2R_5%

RP15 56_0404_4P2R_5%

RP26 56_0404_4P2R_5%

RP12 56_0404_4P2R_5%

RP9 56_0404_4P2R_5%

RP3 56_0404_4P2R_5%

RP18 56_0404_4P2R_5%

C206

1

2

0.1U_0402_16V4Z

1

2

C175

14
23

14
23

14
23

14
23

14
23

14
23

14
23

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C C

B B

A A

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9VS

0.1U_0402_16V4Z

DDR_A_MA5
DDR_A_MA8

DDR_A_MA1
DDR_A_MA3

DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_BS#0
DDR_A_MA10

DDR_A_CAS#
DDR_A_WE#

DDR_CS1_DIMMA#
M_ODT1

1

2

1

2

C643

C130

C129

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C642

RP25

1 4
2 3

RP24

1 4
2 3

RP6

1 4
2 3

RP23

1 4
2 3

RP22

1 4
2 3

RP21

2 3
1 4

5

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C180

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C166

C630

DDR_A_BS#2
DDR_CKE0_DIMMA

DDR_A_MA7
DDR_A_MA6

DDR_A_MA9
DDR_A_MA12

DDR_A_MA4
DDR_A_MA2

DDR_A_MA0
DDR_A_BS#1

M_ODT0
DDR_A_MA13

DDR_CKE1_DIMMA
DDR_A_MA11

1

2

0.1U_0402_16V4Z

C143

1

2

C629

0.1U_0402_16V4Z
C193

1

2

0.1U_0402_16V4Z

1

2

C158

4

0.1U_0402_16V4Z
C187

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Layout Note:
Place these resistor
closely JP41,all
trace length Max=1.5"

4

1

2

C145

0.1U_0402_16V4Z

1

2

C136

3

+1.8V

JP21

1

VREF

3

DDR_A_D4
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D14

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D9
DDR_A_D15

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D29
DDR_A_D24

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA<7>

DDR_A_BS#2<8>

DDR_A_BS#0<8>

DDR_A_WE#<8>

DDR_A_CAS#<8>

DDR_CS1_DIMMA#<7>

1

2

C628

M_ODT1<7>

CLK_SMBDATA<14,15>

CLK_SMBCLK<14,15>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D37

DDR_A_D36
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D35

DDR_A_D32
DDR_A_D40

DDR_A_D44
DDR_A_DM5
DDR_A_D41

DDR_A_D46
DDR_A_D49

DDR_A_D48

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D54
DDR_A_D50

DDR_A_D61
DDR_A_D60

DDR_A_DM7
DDR_A_D59

DDR_A_D58
CLK_SMBDATA

CLK_SMBCLK

+3VS

1

C80

0.1U_0402_16V4Z

2

2005/03/10 2006/03/10

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

Compal Secret Data

Deciphered Date

203

SO-DIMM A
REVERSE

Top side

VSS
DQ4
DQ5

VSS
DM0

VSS
DQ6
DQ7

VSS

DQ12
DQ13

VSS
DM1

VSS

CK0

CK0#

VSS

DQ14
DQ15

VSS

VSS

DQ20
DQ21

VSS

NC

DM2

VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

A7
A6

VDD

A4
A2
A0

VDD

BA1

RAS#

S0#
VDD

ODT0

NC/A13

VDD

NC

VSS

DQ36
DQ37

VSS
DM4

VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS

CK1

CK1#

VSS
DM6

VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS
SAO

SA1

VSS

VSS

FOX_ASOA426-M4R-TR

CONN@

204

2

+1.8V

V_DDR_MCH_REF

2

DDR_A_D6

4

DDR_A_D0

6
8

DDR_A_DM0

10
12

DDR_A_D5

14

DDR_A_D7

16
18

DDR_A_D13

20

DDR_A_D12

22
24

DDR_A_DM1

26
28

M_CLK_DDR0

30

M_CLK_DDR#0

32
34

DDR_A_D11

36

DDR_A_D10

38
40

42

DDR_A_D20

44

DDR_A_D21

46
48
50

DDR_A_DM2

52
54

DDR_A_D23

56

DDR_A_D22

58
60

DDR_A_D28

62

DDR_A_D25

64
66

DDR_A_DQS#3

68

DDR_A_DQS3

70
72

DDR_A_D31

74

DDR_A_D30

76
78

DDR_CKE1_DIMMA

80
82
84
86
88

DDR_A_MA11

90
92

DDR_A_MA6

94
96

DDR_A_MA4

98

DDR_A_MA2

100

DDR_A_MA0

102
104

DDR_A_BS#1

106

DDR_A_RAS#

108

DDR_CS0_DIMMA#

110
112

M_ODT0

114

DDR_A_MA13

116
118
120
122

DDR_A_D39

124

DDR_A_D38

126
128

DDR_A_DM4

130
132

DDR_A_D34

134

DDR_A_D33

136
138

DDR_A_D45

140

DDR_A_D43

142
144

DDR_A_DQS#5

146

DDR_A_DQS5

148
150

DDR_A_D47

152

DDR_A_D42

154
156

DDR_A_D52

158

DDR_A_D53

160
162

M_CLK_DDR1

164

M_CLK_DDR#1

166
168

DDR_A_DM6

170
172

DDR_A_D51

174

DDR_A_D55

176
178

DDR_A_D57

180

DDR_A_D56

182
184

DDR_A_DQS#7

186

DDR_A_DQS7

188
190

DDR_A_D62

192

DDR_A_D63

194
196
198
200

2

R33

10K_0402_5%

12

12

R35

10K_0402_5%

2.2U_0805_16V4Z

0.1U_0402_16V4Z

C368

1

1

2

2

M_CLK_DDR0 <7>
M_CLK_DDR#0 <7>

PM_EXTTS#0 <7,14>

DDR_CKE1_DIMMA <7>

DDR_A_BS#1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <7>

M_ODT0 <7>

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

LA-3342P

C369

1

V_DDR_MCH_REF <7,14>

of

13 40Thursday, July 27, 2006

1

0.1

5

DDR_B_DQS#[0..7]<8>

DDR_B_D[0..63]<8>

DDR_B_DM[0..7]<8>
DDR_B_DQS[0..7]<8>
DDR_B_MA[0..13]<8>

D D

C C

B B

A A

Layout Note:
Place near JP42

+1.8V

1

2

C202

2.2U_0805_16V4Z

1

2

0.1U_0402_16V4Z

1

2

+0.9VS

2.2U_0805_16V4Z

C159

0.1U_0402_16V4Z

C179

RP16 56_0404_4P2R_5%

RP17 56_0404_4P2R_5%

RP13 56_0404_4P2R_5%

RP14 56_0404_4P2R_5%

RP11 56_0404_4P2R_5%

RP2 56_0404_4P2R_5%

RP19

56_0404_4P2R_5%

0.1U_0402_16V4Z

2.2U_0805_16V4Z

1

2

1

2

C146

RP10

RP7

RP8

RP5

RP4

RP1

C214

0.1U_0402_16V4Z

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

2 3
1 4

5

2.2U_0805_16V4Z
C205

1

2

0.1U_0402_16V4Z

1

2

C137

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

2.2U_0805_16V4Z
C132

1

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9VS

0.1U_0402_16V4Z

1

2

C156

DDR_B_MA1
DDR_B_MA3

DDR_B_BS#0
DDR_B_MA10

DDR_B_BS#1
DDR_B_MA0

DDR_CS2_DIMMB#
DDR_B_RAS#

DDR_B_CAS#
DDR_B_WE#

DDR_CS3_DIMMB#
M_ODT3

C157

1

2

1

2

C170

14
23

14
23

14
23

14
23

14
23

14
23

14
23

0.1U_0402_16V4Z
C169

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C165

DDR_B_MA9
DDR_B_MA12

DDR_B_MA11
DDR_CKE3_DIMMB

DDR_B_MA5
DDR_B_MA8

DDR_B_MA6
DDR_B_MA7

DDR_B_MA2
DDR_B_MA4

DDR_B_MA13
M_ODT2

DDR_B_BS#2
DDR_CKE2_DIMMB

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C142

1

2

0.1U_0402_16V4Z

1

2

C147

C144

0.1U_0402_16V4Z

C141

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C191

C133

Layout Note:
Place these resistor
closely JP42,all
trace length Max=1.5"

4

C140

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C176

C168

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V

JP24

1

VREF

3

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D20
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D18

DDR_B_D19
DDR_B_D28

DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB<7>

DDR_B_BS#2<8>

DDR_B_BS#0<8>
DDR_B_WE#<8>

DDR_B_CAS#<8>

DDR_CS3_DIMMB#<7>

M_ODT3<7>

CLK_SMBDATA<13,15>

CLK_SMBCLK<13,15>

3

DDR_CKE2_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D50

DDR_B_D56
DDR_B_D61 DDR_B_D57

DDR_B_DM7
DDR_B_D59

DDR_B_D58
CLK_SMBDATA

CLK_SMBCLK

+3VS

1

C79

0.1U_0402_16V4Z

2005/03/10 2006/03/10

2

Compal Secret Data

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

Deciphered Date

2

2

VSS

4

DQ4

6

DQ5

8

VSS

10

DM0

12

VSS

14

DQ6

16

DQ7

18

VSS

20

DQ12

22

DQ13

24

VSS

26

DM1

28

VSS

30

CK0

32

CK0#

34

VSS

36

DQ14

38

DQ15

40

VSS

42

VSS

44

DQ20

46

DQ21

48

VSS

50

NC

52

DM2

54

VSS

56

DQ22

58

DQ23

60

VSS

62

DQ28

64

DQ29

66

VSS

68

DQS3#

70

DQS3

72

VSS

74

DQ30

76

DQ31

78

VSS

80

NC/CKE1

82

VDD

84

NC/A15

86

NC/A14

88

VDD

90

A11

92

A7

94

A6

96

VDD

98

A4

100

A2

102

A0

104

VDD

106

BA1

108

RAS#

110

S0#

112

VDD

114

ODT0

116

NC/A13

118

VDD

120

NC

122

VSS

124

DQ36

126

DQ37

128

VSS

130

DM4

132

VSS

134

DQ38

136

DQ39

138

VSS

140

DQ44

142

DQ45

144

VSS

146

DQS5#

148

DQS5

150

VSS

152

DQ46

154

DQ47

156

VSS

158

DQ52

160

DQ53

162

VSS

164

CK1

166

CK1#

168

VSS

170

DM6

172

VSS

174

DQ54

176

DQ55

178

VSS

180

DQ60

182

DQ61

184

VSS

186

DQS7#

188

DQS7

190

VSS

192

DQ62

194

DQ63

196

VSS

198

SAO

200

SA1

VSS

VSS

FOX_ASOA426-M4R-TR

201

CONN@

202

SO-DIMM B
STANDARD

Bottom side

2

+1.8V

V_DDR_MCH_REF

DDR_B_D5
DDR_B_D4

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_D14

DDR_B_D15

DDR_B_D21DDR_B_D17
DDR_B_D16

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D26

DDR_B_D24DDR_B_D25
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D29

DDR_B_D27
DDR_CKE3_DIMMB

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D39

DDR_B_D38
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

1

V_DDR_MCH_REF <7,13>

0.1U_0402_16V4Z

2.2U_0805_16V4Z

1

1

C367

C366

2

2

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

PM_EXTTS#0 <7,13>

DDR_CKE3_DIMMB <7>

DDR_B_BS#1 <8>
DDR_B_RAS# <8>
DDR_CS2_DIMMB# <7>

M_ODT2 <7>

M_CLK_DDR2 <7>
M_CLK_DDR#2 <7>

R32

1 2

10K_0402_5%

12

10K_0402_5%

R34

Title

Size Document Number Rev

Date: Sheet

+3VS

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

LA-3342P

1

0.1

of

14 40Thursday, July 27, 2006

5

PCI

SRC

CPU

CLKSEL1

0

1

FSLA

CLKSEL0

Stuff

No Stuff

Stuff

No Stuff

Stuff

No Stuff

MHz

133

166

CLK_Ra

CLK_Rd

CLK_Rd

CLK_Ra

CLK_Rd

CLK_Ra

MHz

1000

100

CLK_Rb

CLK_Re

CLK_Re

CLK_Rb

CLK_Rf

CLK_Rb

MHz

33.31

33.3

CLK_Rc

CLK_Rf

CLK_Rf

CLK_Rc

CLK_Rc

ICH_SMBDATA<20,24>

ICH_SMBCLK<20,24>

FSLC1FSLB

CLKSEL2

0

Table : ICS954306

D D

FSB Frequency Selet:

CPU Driven

(Default)

*

533MHz

667MHz

CLK_Re

+VCCP

R232

@

R237

8.2K_0402_5%

C C

B B

A A

FSA

CLKREF1

1 2

R231

0_0402_5%

CLK_Ra

FSB

1 2

R191

0_0402_5%

CLK_Rb

R205

8.2K_0402_5%

1 2

R177

0_0402_5%

CLK_Rc

10K_0402_5%

CLK_ENABLE#

CPU_BSEL0<5>

CPU_BSEL1<5>

CPU_BSEL2<5>

56_0402_5%

CLK_Rd

1 2

1 2

12

R227

1K_0402_5%

12

R228
1K_0402_5%@

+VCCP

R201
1K_0402_5%@

1 2

1 2

R200

1K_0402_5%

12

R199

@

0_0402_5%

CLK_Re

+VCCP

R202
1K_0402_5%@

1 2

12

1 2

R184

R235

1K_0402_5%

12

R183

@

0_0402_5%

CLK_Rf

+3VS

12

5

MCH_CLKSEL0 <7>

MCH_CLKSEL1 <7>

MCH_CLKSEL2 <7>

High:Pin18/19 = 100MHz
Low:Pin18/19 = 96MHz Low:Pin44/45 = CPUCLK2_ITP

<6/12> Remove CLK_48M_CB

<6/3> PCI_CLK_LAN
selection (33MHz)

CLK_MCH_DREFCLK<7>

CLK_MCH_DREFCLK#<7>

LCD clock select

+3VS +3VS

12

R233

10K_0402_5%@

PCI_ICH REQ_SEL

12

R238
10K_0402_5%

4

2.2K_0402_5%
Q12
2N7002_SOT23

D

1 3

+3VS

CLK_48M_ICH<20>

CLK_14M_ICH<20>

H_STP_CPU#<20>

H_STP_PCI#<20>

CLK_ENABLE#<39>

CLK_PCI_ICH<18>

CLK_PCI_LAN<23>

CLK_PCI_EC<31>
CLK_PCI_SIO<29>

CLK_SMBDATA<13,14>

CLK_SMBCLK<13,14>

2

2

1 3

D

2N7002_SOT23

Q15

+3VS

+3VS

CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#

Pin44/45 function select

High:Pin44/45 = CLKREQ

**

4

+3VS

C424

C425

R236 12_0402_5%

R230 33_0402_5%

1 2

1 2

12

R312
10K_0402_5%

12

R308

10K_0402_5%@

R323

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

+CK_VDD_48

1

2

1

2

+CK_VDD_REF

R2662.4K_0402_1%

R229

33_0402_5%

R92033_0402_5%

12

R21610K_0402_5%

12

R21533_0402_5%

12

R22533_0402_5% @

12

R589100K_0402_5%

MCH_DREFCLK
MCH_DREFCLK#

+CK_VDD_MAIN1

12

12

12

R299

S

G

G

S

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CLK_48M_ICH

CLK_14M_ICH

H_STP_CPU#
H_STP_PCI#
CLK_ENABLE#

CLK_PCI_ICH PCI_ICH

CLK_SMBDATA
CLK_SMBCLK

1 2

R246 10_0402_5%

1 2

R253 10_0402_5%

3

+CK_VDD_MAIN1

1 2

+3VS

FSA
FSB

CLKREF1

CLKIREF

PCI_LAN
REQ_SEL

PCI_EC
PCI_SIO
PCI_PCM

+3VS

16
10

24
33
41
50
55

11
15
59

46
61

60
62

54
53

13
14

12
17
58
47
25
40
32

R324 0_0805_5%

R174 0_0805_5%

5

8
9
7

1
2
3
6

4

1 2

U13

VDD
VDD48
VDDPCI
VDDSRC
VDDSATA
VDDSRC
VDDCPU
VDDREF

FSLA/USB_48MHz
FSLB/TEST_MODE
FSLC/TEST_SEL/REF1

IREF
CPU_STOP#
PCI/SRC_STOP#
Vtt_PwrGd#/PD
**SEL_LCDCLK#/PCICLK_F1

REF0/PCICLK1
*REQ_SEL/PCICLK2
*SEL_PCI1/PCICLK3
**SEL_SATA1/PCICLK4
**SEL_SATA2/PCICLK5
PCICLK6

SDATA
SCLK

DOTT_96MHz
DOTC_96MHz

GND
GND
GND
GND
GNDCPU
GNDSRC
GNDSRC
GNDSATA

ICS954306_TSSOP64

1

C456
10U_0805_10V4Z

2

+CK_VDD_MAIN2

1

C416
10U_0805_10V4Z

2

LCDCLK_SST/SRCCLKT0
LCDCLK_SSC/SRCCLKC0

*CPUCLKT2_ITP/CLKREQC#

*CPUCLKC2_ITP/CLKREQD#

* Internal Pull-Up Resistor
** Internal Pull-Down Resistor

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C422

0.1U_0402_16V4Z

2

1

C418

0.1U_0402_16V4Z

2

X1
X2

SATACLKT

SATACLKC

CPUCLKT0

CPUCLKC0

CPUCLKT1

CPUCLKC1

*CLKREQA#

SRCCLKT2

SRCCLKC2

SATA1/SRCCLKT4
SATA1/SRCCLKC4

*CLKREQB#

SRCCLKT1

SRCCLKC1

SRCCLKT3

SRCCLKC3

SATA2/SRCCLKT5
SATA2/SRCCLKC5

SRCCLKT6

SRCCLKC6

SRCCLKT8

SRCCLKC8

SRCCLKT7

SRCCLKC7

2005/03/10 2006/03/10

1

C431

0.1U_0402_16V4Z

2

1

C417

0.1U_0402_16V4Z

2

Change Crusta l to SJ100002F10

C419 22P_0402_50V8J

12

Y2

CLK_XTAL_IN

57

CLK_XTAL_OUT

56

28

1 2

R305 0_0402_5%

29

1 2

R311 0_0402_5%

CPU_BCLK

52

CPU_BCLK#

51

MCH_BCLK

49

MCH_BCLK#

48

64

SSCDREFCLK

18

SSCDREFCLK#

19

PCIE_MCARD

22

PCIE_MCARD#

23

PCIE_SATA CLK_PCIE_SATA

30
31

63
20
21

MCH_3GPLL

26

MCH_3GPLL#

27

35
34

CPU_XDP

45
37
36

43
42

CPU_XDP# CLK_CPU_XDP#

44
39
38

14.31818MHZ_20P_1BX14318BE1A

C421 22P_0402_50V8J

1 2

R239 27_0402_5%

1 2

R247 27_0402_5%

1 2

R254 27_0402_5%

1 2

R258 27_0402_5%

12

R218 10K_0402_5%@

1 2

R257 10_0402_5%

1 2

R270 10_0402_5%

1 2

R282 10_0402_5%

1 2

R284 10_0402_5%

1 2

R297 27_0402_5%

1 2

R304 27_0402_5%

12

R226 10K_0402_5%@

<7/24> Silego damping resistor

Delete PCIE VGA CLK

10 Ohm->27 Ohm for EMI request.

1 2

R288 10_0402_5%

1 2

R292 10_0402_5%

1 2

R294 10_0402_5%

1 2

R301 10_0402_5%

12

R930 10K_0402_5%

12

R273 10K_0402_5%@

1 2

R278 10_0402_5%@

Delete 17" N e w Card PCIE CLK

12

R931 10K_0402_5%

12

R277 10K_0402_5%@

1 2

R271 10_0402_5%@

<6/12> Delet e 1 5 . 4" New Card PCIE CLK

Compal Secret Data

Deciphered Date

2

1

C440

0.1U_0402_16V4Z

2

1 2

R188

1_0805_1%

1 2

R187

2.2_0805_1%

12

12

<7/24> Silego damping resistor
10 Ohm->27 Ohm for EMI request.

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLKREQA#
MCH_SSCDREFCLK
MCH_SSCDREFCLK#

CLK_PCIE_MCARD

CLK_PCIE_MCARD#

CLK_PCIE_SATA#PCIE_SATA#

CLKREQB#

CLK_MCH_3GPLL

CLK_MCH_3GPLL#

CLK_PCIE_ICHPCIE_ICH

CLK_PCIE_ICH#PCIE_ICH#

CLKREQC#

CLK_CPU_XDP

CLKREQD#

2

1

C450

0.1U_0402_16V4Z

2

+CK_VDD_REF

+CK_VDD_48

+3VS

+3VS

1

C441

0.1U_0402_16V4Z

2

Place crystal within
500 mils of CK410

CLK_CPU_BCLK <4>
CLK_CPU_BCLK# <4>

CLK_MCH_BCLK <7>
CLK_MCH_BCLK# <7>

+3VS

CLKREQA# <24>
MCH_SSCDREFCLK <7>
MCH_SSCDREFCLK# <7>

CLK_PCIE_MCARD <24>
CLK_PCIE_MCARD# <24>

CLK_PCIE_SATA <19>
CLK_PCIE_SATA# <19>

+3VS

CLKREQB# <7>

CLK_MCH_3GPLL <7>
CLK_MCH_3GPLL# <7>

CLK_PCIE_ICH <20>
CLK_PCIE_ICH# <20>

Title

Size Document Number Rev

Date: Sheet of

1

1

C430

0.1U_0402_16V4Z

2

Place near U54

Place these components
near each pin within 40
mils.

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_BCLK
CLK_MCH_BCLK#

MCH_SSCDREFCLK
MCH_SSCDREFCLK#

CLK_PCIE_MCARD

CLK_PCIE_MCARD#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_PCIE_ICH

CLK_PCIE_ICH#
CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#

CLK_PCIE_SATA

CLK_PCIE_SATA#

CLK_CPU_XDP

CLK_CPU_XDP#

CLKREQA#

C802 1000P_0402_50V7K

CLKREQB#

C803 1000P_0402_50V7K

CLKREQC#

C804 1000P_0402_50V7K

CLKREQD#

C805 1000P_0402_50V7K

R240 49.9_0402_1%@
R248 49.9_0402_1%@

R255 49.9_0402_1%@
R259 49.9_0402_1%@

R256 49.9_0402_1%@
R269 49.9_0402_1%@

R281 49.9_0402_1%@
R283 49.9_0402_1%@
R287 49.9_0402_1%@
R291 49.9_0402_1%@

R295 49.9_0402_1%@

R302 49.9_0402_1%@
R245 49.9_0402_1%@
R252 49.9_0402_1%@

R296 49.9_0402_1%@

R303 49.9_0402_1%@

R279 49.9_0402_1% @

R272 49.9_0402_1%@

1 2
1 2
1 2
1 2

12
12

12
12

1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2

12
12

Compal Electronics, Inc.

Clock generator

LA-3342P

15 40Thursday, July 27, 2006

1

1.0

A

B

C

D

E

F

G

H

LCD Panel & inverter Connector

1 1

2 2

+3VS

R434

1 2

10K_0402_5%

R435

1 2

10K_0402_5%

EDID_CLK_LCD

EDID_DAT_LCD

WL_LED#<24,29>

INVT_PWM<31>
DAC_BRIG<31>

EDID_CLK_LCD<9>
EDID_DAT_LCD<9>

+5VS
+3VS

+LCDVDD

WL_LED#

EDID_CLK_LCD
EDID_DAT_LCD

INVPWR_B+

DISPOFF#
INVT_PWM
DAC_BRIG

JP2

UMA

39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

ACES_88107-4000G

LVDSAC+

40

LVDSAC-

38
36

LVDSA1-

34

LVDSA1+

32
30

LVDSBC+

28

LVDSBC-

26
24

LVDSB1-

22

LVDSB1+

20

LVDSB0+

18

LVDSB0-

16

LVDSB2+

14

LVDSB2-

12
10

LVDSA0-

8

LVDSA0+

6

LVDSA2-

4

LVDSA2+

2

Delete 17" LVDS Conn JP1

LVDSAC+ <9>

LVDSAC- <9>

LVDSA1- <9>

LVDSA1+ <9>

LVDSBC+ <9>

LVDSBC- <9>

LVDSB1- <9>
LVDSB1+ <9>
LVDSB0+ <9>

LVDSB0- <9>
LVDSB2+ <9>

LVDSB2- <9>

LVDSA0- <9>
LVDSA0+ <9>
LVDSA2- <9>

LVDSA2+ <9>

+3VS

R430

D17

BKOFF#<31>

GMCH_ENBKL<9>

CH751H-40_SC76

D16
CH751H-40_SC76

R431

100K_0402_5%

1 2

L25 FBMA-L10-201209-301LMT

1 2

L24 FBMA-L10-201209-301LMT@

1 2

0.1U_0402_16V4Z

4.7K_0402_5%

1 2

21

21

DISPOFF#

INVPWR_B+B+

1

1

C806

C807

2

2

68P_0402_50V8K

3 3

+LCDVDD +5VALW

12

R429

100_0402_1%

2N7002_SOT23

GMCH_LVDDEN<9>

4 4

13

D

Q32

S

R428
100K_0402_5%

1 2

2

G

13

2

0.047U_0402_16V4Z

Q31
DTC124EK_SC59

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

1

C572

2

0.1U_0402_16V4Z

+LCDVDD

1

2

C574

Q33
SI2301BDS_SOT23

1 3

D

1

C575

4.7U_0805_10V4Z

2

2005/03/10 2006/03/10

E

+3VS

S

G

2

1

C573

4.7U_0805_10V4Z

2

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

F

Date: Sheet

Compal Electronics, Inc.

LVDS Connector

LA-3342P

G

0.1

of

16 40Thursday, July 27, 2006

H

A

1 1

CRT_R<9>

CRT_G<9>

CRT_B<9>

+5VS

C580

1 2

0.1U_0402_16V4Z

R449

0_0402_5%

0_0402_5%

CRTHSYNC

A2Y

A2Y

CRT_HSYNC<9>

2 2

CRT_VSYNC<9>

1 2

R447

1 2

EMI

1

5

U29

P

4

OE#

G

3

1

5

U28

P

4

OE#

G

3

74AHCT1G125GW_SOT353-5

74AHCT1G125GW_SOT353-5

R14

1 2

75_0402_5%

B

1

2

C29

10P_0402_50V8K

@

CRT_HSYNC_R

CRT_VSYNC_RCRTVSYNC

R10

1 2

75_0402_5%

C

RB411D_SOT23

CRT CONNECTOR

EMI

L3

CRTR CRTL_R

CRTG

CRTB

1

R7

2

75_0402_5%

C20

10P_0402_50V8K

@

MBK2012800YZF

1 2

L2
MBK2012800YZF

1 2

L1
MBK2012800YZF

1 2

1

2

1 2

C9

10P_0402_50V8K

@

EMI

1

1

2

2

C25

C17

22P_0402_50V8J

22P_0402_50V8J

1 2

L27
FBM-L11-160808-800LMT_0603

1 2

L26
FBM-L11-160808-800LMT_0603

+R_CRT_VCC , +CRTVDD (40mils)

1

2

R16 4.7K_0402_5%

1

2

+CRTVDD

C579 10P_0402_50V8K

+CRTVDD

R443 4.7K_0402_5%

1

2

C46 220P_0402_25V8K

+5VS

+R_CRT_VCC

D1

2 1

1

2

C7

22P_0402_50V8J

CRT_HSYNCRFL

CRT_VSYNCRFL

F1

1.1A_6VDC_FUSE

0.1U_0402_16V4Z

CRTL_G

CRTL_B

C581

21

C582

1

2

10P_0402_50V8K

D

JP3
ALLTO_C10510-115A5-L_15P-s

6

11

1
7

12

16

2

17

8

13

3
9

14

4
10
15

5

Q1

D

S

1 3

Q34

2N7002_SOT23

G

2

D

1

2

1 3

C577 220P_0402_25V8K

2N7002_SOT23-3

S

R19

G

2

2.2K_0402_5%

3V_DDCDA

3V_DDCCL

R444

2.2K_0402_5%

+3VS

R21

1 2

R445

1 2

E

NZQA5V6AXV5T1_SOT533-5

2

1 5

D46

CLOSE TO JP3

0_0402_5%

0_0402_5%

3VDDCDA <9>

3VDDCCL <9>

43

TV-Out Connector
S-Video

EMI

L4

R24

TV_LUMA<9>

3 3

4 4

A

TV_CRMA<9>

TV_COMPS<9>

1 2

R31

1 2

R26

1 2

0_0402_5%

0_0402_5%

0_0402_5%

TVLUMA

TVCRMA

TVCOMPS

12

R28

75_0402_5%

B

12

R29

75_0402_5%

12

R23

75_0402_5%

C75

2

2

270P_0402_50V7K

270P_0402_50V7K

1

1

C77

MBC1608121YZF_0603

1 2

L6
MBC1608121YZF_0603

1 2

L5
MBC1608121YZF_0603

1 2

1

C49

2

270P_0402_50V7K

R22

1 2

0_0805_5%

TVGND

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

LUMA_CL

CRMA_CL

COMPS_CL

1

1

C74

2

330P_0402_50V7K

2005/03/10 2006/03/10

1

C76

2

C50

2

330P_0402_50V7K

Compal Secret Data

Deciphered Date

330P_0402_50V7K

JP17

1

1

2

2

3

3

4

4

5

5

6
7

8

6

GND

9

7

GND

SUYIN_030107FR007G317ZR

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

CRT & TVout Connector

LA-3342P

E

of

17 40Thursday, July 27, 2006

0.1

5

4

3

2

1

D D

C C

B B

+3VS

R179 8.2K_0402_5%

1 2

R529 8.2K_0402_5%

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

R528 8.2K_0402_5%
R530 8.2K_0402_5%
R526 8.2K_0402_5%
R540 8.2K_0402_5%
R538 8.2K_0402_5%
R213 8.2K_0402_5%
R178 8.2K_0402_5%
R527 8.2K_0402_5%

+3VS

R195 8.2K_0402_5%
R196 8.2K_0402_5%
R194 8.2K_0402_5%
R193 8.2K_0402_5%
R197 8.2K_0402_5%
R524 8.2K_0402_5%
R525 8.2K_0402_5%
R198 8.2K_0402_5%
R192 8.2K_0402_5%
R211 8.2K_0402_5%
R210 8.2K_0402_5%
R212 8.2K_0402_5%

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#
PCI_REQ4#
PCI_REQ3#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ5#

PCI_AD[0..31]<23>

PCI_PIRQA#<23>

<7/20>Add option resistor for poor LAN
performance.

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

U6B

E18

AD0

C18

AD1

A16

AD2

F18

AD3

E16

AD4

A18

AD5

E17

AD6

A17

AD7

A15

AD8

C14

AD9

E14

AD10

D14

AD11

B12

AD12

C13

AD13

G15

AD14

G13

AD15

E12

AD16

C11

AD17

D11

AD18

A11

AD19

A10

AD20

F11

AD21

F10

AD22

E9

AD23

D9

AD24

B9

AD25

A8

AD26

A6

AD27

C7

AD28

B6

AD29

E6

AD30

D6

AD31

Interrupt I/F

A3

PIRQA#

B4

PIRQB#

C5

PIRQC#

B5

PIRQD#

AE5

RSVD[1]

AD5

RSVD[2]

AG4

RSVD[3]

AH4

RSVD[4]

AD9

RSVD[5]

ICH7_BGA652~D

PCI

REQ4# / GPIO22
GNT4# / GPIO48

GPIO1 / REQ5#

GPIO17 / GNT5#

GPIO2 / PIRQE#
GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#

MISC

MCH_SYNC#

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#
STOP#
TRDY#

FRAME#

PLTRST#

PCICLK

PME#

RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]

<7/20>Add option resistor for poor LAN performance.

PCI_REQ0#

D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8

B15
C12
D12
C15

A7
E10
B18
A12
C9
E11
B10
F15
F14
F16

C26
A9
B19

G8
F7
F8
G7

AE9
AG8
AH8
F21
AH20

PCI_GNT0#
PCI_REQ1#
PCI_GNT1#
PCI_REQ2#

PCI_REQ3#
PCI_REQ4#
PCI_REQ5#

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PCI_PLTRST#
CLK_PCI_ICH
PCI_PME#

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_REQ0# <23>
PCI_GNT0# <23>
PCI_REQ1# <23>
PCI_GNT1# <23>

PCI_CBE#0 <23>
PCI_CBE#1 <23>
PCI_CBE#2 <23>
PCI_CBE#3 <23>

PCI_IRDY# <23>
PCI_PAR <23>

PCI_DEVSEL# <23>
PCI_PERR# <23>

PCI_SERR# <23>
PCI_STOP# <23>
PCI_TRDY# <23>
PCI_FRAME# <23>

CLK_PCI_ICH <15>
PCI_PME# <23,31>

PCI_PIRQE# <23>

MCH_ICH_SYNC# <7>

PCI_PCIRST#

PCI_PLTRST#

+3VS

5

U10

1

P

B

Y

2

A

G

TC7SH08FU_SSOP5@
R186
0_0402_5%

R185
0_0402_5%

3

12

+3VS

5

U11

1

P

B

Y

2

A

G

TC7SH08FU_SSOP5@

3

12

Place closely pin A9

CLK_PCI_ICH

R176

10_0402_5% @

1 2
1

C415

8.2P_0402_50V@

2

4

4

PCI_RST#

PLT_RST#

PCI_RST# <23,29,31>

Delete VGA_RST#

PLT_RST# <7,22,24>

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

ICH7-M(1/4)

LA-3342P

18 40Thursday, July 27, 2006

1

0.1

of

5

C370

18P_0402_50V8J

32.768KHZ_12.5P_1TJS125BJ4A421P

C356

18P_0402_50V8J

D D

0.1U_0402_16V4Z

C C

+RTCVCC

12

R516
1M_0402_5%

SM_INTRUDER#

+RTCVCC

12

R519
332K_0402_1%

B B

A A

ICH_INTVRMEN

47K_0402_5%

EC_RTCRESET<31>

+RTCVCC

C828

@

R608

@

R517
20K_0402_5%

CLRP1

SHORT PADS

1U_0603_10V4Z

1 2

EC_RTCRESET

+3VS

PSATA_ITX_DRX_N0<22>

PSATA_ITX_DRX_P0<22>

1 2

1 2

C707

1 2

Q52

2N7002_SOT23@

S

G

12

D

13

2

4

12

Y1

2

NC

3

OUT

NC

12

R1264.7K_0402_5%

12

R1258.2K_0402_5%

12

PSATA_ITX_DRX_N0

PSATA_ITX_DRX_P0

ICH_RTCX1

1

IN

4

ICH_RTCX2

ACZ_BITCLK<25>

ACZ_SYNC<25>

ACZ_RST#<25,31>

ACZ_SDIN0<25>

ACZ_SDOUT<25>

IDE_LED#<30>

PSATA_IRX_DTX_N0_C<22>
PSATA_IRX_DTX_P0_C<22>

CLK_PCIE_SATA#<15>
CLK_PCIE_SATA<15>

PD_IORDY
PD_IRQ

1 2

C353 3900P_0402_50V7K

1 2

C351 3900P_0402_50V7K

close ICH7

12

R144

10M_0402_5%

Delete INTEL LAN

C381 10P_0402_25V8K@

33_0402_5%

IDE_LED#

PD_IORDY<22>

PD_IRQ<22>

PD_DACK#<22>

PD_IOW#<22>
PD_IOR#<22>

PSATA_ITX_DRX_N0_C

PSATA_ITX_DRX_P0_C

12

1 2

ACZ_BITCLK
ACZ_SYNC

R155

1 2

ACZ_SDIN0

ACZ_SDOUT

PSATA_IRX_DTX_N0_C
PSATA_IRX_DTX_P0_C
PSATA_ITX_DRX_N0_C
PSATA_ITX_DRX_P0_C

CLK_PCIE_SATA#
CLK_PCIE_SATA

R127

1 2

24.9_0402_1%

ICH_RTCRST#
ICH_INTVRMEN

SM_INTRUDER#

R150

10_0402_5%@

ACZRST#

PD_IORDY
PD_IRQ
PD_DACK#
PD_IOW#
PD_IOR#

AF18

AG2

AG6

AH10
AG10

AG16
AH16
AF16
AH15
AF15

AB1
AB2

AA3

W4

Y5

W1

Y1
Y2

W3

V3
U3
U5

V4

T5
U7

V6

V7

U1
R6

R5

T2

T3

T1

T4

AF3
AE3

AH2
AF7

AE7
AH6
AF1

AE1

3

U6A

RTXC1
RTCX2

RTCRST#
INTVRMEN

INTRUDER#

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

LAN_CLK
LAN_RSTSYNC
LAN_RXD0

LAN_RXD1
LAN_RXD2

LAN_TXD0
LAN_TXD1
LAN_TXD2

ACZ_BCLK
ACZ_SYNC

ACZ_RST#
ACZ_SDIN0

ACZ_SDIN1
ACZ_SDIN2

ACZ_SDOUT

SATALED#

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA_CLKN
SATA_CLKP

SATARBIASN
SATARBIASP

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

ICH7_BGA652~D

RTC

LAD0
LAD1
LAD2
LAD3

LDRQ0#

LPCCPU

LDRQ1# / GPIO23

LFRAME#

LAN

A20GATE

A20M#

CPUSLP#

TP1 / DPRSTP#

TP2 / DPSLP#

FERR#

GPIO49 / CPUPWRGD

IGNNE#

INIT3_3V#

INIT#

INTR

AC-97/AZALIA

RCIN#

SMI#

STPCLK#

THERMTRIP#

DCS1#
DCS3#

SATA

DD10
DD11
DD12
DD13

IDE

DD14
DD15

DDREQ

+RTCVCC

2

1

AA6
AB5
AC4
Y6

AC3
AA5

AB3

AE22
AH28

AG27
AF24

AH25
AG26
AG24
AG22

AG21
AF22
AF25

AG23
AF23

AH24

NMI

AH22
AF26

AH17

DA0

AE17

DA1

AF17

DA2

AE16
AD16

AB15

DD0

AE14

DD1

AG13

DD2

AF13

DD3

AD14

DD4

AC13

DD5

AD12

DD6

AC12

DD7

AE12

DD8

AF12

DD9

AB13
AC14
AF14
AH13
AH14
AC15

AE15

DAN202U_SC70

C679
1U_0603_10V4Z

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_DRQ0#

LPC_FRAME#

GATEA20
H_A20M#

H_CPUSLP_R#
DPRSLP#

H_DPSLP#
H_FERR#
H_PWRGOOD
H_IGNNE#
H_INIT#

H_INTR

KB_RST#
H_SMI#

H_NMI
H_STPCLK#
THRMTRIP_ICH#

PD_A0
PD_A1
PD_A2

PD_CS#1
PD_CS#3

PD_D0
PD_D1
PD_D2
PD_D3
PD_D4
PD_D5
PD_D6
PD_D7
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

PD_DREQ

PD_D[0..15]

D26

1

LDO3

2

R488

1 2

3

1K_0402_5%

LPC_AD[0..3] <29,31>

LPC_DRQ#0 <29>

LPC_FRAME# <29,31>

R122 10K_0402_5%

12

GATEA20 <31>
H_A20M# <4>

T23

PAD

R121 0_0402_5%

12

H_DPSLP# <4>

12

H_FERR# <4>
H_PWRGOOD <4>
H_IGNNE# <4>
H_INIT# <4>

H_INTR <4>

R508 10K_0402_5%

12

KB_RST# <31>
H_SMI# <4>

H_NMI <4>
H_STPCLK# <4>

R120

1 2

24.9_0402_1%

PD_A0 <22>
PD_A1 <22>
PD_A2 <22>

PD_CS#1 <22>
PD_CS#3 <22>

PD_DREQ <22>

PD_D[0..15] <22>

BATT1.1

W=20mils

2

+3VS

1

H_DPRSTP# <4,39>

+VCCP

+3VS

JP23

+

56_0402_5%
R114

+-

SUYIN_060003FA002TX00NL~D

+VCCP

-

12

R119
56_0402_5%

2

1

H_THERMTRIP# <4,7>

BATT1

CR2032 RTC BATTERY

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

ICH7-M(2/4)

LA-3342P

1

0.1

of

19 40Thursday, July 27, 2006

5

+3VS

10K_0402_5%

1 2

8.2K_0402_5%

1 2

10K_0402_5%

1 2

150_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

1K_0402_5%

1 2

8.2K_0402_5%
10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

SIRQ

PCI_CLKRUN#

LINKALERT#

ITP_DBRESET#

OCP#

SPI_MISO

SPI_CS#

BT_DET#

ICH_PCIE_W AKE#

ICH_LOW_BAT#

12

WL_ON

SPI_MOSI

PCBEEP

+3VALW

<7/20>Add resistor conect
LAN chip clock LAN pin for
poor LAN performance.

R123

R124

D D

+3VALW

R173

R221

R219

R156

R159

R223

R182

R209

C C

R153

R578

R590

4

R207 10K_0402_5%
R208

PCI_LANCLKRUN#<23>

+3VALW

12

12

R222

R220

SB_SPKR<25>

H_STP_PCI#<15>

EC_SMI#<31>

2.2K_0402_5%

R172

1 2

8.2K_0402_5%

OCP#<4>

R957 0_0402_5%@

1 2

SIRQ<29,31>

VGATE<31,39>

2.2K_0402_5%

ICH_SMBCLK<15,24>

ICH_SMBDATA<15,24>

12
12

10K_0402_5%

+3VALW

ITP_DBRESET#<4>

PM_BMBUSY#<7>

H_STP_CPU#<15>

Remove EC_Flash# (GPIO28)

PCI_LANCLKRUN#

ICH_PCIE_W AKE#<24>

EC_THERM#<31>

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#

ICH_RI#
SB_SPKR

SUS_STAT#
ITP_DBRESET#

PM_BMBUSY#
OCP#
H_STP_PCI#

H_STP_CPU#

PCI_CLKRUN#

ICH_PCIE_W AKE#

SIRQ
EC_THERM#

VGATE

EC_SMI#

3

U6C

C22

SMBCLK

B22

SMBDATA

A26

LINKALERT#

B25

SMLINK0

A25

SMLINK1

A28

RI#

A19

SPKR

A27

SUS_STAT#

A22

SYS_RST#

AB18

GPIO0 / BM_BUSY#

B23

GPIO11 / SMBALERT#

AC20

GPIO18 / STPPCI#

AF21

GPIO20 / STPCPU#

A21

GPIO26

B21

GPIO27

E23

GPIO28

AG18

GPIO32 / CLKRUN#

AC19

GPIO33 / AZ_DOCK_EN#

U2

GPIO34 / AZ_DOCK_RST#

F20

WAKE#

AH21

SERIRQ

AF20

THRM#

AD22

VRMPWRGD

AC21

GPIO6

AC18

GPIO7

E21

GPIO8

ICH7_BGA652~D

GPIO21 / SATA0GP

SMB

GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP

SATA

GPIO

SYS

Clocks

GPIO

GPIO16 / DPRSLPVR

TP0 / BATLOW#

POWER MGT

GPIO

GPIO35 / SATAREQ#

Need update symbol

CLK14
CLK48

SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

PWROK

PWRBTN#

LAN_RST#

RSMRST#

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25

GPIO38
GPIO39

AF19
AH18
AH19
AE19

AC1
B2

C20
B24

D23
F22

AA4
AC22
C21
C23
C19
Y4

E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20

2

1 2

100_0402_5%

CLK_14M_ICH
CLK_48M_ICH

ICH_SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

ICH_POK
DPRSLPVR
ICH_LOW_BAT#
PWRBTN_OUT#
LAN_RST#
EC_RSMRST#

R514 10K_0402_5%

1 2

EC_SCI#
BT_DET#
PCBEEP
LID_OUT#

CPUSB#
WL_ON
BT_ON#

R507

CLK_14M_ICH <15>
CLK_48M_ICH <15>

T28 PADT25PAD

SLP_S3# <31>
SLP_S4# <31>
SLP_S5# <31>

ICH_POK <7,31>

1 2

DPRSLPVR <7,39>

PWRBTN_OUT# <31>

LAN_RST# <31>

EC_RSMRST# <31>

EC_SCI# <31>
BT_DET# <28>
PCBEEP <27>
LID_OUT# <31>

CPUSB# <31>
WL_ON <24>
BT_ON# <28>

1

Place closely pin B2 Place closely pin AC1

CLK_14M_ICH

12

R136

10_0402_5%@

1

C350

4.7P_0402_50V8C@

2

12

R509

100K_0402_5%@

12

R539

1

C740

2

R511
10K_0402_5%

CLK_48M_ICH

10_0402_5%@

4.7P_0402_50V8C@

DPRSLPVR

U6D

F26

PERn1

Issued Date

F25

PERp1

E28

PETn1

E27

PETp1

H26

PERn2

H25

PERp2

G28

PETn2

G27

PETp2

K26

PERn3

K25

PERp3

J28

PETn3

J27

PETp3

M26

PERn4

M25

PERp4

L28

PETn4

L27

PETp4

P26

PERn5

P25

PERp5

N28

PETn5

N27

PETp5

T25

PERn6

T24

PERp6

R28

PETn6

R27

PETp6

R2

SPI_CLK

P6

SPI_CS#

P1

SPI_ARB

P5

SPI_MOSI

P2

SPI_MISO

D3

OC0#

C4

OC1#

D5

OC2#

D4

OC3#

E5

OC4#

C3

OC5# / GPIO29

A2

OC6# / GPIO30

B3

OC7# / GPIO31

ICH7_BGA652~D

3

2005/03/10 2006/03/10

Delete 17" New Card PCIE traces

<6/20> Remove New Card trace

PCIE_RXN3<24>

To mini PCIE Card

B B

USB_OC#7
USB_OC#1
USB_OC#2
USB_OC#4

USB_OC#6

A A

5

PCIE_RXP3<24>
PCIE_TXN3<24>

PCIE_TXP3<24>

RP20

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

R175
10K_0402_5%

1 2

+3VALW

4

USB_OC#0<28>

USB_OC#3<28>
USB_OC#4<29>
USB_OC#5<29>

PCIE_RXN3
PCIE_RXP3
PCIE_C_TXN3

C3890.1U_0402_16V4Z

12

PCIE_C_TXP3

C3870.1U_0402_16V4Z

12

SPI_CS#

SPI_MOSI
SPI_MISO

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7

Security Classification

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PCI-EXPRESS

SPI

USB

DMI0RXN
DMI0RXP
DMI0TXN

DMI0TXP

DMI1RXN
DMI1RXP
DMI1TXN

DMI1TXP

DMI2RXN
DMI2RXP
DMI2TXN

DMI2TXP

DMI3RXN
DMI3RXP
DMI3TXN

DMI3TXP

DMI_CLKN
DMI_CLKP

DIRECT MEDIA INTERFACE

DMI_ZCOMP

DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

USBRBIAS#

USBRBIAS

Compal Secret Data

DMI_RXN0

V26

DMI_RXP0

V25

DMI_TXN0

U28

DMI_TXP0

U27

DMI_RXN1

Y26

DMI_RXP1

Y25

DMI_TXN1

W28

DMI_TXP1

W27

DMI_RXN2

AB26

DMI_RXP2

AB25

DMI_TXN2

AA28

DMI_TXP2

AA27

DMI_RXN3

AD25

DMI_RXP3

AD24

DMI_TXN3

AC28

DMI_TXP3

AC27

CLK_PCIE_ICH#

AE28

CLK_PCIE_ICH

AE27
C25

DMI_IRCOMP

D25

USB20_N0

F1

USB20_P0

F2
G4
G3

<6/12> Remove do cking USB traces

H1
H2

USB20_N3

J4

USB20_P3

J3

USB20_N4

K1

USB20_P4

K2

USB20_N5

L4

USB20_P5

L5

USB20_N6

M1

USB20_P6

M2
N4
N3

<6/12> Remove New Card

USBRBIAS

D2
D1

R166 24.9_0402_1%

1 2

R165 22.6_0402_1%

1 2

Within 500 mils

Deciphered Date

2

DMI_RXN0 <7>
DMI_RXP0 <7>
DMI_TXN0 <7>
DMI_TXP0 <7>

DMI_RXN1 <7>
DMI_RXP1 <7>
DMI_TXN1 <7>
DMI_TXP1 <7>

DMI_RXN2 <7>
DMI_RXP2 <7>
DMI_TXN2 <7>
DMI_TXP2 <7>

DMI_RXN3 <7>
DMI_RXP3 <7>
DMI_TXN3 <7>
DMI_TXP3 <7>

CLK_PCIE_ICH# <15>
CLK_PCIE_ICH <15>

Within 500 mils

USB20_N0 <28>
USB20_P0 <28>

USB20_N3 <28>
USB20_P3 <28>
USB20_N4 <29>
USB20_P4 <29>
USB20_N5 <29>
USB20_P5 <29>
USB20_N6 <28>
USB20_P6 <28>

+1.5VS

Left side USB port

Left side USB port
Audio Board USB port
Audio Board USB port
BT module

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

ICH7-M(3/4)

LA-3342P

1

of

20 40Thursday, July 27, 2006

1.0

5

4

3

2

1

ICH_V5REF_RUN

+1.5VS

D D

100_0402_5%

10_0402_5%

C C

B B

A A

R518

R164

12

12

+3VS+5VS

21

1

2

+3VALW+5VALW

21

1

2

D18
CH751H-40_SC76

ICH_V5REF_RUN

C697

0.1U_0402_16V4Z

D8
CH751H-40_SC76

ICH_V5REF_SUS

C732

0.1U_0402_16V4Z

+1.5VS

1

C729

0.1U_0402_16V4Z

2

Place closely pin AG28 within 100mlis.

+1.5VS_DMIPLLR

1 2

0.5_0805_1%

+1.5VS

R109

2

C800

1

+3VALW

0.1U_0402_16V4Z

10U_1206_16V4Z

C734

1 2

0_0805_5%

1

C698

2

1

2

R129

+3VS

0.1U_0402_16V4Z

+1.5VS

0.1U_0402_16V4Z

C349

1

C693

2

+1.5VS_DMIPLL

1

C352

2

22U_0805_10V4Z

1

2

C742

1

+

C714

2

220U_D2_4VM

0.1U_0402_16V4Z

Place closely pin
D28,T28,AD28.

1

2

0.01U_0402_16V7K

Place closely pin AG5.

C688

0.1U_0402_16V4Z

Place closely pin AG9.

1

2

0.1U_0402_16V4Z

1

C715

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.5VS

C691

0.1U_0402_16V4Z

+1.5VS

C696

1U_0603_10V4Z

T30 PAD
T31 PAD

+3VALW

ICH_V5REF_SUS

1

C739

2

+3VS

1

C743

2

+1.5VS_DMIPLL

1

2

1

2

ICH_AA2
ICH_Y7

G10

AD17

F6

AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28

D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23

J22

J23
K22
K23

L22

L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
U22
U23
V22
V23

W22
W23

Y22
Y23

B27

AG28

AB7
AC6
AC7
AD6
AE6
AF5
AF6

AG5

AH5
AD2

AH11
AB10

AB9

AC10
AD10
AE10
AF10

AF9

AG9

AH9

E3

C1

AA2

Y7
V5

V1
W2
W7

1

C375

0.1U_0402_16V4Z

2

U6F

V5REF[1]
V5REF[2]
V5REF_Sus
Vcc1_5_B[1]

Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]

Vcc3_3[1]
VccDMIPLL
Vcc1_5_A[1]

Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]

VccSATAPLL
Vcc3_3[2]
Vcc1_5_A[10]

Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]

VccSus3_3[19]
VccUSBPLL
VccSus1_05/VccLAN1_05[1]

VccSus1_05/VccLAN1_05[2]
VccSus3_3/VccLAN3_3[1]

VccSus3_3/VccLAN3_3[2]
VccSus3_3/VccLAN3_3[3]
VccSus3_3/VccLAN3_3[4]

ICH7_BGA652~D

Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]

Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]

Vcc3_3 / VccHDA

VccSus3_3/VccSusHDA

V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]

Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]

Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]

Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]

VccRTC
VccSus3_3[1]
VccSus3_3[2]

VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]

VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]

VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]

Vcc1_5_A[19]
Vcc1_5_A[20]

Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]

Vcc1_5_A[24]
Vcc1_5_A[25]

VccSus1_05[1]
VccSus1_05[2]

VccSus1_05[3]

Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]

L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

U6
R7
AE23

AE26
AH26

AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19

A5
B13
B16
B7
C10
D15
F9
G11
G12
G16

W5
P7
A24

C24
D19
D22
G19

K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

AB17
AC17

T7
F17
G17

AB8
AC8

K7
C28

G20
A1

H6
H7
J6
J7

+VCCP

0.1U_0402_16V4Z

1

C711

C721

2

1U_0603_10V4Z

1

C731

2

0.1U_0402_16V4Z

1

C741

0.1U_0402_16V4Z

2

1

C723

0.1U_0402_16V4Z

2

+1.5VS

1 2

C699 0.1U_0402_16V4Z

ICH_K7
ICH_C28

ICH_G20

+1.5VS

1

C727

0.1U_0402_16V4Z

2

1

2

+3VALW

+3VS

1

C700

0.1U_0402_16V4Z

2

1

1

C737

2

2

0.1U_0402_16V4Z

1

C738

0.1U_0402_16V4Z

2

1

C720

0.1U_0402_16V4Z

2

1

+

C708
330U_V_2.5VK_R9

2

+3VS

C730

0.1U_0402_16V4Z

+3VALW

+3VALW

T32PAD
T26PAD

T29PAD

+VCCP

0.1U_0402_16V4Z

0.1U_0402_16V4Z

22U_0805_10V4Z

C695

1 2

1 2

C694

1 2

C690

U6E

A4

VSS[0]

A23

VSS[1]

B1

VSS[2]

B8

VSS[3]

B11

VSS[4]

B14

VSS[5]

B17

VSS[6]

B20

VSS[7]

B26

VSS[8]

B28

VSS[9]

C2

VSS[10]

C6

VSS[11]

C27

VSS[12]

D10

VSS[13]

D13

VSS[14]

D18

VSS[15]

D21

VSS[16]

D24

VSS[17]

E1

VSS[18]

E2

VSS[19]

E4

VSS[21]

E8

VSS[22]

+3VS

1

C701

0.1U_0402_16V4Z

2

+RTCVCC

1

1

C712

C709

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

E15

VSS[23]

F3

VSS[24]

F4

VSS[25]

F5

VSS[26]

F12

VSS[27]

F27

VSS[28]

F28

VSS[29]

G1

VSS[30]

G2

VSS[31]

G5

VSS[32]

G6

VSS[33]

G9

VSS[34]

G14

VSS[35]

G18

VSS[36]

G21

VSS[37]

G24

VSS[38]

G25

VSS[39]

G26

VSS[40]

H3

VSS[41]

H4

VSS[42]

H5

VSS[43]

H24

VSS[44]

H27

VSS[45]

H28

VSS[46]

J1

VSS[47]

J2

VSS[48]

J5

VSS[49]

J24

VSS[50]

J25

VSS[51]

J26

VSS[52]

K24

VSS[53]

K27

VSS[54]

K28

VSS[55]

L13

VSS[56]

L15

VSS[57]

L24

VSS[58]

L25

VSS[59]

L26

VSS[60]

M3

VSS[61]

M4

VSS[62]

M5

VSS[63]

M12

VSS[64]

M13

VSS[65]

M14

VSS[66]

M15

VSS[67]

M16

VSS[68]

M17

VSS[69]

M24

VSS[70]

M27

VSS[71]

M28

VSS[72]

N1

VSS[73]

N2

VSS[74]

N5

VSS[75]

N6

VSS[76]

N11

VSS[77]

N12

VSS[78]

N13

VSS[79]

N14

VSS[80]

N15

VSS[81]

N16

VSS[82]

N17

VSS[83]

N18

VSS[84]

N24

VSS[85]

N25

VSS[86]

N26

VSS[87]

P3

VSS[88]

P4

VSS[89]

P12

VSS[90]

P13

VSS[91]

P14

VSS[92]

P15

VSS[93]

P16

VSS[94]

P17

VSS[95]

P24

VSS[96]

P27

VSS[97]

ICH7_BGA652~D

VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]

P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

ICH7-M(4/4)

LA-3342P

1

0.1

of

21 40Thursday, July 27, 2006

5

4

3

2

1

<6/23> Not populated on PV2

D D

C C

1

+

C439

C831

2

@

330U_V_2.5VK_R9

+5VS +3VS

0.1U_0402_16V4Z

1

1

C453

2

2

22U_1206_6.3V6M

1000P_0402_50V7K

Pleace near HD CONN

PSATA_IRX_DTX_N0_C<19>

PSATA_IRX_DTX_P0_C<19>

3900P_0402_50V7K

1

1

C449

2

2

1U_0603_10V4Z

C505

C503

3900P_0402_50V7K

C445

1

C457

2

0.1U_0402_16V4Z

PSATA_ITX_DRX_P0<19>
PSATA_ITX_DRX_N0<19>

12

12

close SATA connector

C434

+3VS

+5VS

1

C468

2

22U_1206_6.3V6M

PSATA_ITX_DRX_P0
PSATA_ITX_DRX_N0

PSATA_IRX_DTX_N0

PSATA_IRX_DTX_P0

0.1U_0402_16V4Z

1

1

2

1000P_0402_50V7K

C464

2

Pleace near HD CONN

1
2
3
4
5
6
7

8

9
10
11
12
13
14
15
16
17
18
19
20
21
22

SUYIN_127059FR022S305ZL

1

C447

2

1U_0603_10V4Z

JP33

GND
A+
A­GND
B­B+
GND

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

1

1

+

C832

C460

@

2

2

330U_V_2.5VK_R9

0.1U_0402_16V4Z

<6/23> Not populated on PV2

Main HDD

Need update symbol

Main SATA +5V Default

PD_D[0..15]

PD_D[0..15] <19>

Delete CD traces (JP25 pin1,2 and3)

B B

PLT_RST#<7,18,24>

A A

PLT_RST#

PD_IOW#<19>

PD_IORDY<19>

PD_IRQ<19>
PD_A1<19>
PD_A0<19>

PD_CS#1<19>

ACT_LED#<30>

R217 33_0402_5%

12

PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0

PD_IOW#
PD_IORDY
PD_IRQ
PD_A1
PD_A0
PD_CS#1
ACT_LED#

+5VS

PRI_CSEL

R147
470_0402_5%

1 2

JP25

1

1

3

3

5

5

7

7

9

9
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
GND51GND

53

GND

SUYIN_800059MR050S119ZL

GND

2

2

4

4

6

6

8

8

10

10

12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54

PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15
PD_DREQ
PD_IOR#

PD_DACK#
PDIAG#

PD_A2
PD_CS#3

12

C380

0.1U_0402_16V4Z

PD_DREQ <19>
PD_IOR# <19>

PD_DACK# <19>

1 2

PD_A2 <19>
PD_CS#3 <19>

+5VS

R157
100K_0402_5%

+5VS

+5VS

1

2

C371
1U_0603_10V4Z

1

C357

2

10U_0805_10V4Z

1

+

C835

@

330U_V_2.5VK_R9

2

<6/23> Not populated on PV2

CD-ROM Connector

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

HDD & CDROM

LA-3342P

1

0.1

of

22 40Thursday, July 27, 2006

5

PCI_GNT1#<18>
PCI_GNT0#<18>

PCI_REQ0#<18>
PCI_REQ1#<18>

D D

PCI_AD[0..31]<18>

C C

PCI_CBE#0<18>
PCI_CBE#1<18>
PCI_CBE#2<18>
PCI_CBE#3<18>

PCI_AD24

1 2

R916 100_0402_5%

PCI_PAR<18>

PCI_FRAME#<18>

PCI_IRDY#<18>
PCI_TRDY#<18>

PCI_DEVSEL#<18>

PCI_STOP#<18>
PCI_PERR#<18>

PCI_SERR#<18>

B B

A A

PCI_LANCLKRUN#<20>

PCI_PME#<18,31>

CLK_PCI_LAN<15>

CLK_PCI_LAN

12

R905

@

10_0402_5%

1

C914

@

10P_0402_50V8K

2

PCI_RST#<18,29,31>

PCI_LANCLKRUN#

1 2

5

PCI_AD[0..31]

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

LAN_IDSEL

PCI_PAR
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#

PCI_PERR#
PCI_SERR#

PCI_REQ#_LAN
PCI_GNT#_LAN

PCI_PIRQ#_LAN
PCI_PME#
PCI_RST#
CLK_PCI_LAN

R915
10K_0402_5%

PCI_PIRQA#<18>
PCI_PIRQE#<18>

U41

104

AD0

103

AD1

102

AD2

98

AD3

97

AD4

96

AD5

95

AD6

93

AD7

90

AD8

89

AD9

87

AD10

86

AD11

85

AD12

83

AD13

82

AD14

79

AD15

59

AD16

58

AD17

57

AD18

55

AD19

53

AD20

50

AD21

49

AD22

47

AD23

43

AD24

42

AD25

40

AD26

39

AD27

37

AD28

36

AD29

34

AD30

33

AD31

92

C/BE#0

77

C/BE#1

60

C/BE#2

44

C/BE#3

46

IDSEL

76

PAR

61

FRAME#

63

IRDY#

67

TRDY#

68

DEVSEL#

69

STOP#

70

PERR#

75

SERR#

30

REQ#

29

GNT#

25

INTA#

31

PME#

27

RST#

28

CLK

65

CLKRUN#

4

GND/VSS

17

GND/VSS

128

GND/VSS

21

GND/VSSPST

38

GND/VSSPST

51

GND/VSSPST

66

GND/VSSPST

81

GND/VSSPST

91

GND/VSSPST

101

GND/VSSPST

119

GND/VSSPST

35

GND

52

GND

80

GND

100

GND

RTL8100CL_LQFP128

PCI_GNT1#
PCI_GNT0#

PCI_REQ0#
PCI_REQ1#

PCI_PIRQA#
PCI_PIRQE#

TXD+/MDI0+

TXD-/MDI0-

RXIN+/MDI1+

RXIN-/MDI1-

NC/SMBCLK

NC/SMBDATA

NC/M66EN
NC/AVDDH

PCI I/F

NC/HSDAC+

LAN I/F

RTT3/CRTL18

AVDD33/AVDDL
AVDD33/AVDDL
AVDD33/AVDDL

NC/AVDDL

VDD25/VDD18
VDD25/VDD18
VDD25/VDD18
VDD25/VDD18

NC/VDD18
NC/VDD18
NC/VDD18
NC/VDD18
NC/VDD18

Power

AVDD25/HSDAC-

EEDO

AUX/EEDI

EESK
EECS

LED0
LED1
LED2

NC/LED3

NC/MDI2+

NC/MDI2-

NC/MDI3+

NC/MDI3-

LWAKE

ISOLATE#

RTSET

NC/HV

NC/HG
NC/LG2
NC/LV2

NC/VSS
NC/VSS

NC/GND
NC/GND
NC/GND
NC/GND
NC/GND
NC/GND

CTRL25

VDD33

VDD33

VDD33

VDD33

VDD33

VDD33

VDD33

4

R956 0_0402_5%

1 2

R953 0_0402_5%@

1 2

R952 0_0402_5%@

1 2

R955 0_0402_5%

1 2

R951 0_0402_5%

1 2

R954 0_0402_5%@

1 2

LAN_EEDO

108

LAN_EEDI

109

LAN_EECLK

111

LAN_EECS

106

ACTIVITY#

117

LINK_100#

115
114
113

TXD+/MDI0+

1

TXD-/MDI0-

2

RXIN+/MDI1+

5

RXIN-/MDI1-

6
14

15
18
19

LAN_X1

121

X1
X2

LAN_X2

122

R900 1K_0402_5%

105

R901 15K_0402_5%

23

R902 5.6K_0603_1%

127
72

R313 5.6K for 8100CL

74
88
10

120
11

123
124
126

9
13

22
48
62
73
112
118

8
125
26

41
56
71
84
94
107

3
7
20
16

32
54
78
99

24
45
64
110
116

V_12P

12

1

C913

0.1U_0402_16V4Z

2

4

1 2
1 2
1 2

CTRL25

1

C901

0.1U_0402_16V4Z

2

1

C906

0.1U_0402_16V4Z

2

1

C909

0.1U_0402_16V4Z

2

PCI_GNT#_LAN

PCI_REQ#_LAN

PCI_PIRQ#_LAN

R912

3.6K_0402_5%

1 2

+3VALW

1

R904
0_0402_5%

1 2

+3VALW

U90

4

DO

GND

3

DI

NC

2

SK

NC

1

CS

VCC

AT93C46-10SI-2.7_SO8

Y6
25MHZ_20P_1BG25000CK1A

1 2

+3VS

C920 1U_0603_10V4Z

1 2

Q900
2SB1188_SC62

2 3

C919 4.7U_0805_10V4Z

1 2

1

C902

0.1U_0402_16V4Z

2

1

C907

0.1U_0402_16V4Z

2

1

C910

0.1U_0402_16V4Z

2

V2.5_LAN

5

1
6
7
8

2

C915 27P_0402_50V8J

1 2

C916 27P_0402_50V8J

1 2

3

C918 0.1U_0402_16V4Z

+3VALW

C917

0.1U_0402_16V4Z

1 2

TXD+/MDI0+
TXD-/MDI0-

RXIN+/MDI1+

RXIN-/MDI1-

U12

TD-8TX-

7

TD+

6

CT

3

CT

2

RD-

1

RD+

NS0013_16P

TX+

RX­RX+

CT

CT

2

ACTIVITY#

MDO0+

9

MDO0-

10
11

MCT1

14

MDO1+

15

MDO1-

16

close to chip

TXD+/MDI0+

V2.5_LAN

+3VALW

1

C903

0.1U_0402_16V4Z

2

1

C908

0.1U_0402_16V4Z

2

1

C911

0.1U_0402_16V4Z

2

1

C904

0.1U_0402_16V4Z

2

+3VALW

1

C912

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C905

0.1U_0402_16V4Z

2

V2.5_LAN

2005/03/01 2005/04/06

Compal Secret Data

Deciphered Date

TXD-/MDI0-

close to magnetic

RXIN+/MDI1+

RXIN-/MDI1-

2

LINK_100#

1

R36
300_0603_5%

1 2

+3VALW

MDO1-

MDO1+
MDO0-

R43
300_0603_5%

1 2

+3VALW

R906

49.9_0402_1%

R907

49.9_0402_1%

R908

49.9_0402_1%

R909

49.9_0402_1%

MDO0+

R910
75_0402_5%

R911
75_0402_5%

C925

0.01U_0402_16V7K

12
12

C926

0.01U_0402_16V7K

12
12

Title

Size Document Number Rev

Custom

Date: Sheet

RJ45_GNDMCT0

12

12

12

12

JP19

12

Amber LED-

11

Amber LED+

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

10

Green LED-

9

Green LED+

SUYIN_100073FR012S100ZL

C486

12

1000P_1206_2KV7K

LAN-8100CL
LA-3342P

SHLD4
SHLD3

SHLD2
SHLD1

1

16
15

14
13

1.0

of

23 40Thursday, July 27, 2006

A

B

C

D

E

Mini-Express Card(Slot 1-WLAN)

C608

12

0.1U_0402_16V4Z

R600 100_0402_5%

1 2

JP18

112
334
556
778
9910
111112
131314
151516

171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
535354
555556

MOLEX_67910-0002

2
4
6
8
10
12
14
16

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56

C797

0.1U_0402_16V4Z@

PLT_RST#

+3VALW

ICH_SMBCLK

ICH_SMBDATA

LED_WLAN_OUT#

1 2

C78

WL_ON <20>
PLT_RST# <7,18,22>

ICH_SMBCLK <15,20>
ICH_SMBDATA <15,20>

D2

1

BAS16_SOT23

1

2

0.1U_0402_16V4Z

2

3

+3VS
+1.5VS

1

C167

2

0.1U_0402_16V4Z

LED_WLANOUT#

DTA114YKA_SC59

WIRELESS_LED_BT<28>

10K

2

Q48

R593

100K_0402_5%

100K_0402_5%

+3VS

47K

1 3

12

R594

2

G

Q49

2N7002_SOT23

12

2N7002_SOT23

WLED#

13

D

S

13

D

2

G

Q50

S

12

WL_LED# <16,29>

R592

470_0402_5%

1 1

2 2

ICH_PCIE_WAKE#<20>

WL_PRIORITY<28>

BT_PRIORITY<28>

CLKREQA#<15>

CLK_PCIE_MCARD#<15>
CLK_PCIE_MCARD<15>

PCIE_RXN3<20>
PCIE_RXP3<20>

PCIE_TXN3<20>
PCIE_TXP3<20>

CLK_PCIE_MCARD#
CLK_PCIE_MCARD

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Mini Card

LA-3342P

E

0.1

of

24 40Thursday, July 27, 2006

A

B

C

D

E

+3VAMP_CODEC

W=40Mil

MONO_INR <27>

1

2

+5VS

1

C526

C504

2

10U_0805_10V4Z

0.1U_0402_16V4Z

For Layout:

Place decoupling caps near the
power pins of SmartAMC
device.

U27

1

12

9

DVDD1

DVDD3
RST#
DIBN

DIBP
PWRCLKP
PWRCLKN

BCLK
SYNC
SDI
SDO

PCBEEP

XTALIN
XTALOUT

VREF_FILT
VREF
VC

DVDD2

DVSS1

DVSS3

DVSS2

2

5

46

R393

0_0402_5%

6

VSUB

11
47

48

3
4

13
10

8
7

43

15
16

23
19
18

1

2

10K_0402_5%

14

VDDCK

VSSCK

17

12

12

R408
10K_0402_1%

R411

3 1

+3VALW

C571

C570

2

0_0402_5%

1 2

R422
560_0402_5%

1 2

R401
0_0805_5%

1 2

2

1

2

1

1

2

0.1U_0402_16V4Z

C548

ACZ_BITCLK<19>

ACZ_SYNC<19>

ACZ_SDIN0<19>
ACZ_SDOUT<19>

1

2

MONO_IN1 MONO_INRMONO_IN

DIB_DATAN<26>
DIB_DATAP<26>

10K_0402_5%

C547

1U_0603_10V4Z

1 1

<6/12> Remove PCM_SPK

MMBT3904_SOT23

2 2

3 3

Q28

150P_0402_50V8J

PWRCLKP<26>
PWRCLKN<26>

150P_0402_50V8J

R409

5.1K_0402_5%

1 2

SB_SPKR <20>

1

2

C560

C566

10U_0805_10V4Z

0.1U_0402_16V4Z

ACZ_RST#<19,31>

R149

1

C549

2

0.1U_0402_16V4Z

C563
1U_0603_10V4Z

1 2

1

1

2

2

C569

0.1U_0402_16V4Z

R418 0_0402_5%
R417 0_0402_5%
R420 0_0402_5%
R419 0_0402_5%

R407 33_0402_5%
R158 33_0402_5%
R421 33_0402_5%
R151 33_0402_5%

12

12

R152
10K_0402_5%

1

C562

2

0.1U_0402_16V4Z

C568

0.1U_0402_16V4Z

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

MONO_INR

+3VDD_CODEC

1

2

C567

0.1U_0402_16V4Z

ACZ_RST#

REF_FILT

VREF
VC

4

12

2

R385

8

C564

0.1U_0402_16V4Z

25

35

AVDD1

AVDD2

MIC_R

MIC_L
MICBIAS_F
MICBIAS_C
MICBIAS_B

CD_L

CD_GND

CD_R

PORT-A_L
PORT-A_R

PORT-B_L
PORT-B_R

PORT-C_L
PORT-C_R

PORT-D_L
PORT-D_R

EAPD

SPDIF_OUT

SENSEA
SENSEB

AVSS1

AVSS2

24

36

CX20551-22_TQFP48

U26

VIN

SENSE or ADJ

DELAY
ERROR7CNOISE
SD

SI9182DH-AD_MSOP8

1

1

2

2

C546

0.1U_0402_16V4Z

MIC_INR

26

MIC_INL

27
20
21
22

28
29

Delete CD traces

30

LINE_OUTL

40

LINE_OUTR

39
38

<6/12> Remove Docking line out

37
34

<6/12> Remove Docking MIC

33
32

31

EAPD

45

SPDIFO

44

SENSEA

41

SENSEB

42

SENSEA

SENSEB

250mA

5

VOUT

6
1
3

GND

0.01U_0402_16V7K

+3VAMP_CODEC

1

2

1U_0603_10V4Z

C559

C539 10U_0805_10V4Z
C540 10U_0805_10V4Z

+CODEC_REFF

SPDIFO <29>

R410

1.5K_0402_5%

1 2

1

C565

2

R404
0_0805_5%

1 2

1 2
1 2

R414

1 2

20K_0402_5%

R405

1 2

5.1K_0402_5%

LINE_OUTL <27>
LINE_OUTR <27>

<6/12> Remov e J A CK_DET from Docking

00

0

NC OFF
NC 0
NC NC

4 4

MIC_DET

PORT-C P ORT-F

0

ON

NC

OFF

1 2

R392

12

47K_0603_1%
R403

27K_0603_1%

2.2K_0402_5%

OFF

ON

+VDDA_CODEC

+VDDA_CODEC

+CODEC_REFF

R386

HP_DET# <27>

MIC_DET <29>

ON
ON

OFF

ON

1

C533
1U_0603_10V4Z

2

12

12

R387

2.2K_0402_5%

PORT-BPORT-AJACK_DET#HP_DET#

OFF

ON

OFF

(3.33V)

1

2

MIC_R <29>
MIC_L <29>

C538

@

0.1U_0402_16V4Z

EQ

Disable
Disable
Disable

Enable

C502

@

0.1U_0402_16V4Z

1 2

C519

@

0_0402_5%

1 2

C516

@

0.1U_0402_16V4Z

1 2

R423
0_1206_5%

1 2

R300

@

0_1206_5%

1 2

EAPD

2

G

GNDAGND

+3VS

R591

100_0402_5%

1 2
13

D

Q47

S

2N7002_SOT23

GNDA <27,29>

MUTE_LED <29>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

AMOM_codec

LA-3342P

E

0.1

of

25 40Thursday, July 27, 2006

MTP28

MC930

2.2U_0805_10V6K

MC926
10P_0402_50V8J

1 2

MFB906

MTP60

1

DIB_P2

DIB_N2DIB_N1

1

Vc_LSD
Vref_LSD

1

1

MC976

2

2

1

CLK

PWR+

MTP62

MTP63

MTP30

1

1

2

1

1

VDD

1

2

AGND_LSD

MU902

26

CLK

7

PWR+

27

DIB_P

28

DIB_N

3

Vc

4

VRef

8

NC1

22

NC2

25

NC3

29

PADDLE

AGND_LSD

0.1U_0402_10V6K
MC928

MTP58

2

AVdd

AGnd

DC_GND

6

15

DGND_LSD AGND_LSD

MTP59

1

VDD

MC978

0.1U_0402_10V6K

1 2

1

DVdd

23

RAC1
TAC1

RAC2
TAC2

TRDC

GPIO1

RBias

DGnd

DGND_LSD

21
20

MTP34

19
18

12
11

EIC

9

RXI

1
5

10

VZ

17

EIO

16

EIF

14

TXO

13

TXF

CX20493-58_QFN28

24

1

MTP36

1

MTP35

MR902
1M_0805_5%

RAC1
TAC1

1

TRDC

1

EIC

0.015U_0603_25V7K
MR910
237K_0805_1%

RXI

1 2

1

RBias

1 2

1

1

EIO

Use 59K_0402_1% for MR954

EIF

TXO

TXF

1 2

1M_0805_5%
MR904

MTP33

MC958

1 2

RXI-1

MTP70

AGND_LSD

MR954
59K_0402_1%
MTP69

MR908

1 2

348K_0805_1%
MTP68

RAC1/RING
TAC1/TIP

12

MR906 6.8M_0805_5%

1

MC918

0.1U_0603_16V7K

2

AGND_LSD

MTP67

1

1

MTP65

1

MTP37

1

MTP38

MC902
MC904

1 2

1

1 2

0.047U_1206_100V7K

1 2
1 2

MTP40

MTP71

MC910

2

B

1

0.033U_1206_100V7K

0.033U_1206_100V7K

1

1

MTP32

C

MQ906

PMBTA42_SOT23

E

3 1

1

MTP64

12

MR938
110_0603_5%

AGND_LSD

MTP39

2

B

TIP_2

1 2

BRIDGE_CCVZ

C

MQ902
PMBTA42_SOT23

E

3 1

MTP31

1

3
3

1

MC966

0.01U_0805_100V7M

1

1

C906 and C908 must be Y3 type
Capacitors for Nordic
Countries only

MFB902

1 2

MMZ1608D301BT_0603

MBR904
MMBD3004S_SOT23

TIP_2

2
2

AGND_LSD

MBR906
MMBD3004S_SOT23

MFB904

1 2

MMZ1608D301BT_0603

2

4

MQ904

FZT458TA_SOT223

MTP66

3

1

12

MR928
27_0805_5%

1

AGND_LSD

MTP49

MOD_RINGRING_2

MC906

1

470P_1808_3KV

2

GND

1

MC908
470P_1808_3KV

2

AGND_LSD

TB3100M-13-01_SMB

1

1
2

2

MOD_TIP

1

MTP41

E&T_3800-02

1

MTP42

MJ2

2
1

MRV902

MTP52

1

MTP26

1

MTP22

1

PWRCLKN<25>

PWRCLKP<25>

DIB_DATAP<25>

DIB_DATAN<25>

MJ1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

HEADER8@
MJ1B

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

HEADER8@

MTP23

1

2 3

MTP24

1

MT902

30U_82154R_1%_1:1.67

MTP25

GND

BR908_AC1

41

1

MC962
47P_0603_50V8J

2

PCLK

SECPRI

Check 0.047u or 10p cap

MTP27

1

MC922 10P_1808_3KV

MC924 10P_1808_3KV

1

MT922

2 3

30U_82154R_1%_1:1.67@

1 2

1 2

BR908_CC

MBR908A

6

BAV99DW-7_SOT363

1

2

4

5

MBR908B

3

BAV99DW-7_SOT363

41

SECPRI

0.001U_0402_50V7M@

1

MC974

MR932
15K_0402_5%

MTP72

1

MC944

2

AGND_LSD

MTP29

CLK2

1 2

MMZ1608D301BT_0603

1

MC970

0.1U_0402_10V6K

2

AGND_LSD

DIB_P1

1 2

1 2

MTP73

1

MC940
1U_0603_6.3V6M

1

2

0.1U_0402_10V6K

1

1 2

MR922
0_0402_5%

0_0402_5%
MR924

MTP61

0.001U_0402_50V7M

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

AMOM_modem

LA-3342P

26 40Thursday, July 27, 2006

0.1

A

1 1

C475 0.047U_0603_16V7K

LINE_OUTR<25>

LINE_OUTL<25>

+5VS

1
2

MONO_INR<25>

PCBEEP<20>

2 2

3 3

1 2

C476 0.47U_0603_16V7K

1 2

C509 0.47U_0603_16V7K

C510 0.47U_0603_16V7K

C508 0.47U_0603_16V7K

1 2

C507 0.047U_0603_16V7K

1 2

U45

IN
V+
GND3NC

PI5A4599ACEX

COM

NO

HP_DET#<25>

C477 0.47U_0603_16V7K

6
5
4

10K_0402_5%

HP_DET

Q13

2N7002_SOT23

1 2

1 2

1 2

EC_MUTE#<31>

12

R353

74AHCT1G125GW_SOT353-5

R345

10K_0402_5%

13

D

2

G

S

4

U44

LINE_C_OUTR
HP_C_OUTR

HP_C_OUTL
LINE_C_OUTL

+5V+5VS

12

+5V

1

OE#

A2Y

B

23
20

8

10

6
5

14
22

1 2

5

P

G

3

19

U21

VDD

RLINEIN
RHPIN
RIN

LIN
LHPIN
LLINEIN

PC-BEEP
SHUTDOWN#

GND424GND3

GND212GND1

1

13

TPA0312PWPRG4_TSSOP24

HPDET#

C785

0.1U_0402_16V4Z

C462

10U_0805_10V4Z

18

PVDD17PVDD2

LOUT+
ROUT-

ROUT+

SE/BTL#

HP/LINE#

BYPASS

HPDET# <29>

LOUT-

GAIN1
GAIN0

0.1U_0402_16V4Z

1

C479

2

9
4
16
21

15
17

3
2

11

1

C501

2

0.1U_0402_16V4Z

SPKL­SPKL+
SPKR­SPKR+

2

C511
1U_0603_10V4Z

1

1

2

HP_DET

R322
0_1206_5%

1 2

SPKL+ <29>
SPKR+ <29>

C

+5VS+5VAMP

R371

100K_0402_5%

R373

@

100K_0402_5%

12

12

10 dB

+5VS

12

R368

@

100K_0402_5%

12

R364
100K_0402_5%

GAIN0

0
0
1 0
1

D

HEADPHONE OUT/LINE OUT

Gain Settings

0
1

SE/BTL#

0
0

GAIN1

0

1

0
1XX

SPKL+
SPKL­SPKR+
SPKR-

1

1

C497

C496

2

@

@

47P_0402_50V8J

1

C498

2

47P_0402_50V8J

C499

2

@

@

47P_0402_50V8J

47P_0402_50V8J

* 10 dB

1

2

Av(inv)

6 dB

15.6 dB

21.6 dB

4.1 dB

JP11

1

1

2

2

3

3

4

4

ACES_85205-0400

E

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

AMP & Audio Jack

LA-3342P

E

0.1

of

27 40Thursday, July 27, 2006

0.1U_0402_16V4Z

USB20_P0<20>

USB20_N0<20>

+USB_VCCB +USB_VCCB

C789

100U_6.3V_M

Change to Aluminum Cap

<7/20>In PV2 The part footprint
error update to correct
footprint.

<6/19> Remove C736 (not reserved)

+5V

C754

12

R535 0_0603_5%
R537 0_0603_5%

1

+

2

U38

3

VIN

VOUT

4

VIN/CE

VOUT

2

GND

RT9701PBL_SOT25

1
5

+USB_VCCB

R542

10K_0402_5%

R544

20K_0402_5%

12

12

USB CONNECTOR (Left side)

JP26

1

5

1

1 2
1 2

1

C401

2

0.1U_0402_16V4Z

USBP0+USB20_P0
USBP0-USB20_N0

W=40mils W=40mils

1

C400

2

1000P_0402_50V7K

SUYIN_020122MR008S573ZR

5

2

6

2

6

3

7

3

7

4

8

4

8

9

GND

10

GND

11

GND

12

GND

USB_OC#0
USB_OC#3

R543

1 2

0_0402_5%

USBP3+ USB20_P3

R523 0_0603_5%

USBP3- USB20_N3

1 2

R532 0_0603_5%

1 2

1

C397

C394

2

0.1U_0402_16V4Z

1000P_0402_50V7K

USB_OC#0 <20>
USB_OC#3 <20>

1

1

+

C408

@

150U_D_6.3VM

2

2

USB20_P3 <20>
USB20_N3 <20>

USBP0+

USBP3+ USBP0-

U9

1

D1+

2

VCC

GND

3

D2-

IP4220CZ6_SO6@

USBP3-

4

D2+

5
6

D1-

+USB_VCCB

WIRELESS_LED_BT<24>

USB20_P6<20>

USB20_N6<20>

WL_PRIORITY<24>

BT_ON#<20>

+3VALW

12

C118

BT@

1U_0603_10V4Z

1 2

BT_PRIORITY<24>

BT_DET#<20>

BT@

100K_0402_5%

R601 100_0402_5%BT@

0.1U_0402_16V4Z@

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BT CONNECTOR

R541

G

2

+3V_BT

13

D

S

1

AO3419_SOT23

Q2

BT@

2

USB20_P6
USB20_N6
WIRELESS_LED_BT

BT_DET#

1

C808

2

2005/03/10 2006/03/10

BT@

1U_0603_10V4Z

1 2

1
2
3
4
5
6
7
8

ACES_87213-0800

1

C611

BT@

0.1U_0402_16V4Z

2

Compal Secret Data

C108

JP6

1
2
3
4
5
6
7
8

Deciphered Date

Reserve Blueooth

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Bluetooth & U S B CONN.

LA-3342P

of

28 40Thursday, July 27, 2006

1.0

5

D38

KSO2

1 5

2

KSI[0..7]

D D

KSO[0..16]

KSI[0..7] <31>

KSO[0..16] <31>

KSO4

NZQA5V6AXV5T1_SOT533-5
D40

KSO6 KSO0

1 5

2

KSO3

NZQA5V6AXV5T1_SOT533-5
D42

1 5

2

4

D39

KSI1

KSO7

KSO8

43

KSO12

KSO13

43

KSO15KSO14

1 5

2

KSI7 KSI6

NZQA5V6AXV5T1_SOT533-5
D41

KSI4

1 5

2

KSI5 KSI2

NZQA5V6AXV5T1_SOT533-5
D43

KSI3

1 5

2

KSO9

43

43

KSO1

3

15.4 ( TYPE "C" KB)

KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

JP8

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

ACES_85201-2405

ESD

EC_ON<31,36>

Q25

2N7002_SOT23@

2

ON/OFFBTN#

C809

0.1U_0402_16V4Z

LDO3

12

EC_ON

13

D

S

R383

4.7K_0402_5%

0_0402_5%

2

G

Power BTN

D11
DAN202U_SC70

1

1

2

Q26
DTC124EK_SC59

R603

12

12

R604

@

0_0402_5%

3

2

I

2

R396 100K_0402_5%

1 2

ON/OFF#

1

O

1

G

2

3

1000P_0402_50V7K

WHEN R=0,Vbe=1.35V
WHEN R=33K,Vb e =0.8V

C544

1

LDO3

ON/OFF# <31>

EC_PWR_ON# <34>

12

D12
RLZ20A_LL34

C C

KSO11

43

KSO10

KSO5

KSI0

43

TP to MB CONN(15.4)

NZQA5V6AXV5T1_SOT533-5
D44

KSO16

1 5

2

KSO_D_17<31>

JP15

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

+5VS

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ#0
PCI_RST#

SIRQ

+3VS

LPC_AD[0..3] <19,31>

LPC_FRAME# <19,31>
LPC_DRQ#0 <19>

PCI_RST# <18,23,31>
CLK_PCI_SIO <15>

SIRQ <20,31>

1
2

B B

A A

3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

ACES_85201-2005

KSO_D_17

NZQA5V6AXV5T1_SOT533-5

FOR LPC SIO DEBUG PORT

R424

@

10K_0402_5%

12

43

NZQA5V6AXV5T1_SOT533-5

VOL_DWN#<31>

PWR_ACTIVE#<31>

PA_LED_ALW<31>
PR_LED_ALW<30>

PR_LED<30>

PR_LED_VS<30>

VOL_UP#
VOL_DWN#

KSI0<31>
KSI1<31>
KSI3<31>
KSI4<31>

WL_LED#<16,24>
VOL_UP#<31>

LID_SW#<31>
NUMLED#<31>
MUTE_LED<25>

+3VALW

ESD

+5VALW

+5VS

Switch board conn

ON/OFFBTN#
KSI0
KSI1
KSI3
KSI4
KSO_D_17
WL_LED#
VOL_UP#
VOL_DWN#
LID_SW#
NUMLED#
MUTE_LED

PWR_ACTIVE#
PA_LED_ALW

PR_LED_ALW

+5V

PA_LED
PR_LED

PA_LED_VS
PR_LED_VS

D47

2
3

SM05_SOT23

1

+5V

1

TP_DATA<31>
TP_CLK<31>

2

@

C442

0.1U_0402_10V6K

D45

JP5

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

ACES_85201-2505

KSI0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

1 6

2

KSI1

NUP5120X6T1_SOT563-6

NUMLED#

C795 100P_0402_50V8J

WL_LED#

LID_SW#
MUTE_LED
PWR_ACTIVE#
PA_LED_ALW
PR_LED_ALW
PA_LED
PR_LED
PA_LED_VS
PR_LED_VS

C796 100P_0402_50V8J

C810 0.1U_0402_16V4Z

C813 0.1U_0402_16V4Z
C814 0.1U_0402_16V4Z
C815 0.1U_0402_16V4Z
C816 0.1U_0402_16V4Z
C817 0.1U_0402_16V4Z
C818 0.1U_0402_16V4Z
C819 0.1U_0402_16V4Z
C820 0.1U_0402_16V4Z
C821 0.1U_0402_16V4Z

+5VALW +5VS

1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

TP_DATA
TP_CLK

KSI4

5

KSO_D_17

43

JP7

ACES_87152-0807

KSI3

1
2
3
4
5
6
7
8

USB_OC#5<20>

USB_OC#4<20>

SPDIFO<25>

FBMA-L10-201209-301LMT

220P_0402_25V8K

<6/21> Remove CIR

USB_OC#5

0_0402_5%

1 2

Audio board conn

12

R274

Q10

1 3

2N7002_SOT23

L32

1

C822

2

+5V

2

G

USB20_P4<20>

USB20_N4<20>

D

S

USB20_P5<20>
USB20_N5<20>

SPDIFO_R

MIC_L<25>

MIC_R<25>

MIC_DET<25>
HPDET#<27>
SPKR+<27>
SPKL+<27>

+5V

MIC_L

MIC_R
MIC_DET

HPDET#
SPKR+
SPKL+

USB20_P4
USB20_N4
OVCUR#4USB_OC#4

USB20_P5
USB20_N5

ACES_87213-2000

JP9

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

KBD,ON/OFF,T/P,LED/B,DEBUG

LA-3342P

1

of

29 40Thursday, July 27, 2006

0.1

5

4

3

2

1

D D

+5VS

R568

10K_0402_5%

IDE_LED#
ACT_LED#

0.1U_0402_16V4Z

+3VS

+5VS

1 2

C830

5

U48

1

P

A

O

2

B

G

SN74AHCT1G08DCKR_SC70

3

1

2

R570
20K_0402_5%

1 2

IDE_LED#<19>
ACT_LED#<22>

C C

FOR POWER BUTTON B A CKLIGHT SYSTEM POWER

"Right Angle"

R425
560_0402_5%

PMLED_1#

PMLED_1#<31>

BATLED_0#<31>

IDE_ACT_LED#

4

CAPSLED#<31>

1 2

R426
560_0402_5%

BATLED_0#

R427
560_0402_5%

1 2

R92
560_0402_5%

CAPSLED# PR_LED_VS

1 2

1

1

12

1

D13

12-21UYOC/S530-A2/TR8_YEL

D14

12-21UYOC/S530-A2/TR8_YEL

D15

12-21UYOC/S530-A2/TR8_YEL

D7

17-21UYOC/S530-A2/TR8_ORG

2
3

2
3

2
3

21

PR_LED <29>

PR_LED_ALW <29>

PR_LED_VS <29>

For PR

B B

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

INDICATE LED

LA-3342P

1

0.1

of

30 40Thursday, July 27, 2006

5

Cd(uF)=T(ms) / 1685
Cd=2700PF ------> T=3.6ms

1

C51

5

2700P_0603_50V7K~D

2

CD

RESET

1

12

J1
JOPEN

12

R611

22K_0402_5%

1 2

10K_0402_5%

3/29 Design Change

TP_DATA

TP_CLK

12
12
12

10K_0402_5%@

12

10K_0402_5%@

12
12

12
12
12

4

U47

N.C.

3

R382

1 2

47K_0402_5%@

EC_SMD_2
EC_SMC_2

EC_SMI#
EC_SCI#

CONA#

EC_SMD_1
EC_SMC_1

FSEL#
FRD#
LID_SW#

12
12

VOL_UP#

VOL_DWN#

DOCK_VOL_UP#

DOCK_VOL_DWN#

5

VCC2GND

+3VALW

D D

G696L263T1UF_SOT23-5

LDO3

CLK_PCI_EC

12

R399

@

10_0402_5%

1

C C

B B

A A

+3VALW

+5VALW

LDO3

+3VS

C556

@

15P_0402_50V8J

2

R337

10K_0402_5%

R338

10K_0402_5%

R400
R397
R950

10K_0402_5%

1 2

R339

10K_0402_5%

R340

10K_0402_5%

R394

10K_0402_5%

R390

10K_0402_5%

R585

10K_0402_5%

+5V

R335
10K_0402_5%
R336
10K_0402_5%

R372
10K_0402_5%

1 2

R402
10K_0402_5%

1 2

R331
10K_0402_5%

1 2

R330
10K_0402_5%

1 2

R586

LDO3

4.7U_0805_6.3V6K

1

C525

0.1U_0402_16V4Z@

2

GM_PM#DET

0.1U_0402_16V4Z

1

C472

2

GATEA20<19>

KB_RST#<19>

SIRQ<20,29>

LPC_FRAME#<19,29>

LPC_AD3<19,29>
LPC_AD2<19,29>
LPC_AD1<19,29>
LPC_AD0<19,29>

CLK_PCI_EC<15>

PCI_RST#<18,23,29>

EC_SCI#<20>

KSI[0..7]<29>

KSO[0..16]<29>

KSO_D_17<29>

EC_SMD_2<4>
EC_SMC_2<4>
EC_SMD_1<32,40>
EC_SMC_1<32,40>

SLP_S4#<20>

PMLED_1#<30>

NUMLED#<29>

BATLED_0#<30>

CAPSLED#<30>

CPUSB#<20>

SYSON<33,37>

EC_RSMRST#<20>

BKOFF#<16>

SLP_S3#<20>

LID_OUT#<20>

SLP_S5#<20>
EC_SMI#<20>
LAN_RST#<20>
LID_SW#<29>

SUSP#<33,37,38>

PWRBTN_OUT#<20>

PCI_PME#<18,23>

Y7 32.768KHZ_12.5P_MC-146

10P_0402_50V8K

C527

23

C517

1

C512

2

0.1U_0402_16V4Z

GATEA20
KB_RST#
SIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
CLK_PCI_EC
PCI_RST#

EC_SCI#
PA_PR#DET

KSI[0..7]

KSO[0..16]

KSO_D_17

EC_SMD_2
EC_SMC_2
EC_SMD_1
EC_SMC_1

UTXD
SLP_S4#
PMLED_1#
NUMLED#
BATLED_0#
GM_PM#DET
CAPSLED#

SYSON
EC_RSMRST#

BKOFF#
SLP_S3#
LID_OUT#
SLP_S5#
EC_SMI#
LAN_RST#
LID_SW#
SUSP#
PWRBTN_OUT#
PCI_PME#

14

1

2

EC_RST#

1

2

4

0.01U_0402_16V7K

1

1

2

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16

CRY2
CRY1

C522
10P_0402_50V8K

C550

C551

2

0.1U_0402_16V4Z

U24

1

GA20/ GPIO00/GA20

2

KBRST#/GPIO01/KBRST#

3

SERIRQ

5

LPC_FRAME# / LFRAME#

6

LPC AD3/LAD3

9

LPC AD2/LAD2

10

LPC AD1/LAD1

12

LPC AD0/LAD0

14

CLK_PCI_EC/PCICLK

15

PCIRST#

42

EC RST#/ ECRST#

24

EC SCI#/SCI#/GPIO0E

44

PM_CLKRUN#/ CLKRUN#

63

KSI0/GPIO30

64

KSI1/GPIO31

65

KSI2/GPI032

66

KSI3/GPIO33

67

KSI4/GPIO34

68

KSI5/GPI035

69

KSI6/GPIO36

70

KSI7/GPIO37

47

KSO0/GPIO20

48

KSO1/GPIO21

49

KSO2/GPIO22

50

KSO3/GPIO23

51

KSO4/GPIO24

52

KSO5/GPIO25

53

KSO6/GPIO26

54

KSO7/GPIO27

55

KSO8/GPIO28

56

KSO9/GPIO29

57

KSO10/GPIO2A

58

KSO11/GPIO2B

59

KSO12/GPIO2C

60

KSO13/GPIO2D

61

KSO14/GPIO2E

62

KSO15/GPIO2F

89

EC URXD/KSO16/GPIO48

90

EC UTXD/KSO17/GPIO49

88

EC SMD2/ GPIO47/SDA2

87

EC SMC2/GPIO46/SCL2

86

EC SMD1/GPIO44/SDA1

85

EC SMC1/GPIO44/SCL1

34

PCM_SPK#/EMAIL_LED#/ GPIO16

35

SB_SPKR/PWR_SUSP_LED#/ GPIO17

38

PWRLED#/ GPIO19

40

NUMLED#/ GPIO1A

99

BATT CHGI LED#/ E51CS#

101

BATT LOW LED#/ E51MR0

100

CAPS LED#/ E51TMR1

102

ARROW LED#/ E51 INT0

104

SYSON/GPIO56/ E51 INT1

4

EC_RSMRST#/ GPIO02

7

BKOFF#/GPIO03

8

PM SLP S3#/GPIO04

16

EC LID OUT#/GPIO06

17

PM SLP S05#/ GPIO07

18

EC SMI#/GPIO08

19

EC SWI#/GPIO09

20

LID SW#/ GPIO0A

21

SUSP#/GPIO0B

22

PBTN_OUT#/GPIO0C

23

EC PME#/GPIO0D

140

XCLKO

138

XCLKI

KB910LQF_LQFP144

EC DEBUG port

JP20

1

1

2

2

3

3

4

4

ACES_85205-0400

4

1

2

UTXD

Host

INTERFACE

key Matrix

scan

LDO5

11

26

VCC/ EC VCC

VCC / EC VCC

SM BUS

GND

GND

103

129

139

0_0603_5%

VCC / EC VCC37VCC / EC VCC

GND

3

R579

@

PA_LED_ALW<29>

+EC_AVCCLDO3

75

105

127

141

BATTEMP/AD0/GPIO38

VCC

VCC

BATT OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD BID0/AD3/GPIO3B

AD INtput or GPI

EC_AVCC / AVCC

DAC_BRIG/DA0/GPIO3D

PWR

EN DFAN1/DA1/GPIO3D

IREF2/DA2

EN DFAN2/DA3/ GPIO3F

DA output or GPO

FAN/PWM

INVT_PWM/GPIO0F/PWM1

BEEP#/GPIO10/PWM2

OUT BEEP/GPIO12/PWM3

ACOFF/GPIO18/PWM4
FAN SPEED1/GPIO14/FANFB1
FAN SPEED2/GPIO15/FANFB2

PSCLK1
PSDAT1

ADB3/ D3

KBA10/A10
KBA11/A11
KBA12/A12
KBA13/A13
KBA14/A14
KBA15/A15
KBA16/A16
KBA17/A17
KBA18/A18
KBA19/A19

SELIO2#/ GPIO43

SELIO#/ GPIO50

FRD#/RD#

FWR#/WR#

FSEL#/SELMEM#

EC ON/ GPIO1B

AC IN/ GPIO1C

ECTHERM#/GPIO11

ONOFF/GPIO18

PCMRST#/GPIO1E

WL OFF#/GPIO1F

ALI/MH#/GPIO40

FSTCHG/GPIO41

VR ON/ GPIO42
GPIO57/GPIO57
GPIO58/GPIO58
GPIO59/GPIO59

AGND

77

0_0603_5%

ECAGND

0.1U_0402_16V4Z

PSCLK2
PSDAT2
PSCLK3
PSDAT3

ADB0/D0
ADB1/D1
ADB2/D2

ADB4/D4
ADB5/D5
ADB6/D6
ADB7/D7
KBA0/A0
KBA1/A1
KBA2/A2
KBA3/A3
KBA4/A4
KBA5/A5
KBA6/A6
KBA7/A7
KBA8/A8
KBA9/A9

C474

1 2

PS2 interface

Data
BUS

Address

BUS

GND13GND28GND

39

R326

12

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

BATT_TEMP

71

BATT_OVP

72

ADP_IR

73

BID

74

DAC_BRIG

76

EN_FAN1

78

IREF

79
80

INVT_PWM

25

CONA#

27

PGD_IN

30

ACOFF

31

FAN_SPEED1

32

VOL_DWN#

33

91
92

PWR_ACTIVE#

93

DOCK_VOL_UP#

94

TP_CLK

95

TP_DATA

96

ADB0

125

ADB1

126

ADB2

128

ADB3

130

ADB4

131

ADB5

132

ADB6

133

ADB7

134

KBA0

111

KBA1

112

KBA2

113

KBA3

114

KBA4

115

KBA5

116

KBA6

117

KBA7

118

KBA8

119

KBA9

120

KBA10

121

KBA11

122

KBA12

123

KBA13

124

KBA14

110

KBA15

109

KBA16

108

KBA17

107

KBA18

106

KBA19

98

NV_ENBKL

84

DOCK_VOL_DWN#

97

FRD#

135

FWR#

136

FSEL#

144

EC_ON

41

ACIN

43

EC_THERM#

29

ON/OFF#

36

VOL_UP#

45

ICH_POK

46

AIR_ACIN

81

FSTCHG

82

VR_ON

83

R365 0_0402_5%

137

CIR_IN

142

EC_MUTE#

143

LDO3

12

+EC_AVCC

R327

2005/03/10 2006/03/10

1 2

1K_0402_5%

ADB[0..7]

KBA[0..19]

12

Compal Secret Data

PA_PR#DET

12

R580
2K_0402_5%

BATT_TEMP <40>
BATT_OVP <35>

DAC_BRIG <16>
EN_FAN1 <4>
IREF <35>
EC_RTCRESET <19>

INVT_PWM <16>
PGD_IN <39>

ACOFF <35>
FAN_SPEED1 <4>

VOL_DWN# <29>

ACZ_RST# <19,25>
PWR_ACTIVE# <29>
TP_CLK <29>

TP_DATA <29>

ADB[0..7] <32>

KBA[0..19] <32>

FRD# <32>
FWR# <32>

FSEL# <32>
EC_ON <29,36>

ACIN <34,36>
EC_THERM# <20>
ON/OFF# <29>

VOL_UP# <29>

ICH_POK <7,20>

AIR_ACIN <35>

FSTCHG <35>

VR_ON <39>

VGATE <20,39>

EC_MUTE# <27>

Deciphered Date

1 2

R332
10K_0402_5%

1

C463

0.22U_0603_10V7K

2

2

NV_ENBKLCPUSB#

<6/21> Remov e C I R, b u t keep CIR_IN pull-high

2

BID definition,
High (3.3V): Before SI2 type D KB(17")
Low (0V): Before SI2 type C KB(15")

2.2V(R325=1K,R333=2K): After PV type D KB(17")

1.65V(R605=2K,R333=2K): After PV type C KB(15")

ADP_I <35>

VOL_UP#

C921 68P_0402_50V8J@

VOL_DWN#
LID_SW#

1 2

C922 68P_0402_50V8J@

1 2

C923 68P_0402_50V8J @

1 2

<6/3> To elimi na te coupling noise

R581
100K_0402_5%

1 2

LDO3

R612

10K_0402_5%

1 2

CIR_IN

Title

Size Document Number Rev

Custom

Date: Sheet

2K_0402_5%

BID

Compal Electronics, Inc.

EC KB910L(LPC)

LA-3342P

R605

+3VALW

12

1

12

@

1K_0402_5%

12

R333
2K_0402_5%

1

R325

0.1

of

31 40Thursday, July 27, 2006

A

1 1

B

C

D

E

ADB[0..7]<31>

KBA[0..19]<31>

KBA16
KBA15
KBA14
KBA13
KBA12
KBA11
KBA9
KBA8
FWR#
RESET#

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

FSEL#
FRD#
FWE#

KBA18
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1

2 2

3 3

FSEL#<31>

FRD#<31>

ADB[0..7]
KBA[0..19]

JP12

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40

SUYIN-80065A-040G2T

U14

21

A0

20

A1

19

A2

18

A3

17

A4

16

A5

15

A6

14

A7

8

A8

7

A9

36

A10

6

A11

5

A12

4

A13

3

A14

2

A15

1

A16

READY/BUSY#

40

A17

13

A18

37

A19

22

CE#

24

OE#

9

WE#

SST39VF080-70_TSOP40

VCC0
VCC1

GND0
GND1

RP#

NC0
NC1

GND

A0
A1
A2

+3VALW+3VALW

1
2
3
4

FWR# <31>

12

R366
100K_0402_5%

12

R367
100K_0402_5%

KBA17

KBA19
KBA10
ADB7
ADB6
ADB5
ADB4

ADB3
ADB2
ADB1
ADB0
FRD#

FSEL#
KBA0

31
30

25

D0

26

D1

27

D2

28

D3

32

D4

33

D5

34

D6

35

D7

10
11

NC

12
29
38

23
39

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

RESET#

LDO3

LDO3

1 2

R370

100K_0402_5%

2

C437

0.1U_0402_16V4Z

1

LDO3

0.1U_0402_16V4Z

EC_SMC_1<31,40>
EC_SMD_1<31,40>

LDO3

C531

FWE#

1

2

1 2

R610 0_0402_5%

U22

8

VCC

7

WP

6

SCL

5

SDA

AT24C16AN-10SI-2.7_SO8

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

BIOS & EC I/O Port

LA-3342P

E

0.1

of

32 40Thursday, July 27, 2006

A

B

C

D

E

F

G

H

I

J

+5VALW to +5V Transfer

1 1

+5VALW

U39

8

B+

12

R545
100K_0402_5%

2 2

SYSON#

2N7002_SOT23

13

D

2

G

S

Q40

C758

10U_0805_10V4Z

1

2

12

R546
470_0402_5%

1

C755

0.01U_0402_16V7K

2

D

7

D

6

D

5

D

SI4800DY_SO8

SUSON

+5V

1

C760
10U_0805_10V4Z

2

0.1U_0402_16V4Z

1

C759

2

12

R549
470_0402_5%

13

D

Q41

S

2N7002_SOT23

G

2

SYSON#

C438

10U_0805_10V4Z

1

S

2

S

3

S

4

G

3 3

+3VALW to +3VS Transfer

+3VALW

U17

8

S

D

7

1

2

D

6

D

5

D

SI4800DY_SO8

S
S

G

+3VS

1

C459
10U_0805_10V4Z

2

0.1U_0402_16V4Z

1

C455

2

12

13

D

S

R306
470_0402_5%

SUSPRUNON

2

G

Q11
2N7002_SOT23

FM3

1

1

CF2

CF11CF3

1

FM1

FM5

FM2

1

1

CF10

CF4

1

1

1

CF9

CF8

1

1

1

CF12

FM6

FM4

1

1

1
2
3
4

+5VALW to +5VS Transfer

+5VALW +5VS

U25

S

D

S

D

S

D

G

D

SI4800DY_SO8

RUNON

SYSON#

2

G

1
2
3
4

B+

12

R341
330K_0402_5%

13

D

Q16
2N7002_SOT23

S

B+

12

4 4

SUSP

2N7002_SOT23

R398
100K_0402_5%

13

D

2

G

Q21

S

5 5

C515

10U_0805_10V4Z

12

1

2

8
7

1

6
5

2

R395
470_0402_5%

C557

0.01U_0402_16V7K

6 6

SYSON<31,37>

1

C561
10U_0805_10V4Z

2

0.1U_0402_16V4Z

1

C552

2

12

R347
470_0402_5%

13

D

S

SUSP

2

G

Q18
2N7002_SOT23

2N7002_SOT23

+2.5VS +1.8V

12

R137
470_0402_5%

13

D

SUSP SYSON# SUSP SUSP

2

G

Q5

S

2N7002_SOT23-3

12

R131
470_0402_5%

13

D

Q4

2

G

S

+1.5VS +VCCP

12

R522
470_0402_5%

13

D

2

G

Q37

S

2N7002_SOT23

+0.9VS

12

13

D

S

R68
470_0402_5%

2

G

Q3
2N7002_SOT23

SUSP

12

R346
470_0402_5%

13

D

S

2

G

Q17
2N7002_SOT23

H15
HOLEA

1

H5
HOLEA

1

H23
HOLEA

1

H3
HOLEA

1

H10
HOLEA

1

H24
HOLEA

1

H2
HOLEA

1

H4
HOLEA

1

H25
HOLEA

1

H11
HOLEA

1

H9
HOLEA

1

H26
HOLEA

1

H20
HOLEA

1

H6
HOLEA

1

H12
HOLEA

1

H21
HOLEA

1

H7
HOLEA

1

H17
HOLEA

1

H14
HOLEA

1

H18
HOLEA

1

H22
HOLEA

1

H13
HOLEA

1

H8
HOLEA

1

B+

SUSP

2

G

12

R406
330K_0402_5%

13

D

Q27
2N7002_SOT23

S

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

C

D

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

2005/03/10 2006/03/10

F

Compal Secret Data

Deciphered Date

G

Title

Size Document Number Rev

Custom

H

Date: Sheet

Compal Electronics, Inc.

DC/DC Circuit

LA-3342P

I

0.1

of

33 40Thursday, July 27, 2006

J

7 7

SUSP<38>

SUSP#<31,37,38>

8 8

A

B

5

4

3

2

1

Detector/Precharge

VIN

12

12

0.22U_1206_25V7K

3.3V

12

PC11

4.7U_0805_6.3V6K

+5VALW

+3VALW

+2.5VS

+1.8V

ADPIN

12

PC1

100P_0402_50V8J

PJP27
JUMP_43X39@

2

2

N6

3

+1.5VSP

+1.05VSP

+0.9VSP

PL1

HCB4532KF-800T90_1812

1 2

PC2

1000P_0402_50V7K

N58

112

13

PR215
47_1206_5%

PQ1
TP0610K-T1-E3_SOT23

PU2
G920AT24U_SOT89

OUT

GND

2

IN

1

PC3

100P_0402_50V8J

VIN

12

PR11
47_1206_5%

N5

1 2

12

12

PC9

0.1U_0603_25V7K

12

N8

12

PJP7
JUMP_43X118@

112

PJP12
JUMP_43X118@

112

PJP14
JUMP_43X118@

112

ADPIN2

12

PC4

1000P_0402_50V7K

PD4
RLS4148_LLDS2

PR17
200_0603_5%

PC10
1U_0805_25V4Z

2

2

2

12

N1 N2

12

PR8

1 2

1K_1206_5%

PR10

1 2

1K_1206_5%

PR12

1 2

1K_1206_5%

VS

N4

PD2

12

RLS4148_LLDS2

PC6

B+

0.047U_0603_25V7M

ACIN: BATT

12.384 12.000 11.624

10.927 10.600 10.223

PR15
10K_0402_5%

1 2

VL

ACON<35>
MAINPWON<36,40>

+1.5VS

+VCCP

+0.9VS

PD5
RB715F_SOT323

2
3

D D

4

3

2

1

PCN1

ACES_88290-0400M

C C

BATT+

EC_PWR_ON#<29>

B B

CHGRTC

+5VALWP

+3VALWP

A A

+2.5VSP

+1.8VP

PR19
510_0603_5%@

1 2

PD3
RLS4148_LLDS2

CHGRTCP

100K_0603_1%

1 2

PR14
22K_0603_1%

PR20
510_0603_5%@

N7

1 2

47K_0603_1%

PJP6
JUMP_43X118@

112

PJP8
JUMP_43X118@

112

PJP4
JUMP_43X39@

2

PJP10
JUMP_43X118@

112

ADPIN

12

12

PR13

PC8

RTCVREF

12

PR256

2

2

112

2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Vin Detector :

14.698 14.285 13.879

13.818 13.411 13.000

PR1
1M_0603_1%

N3

1 2

VS

8

3

+

2

-

4

PR9

10K_0402_5%

12

12

P

1

O

G

PU1A
LM393DR_SO8

PC5

0.01U_0402_25V7K

RLZ4.3B_LL34

RTCVREF

3.3V

VIN

12

12

PR6

27K_0603_1%

PR2

82.5K_0603_0.1%
PR5

47K_0603_1%

1 2

12

PC7
1000P_0402_50V7K

Precharge detectorPrecharge detector

7.558 7.333 7.112

6.108 5.933 5.704

PR16

1M_0603_1%

12

VS

PU1B
LM393DR_SO8

8

N10

5

P

1

N9

12

PC13

0.1U_0603_25V7K

VL

2006/04/03 2007/04/03

+

7

O

N11

6

-

G

4

12

PR24
10K_0402_5%

12

Compal Secret Data

Deciphered Date

PC14

1000P_0402_50V7K

2

12

N12

13

D

S

PZD1

PR21
300K_0603_0.1%

VIN

12

PR3
10K_0805_5%

12

B+

12

PR18
280K_0603_1%

12

PR22

1.5M_0603_1%

PR23
47K_0402_5%

N13

2

G

PQ2
2N7002LT1G_SOT23-3

13

PR4
1K_0402_1%

1 2

PACIN

12

PR7
10K_0402_5%

1 2

PACIN

12

+5VALWP

2

PQ3
DTC115EUA_SC70

Title

Size Document Number Rev

Custom

Date: Sheet

ACIN <31,36>

PACIN <35>

PC12
1000P_0402_50V7K

PACIN <35>

Dectector / Precharge

1

0.2

of

34 40Thursday, July 27, 2006

5

4

4

3

2

1

8
7

5

1 2

PR29
47K_0603_1%

2

PQ7
DTC115EUA_SC70

12

PC29

4.7U_1206_25V6K

4.7U_1206_25V6K

Charger

VIN

ACOFF <31>

12

12

PC30

4.7U_1206_25V6K

BATT+

B+

P2

PQ49

AO4407_SO8

150K_0402_1%

1
2
36

4

12

PC206

0.1U_0603_25V7K

PR33

2

G

VIN

D D

12

PR27
15K_0603_5%

12

PR248
47K_0402_5%

N65

13

D

PQ52

2

2N7002LT1G_SOT23-3

G

S

C C

ACON

>

2

DTA144EUA_SC70

N64

13

PQ53
DTC115EUA_SC70

PACIN<34>

IREF<31>

IREF=1.096*Icharge

PQ54

ACOFF#

47K

2

47K

PD9
1SS355_SOD323

PACIN

1 2

PR43
174K_0603_1%

8
7

5

1 3

1 2

1 2

PR37
3K_0603_5%

IREF=0.438~3.069V

B B

PQ4
AO4407_SO8

1
2
3 6

12

PR28

200K_0402_1%

65W==>1.202V

12

N15

PC22

13

D

PQ8

S

2N7002LT1G_SOT23-3

12

PR44
100K_0603_1%

4

65W:1.40V(-1 level); 1.30V (+1 level)

N14

12

12

PR36

0.1U_0402_16V7K

8
7

5

ADP_I<31>

12

12

10K_0402_1%

12

PR34

5.0V

PC24

PC31

65W Iadp=0~3.0A

P3

PR26

0.02_2512_1%

PR32

100K_0402_1%

PC21

1500P_0402_50V7K

N16

1 2

1 2

31.6K_0603_1%

N17

1 2

1 2

PR38
PC25
1500P_0402_50V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

1K_0603_1%

PR41
10K_0603_1%

12

12

3887+INE2

3887-INE2

3887FB2

PR35

4.7K_0402_1%

3887VREF

3887FB1

3887-INE1

3887+INE1

3887OUTC1

12

3887OUTD

HCB4532KF-800T90_1812

PU3

1

-INC2

+INC2

2

OUTC2

GND

3

+INE2

CS

4

-INE2

VCC(o)

5

FB2

OUT

6

VREF

VH

7

FB1

VCC

8

-INE1

RT

9

+INE1

-INE3

10

OUTC1

FB3

11

OUTD

CTL

12

-INC1

+INC1

MB3887PFV-ERE1_SSOP24

12

PR45
150K_0603_0.1%

1 2

24

23

3887CS

22

3887VCC

21

3887OUT

20

3887VH

19

18

3887RT

17

3887-INE3

16

3887FB3

15

ACON

14

3887+INC1

13

PL18

1 2

PC23

0.1U_0603_25V7K

1 2

PR39
68K_0603_5%

1 2

PR42
47K_0603_1%

12

PR30

2.2_0603_5%

1 2

PC26

0.1U_0603_25V7K

1 2

N18

4.2V

12

PC15

PC16

4.7U_1206_25V6K

PC19
2200P_0402_50V7K

1 2

1 2

PC20

0.1U_0603_25V7K

1 2

PC27
1500P_0402_50V7K

4.7U_1206_25V6K

12

PC17

12

PC18

0.1U_0603_25V7K
2200P_0402_50V7K

12

PR46
300K_0603_0.1%

B++

1

+

PC209
100U_25V_M

@

2

36

241

PQ6
AO4407_SO8

578

N19

1 2

12

PD11
EC31QS04

PL2

16UH_LF919AS-160M=P3_3.7A_20%

12

PD10
EC31QS04

@

CC=0.4~2.8A

1
2
3 6

ACOFF#

12

PR40

0.02_2512_1%

PQ5

4

AO4407_SO8

DIS

12

PR31
10K_0603_1%

13

PC28

3S2P/3S4P : 13.5V--> BATT_OVP= 2.0V

(BAT_OVP=0.14753 *BATT+)

VS

PU4A
LM358ADR_SO8

8

P

+

1

BATT_OVP<31>

12

A A

PR56
22K_0402_5%

5

0

-

G

4

BATT++

12

PR47
340K_0603_1%

12

3
2

N20

12

PC32

0.01U_0402_25V7K
PR49

499K_0603_1%

N22

12

PR55
105K_0603_0.5%

N21

12

PR57

40.2K_0603_1%

12

PC33

0.01U_0402_25V7K

4

DTC115EUA_SC70

PQ9

AIR_ACIN<31>

3887CS

+3VALWP

2

G

3887CS

13

D

PQ10
2N7002LT1G_SOT23-3

S

1

35 40Thursday, July 27, 2006

0.2

of

12

13

PR51

4.22K_0603_1%

2

12

12

PZD2

PR53
10K_0603_1%

RLZ4.3B_LL34

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

N24

7

12

PU4B
LM358ADR_SO8

8

P

+

0

-

G

4

2006/04/03 2007/04/03

N23

5

N25

6

PR50
10K_0603_1%

PR52

42.2K_0603_0.1%

PR54

10.2K_0603_1%

1 2

12

RTCVREF

12

VIN

(17V+-5%)

Compal Secret Data

Deciphered Date

FSTCHG<31>

2

PR48
47K_0603_1%

N26

13

2

PQ11
DTC115EUA_SC70

Title

Charger

Size Document Number Rev

Custom

Date: Sheet

5

4

3

2

1

B+

D D

C C

B B

A A

1

1

PJP25

@

JUMP_43X118

2

2

B+++

12

12

12

PC183

PC182

PC181

4.7U_1206_25V6K

4.7U_1206_25V6K
2200P_0402_50V7K

10U_LF919AS-100M-P3_4.5A_20%

PL16

PQ41

1

D2

2

D2

3

G1

4

S1/A

AO4916_SO8

12

D1/S2/K
D1/S2/K
D1/S2/K

8

G2

7
6
5

PC179

0.1U_0603_25V7K

DH5A

1 2

PR216
0_0402_5%

12

DH5

LX5

+5VALWP

DL5

1999_V+

1

+

PC192

2

150U_D2E_6.3VM_R18

PR226

18.2K_0402_1%

1 2

PR229

1 2

11.5K_0402_1%

PR227

47K_0402_5%

12

12

PC193
1U_1206_25V7K

@

2REF_1999 N67

1999_SHDN

10K_0402_5%

ACIN<31,34>

ACIN

VL

12

1999_ON

PC197

PR233

12

PR234

0_0402_5%

12

0.047U_0603_25V7M

MAINPWON<34,40>

BST5B BST3B

LDO5

PR217
0_0402_5%

1 2

PR241

0_0805_5%

VL

12

PC190

4.7U_0805_6.3V6K

BST5A

PR258 0_0402_5%@

1 2

1 2

PR257 0_0402_5%

PR228

806K_0603_1%

2REF_1999

2VREF_1999

1 2

13

D

2

G

PQ46

S

2N7002LT1G_SOT23-3

1999_SKIP

12

PR251

0_0805_5%

@

FB5

LDO3P

D

S

VS

PR255

0_0805_5%@

1 2

1999_V++

12

12

PR239

10_1206_5%

PC188

+5VALWP

PU5

14

BST5

16

DH5

15

LX5

19

DL5

21

OUT5

9

FB5

1

N.C.

6

SHDN#

4

ON5

3

ON3

12

SKIP#

8

REF

12

PC195

0.22U_0603_16V7K

PR242
100K_0402_5%

1 2

N60

13

ACIN

2

G

PQ47
2N7002LT1G_SOT23-3

4.7U_1206_25V6K

PR254

12

18

P2

0_0805_5%

1 2

12

PR219
10_1206_5%

1999_V+

20

V+

LD05

GND

23

D

S

0.1U_0603_25V7K

PC191

12

13

TON

LDO3

25

LDO3P

12

PC196

4.7U_0805_6.3V6K

13

G

PQ48
2N7002LT1G_SOT23-3

2

1

12

PR218
47_0402_5%

1 2

PC189
1U_0603_10V6K

1 2

1999_VCC

17

5

VCC

ILIM3

11

ILIM5

28

BST3

26

DH3

24

DL3

27

LX3

22

OUT3

7

FB3

2

PGOOD

PRO#

MAX8734AEEI+_QSOP28

10

1999_PRO

1 2

PR231
0_0402_5%

+3VALWP

2

EC_ON <29,31>

3

PD24
DAP202U_SOT323

PC184

0.1U_0402_16V7K

2VREF_1999

1 2

ILIM3

1 2

ILIM5

FB3

PR240
0_0805_5%

VL

PR221

118K_0402_1%

PR224

499K_0402_1%

BST3A

1 2

1 2

PR252
0_0805_5%@

1 2

1 2

PR222

200K_0402_1%

PR225

499K_0402_1%

1 2

PC180

0.1U_0603_25V7K

12

PR220
0_0402_5%

DH3

LDO3

B+++

12

12

PC187

PC186

2200P_0402_50V7K

4.7U_1206_25V6K

1 2

DL3

PC185

12

4.7U_1206_25V6K

PR223
0_0402_5%

+3.3VALWP/+5VALWP

PQ42

1

D2

2

D2

3

G1

4

S1/A

AO4916_SO8

DH3A

LX3

1 2

1 2

D1/S2/K
D1/S2/K
D1/S2/K

PR230

3.57K_0402_1%@

PR232

0_0402_5%

8

G2

7
6
5

12

PL17
10U_LF919AS-100M-P3_4.5A_20%

1

+

2

PC194

150U_D2E_6.3VM_R18

+3VALWP

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/04/03 2007/04/03

Compal Secret Data

Deciphered Date

Title

+3VALWP/+5VALWP

Size Document Number Rev

Custom

2

Date: Sheet

1

36 40Thursday, July 27, 2006

of

5

4

3

2

1

D D

+5VALWP

IS6227A_B+

PR84

2.2_0603_5%

1 2

1 2

PC67

2.2U_0805_10V6K

ISL6227A_VCC

28

13

17

SOFT2

VCC

23

BOOT2

24

UGATE2

25

PHASE2

22

ISEN2

27

LGATE2

26

PGND2

20

VOUT2

19

VSEN2

21

EN2

16

PG2/REF

18

OCSET2

DDR

ISL6227CAZ-T_SSOP28

PC69

0.01U_0402_25V7K

SOFT1.5

PR86
0_0402_5%

BOOT1.5

1 2

PR88
0_0402_5%

1 2

PHASE1.5

2.43K_0603_1%

ISEN1.5

1 2

LG1.5

VOUT1.5
VSEN1.5
EN1.5

12

PR102

73.2K_0603_1%

12

PR94

PC71

0.1U_0603_25V7K

12

UG1.5A

12

PC79

0.1U_0402_16V7K@

1 2

PR96

0_0402_5%

5

4

5

4

12

12

6

5
4

7
2

3

9

10

8

15
11

PR83

51_1206_5%

12

PC66

0.1U_0603_25V7K

PU6

SOFT1

BOOT1

UGATE1
PHASE1

ISEN1
LGATE1

PGND1

VOUT1
VSEN1
EN1
PG1

OCSET1

ISL6227A_VIN

14

VIN

GND

1

12

12

PC60

PC59

4.7U_1206_25V6K

5

D8D7D6D

PQ16

C C

B B

+1.8VP

1

12

+

PC75

4.7U_0805_6.3V6K

2

PC74

12

12

PR89

10.5K_0402_1%

PR97

10K_0402_1%

PC76

1 2

0.01U_0402_25V7K

12

12

220U_D2_4VM

PL4

4.7UH_PCMB104E-4R7MS_10A_20%

1 2

PR90

0_0402_5%

PR98

0_0402_5%@

SYSON<31,33> SUSP# <31,33,38>

S1S2S3G

D8D7D6D

S1S2S3G

4

5

4

SI4800BDY-T1-E3_SO8

PQ17
SI4800BDY-T1-E3_SO8

1 2

PR95

0_0402_5%

4.7U_1206_25V6K

UG1.8A

12

PC61

2200P_0402_50V7K

PC65

0.1U_0603_25V7K

0.1U_0402_16V7K@

4.7U_0805_6.3V6K

12

PC70

VOUT1.8
VSEN1.8

EN1.8

2

BOOT1.8A

1 2

12

PR87
0_0402_5%

1 2

PR93

2.43K_0603_1%

1 2

PC78

1

PD17

DAP202U_SOT323

3

BOOT1.5A

PC68

0.01U_0402_25V7K

SOFT1.8

12

PR85
0_0402_5%

BO0T1.8

UG1.8 UG1.5

PHASE1.8

ISEN1.8
LG1.8

OC1.8 OC1.5

12

12

PR101

73.2K_0603_1%

+2.5VSP/+1.8VP/+1.5VSP

PJP18

JUMP_43X118@

2

112

PC63

4.7U_1206_25V6K

12

PC64

12

PR91

0_0402_5%@

12

PR99

0_0402_5%

12

2200P_0402_50V7K

12

12

PC77

PR92

0.01U_0402_25V7K

6.81K_0402_1%

12

PR100

10K_0402_1%

12

PC62

4.7U_1206_25V6K

D8D7D6D

PQ58
SI4800BDY-T1-E3_SO8

S1S2S3G

PL5

3.3UH_PLC1045P-3R3A_6.1A_30%

1 2

D8D7D6D

PQ59
SI4810BDY-T1-E3_SO8

S1S2S3G

B+

+1.5VSP

1

12

+

PC72

2

220U_B2_2.5VM

PC73

4.7U_0805_6.3V6K

(400mA,40mils ,Via NO.= 1)

OUT

+2.5VSP

3

12

12

PC82
10U_1206_25V6M

PC81

4.7U_0805_6.3V6K

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/04/03 2007/04/03

Compal Secret Data

Deciphered Date

Title

+2.5VSP/+1.8VP/+1.5VSP

Size Document Number Rev

Custom

2

Date: Sheet

1

37 40Thursday, July 27, 2006

of

PJP19
JUMP_43X39@

+3VS

A A

1 2

PR103
47K_0603_1%@

5

2

112

D

6

S

45

2

PQ18

1

SI3456DV-T1_TSOP6@

G

3

N32SUSP#

12

PC83

0.1U_0603_25V7K@

VIN2.5

APL5508-25DC-TRL_SOT89-3

2

12

PC80

4.7U_0805_6.3V6K

PU7

IN

GND

1

4

5

4

3

MAX8575_B+

2

HCB4532KF-800T90_1812

PL6

1 2

1

B+

+1.05V_VCCPP/+0.9VSP

12

PC88

+1.8VP

12

PR113
1K_0402_1%

12

PR115
1K_0402_1%

12

PC86

0.01U_0402_25V7K

MAX8575_SS

12

FB1.05

MAX8578_VCC

PC91

4.7U_0805_6.3V6K

VIN0.9

VREF0.9

PR104

6.81K_0402_1%

MAX8575_OCSET

PU8

MAX8578EUB_10UMAX

10

OCSET

2

SS

1

FB

3

VCC

4

12

GND

12

PC96

0.1U_0402_16V7K

Security Classification

PD18
1SS355_SOD323

PU9

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL5331KAC-TRL_SO8

12

PC98
10U_1206_6.3V7K

D D

3300P_0402_50V7K

1 2

+5VS

C C

12

PR110

866_0402_1%

B B

PR114

510K_0402_5%

SUSP<33>

A A

1 2

PR253

12

510K_0402_5%

N66

12

PC97

@

0.1U_0402_16V7K

+1.8V

2

G

PR107
0_0402_5%

2

2

PJP20

1

JUMP_43X118@

1

12

PC94
10U_1206_6.3V7K

13

D

S

PQ21
2N7002LT1G_SOT23-3

BST

12

MAX8575_IN

9

IN

DH1.05

8

DH

LX1.05

7

LX

DL1.05

5

DL

BST1.05

6

NC
NC
NC

TP

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PR105
0_0402_5%

1 2

12

PC87

0.1U_0603_16V7K@

PR106
0_0402_5%

1 2

PC89

0.1U_0603_25V7K

6
5
7
8
9

+0.9VSP

SUSP# <31,33,37>

5

4

DH1.05A

12

1 2

PR111

4.7_0402_5%

+3VALW

1 2

PC95

1U_0603_10V6K

5

4

DL1.05A

12

PC84

D8D7D6D

S1S2S3G

PQ19
SI4800BDY-T1-E3_SO8

D8D7D6D

S1S2S3G

PQ20
SI4810BDY-T1-E3_SO8

Compal Secret Data

2006/04/03 2007/04/03

3

Deciphered Date

12

10U_1206_25V6M

3.3UH_PLC1045P-3R3A_6.1A_30%

12

PC92

0.047U_0603_25V7M

PR112
750_0603_1%

PC85

0.1U_0603_25V7K

PL7

1 2

PR108

7.15K_0402_1%

1 2

1 2

2

12

PR109

30_0402_5%

N33

12

PC93

0.1U_0402_16V7K

+1.05VSP

1

12

+

2

PC201

PC90

220U_B2_2.5VM

4.7U_0805_6.3V6K

Title

+1.05V_VCCPP/+0.9VSP

Size Document Number Rev

B

Date: Sheet

1

of

38 40Thursday, July 27, 2006

8

7

6

5

4

3

2

1

B+

PC99
100U_25V_M

1 2

VO

12

12

PR118
10_0402_1%

+CPU_CORE

+CPU_CORE

+CPU_CORE

PR136
10_0402_1%

1 2

VO

39 40Thursday, July 27, 2006

1

of

+CPU_B+

H H

+CPU_B+

PR116
10_0603_5%

PC106

4

VR_TT#

3

RBIAS

5

NTC

6

SOFT

28

VID0

29

VID1

30

VID2

31

VID3

32

VID4

33

VID5

34

VID6

37

DPRSTP#

36

DPRSLPVR

1

PSI#

2

PGD_IN

38

CLK_EN#

35

VR_ON

12

VSEN

13

RTN

11

VDIFF

10

FB

9

COMP

8

VW

PC136
330P_0402_50V7K

12

0.01U_0402_25V7K

ISL6260_VIN

19

20

VSS

VDD

PU11

DROOP

14

ISL6260_DFB

ISL6260_DROOP

12

12

1 2

+3VS

39

18

VIN

3V3

thermal

OCSET

DFB15VO

PR167
1K_0402_1%

6

PR124

1.91K_0603_1%

1 2

PR236
0_0402_5%@

ISL6260_PGOOD

40

ISL6260CRZ-T_QFN40

PGOOD

27

PWM1

23

ISEN1

26

PWM2

22

ISEN2

41

24

FCCM

25

PWM3

21

ISEN3

7

17

VSUM

16

VO

12

12

12

ISL6260_PWM1

ISL6260_ISEN1

ISL6260_PWM2

ISL6260_ISEN2

ISL6260_FCCM

ISL6260_PWM3

ISL6260_ISEN3

ISL6260_OCSET

VSUM

12

1 2

PR159

4.53K_0402_1%

12

PC200

0.1U_0402_16V7K

PC208
1U_0603_10V6K@

PR147
0_0402_5%

PR151
0_0402_5%

PC130

0.22U_0603_16V7K

12

PC134

VGATE <20,31>

12

12

PR152

11.5K_0402_1%

1 2

PC129

1000P_0402_50V7K

@

12

0.1U_0402_16V7K

PH2

10KB_0603_5%_ERTJ1VR103J

+5VS

12

12

PR158

3K_0402_1%

N35

12

PR165

1K_0402_1%@

5

G G

+5VS

PR121
10_0603_5%

1 2

ISL6260_VDD

12

PR126
0_0402_5%

12

12
12
12
12

PR141

PR145

PR148

12

PC199

12

12

12

7

12

PC109
1U_0603_10V6K

ISL6260_VRTT
ISL6260_RBIAS
ISL6260_NTC
ISL6260_SOFT

ISL6260_VID0
ISL6260_VID1
ISL6260_VID2
ISL6260_VID3
ISL6260_VID4
ISL6260_VID5

ISL6260_VID6
ISL6260_DPRSTP
ISL6260_DPRSLPVR

12

ISL6260_PSI
ISL6260_PGD

12

ISL6260_CLK
ISL6260_VRON

12

ISL6260_VSEN

1 2

PR156

0_0402_5%

12

12

PR125
0_0402_5%

ISL6260_RTN

ISL6260_VCIFF

12

ISL6260_FB

ISL6260_COMP

N59

ISL6260_VW

PR166

6.19K_0603_1%

F F

PC110

0.01U_0402_25V7K

ISL6260_NTC

12

H_PROCHOT#<4>

E E

D D

VCCSENSE<5>

+CPU_CORE

VSSSENSE<5>

C C

PR154

10_0402_1%@

B B

A A

H_DPRSTP#<4,19>

CLK_ENABLE#<15>

12

8

CPU_VID0<5>
CPU_VID1<5>
CPU_VID2<5>
CPU_VID3<5>
CPU_VID4<5>
CPU_VID5<5>
CPU_VID6<5>

DPRSLPVR<7,20>

H_PSI#<5>

PGD_IN<31>

VR_ON<31>

PR149
0_0402_5%

PR150
10_0402_1%@

PR153

0_0402_5%

PR128

4.22K_0402_1%

12

0.022U_0402_16V7K

12

12

12

12

PR155
180_0603_1%

PC128

0.022U_0402_16V7K

1 2

PC132
220P_0402_50V7K

PR127

150K_0402_1%

PC116

PR131

0_0402_5%

PR133

0_0402_5%

PR135

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

N45

1 2

PC126
1800P_0402_50V7K

1 2

N56

12

PR139

PR142

PR146

12

PH1
470KB_0402_5%_ERTJ1VR103J

PR130

0_0402_5%

12

PR132

0_0402_5%

12

PR134

0_0402_5%

12

PR137

0_0402_5%

12

499_0402_1%

12

0_0402_5%

12

0_0402_5%

PC120

1000P_0402_50V7K

0.082U_0603_25V7K

PC121
1000P_0402_50V7K

N34

PR157

1 2

1.2K_0402_1%

N57

PR160

68.1K_0402_1%

PC133
1000P_0402_50V7K

PR164

6.98K_0402_1%

+5VS

12

PC104

1U_0603_10V6K

5

VCC

6

FCCM

2

PWM

3

GND

9

+5VS

12

PC115

1U_0603_10V6K

5

VCC

6

FCCM

2

PWM

3

GND

9

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

BOOT
UGATE
PHASE

LGATE

Thermal

BOOT
UGATE
PHASE

LGATE

Thermal

PR117

2.2_0603_5%

N36 N37

1
8
7
4

PU10
ISL6208CRZ-T_QFN8

2.2_0603_5%

N38 N39

1
8
7
4

PU12
ISL6208CRZ-T_QFN8

4

PC105

0.22U_0603_16V7K

1 2

12

12

PR235
0_0603_5%

6208A_LG

PR129

12

PR237
0_0603_5%

0.22U_0603_16V7K

1 2

12

6208B_LG

PC117

2006/04/03 2007/04/03

6208A_UGA6208A_UG

5

4

6208B_UGA6208B_UG

5

4

Compal Secret Data

5

S

4

2

D8D7D6D

PQ23

S1S2S3G

5

4

D8D7D6D

S1S2S3G

Deciphered Date

SI4856DY-T1-E3_SO8

2

PQ26

D8D7D6D

PQ22

S1S3G

SI4684DY-T1-E3_SO8

5

4

D8D7D6D

PQ25

S1S3G

S

SI4684DY-T1-E3_SO8

5

4

SI4856DY-T1-E3_SO8

3

12

12

PC100

PC101

0.1U_0603_25V7K
2200P_0402_50V7K

5

D8D7D6D

PQ43

S1S3G

S

4

2

SI4684DY-T1-E3_SO8

CPU_PHASE1

D8D7D6D

PR119

4.7_1206_5%

1 2

PQ24

S1S2S3G

N42

SI4856DY-T1-E3_SO8

12

PC108
680P_0603_50V8J

5

D8D7D6D

PC111

PQ45

S1S3G

S

4

2

SI4684DY-T1-E3_SO8

CPU_PHASE2

D8D7D6D

PR138

4.7_1206_5%

1 2

PQ27

S1S2S3G

N43

SI4856DY-T1-E3_SO8

12

PC119
680P_0603_50V8J

12

PC102

10U_1206_25V6M

12

PC112

0.1U_0603_25V7K
2200P_0402_50V7K

12

PC103

10U_1206_25V6M

0.36UH_MPC1040LR36_24A_20%

PR120
10K_0402_1%

1 2

PR122

5.11K_0603_1%

1 2

VSUM

12

PC113

10U_1206_25V6M

1 2

VSUM

2

PL8

HCB4532KF-800T90_1812

1 2

1

+

2

PL9

1 2

12

PC107

0.22U_0603_16V7K

12

PR123
NC@

+CPU_B+

12

12

PC114

10U_1206_25V6M

PL10

0.36UH_MPC1040LR36_24A_20%

1 2

PR140
10K_0402_1%

1 2

PR143

5.11K_0603_1%

Title

Size Docu me n t N u m ber Re v

C

Date: Sheet

+CPU_CORE

PC118

0.22U_0603_16V7K

PR144
NC@

5

D D

BATT++ BATT+

4

3

2

1

Battery Connect/OTP

BATT+

12

PC175

0.01U_0402_25V7K

EC_SMD_1 <31,32>
EC_SMC_1 <31,32>

BATT_TEMP <31>

+3VALWP

PC177

0.22U_0603_16V7K

CPU

12

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
Recovery at 50 +-3 degree C

VL

12

PH3
100K_0603_1%_TH11-4H104FT

N53

12

PR210
0_0402_5%

PR211
215K_0603_1%

N52

1 2
1 2

VL

PR212
470K_0402_1%

12

PR213
20K_0603_1%

470K_0402_1%

PR214

N54

OTPREF

12

PR208
470K_0402_1%

1 2

3

+

2

-

12

PC178
1000P_0402_50V7K

VS

8

PU17A

P

O

G

LM393DR_SO8

4

12

PC176

0.1U_0603_25V7K

1

VS

VL

<34,36>

MAINPWON

12

PR209
470K_0402_1%

13

N55

2

G

D

PQ40
2N7002LT1G_SOT23-3

S

1 2

PR206

1K_0402_1%

1 2

PR207

6.49K_0402_1%

12

BATT_TEMP

PL15
HCB4532KF-800T90_1812

12

PC174
1000P_0402_50V7K

PCN2

1

BATT+

SMD
SMC

Res

8

Temp

C C

G

7

GND6G

SUYIN_200045MR006G110ZR

SMD

2

SMC

3
4

TS

5

PR204

100_0402_5%

1 2
1 2

PR205

100_0402_5%

PJPB1 battery connector

SMART
Battery:

1.BATT+

2.SMBD

3.SMBC

4.Res

5.Temp

6.GND

B B

8

PU17B

5

P

+

7

O

6

-

G

LM393DR_SO8

4

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/04/03 2007/04/03

Compal Secret Data

Deciphered Date

Title

Battery Connect/OTP

Size Document Number Rev

Custom

2

Date: Sheet of

1

40 40Thursday, July 27, 2006