Hitachi TV CP-2896 Schematic

CP2896TA

SERVICE MANUAL

VORSICHT:

Data contained within this Service

Verbesserungen

ä

ndern.

MANUEL D’ENTRETIEN
WARTUNGSHANDBUCH

CAUTION:

Before servicing this chassis, it is important that the service technician read
the “Safety Precautions” and “Product Safety Notices” in this service manual.

ATTENTION:

Avant d’effectuer l’entretien du châassis, le technicien doit lire les
«Précautions de sécurité» et les «Notices de sécurité du produit» présentés
dans le présent manuel.

No. 0103

CP2896TAN
CP2996TA
CP2996TAN

manual is subject to alteration for
improvement.

Les données fournies dans le
présent manuel d’entretien
peuvent faire l’objet de
modifications en vue de
perfectionner le produit.

Vor Öffnen des Gehäuses hat der Service-Ingenieur die „Sicherheitshinweise“
und „Hinweise zur Produktsicherheit“ in diesem Wartungshandbuch zu lesen.

TECHNICAL SPECIFICATIONS

TV System.............................PAL/SECAM B,G

NTSC 3.58/4.43 MHz via Scart

Mains voltage........................210..240 V, 50Hz

Power consumption................................135W

Standby power consumption...................0.2W

Picture tube

2896 TAN,2896 TA 71cm

2996 TAN,2996 TA 74cm

Sound output (RMS) ..................... 2 x 10W/8Ω

Connections

Front panel

Headphones 32..600Ω, 3.5mm
Audio/Video Audio in: 0..2V (RMS)

Video in: 1V/75Ω

Y/C in (SVHS)

Rear panel

A/V Audio in: 0..2V (RMS)

Audio out: 0..2V/10k (RMS)

Video in/out: 1V/75Ω

RGB in: 0.7V/75Ω (E1)

Y/C in: (SVHS)(E2)
Loudspeakers min 10W/8Ω (RMS)
Aerial 75Ω
Audio output 0..2V/10k (RCA)

SPÉCIFICATIONS TECHNIQUES

Systéme TV...........................PAL/SECAM B,G

NTSC 3.58/4.43 MHz via Scart

Tension secteur.....................210..240 V, 50Hz

Consommation .......................................135W

Consommation en veille...........................0.2W

Tube-image

2896 TAN,2896 TA 71cm

2996 TAN,2996 TA 74cm

Sortie sonore (RMS).........................2 x 10W/8

Connexions

Sur le panneau avant

Ecouteurs 32..600Ω, 3.5mm
Audio/vidéo Entrée audio:0..2V(RMS)

Entrée video: 1V/75Ω

Entrée Y/C: (SVHS)

Sur le panneau arrière

Audio/video Entrée audio:0..2V(RMS)

Sortie audio: 0..2V/10k (RMS)

Entrée vidéo/out: 1V/75Ω

Entrée RGB: 0.7V/75Ω (E1)

Entrée Y/C: (SVHS)(E2)
Haut-parleurs min 10W/8Ω (RMS)
Antenne 75Ω
Sortie audio 0..2V/10k (RCA)

Die in diesem Wartungshandbuch
enthaltenen Spezifikationen
können sich zwecks

TECHNICAL SPECIFICATIONS

TV-Norm................................PAL/SECAM B,G

NTSC 3.58/4.43 MHz via Scart

Netzspannung.......................210..240 V, 50Hz

Leistungsaufnahme.................................135W

Leistungsaufnahme im standby-modus...0.2W
Bildröhre

2896 TAN,2896 TA 71cm

2996 TAN,2996 TA 74cm

Tonleistung (RMS)......................... 2 x 10W/8Ω

Anschlüsse

An der Vorderseite

Kopfhörer 32..600Ω, 3.5mm
Audio/Video Audio ein: 0..2V (RMS)

Video ein: 1V/75Ω

Y/C ein (SVHS)

An der Rückseite

Audio/video Audio ein: 0..2V (RMS)

Audio aus: 0..2V/10k (RMS)

Video ein/aus: 1V/75Ω

RGB ein: 0.7V/75Ω (E1)

Y/C ein: (SVHS)(E2)
Lautsprecher min 10W/8Ω (RMS)
Antenne 75Ω
Audio-Ausgang 0..2V/10k (RCA)

December 1998

2

Technical data

Technische Daten

Données téchniques

System

NTSC

Mains power

Consumption

1)

In stand-by

Frequency range

Sound output (RMS)

Subwoofer

2)

Connections on the front
panel

Headphones
Audio/Video

Connections on the rear
panel

Audio/Video

External loudspeakers

Antenna

Audio output

2)

Norm

NTSC

Netzanschluß

Leistungsaufnahme
Im Bereitschaft

Frequenzbereich

Tonendstufe (RMS)

Subwoofer

2)

Anschlüsse an der
Vorderseite

Kopfhöreranschluß
Audio/Video

Anschlüsse an der
Rückseite

Audio/Video

Externe Lautsprecher

Antennenanschluß

Audio Ausgang

2)

Systéme

NTSC

1)

Alimentation

Consommation

1)

En mode veille

Gamme de fréquences

Sortie sonore (RMS)

Subwoofer

2)

PAL/SECAM B, G

3.58/4.43 MHz via Scart

210...240 V, 50 Hz
135 W (normal)

0.2 W

48.25 - 855.25

2 x 10 W/8 Ω
14 W/16 Ω

Connexions sur le
panneau avant

Ecouteurs
Audio/Vidéo

32...600 Ω , 3.5 mm
Audio in: 0...2 V (RMS)
Video in: 1 V/75 Ω
Y/C in (SVHS)

Connexions sur le
panneau arrière

Audio/Vidéo

Audio in: 0...2 V (RMS)
Audio out: 0...2 V/10 kΩ
(RMS)
Video in/out: 1 V/75Ω
RGB in: 0.7 V/75Ω (E1)
Y/C in (SVHS) (E2)

Haut-parleurs externes

Antenne

Sortie audio

2)

min 10 W/8 Ω (RMS)

75 Ω

0...2 V/10 kΩ (RCA)

Specifications are subject
to change.

1)

Depends on option
modules and picture tube.

2)

Not in all models.

Änderungen vorbehalten

1)

Abhängig von
Optionsmodulen und
Bildröhre.

2)

Nicht in allen Modellen.

Les Spécifications
peuvent êt re modifiées
sans préavis.

1)

Dépend des modules
option-nels et du tube
cathodique.

2)

Pas sur tous les modèles.

15

20, 22, 24

19

10-12

13

fb

2-4

1

fb

bcl

BC

8

6

7

ICt1

ICr2

44-46

18-27

ICr1

47

BLAN

141312

Y

ICd1

25

26

V

U

ICd3

423

1

RGB + fb

1718161514

C

CVBS/Y

C

ICq1

OUT

OUT

13

3

11

IN

IN

CVBS/Y

5, 6

IN

8, 10

IN

2H

2V

14

sc

17

11

HA

VA

10

SSc

D1D0D2

D3

32

33

34

35

I/O2

I/O1

I/O3

I/O4

2

1

24

25

9

CVBS

3

2V

4

2H

A0-A9

RGB

ICs1

Mk1

DATA IN

DATA OUT

WS

L

R

CL

L, R

L, R

L, R

AM

SIF

R, L

R, L

L

R

3D/Pro Logic

module

AR7xx

4

6

1

7

ICa1

29

28

26

25

9

1

ICa2

2

6

33, 34

36, 37

46, 47

49, 50

52, 53

55

60

141312

11

5

6

7

8

SOUND BLOCK

CRT module

HH7xx

ICh3

ICh2

ICh1

R

G

B

6

5

4

9

7

BC

SVM

module

VMxxx

PIP

module

PP7xx

RGB

RGB

IQTV2

&

DPLL

DB7xx

Flyback

EW

Ver

Ver

Hor

sc

111412

16

Comb filter

module

CF7xx

V

Y

U

11

10

67

13

15

14

18-21

Scart 1

3435333738

Camera

Scart 2

Scart 1

RF BLOCK

PIP

module

109

C

CVBS/Y

11 12

Scart 2

Scart 2

RGB

2H

2V

27 26

24

TELETEXT

VIDEO BLOCK

Adjustable

audio

Scart 1

Camera

Scart 3

VGA

Scart 2

Scart 1

17

Y

Tk3

SWxxx

U1

12V

22

17

20

19

18

12

11

1

9

2

Scart 1

26

Y

SVM coil

Diode

modulation

Dk7, Dk8

Tk4,ts1,ts2

5

Vertical

deflection

yoke

Horizontal

deflection

yoke

Line

driver

Tk1, Tk2

Vertical

deflection

and

E-W driver

Horizontal

deflection

5,9-12,14-18

MSP3410D

Audio

processor

TDA9143

Colour

decoder

TDA4780

RGB processor

SDA5275S

Megatext

514400

Text memory

TEA6417

Video switch

TDA8354

Vertical output

TDA2616

Audio power

amplifier

TL082

Headphone

amplifier

TV-Frontend

Tuner+IF

19

18

20

PIP

CVBS

1

Scart 3

IN

IN

23

1

Fsc

clock

VGA

VGA/RGB

5

6

4

ICa4

1

9

TDA2616

Active subwoofer

amplifier

ICa3

31

SUB

Block diagram, signal routes

3

Scart-

buffers

TXT

ICr1

RAM

ICr2

Delay

ICd3

Deco/Sync

ICd1

RGB-proc.

ICt1

ROM

ICf1

NVM

ICf2

µP

ICf3

Video Switch

ICq1

HP-Ampl.

ICa3

Service

conn. &

buffer

Sound

processor

ICa2

Frontend

PIF SIF

TV-

Tuner

ICo6

Rec

ICo3

Rec

5V-r

12V-r

To4

Pict

12V-p

SVM module

CRT-module

8V-p

FEATURE BOX

32

30

8V-p

Comb-Filter

3

4

PIP-module

Decoder

ICp3

µP, ICp6

&

A/D, ICp5

13

12V-p

7V-fb

8V-p

12V-p

7

28

5

5V-r

Amplifiers

Digital Sound

Processor

5V-r

12

1

28V

ICo4

12V-r

10V

5V-stb

Control module

IR-

receiver

8

10

6

12V-p

5V-stb

Loudspeaker

Amplifier

ICa1

PP7xx

Rq48

AR7xx

FC7xx

CF7xx

20

22

23

24

15

17

18

14

21

19

3

4

ICo2

3

2

11

5

ICo1

6

16

1

14

Ro8,

14

Do8

Co10

Do2

Do1

Do4

Do3

Ro4, 10

Ro15

Ro18, 19

21, 22

To1

Ro70

Co15

230V

50Hz

Ftc1

Fo1

Do12

Do11

Do9

Do13

U1

32

PWM

Line

sync.

Do17

Ro32

Fo3

Fo2

Do14

Do16

Ro42

Ro45

Ro50

Do20

8

2

5

!

!

Ro44, 46

ZDk1

7V

Mains non isolated

17V

7V-fb

Ro49

Ro48

!

Mo2
!

Mo3

!

Vert.deflection

& EW driver

ICs1

Mk1

Rk2

Dk1

8

10

11

12

1

7

Rk9

Dk2

Rk19

Dk3

6.3V RMS

30kV

500V

8 kV

Rk15

Rk45

200V

53V

Rk4

!

!

!

!

!

Tk3

Rk20

!

16V

SWxxx

Rk11, 12

13, 14

HH7xx

Line

driver

12V-p

12V-p

12V-p

!

7V

G2

Focus

Heater

5

4

3

6

12V-p

8V

Ra18

AUX

module

12V-p

TA700

And

ICf4

Reset

ICf5

Subwoofer

Amplifier

ICa4

I

2

C Switch

11

30V

2

30V

Rq54

Rq2

Tq5

8.5V

Rr18

Scart 3 module

TA710/711

4

10

Tuner

To15

To9

Cfc23

FC7xx

Control module

Start

ICfc1

ICfc2

2

1

47

14

Cfc24

Cfc26

Dfc11

Hfc2

3

Zdo1,To8

RGB

Switch

ICp7

I

2

C Switch

ttp5

IF

ICp1

Delay-line

ICp4

DB7xx

SR7xx

Cancellor

VMxxx

Defl. ctrl

IC17

Filters

5V

3V

IC1

DSP

IC4

IQTV

4

Block diagram, power supply

Block diagram, control signals

µP

ICf3

PIP-MODULE

FEATURE BOX DB7xx

Comb-Filter

module

TV tuner

SDA

SCL

+5V

Local control

HP ind

Rec / IR

IR Receiver

TXT

ICr1

M3L

Status 2

Status 1

Status 3

Hold

Surround

processor

ICar2

Sound

processor

ICa2

Deflection

IC 17

IQTV µP

IC 18

Deco/Sync

ICd1

Subwoofer

mute

5

MSP Reset

Bypass /

Comb-ID

NTSC

RGB processor

ICt1

Video Switch

ICq1

NVM

ICf2

PIP µP

ICp6

Deco/Sync

ICp3

Video switch

PIP/ext. RGB

Service

connector

545352

7

50

1

61 62

46

64

44, 45

4, 59, 60

AUDIO FEATURE BOX

17, 18

5, 6

8, 9

17, 18

5, 6 2, 4 27, 28

9, 10

49, 50, 51

51, 61

85

DPLL

IC 11

40, 41

9,10

24

40,41

3, 4

1, 2

3

PIP tuner

IF

ICp1

L-norm

15

16

37

38

VGA

1/2 FM

Bridges:

Mute

2

7

E3-control

(3-state)

&

APSi

test

Subwoofer

ident.

RGB

status

Line-out

status

6

3

FRONTEND

Multi: Strobe to write I/O-latch

Single: APSi control

IF ident.

resistor

APSi filter/Strobe

Strobe

APSi

(Single norm)

47

55

IF Ident.

15

16

23

13

2

1

5, 6

FSC /

SVHS

263

AV-link

PWM

Scart pin 10

16:9 ident.

51

12Vp

PA-mute

&

OR

28V

PA

PA

mute

mute

Subwoofer

Int-LS

15

4

I

2

C

I

2

C

DSP Reset

12V

4, 57, 8

10

A/D

Hor. shift

5

A/D

A/D

A/D

4, 5

8

8

ΤΑ700

8,9

Picture tilt

PWM

1

)

1

)

1

)

If no mux. and

picture tilt

mux.

ΤΑ710

Upict

Urec

U

49

48

Start

Rec-on

Pict-on

11 = Off

00 = TV

01 = Record

10 = Service

3

5

MULTI CONCEPT
MX/MZ-CHASSIS

G Functional description

2

C

I

4, 57, 8

APSi filter/Strobe

Scart pin 10

Strobe
APSi

RGB status

FRONTEND

Multi: Strobe to write I/O-latch
Single: APSi control

(Single norm)

IF Ident.

Line-out
status

Rec / IR

IF ident.
resistor

47

55

3

6

HP ind

10

+5V

A/D

1

TV tuner

AV-link

µP

ICf3

61 62

Local control

263

46

64

Subwoofer

ident.

16:9 ident.

MSP Reset

50

PWM

SDA
SCL

A/D

A/D

A/D

M3L

4, 59, 60

49, 50, 51

TXT
ICr1

PA-mute

51

5

44, 45

54

53

52
7

Sound

processor

ICa2

24

12Vp

APSi
test

Hor. shift

Status 2

Status 1

Status 3
Hold

7

E3-control

9, 10

&

(3-state)

4

5

12V

28V

DSP Reset

Subwoofer
mute

&

Comb-Filter

module

13

Bypass /
Comb-ID

15

Deco/Sync

Service

3

connector

OR

mute

2

NTSC

16

ICd1

5, 6

1, 2

PIP-MODULE

Video switch

PIP/ext. RGB

mute

1

FSC /
SVHS

23

T V

1997

AUDIO FEATURE BOX

15

85

PA

Subwoofer

Mute

Int-LS

PA

FEATURE BOX DB7xx

Deflection

40,41

2

I

C

5, 6 2, 4 27, 28

NVM

ICf2

PIP tuner

16

Deco/Sync

15

ICp3

Surround
processor

2

IC 17

17, 18

40, 41

DPLL

IC 11

Video Switch

ICq1

L-norm

8

4, 5

5, 6

ICar2

37

38

Bridges:

1/2 FM

VGA

8

PIP µP

IQTV µP

IC 18

RGB processor

ICp1

ICp6

51, 61

IF

17, 18

9,10

8, 9

ICt1

3, 4

IR Receiver

6611 72 76

Contents

MICROPOWER CONTROL.........................................................................................................................................................1

POWER SUPPLY ........................................................................................................................................................................ 2

RECEPTION ................................................................................................................................................................................4

AUDIO SECTION........................................................................................................................................................................5

Multistandard Sound Processor, ICa2................................................................................................................................ 5

Audio Power Amplifier, ICa1...............................................................................................................................................6

Headphone Amplifier, ICa3 .................................................................................................................................................6

VIDEO SECTION ........................................................................................................................................................................7

Video Matrix Switch, ICq1...................................................................................................................................................7

Colour Decoder / Sync Processor, ICd1 .............................................................................................................................7

Baseband Delay Line, ICd3 ................................................................................................................................................. 8

Feature boxes, DB7** .........................................................................................................................................................9

Feature box DB711 ..............................................................................................................................................................9

Analog to digital converter, ic9...........................................................................................................................................9

Field memory, ic14 ............................................................................................................................................................10

IQTV2 circuit, ic18 ..............................................................................................................................................................10

DPLL1 circuit, ic11 .............................................................................................................................................................11

Deflection Controller TDA9151, IC17 ...............................................................................................................................11

Feature box DB710 ............................................................................................................................................................ 12

Feature box DB700 ............................................................................................................................................................ 12

RGB Video Processor TDA4780, ICt1 ............................................................................................................................... 13

CRT module........................................................................................................................................................................14

Teletext ...............................................................................................................................................................................15

Megatext SDA5273, ICr1 ...................................................................................................................................................15

Megatext Plus SDA5275, ICr1 ...........................................................................................................................................15

Teletext memory DRAM, icr2 ............................................................................................................................................15

29

CONTROL SYSTEM ................................................................................................................................................................. 16

Program memory, ICf1...................................................................................................................................................... 16

NV RAM, ICf2 ..................................................................................................................................................................... 16

Microcontroller, icf3........................................................................................................................................................... 16

AND gate, icf4 ....................................................................................................................................................................17

Reset circuit, icf5................................................................................................................................................................ 17

DEFLECTION STAGES............................................................................................................................................................. 19

Vertical deflection ..............................................................................................................................................................19

Horizontal deflection ......................................................................................................................................................... 19

OPTIONS ..................................................................................................................................................................................21

Active Subwoofer ..............................................................................................................................................................21

Comb Filter module, CF700 .............................................................................................................................................. 21

Scan Velocity Modulation module, VM600 .....................................................................................................................22

Audio Feature modules, AR700 and AR701 .................................................................................................................... 23

Adjustable Audio Output module, TA700 ........................................................................................................................27

Scart 3 + VGA-audio module, TA710 ...............................................................................................................................27

Scart 3 module, TA711 ......................................................................................................................................................27

Picture in Picture module, PP700 ..................................................................................................................................... 27

Picture in Picture module, PP710 ..................................................................................................................................... 28

MICROPOWER CONTROL

1

General

The power supply is equipped with a micropower system
in order to reduce the standby power consumption to about
<200 mW (generally about 5 to 7W). To make this possible,
the power supply and degaussing circuitry must be totally
switched off in standby mode.
The only active part in standby mode is the micropower
circuitry which gets its supply voltage from a capacitive
coupled rectifier. This provides the supply voltage for re­quired circuits, like a “primary” infrared receiver and a gate
circuit. When the TV set is switched on with the mains
switch or with a remote control command, the gate circuit
drives a triac switch to conduct, thereby supplying the
mains voltage to the power supply. At the same time, the
micropower circuit controls the main microcontroller via
optocouplers.
The micropower circuitry is not mains isolated.

Start up via the mains switch

The mains voltage is fed directly to the micropower circuit
which is located on the local control panel.
The circuitry gets its supply voltage from the capacitive
coupled rectifier consisting of capacitors Cfc24/26, resis­tors Rfc23/24 and diodes Dfc6...Dfc9. The supply voltage is
regulated to +5.1 V by zener diode DZfc1 and fed onwards
to the infrared receiver Hfc2, NAND gate ICfc1 and LED
Dfc16, that indicates the mains voltage is connected.
The TV set can be switched on by firmly pressing the mains
switch. An additional contact in the mains switch causes a
low level pulse on pins 12/13 of the NAND gate. Due to the
effect of the NAND gate, pin 11 as well pins 1/2 are high
and pin 3 is low. Moreover, pins 5/6 go low via diode dfc13
and pin 4 is high.
Transistor tfc1 conducts and grounds the cathode of the
internal LED of the optocoupler ICfc2. The optocoupler then
conducts, feeding the mains voltage via resistor Rfc27 to
the gate of triac Dfc11. The triac’s gate gets sufficient start­ing voltage via Rfc27, after which resistor Rfc26 is con­nected in parallel with Rfc27 to keep the triac in a conduct­ing state. Thus the mains voltage is available for the power
supply.
Furthermore, when the TV set is started up with the mains
switch, a low level on pin 3 causes transistor tfc6 to con­duct. Also the optocoupler ICfc4 conducts grounding the
cathode of diode dfc18. This indicates to the microcontroller
that the TV set is being powered on via the mains switch.
Because the additional contact causes only a momentary
low on pins 12/13, capacitor Cfc31 discharges and pins 12/
13 go high. Because of this, both transistor tfc6 and
optocoupler ICfc4 stop conducting.
The power supply then generates the supply voltages, the
microcontroller is reset, and its pins 48 (Pict_on) and 49
(Rec_on) go low. This causes optocoupler ICfc3 to conduct
holding pins 5/6 low in order to keep triac Dfc11 conduct­ing.
If the mains switch is not pressed firmly, the additional
contact may not close for a long enough time and the TV
set may remain in standby mode.

Start up / switch off by the remote control

The TV set must, of course, be in standby mode. This means
the optocoupler Icfc3 does not conduct, voltage level on
pins 5/6 is high and capacitor Cfc28 is charged via rfc29.
When the remote control command is given, pulses on pin
3 of the “primary” IR receiver discharge capacitors Cfc28.
Thus pins 5/6 of the NAND circuit go low via diode Dfc12,
and the mains triac starts to conduct. The command must
be sufficiently long that the power supply has time to gen­erate supply voltages, the microcontroller has time to be
reset and to receive the start command from the “second­ary” IR receiver. After that, pins 48 (P_on) and 49 (Rec_on)
of the microcontroller go low and optocoupler ICfc3 con­ducts and holds pins 5/6 of the NAND gate low.

When the TV set is switched off by the remote control, pins
48 (P_on) and 49 (Rec_on) of the microcontroller go high.
Therefore all Vp and Vr voltages will be switched off (hori­zontal and vertical stages are switched off), the optocoupler
ICfc3 will not conduct causing pins 5/6 of the NAND gate
to go high. Optocoupler ICfc2 does not conduct and resis­tor Rfc27 will be disconnected from the gate of Dfc11.
Resistor Rfc26 alone is not able to feed enough holding
voltage to the mains triac, and so the power supply will be
disconnected from the mains.

2

POWER SUPPLY

General

The power supply is a mains isolated Switched Mode Power
Supply (SMPS). Mains isolation is provided by transformer
Mo2. The mains voltage is full wave rectified by diodes
Do1...Do4 and filtered by capacitor Co10. This filtered volt­age is fed to the switching transistor To1 (MOSFET) via the
primary winding 11 and 5 of the mains transformer. Dur­ing the conduct period of To1, energy is stored in the pri­mary winding 11 and 5. When transistor To1 is switched
off, energy flows to the secondary windings. These pulses
are rectified by secondary diodes Do11...14 and Do16.
The following supply voltages are available from the sec­ondary diodes:

+130 V horizontal output stage
+28 V audio amplifier, subwoofer and audio feature

module

+17 V +12 V regulator IC, horizontal driver and +8 Vp

regulator transistor
+7 Vfb feature box
+7 V +5 Vr regulator IC, +5 Vstb regulator IC and +7 V

supply voltage

Note! The voltage levels may vary depending on the pic­ture tube. More detailed values are given in the schematic
diagrams.

The power supply is designed to operate with a master­slave structure, where the power supply controller ICo1
operates as a slave and the secondary controller ICo2 as a
master. The power supply operates in the following ways
in different operation states:

Start up phase:

Power supply is in the primary regulation mode (burst
mode). Power supply controller ICo1 generates independ­ent drive pulses for switching transistor.

Normal on mode:

Power supply is in the secondary regulation mode (mas­ter-slave mode). Secondary controller ICo2 generates drive
pulses for power supply controller ICo1. The secondary
controller is synchronized to the line flyback pulses.

Recording mode:

Power supply is in the secondary regulation mode (mas­ter-slave mode). Secondary controller ICo2 generates drive
pulses for power supply controller ICo1. The secondary
controller is synchronized to the free running frequency of
an internal oscillator.

Switching off to standby phase:

Power supply is in the primary regulation mode (burst
mode). Power supply controller ICo1 generates independ­ent drive pulses for switching transistor.

Standby mode:

Due to the micropower control, the power supply is com­pletely without voltage.
The power supply also has a so-called Service standby
mode. The receiver is in service standby mode when it is
set to the service mode by pressing the buttons -vol / menu,
TV and i, but has not yet been switched on by pushing the
TV button twice. In this mode, the power supply operates
(burst mode), but the Vr and Vp voltages are not available.

Start up

After switching on with the mains switch and when triac
Dfc11 (on the micropower control) conducts, capacitor Co15
is charged via resistors Ro9, Ro11, Ro70 and thyristor To15.
When the start up voltage on pin 16 of ICo1 reaches the
switch-on threshold level, that is typically +11.8 V, the IC
starts to operate.
The supply voltage of ICo1 is then taken from the second­ary winding pin 3 via half wave rectifier diode Do8. The
same winding pin 3 supplies pulses to diode Do9. This
voltage drives transistor To9 to conduct putting the gate of
thyristor To15 to ground, and thus switching off the start
up voltage.
The same DC voltage that is taken from the cathode of di­ode Do9 is used for power supply regulation. The DC volt­age is fed via the filter network Ro26, Co28 and Ro24 to the
error amplifier input pin 6. The error amplifier compares
the input voltage with the internal reference (+2.5 V) and
varies the burst time. Resistors ro4 and ro10 set the volt­age to the proper level.
Furthermore, a possible magnetization state of the trans­former can be checked by sensing the voltage across the
winding pins 3 and 2. This information is fed via resistor
Ro15 to pin 1 of ICo1, and if the specified level is exceeded,
the output pulses can not be generated.
To avoid magnetization during the start up phase, the op­eration will be started with the internal oscillator’s operat­ing frequency divided by four, until voltage on soft start
pin 9 reaches a level of +2.5 V. The operating frequency of
the oscillator is set to 27 kHz by capacitor Co16 on pin 10
and resistor Ro3 on pin 11.

Drive of the switching transistor

Pin 14 outputs square wave pulses to the gate of switching
transistor To1. Resistors Ro2 and Ro13 limit the gate cur­rent. To1 conducts during the positive going pulse and drain
current flows through the primary winding pins 11 and 5.
The clamping circuit Do6, Co11 and Ro16 limits the volt­age spikes, when To1 is switched off. The source of To1 is
connected to ground via current limiting resistors Ro18,
Ro19, Ro21 and Ro22. Information about the current is fed
to pin 3 of the power supply controller.

After the start up phase, when supply voltages are gener­ated, the power supply moves from primary regulation
mode to secondary regulation mode. The microcontroller
will be reset and it’s pins 48 (P_on) and 49 (R_on) will go
low. The R_on line allows, via transistor to6, regulator ICo3
to feed +12 Vr out. This voltage is fed to the secondary
controller ICo2 (pin 2) and the IC starts operation.
The capacitor co58 on pin 1 operates as a soft-start capaci­tor causing the duration of soft-start to be around 20ms.

The free running frequency of an internal oscillator is set
to 32 kHz by capacitor co72 on pin 7 and resistor Ro37 on
pin 8. In normal operating mode, the oscillator is synchro­nized using the line flyback pulses via differentiator Ck6,
resistor ro38 and diode Do18.
In recording mode, the Vp voltages are switched off and
therefore the line flyback signal is not available. In this case,
the oscillator is in free running mode.

The internal pulse width modulator is controlled by com­paring the input voltage level on pin 5 with the oscillator’s
sawtooth pulses. Pin 5 is connected to +140 V via resistor

network Ro46, Ro44, Ro50, Ro45 and Ro42. By adjusting
the trimmer potentiometer Ro45, the output voltages of
the power supply can be controlled.
In order to avoid excessive decreasing of +7 V during re­cording mode, diode Do20 is connected from the above
mentioned resistor network to +7 V. If the voltage level
drops too far below +7V, the diode conducts causing a lower
voltage level on pin 5. The controller then generates wider
pulses from the output pin 3 and the supply voltages of
the power supply will be increased.
The width modulated drive pulses are output from pin 3
via the pulse transformer Mo3 to power supply controller
pin 2. The rising edge of the drive pulse causes the switch­ing transistor to conduct and the falling edge, which is syn­chronized to the line flyback pulse, switches off the tran­sistor.
This arrangement prevents disturbances caused by the
switching-off time of the transistor from upsetting the
screen display.

Under / over voltage detection

The power supply controller has an internal monitor for
both under and over supply voltage on pin 16. The under
voltage threshold level is typically +8.5 V. Lower voltage
levels disable the output pulses.
The over voltage threshold is typically +15.7 V. Higher volt­age levels disable the output pulses.
Restarting requires that the voltage level on pin 16 is first
decreased below +8.5 V and then increased to +11.8 V,
unless the voltage level across capacitor Co22 has reached
+2.5 V. In this case, circuit operation is completely stopped.

3

tor to7 conducts and transistor to4 is switched off.
The +12 Vp and +8 Vp voltages are absent, and therefore
the horizontal deflection stage will not operate.

ICo6 regulates +5 Vr, which is available in normal and re­cording modes, but not in service standby mode.

The tuning voltage +30 V for the tuner is regulated from
+130 V. The circuitry is located in the horizontal output stage
consisting of resistors Rk11...Rk114 and zener diode ZDk1.

Current limitation

As mentioned above, the source of the switching transis­tor is connected to ground via resistor network Ro18/19
and Ro21/22. The measured result is fed to input pin 3 of
ICo1. A double threshold system is used, first limitation
level (+0.6 V) against momentary overloads and a second
limitation level (+0.8 V) against very strong overloads.
When the first threshold level is reached, the switching tran­sistor stops conducting until the end of the period, and a
new pulse is needed to start it conducting again. During
the first threshold period, capacitor Co22 is charged. If the
voltage level across Co22 reaches +2.5 V, the output will
be disabled. This system is called “repetitive overload pro­tection”. However, if the overload subsides before +2.5 V
is reached, capacitor Co22 will be discharged and normal
operation will continue.
If a very powerful overload causes the second threshold
level to be reached, the output will immediately be disa­bled.
If the power supply stops because the first threshold has
been exceeded, it can be restarted by decreasing the sup­ply voltage on pin 16 below +8.5 V and then increasing it
to +11.5 V.
If, however, the power supply stops due to exceeding the
second threshold, the circuit is stopped completely and can
only be restarted with mains switch.

Regulators / voltage switches

ICo4 regulates the +5 Vstby, which is always available when
the power supply is operating . Due to the micropower
system, there are no voltages available in standby mode.

ICo3 regulates the +12 Vr and +12Vp supply voltages. The
+12 Vr is available in normal and recording modes, but not
in service standby mode.

The +12 Vp can be switched off in recording mode by the
microcontroller. In this case the P_on line is high, transis-

4

RECEPTION

Tuner / IF

The tuner is known as a “front end” type tuner. This is
because the tuner block and IF block are both combined
into one complex module pack. Channel tuning is based
on a frequency synthesis system with a frequency range
of 48.25 MHz up to 855.25 MHz including cable and
hyperband channels.
In multistandard sets, both blocks are IIC-bus controlled.
The IIC-bus of the IF block has only one-way data traffic.
In BG standard sets, the IF block has no IIC-bus interface.

Multistandard IF block

The filter SAW501 operates as a picture signal filter. The
video IF signal is input to pins 28 and 29 of the Picture /
Sound Detector circuit, IC501.
The filters SAW502 (BG, DK, I, Nicam L) and SAW503
(Nicam L’, L/L’ AM) operate as sound signal filters. Stand­ard selection takes place by diodes D501 and D502 and
transistors T502 and T503. Transistors are driven via pin 7
of the IIC-bus expander (IC502). Sound IF signals are input
to pins 31/32 (BG, DK, I, Nicam L), 1/2 (Nicam L’) and 4/5
(AM L/L’) of the detector circuit.

The AGC adjustment is implemented by potentiometer
P501 on pin 26. Pins 20 and 21 are inputs for standard
switches, which are controlled by the IIC-bus expander. The
AFC information is output from pin 11 to the tuner block
and onward to the IIC-bus. The AGC control is taken from
pin 27 to the tuner block. The tank coil of the FPLL-VCO is
connected between pins 14 and 19. This PLL reference coil
determines the stopping place of the found channel dur­ing the APSi. The VCO frequency is two times video carrier
frequency, 2 x 38.9 MHz = 77.8 MHz. For L’ standard re­quirements, the VCO frequency is switched to 67.8 MHz (2
x 33.9 MHz) using standard switches on pins 20 and 21,
and adjusted by the potentiometer P502 on pin 20.

The sound IF signal is output from pin 8 and the AM signal
from pin 7 onwards to the Multistandard Sound Proces­sor, ICa2.
The CVBS signal is output from pin 23 to the group delay
correction circuitry and amplifiers consisting of transistors
T504...514 and associated components. The CVBS signal
is then fed to the Video Matrix Switch, ICq1.

Standard pin 11 pin 13 pin 14 pin 7 pin 6 pin 5

B/G H L L L H H
I, K1 H L H H H H
D/K H H L H H H
L HHHLLL
Lí HHHHHL

Pin 11 drives input switches of IC501. Pin 11 is normally

high. During channel search (APSi), pin 11 goes
low. A low level on pins 27 and 28 of IC501
switches the video IF signal (instead of sound IF)
to the FPLL block. This is because the video band
is wider, and thus channel finding is more reli­able.

Pin 13 drives the group delay correction circuitry

Pin 14 selects the output of the group delay correction

circuitry

Pin 7 selects the correct sound IF filter

Pin 6/5 drives input switches and AM demodulator, se-

lects right modulation and VCO frequency

BG standard IF block

The BG IF block is considerably simpler than the
multistandard IF block. Only one SAW filter is used and
the IIC-bus expander, group delay correction circuitry as
well as several switching transistors are omitted.
During channel search (APSi), the microcontroller (pin 47)
drives transistor T501 to conduct. A low level on pins 27
and 28 switches the video IF signal to the FPLL block in
order to make channel finding more reliable.

Tuning

Tuning is based on the APSi system (Automatic Program
search, Sorting and channel identification). The naming and
identification of the channels takes place using either the
PDC (Program Delivery Code), VPS (Video Programming
System), NI (Nation Identification) or Teletext header. Chan­nel sorting is country dependant, and is therefore deter­mined beforehand by the software.

The circuit IC502 operates as an IIC-bus expander (8-bit
shift register). Transistors T515 and T516 disconnect the
IIC-bus from pins 2 and 3 in order to eliminate possible
malfunctions on the IIC-bus when the TV set is switched
off. Standard definition takes place via the IIC-bus. The
microcontroller sends data to the shift register, the out­puts change their state according to the data and strobe
pulse latches the outputs. The strobe pulse (high level) is
taken from the microcontroller (pin 47) to the base of tran­sistor T517 and onward to pin 1. In addition, the base re­sistor (R556) of T517 operates as an indication of the in­stalled IF module version. The value of this resistor de­pends on the module version. Pin 55 of the microcontroller
senses the voltage across this resistor and the base-emit­ter junction , and thus identifies the module version.
The data from the microcontroller determines the outputs
of IC502 according to the transmission standard as follows:

AUDIO SECTION

r

- Sound Processor

- Audio Power Amplifier

- Headphone Amplifier

Multistandard Sound Processor, ICa2

5

General

The MSP3410D is a single-chip Multistandard Sound Proc­essor which uses CMOS technology. The circuit is control­led by the microcontroller via the IIC-bus.
The sound processor performs simultaneous digital de­modulation and decoding of NICAM-coded TV stereo
sound, as well as demodulation of FM-mono TV sound. As
an alternative, a two carrier FM system (according to the
German terrestrial specs, A2 stereo), or satellite specs can
be processed by the sound processor.
All FM modulated signals over the range 0.2 MHz to 9.0
MHz can be handled.
The sound processor can select the audio signal source,
convert analog audio signals into digital form, de-empha­size in several ways - including Wegener Panda 1, 50/75 µs
and J17, perform digital FM-identification decoding and
dematrixing, and perform digital baseband processing. It
can also control the volume separately for loudspeaker and
headphones, control bass, treble, graphic equalizer and
balance, perform pseudo stereo and basewidth enlarge­ment, as well as convert digital audio signals into analog
form by using fourfold oversampled D/A-converters. This
provides an audio spectrum from 20 Hz to 16 kHz with a S/
N ratio of 85 dB.
The sound processor requires an 18.432 MHz crystal, whose
nominal free running frequency should be no more than
±1 kHz, which means a tolerance of ±0.005 %.
An audio signal to the sound processor can be taken from
the IF-section, scart 1, scart 2, or scart 3 / camera / VGA-

audio connector (or scart 4) sources. The source is inter­nally selected in the sound processor. The processed au­dio signal is fed to several outputs such as loudspeaker
amplifier / adjustable audio output module, headphone
amplifier, scart 1 and scart 2 connectors (scart 3 optional).
The circuit also has a separate output for a subwoofer
amplifier including highpass filters for the loudspeaker
outputs and lowpass filters for the subwoofer output as
integrated into the chip. The upper barrier frequency is
programmable from 50 Hz to 400 Hz in 10 Hz steps. De­pending on the programming of the upper barrier fre­quency, the lower barrier frequency for the loudspeaker
channels will also be changed automatically.
An IIS-bus interface with two data inputs is available for
optional audio feature purposes.
In some TV versions, the sound processor may be of type
MSP3400. The only difference is that MSP3400 cannot iden­tify or process Nicam signals.
The sound processor is split into three functional blocks:

- Demodulator and decoder section

- Digital signal processing section performing audio
baseband processing

- Analog section containing two A/D-converters, nine D/
A-converters and channel selection

The simplified block diagram below shows the architec­ture of the MSP3410D.

Sound IF

ANA_IN 1+

ANA_IN 2+

Mono

Mono_in

SC1_IN_L

Scart 1

SC1_IN_R

SC2_IN_L

Scart 2

SC2_IN_R

SC3_IN_L

Scart 3

SC3_IN_R

SC4_IN_L

Scart 4

SC4_IN_R

ADR-bus

Demodulator

SDA SCL

2

I C-bus Interface

Ident

A/D
A/D

2

I S1/2L/R

2

I S1/2L/R

FM1 / AM
FM2
NICAM A
NICAM B

Ident

Digital
Function
Processing

SCART_L

SCART_R

SCART Switching Facilities

LOUD­SPEAKER L

LOUD­SPEAKER R

SUBWOOFER DACM_SUB

HEADPHONE L

HEADPHONE R

SCART1_L

SCART1_R

SCART2_L

SCART2_R

2

2

I S_DA_OUT

2

I S_DA_IN2

2

I S Interface

D/A

D/A
D/A

D/A
D/A

D/A

D/A

D/A

D/A

2

I S_CL

2

I S_WSI S_DA_IN1

DACM_L

Loudspeake

DACM_R

Subwoofer

DACA_L

Headphone

DACA_R

SC1_OUT_L

Scart 1

SC1_OUT_R

SC2_OUT_L

Scart 2

SC2_OUT_R

6

The pin functions of the Sound
Processor:

ance of external speakers is 8 Ohm. When an external
speaker is used, the internal speaker is muted by a switch
in the speaker connector.

Pin I / O Short description

04 O DSP reset and off by low
05 O Subwoofer off by high
07 I Supply voltage +5 Vr
09 I I2C clock (SCL)
10 I/O I2C data (SDA)
11 O I2S clock
12 I/O I2S word select
13 O I2S data output
14 I I2S1 data input
18 Digital power supply +5Vr
19 Digital ground
20 I I2S2 data input
24 I MSP power-on-reset by low
25 O Headphone output, R
26 O Headphone output, L
28 O Loudspeaker output, R
29 O Loudspeaker output, L
31 O Subwoofer output
33 O Scart output, R
34 O Scart output, L
36 O Scart output, R
37 O Scart output, L
38 Volume capacitor (Hp amp)
39 Analog power supply +8.0V
40 Volume capacitor (Ls amp)
42 Analog ref V, high V part
43 I Scart input, L
44 I Scart input, R
46 I Camera input, L
47 I Camera input, R
49 I Scart input, L
50 I Scart input, R
52 I Scart input, L
53 I Scart input, R
54 Ref voltage IF A/D conv
55 I Mono input
57 Analog power supply +5Vr
58 I IF input 1
59 I IF input common
60 I IF input 2 (Tuner SIF)
62 I Crystal osc 18.432 MHz
63 O Crystal osc

Headphone Amplifier, ICa3

Audio signals from the sound processor are fed to the in­verting input pins 2 (L) and 6 (R). Outputs to the headphone
connector are from pins 1 (L) and 7 (R). There is a switch in
the headphone connector that informs the microcontroller
(pin 1), that headphones are connected. The headphone
volume control then appears in the OSD in addition to the
loudspeaker volume control.

Audio Power Amplifier, ICa1

The audio signal is amplified using the TDA2616 dual chan­nel hi-fi Audio Power Amplifier. The amplifier has a built­in protection system against short circuits and thermal
overloads. It also has an internal input mute circuit that
silences unwanted signals at the inputs when the TV set is
switched on or off.
Audio signals from the audio processor are fed to pins 1
(L) and 9 (R). A logical low on pin 2 mutes the amplifier.
The mute control signal is taken from the microcontroller
(pin 51) via transistors ta10, ta4 and ta3. A high level on
microcontroller pin 51 causes a so-called “central mute”,
which means that each of the audio power amplifiers are
muted.
The supply voltage +28 V is taken from the power supply
to pin 7. The amplified audio signals for the loudspeakers
are output on pins 4 (L) and 6 (R). The impedance of the
internal loudspeakers is 8 ohm and the minimum imped-

VIDEO SECTION

7

The video section is divided into the following functional
blocks:

- Video Matrix Switch / Scarts

- Colour Decoder / Sync Processor

- Baseband Delay Line

- Feature Boxes

- RGB Video Processor

- CRT module

- Teletext

Video Matrix Switch, ICq1

The TEA6417 is an IIC-bus controlled signal switch, which
makes it possible to switch 8 input sources to 6 outputs.
Each output can be connected to only one input, but one
input may be connected to several outputs. The bandwidth
is 15 MHz and nominal gain from input to output is 6.5 dB.
All switching possibilities are controlled via the IIC-bus
using pins 2 (SDA) and 4 (SCL). The circuit operates with
+10 V supply voltage, that is fed to pins 9 and 12. The +10
V is regulated from +12Vr by zener diode Zdq1.
The inputs and outputs are connected as follows:

Input Signal Source

1 CVBS Scart 3
3 CVBS Scart 1
5 C Scart 2
6 CVBS / Y Scart 2
8 CVBS / Y Cam connector
10 C Cam connector
11 CVBS Tuner
20 CVBS PIP tuner

Output Signal Target

13 CVBS / Y Decoder / Comb filter
14 C Decoder / Comb filter
15 CVBS / Y PIP module
16 C PIP module
17 CVBS / Y Scart 2
18 CVBS Teletext

The system is based on the “P50” standard and enables,
for example, transferring of channel tuning information and
EPG (Electrical Program Guide) programming.

Scart 2

In addition to the S-VHS input possibility, scart 2 is designed
to output the S-VHS signals, which are taken from the cam­era connectors. Output of the luminance signal takes place
via transistor Tq1 and chrominance via tt3 and tt2.
Scart 2 also operates as an AV-link connector.

Scart 3 (option)

Scart 3 is an optional connector having the same character­istics as scart 1.
More detailed information can be found in the section enti­tled “Options, TA710”.

Colour Decoder / Sync Processor, ICd1

General

The TDA9143 is an IIC-bus controlled, alignment-free PAL /
NTSC / SECAM decoder / sync processor.
The colour decoder is able to process CVBS as well as Y / C
signals. The internal fast switch can select either the Y sig­nal with the UV input signals, or YUV signals made up of
RGB input signals.
The sync processor provides a two level sandcastle pulse
(SC), a horizontal sync pulse (HA) and a vertical sync pulse
(VA).

Input switches

The circuit has a two pin input for the CVBS (pin 26) or Y / C
(pins 26 and 25) input signals. Selection between the sig­nals is carried out using the IIC-bus.

RGB colour matrix

The RGB signals from scart 1 (or scart 3 ) connector are fed
to input pins 19 (B), 20 (G) and 21 (R). The RGB colour ma­trix converts RGB signals into the YUV signals. The desired
input signal, between the converted YUV and decoded YUV
signals, is selected by the fast switch. This switch is con­trolled by the fast blanking signal on pin 18.

Scart 1

Scart 1 is fully connected, thus RGB input is also available
from it . In RGB mode, the fast blanking signal from scart
pin 16 is fed to the colour decoder pin 18 and via tq3, tq4,
Cq32 (and NAND gate icf4-4) to the microcontroller pin 6.
The RGB status signal is fed to the microcontroller in order
to activate the correct H-shift setting. It also enables the
colour decoder to choose the input between the RGB sig­nal and the processed YUV signals. Selection takes place
by a switch block in the colour decoder via the IIC-bus.
Scart 1 has a fixed output connection for the Tuner CVBS
from scart pin 19 via transistors tq9 and Tq2.
Scart 1 also operates as an AV-link connector. The AV-link
output is from microcontroller pin 2, onward via transistor
tq7 and scart pin 10. The AV-link input is from the same
scart pin, onward via diode dq4 and transistor tq8 to the
microcontroller pin 63. The AV-link system makes it possi­ble to transfer data between the TV set and e.g. a video
recorder.

Luminance processing

From the input pin 26, the CVBS / Y signal is fed via the Y
clamp circuit to the gyrator-capacitor type notch filters, in­cluding adjustable luminance delay and chrominance trap.
The luminance delay compensates the delay, that is caused
by the external baseband delay line for the UV signals. The
chrominance trap can be switched to 4.43 MHz (PAL / NTSC),

4.28 MHz (SECAM) or 3.58 MHz (NTSC). Switching is con-

trolled by the standard identification circuit. PAL Y, NTSC

3.58 Y (from the comb filter ) and S-VHS Y signals bypass

the chrominance notch filters in order to preserve the sig­nal bandwidth. The bypass function takes place automati­cally via the IIC-bus in S-VHS mode and in PAL / NTSC 3.58
reception, if the comb filter is installed. After the chroma
trap, the Y signal is fed to the switch stage and is output
from pin 12 to the feature box module.

8

Chrominance processing

From the input switch, the CVBS / C signal is fed through
the ACC amplifier to the chroma bandpass filters. PAL C,
NTSC 3.58 C (from the comb filter) and S-VHS C signals
bypass these bandpass filters in order to preserve the sig­nal bandwidth. The chrominance is then fed to the stand­ard identification and colour decoder stages.
The standard identification circuit is a digital circuit with
no external components. The crystals on pins 30 (refer­ence crystal) and 31 (second crystal) specify the standards
which can be decoded. The IIC-bus is used to indicate which
crystals are connected in order to allow proper setting of
the calibration circuits. The components on pin 29 form
the colour PLL filter. Pin 23 drives the multiplexer circuit
on the comb filter module to bypass the S-VHS signals in
the multiplexer (“L”) or to feed signals onwards to the comb
filter IC (“H”). In addition, pin 23 feeds out the subcarrier
frequency (Fsc) of the active crystal to the comb filter IC.
After the PAL / NTSC demodulator and SECAM
demodulator, the signals are taken to the switch stage,
which is controlled by the standard identification circuit.
Finally, the colour difference signals are output to the
baseband delay line from pins 2 (U) and 1 (V).
From the delay line, the colour difference signals are input
to pins 3 (U) and 4 (V), then onward to the switch stage
and output from pins 14 (U) and 13 (V) to the feature box
module.

Sync processing

The CVBS / Y signal is fed through the sync separator to
the horizontal PLL and to the vertical sync separator.
The main part of the sync circuit is a 432 x fH (6.75 MHz)
oscillator. This frequency is divided by 432 to lock phase
discriminator 1 to the incoming signal. The time constant
of the loop can be selected to be either fast, auto or slow
mode using the IIC-bus. The free-running frequency of the
432 x fH oscillator is determined by a digital control circuit,
which is locked to the active crystal. Components on pin
24 form the horizontal PLL. The phase loop can be unlocked
using the IIC-bus. This is to facilitate On Screen Display
information. If there is no input signal or a very noisy sig­nal, the phase loop can be unlocked to give a stable line
frequency and hence a stable OSD.
The horizontal sync pulse (HA) is fed from the timing gen­erator via output pin 17 to the Feature box.

The vertical divider system has a fully integrated vertical
sync separator. The divider can handle both 50 Hz and 60
Hz systems. It can either determine the field frequency
automatically or it can be set to the desired frequency us­ing the IIC-bus.
The divider system consists of a line counter, a norm coun­ter , a timing generator, and a controller. The system oper­ates at 432 times the horizontal line frequency. The line
counter receives enable pulses at twice the line frequency,
so that it counts two pulses per line. This count result is
fed to the controller. The controller can be in one of three
count states, norm, near-norm or no-norm. When the coun­ter is in the norm state, it automatically generates a verti­cal sync pulse (VA) from the timing generator. The VA pulse
is fed via output pin 11 to the Feature box.

Noise detector

The decoder includes an internal S/N ratio detector, which
was originally designed to control the PALplus signal proc­ess. During PALplus transmission, the detector measures
the S/N ratio of the input signal on pin 26. When the S/N
ratio is over 20dB, the signal is accepted and the helper
signal is processed in the PALplus decoder. If the S/N ratio
is below 20dB, the PALplus process is disabled, and the

signal is handled as a normal signal. The detector can be
activated / deactivated via the IIC-bus.

In the Multi Concept, this detector is used to drive the APSi
system to accept or bypass tuned channels. The detector
controls the APSi system via the IIC-bus and it works only
during the automatic channel search.
However, the limit value of the bypass criteria (fixed 20dB)
seems to be too high for this purpose and therefore the
APSi may be too sensitive and bypass channels that it could
accept.
On the other hand, if the tuning system does not include
any signal level qualification, the APSi system accepts all
multiple and very noisy channels.

Utilizing an existing detector and avoiding both above
mentioned disadvantages, an external LPF filter is imple­mented. This filter is located at the luminance / CVBS input
(pin 26) and it consists of switching transistors tq10 / tq11,
and RC filter rq85 / cq45.
The RC-coupling is designed to filter high frequencies
(noise) from the luminance / CVBS signal.
When the S/N ratio of the tuned signal on pin 26 is over
20dB, the filter is not activated, but the channel is accepted
as such and it will be memorized and named.
If the S/N ratio is below 20dB, the detector causes a high
level on output pin 16. Transistor tq11 conducts and the
RC-coupling filters noise from the signal improving the S/
N ratio at the decoder input. When this noise-filtered sig­nal is fed to the detector, it considers the S/N ratio to be
better than it actually is and accepts it. This channel will be
memorized, but not named.
In any case if the S/N ratio of the noise-filtered signal stays
below 10dB, it will be completely bypassed.
By tricking the detector in this way, the signal level qualifi­cation is reduced from an S/N ratio of 20dB to 10dB.

Sandcastle

The sync part also generates a two level sandcastle pulse
(SC) from pin 10. This pulse is used only for timing pur­poses in the baseband delay line.

IIC-bus

The decoder / sync processor is connected to the IIC-bus
via pins 5 (SCL) and 6 (SDA).The bus address is determined
by connecting pin 22 to +8 V.
The output pin 16 controls the filtering method of the comb
filter, either PAL 4.43 MHz (“L”) or NTSC 3.58 MHz (“H”).
The input / output pin 15 is primarily used to detect whether
the comb filter module is installed or not, by checking the
transistor tc3 (base-collector junction). In addition, pin 15
controls the comb filter IC to be in the filtering mode (“H”)
or in the internal bypass mode (“L”).

Baseband Delay Line, ICd3

General

The circuit TDA4665 is a delay line which requires no ad­justments. It includes two colour difference comb filters
and uses switched capacitor techniques.
Each comb filter consists of an undelayed signal path and
a 64 µs delayed signal path.
In PAL mode, comb filters operate as a geometric adder to
carry out the requirements of PAL demodulation.
In NTSC mode, the comb filters suppress cross-colour in­terference.
In SECAM mode, the circuit repeats the colour difference
signal on consecutive horizontal scan lines.

Functional description

The colour difference signals are fed to input pins 14 (U)
and 16 (V). First the signals are clamped, and then they are
fed through pre-amplifiers to the undelayed / delayed sig­nal paths. All the switching signals needed in the delay
process are generated from the 3 MHz master clock fre­quency. This frequency is divided from the internal 6 MHz
VCO, which is line-locked by the sandcastle pulse (SC). The
SC pulse taken from the sync processor is fed to pin 5.
Delay processed colour difference signals are fed through
the addition circuits to the output buffers and are finally
output on pins 12 (U) and 11 (V).

Feature boxes, DB7**

The feature box has two main functions, to perform the
conversion of the 50 (60) Hz scan to 100 (120) Hz scan for­mat and to improve the picture quality. Depending on the

Feature DB711 DB710

100 Hz flicker reduction - field repetition - median interpolation
Line flicker reduction - no - median filter
Noise reduction (Y / C) - no - motion adapted
Aspect ratio conversions

- horizontally - ±12.5 and ±25 % - ±12.5 and ±25 %

- vertically - by deflection - +12.5 and +25 % (by DSP)

- hor picture position - fully programmable - fully programmable

- lift - no - yes

- side panels - programmable grey - programmable grey

Picture sharpening - vertical / horizontal peaking - vertical / horizontal peaking

- CTI, LTI - CTI, LTI
Histogram equalizing - yes - yes
Still picture - yes - yes
A/D conversion - YUV 4:1:1 signal format - YUV 4:1:1 signal format

- 8-bit per component - 8-bit per component

- input signal amplitude adapted - input signal amplitude adapted

- sampling rate - 13.5 MHz - 13.5 MHz

D/A conversion - Y-component 9-bit - Y-component 9-bit

- U- and V-component 8-bit - U- and V-component 8-bit

- sampling rate - 20.25 MHz ... 36 MHz - 20.25 MHz ... 36 MHz
Field memory - 3 Mbit (1 x 3 Mbit) - 6 Mbit (2 x 3 Mbit)
Synchronizing - line locked operation - line locked operation

- crystal based sync generation - crystal based sync generation

chassis version, there are few different feature boxes with
more or less variant features. The whole signal processing
takes place digitally and all functions are controlled using
the IIC-bus.
The basic version is DB711, that contains only one 3 Mb
field memory. The use of one field memory allows the con­version of 50 (60) Hz video to 100 (120) Hz video, but not
line flicker and noise reduction or vertical zooms. This
module is designed for TV sets with a 4:3 picture aspect
ratio.

The DB710 version contains two 3 Mb field memories, so
noise reduction and vertical zooms are also implemented.
The DB710 (and DB700) are designed for TV sets with both
a 4:3 and 16:9 picture aspect ratio.
The DB700 version is called a “full feature” version, that
includes in addition to the features of DB710, a signal in­terface in accordance with the VGA standard.

9

Feature box DB711

The main components of the DB711 are an A/D converter,
field memory (FM), picture quality improvement circuit
(IQTV2), digital phase locked loop (DPLL) and deflection
controller.

Y, U and V inputs

The luminance (Y) and colour difference signals (U and V)
are taken from the colour decoder to the module connec­tor Q101, pins 6 (Y), 7 (U) and 8 (V). Each signal is first
amplified and then low pass filtered. After that the signals
are fed via buffer transistors to the A/D-converter, pins 63
(Y), 50 (U) and 31 (V).

Analog to digital converter, ic9

Analog to digital conversion is carried out using A/D-con­verter circuit TLC5733, which contains three separate 8-bit
A/D-converters. Each signal is clamped using the horizon­tal sync pulse (HOUT1) on pin 55 and then converted to
digital form. The converters sample the input signals at a

13.5 MHz sampling rate. The sampling frequency is taken

to pin 56. The converters are controlled by reference
voltages REFH (pins 61, 52 and 29) and REFL (pins 1, 48
and 33).
If an overflow is detected, the reference voltages will be
either increased or decreased. Information about a possi­ble overflow is taken from the luminance output data (pins

6...13) and fed to the NAND gate ic28 and onward to the
DPLL circuit ic11 pin 42 (ADC_OVFL). The circuit detects
the overflow data and if necessary, it changes the width of
the pulses on pin 43 (PWM_REF). These width modulated
pulses are fed to the low pass filter consisting of transis­tors t1 and t9 and associated capacitor network. The low
pass filter generates both voltages, the REFH and REFL,
and these are fed to control the A/D-converters.
After converters the signals are fed to the output format
multiplexer, which is controlled by pins 45 (mode1) and 46
(mode0). The combination of a logical low on both pins
causes the output data format of the YUV signals to be
4:1:1. The U and V components have 1/4 of the signal
strength of the Y component.
The luminance data bus (pins 6...13) is eight bits wide and
the chrominance data bus (pins 17...20) four bits wide.

10

Field memory, ic14

Field Memory 1 (FM1) is a 3 Mb, high-speed Dynamic Ran­dom Access Memory (DRAM). The circuit is used as a
memory circuit in the 50 to 100 Hz upconversion and in
certain horizontal zoom functions.
The luminance and chrominance data are input from the
A/D-converter to pins 2...13.
The write operation is performed using the input control
signals RSTW (reset write) on pin 15, SWCK (serial write
clock) on pin 14 and ENW (enable write) on pin 16. The
write clock (SWCK / CLK27_1) frequency is 27 MHz. The
ENW signal enables memory writes only on every second
clock cycle.
The read operation is performed using the read output
control signals RSTR (reset read) on pin 22, SRCK (serial
read clock) on pin 23 and ENR (enable read) on pin 21.
The read clock (SRCK / CLK) frequency varies depending
on the picture format. The IQTV is able to generate the
following formats (implementation depends on the feature
box and software):

36.000 MHz = - 25.0 % hor compression

30.375 MHz = - 12.5 % hor compression

27.000 MHz = 0 no compression / no expansion

23.625 MHz = + 12.5 % hor expansion

20.250 MHz = + 25.0 % hor expansion

All vertical compression is carried out by the deflection
processor. Only the DB710 and DB700 comprise the verti­cal expansions (FM2 required).
The luminance and chrominance data are output to the
IQTV2 circuit from pins 24...35.

IQTV2 circuit, ic18

The main function of the IQTV2 (Improved Quality TV) cir­cuit is to perform the upconversion, which reduces the
flicker caused by interlacing. The idea of the upconversion
is that the interlaced 50 (60) Hz scan will be converted to a
100 (120) Hz scan format.
The flicker reduction (upconversion) in the DB711 module
is based on a field repetition algorithm for both luminance
and chrominance signals. The field repetition method uses
zero degree interpolation and displays the original field
twice.
The characteristics of the IQTV2 make it possible to utilize
both the horizontal and vertical zoom functions, but be­cause there is only one field memory, only the horizontal
zoom can be utilized. Thus all vertical zoom functions are
performed using the deflection controller circuit.
Picture sharpening is implemented not only in the hori­zontal direction, but also in the vertical direction. The peak­ing stage consists of high pass and band pass filters which
emphasize the middle band frequency range where most
of the details and edges are located.
The colour transient improvement (CTI) makes the slopes
of colour edges steeper by controlling the inputs between
the delayed, look ahead and current chrominance signals.
A new feature in the CTI of the IQTV2 circuit is that the
center of the transient always stays at the same point in
comparison with input and output signal.
The luminance transient improvement (LTI) is performed
by taking the 3-point median of three intermediate signals,
peaked, maximum and minimum. As a result of the LTI
process the luminance transients are made steeper with­out any undershoots or overshoots.
The histogram equalization (HEQ) system is designed to
carry out an automatic contrast enhancement. The system

is designed to give a uniform histogram for the output pic­ture signal, changing the original pixel values for new ones
using a non-linear mapping. As a result, both under and
over contrasted picture signals are equalized to have the
desired contrast and gray level distribution.

Pin description of ic18:

Pin Symbol Description

1, 5-12, 14-15,
18-21, 100 D0_FM1...

D15_FM1 Data input from FM1
2, 16, 41,
56, 81 +3.3V (core) Power supply for logic
3, 28, 61, 77 +5V (i/o, AC) Power supply for I/O
4, 29, 60, 69 GND (i/o, AC)

Ground for I/O
13, 34, 78 +5V (i/o, DC) Power supply for I/O
17, 37, 57,
79, 99 GND (CORE) Ground for CORE
22 FM1_ENR Read enable, FM1
23 FM1_ENW Write enable, FM1
24 FM1_RSTW Reset write, FM1
25 HS_IPLL Horizontal sync
26 FM2_ENW Write enable, FM2
27 FM2_ENR Read enable, FM2
30 CLK_IPLL

(CLK27_1) System input clock

(27 MHz)
31 CLK_OPLL

(CLK) System output clock
32 VS_50 Vertical sync
33 HS_OPLL Output horizontal sync
35 HS32 32 kHz horizontal sync
36 FM_RSTR Reset, FM2W/R, FM1R
38 SDA IIC-bus, serial data
39 SCL IIC-bus, serial clock
40 FSY Format sync for ADC
42 +5V (analog) Analog supply voltage

for DAC
43 VBIAS Analog
44, 47, 49, 51 GND (analog) Ground for DAC
45 VT Analog
46 Vref Current reference

for DAC
48 AY Analog Y output
50 AV Analog V output
52 AU Analog U output
53 RST System reset
54 TEST_EN Test mode enable
55 VS_50_100 Double frequency

vert sync
58-59, 62-67,
70-76, 80 Q0_FM2...

Q15_FM2 Data output to FM2
68 DIG_OUT8 9th bit in digital output
82-89, 91-98 D0_FM2...

D15_FM2 Data input from FM2
90 SYNC_SEL Selection of sync mode

After digital signal processing (DSP), the IQTV2 circuit con­verts the signals to analog form and outputs them from
pins 48 (Y), 52 (U) and 50 (V).
The colour difference signals are low pass filtered and out­put from module pins Q102-3 (U) and Q102-2 (V). The lu­minance signal is first amplified by transistors t18 and t19,
then the signal is low pass filtered and output from mod­ule pin Q102-4.

DPLL1 circuit, ic11

The DPLL (Digital Phase Locked Loop) circuit generates all
line locked clock and sync signals for the whole digital sig­nal processing system. The circuit is IIC-bus controlled and
it needs only a few external components, one of them a 27
MHz crystal. The 27 MHz clock operates as a main clock,
from which the other clock frequencies are generated us­ing suitable factors.

Pin description of ic11:

Pin Symbol Description

11

The horizontal (HDFL) and vertical (VDFL) sync signals from
the DPLL1 are fed to input pins 13 and 12 to synchronize
the circuit.
The horizontal flyback pulse is taken from the horizontal
output stage to input pin 1.

Horizontal drive signal

From the horizontal detector stage, the horizontal sync sig­nal is fed to the horizontal counter, the horizontal place
control, the phase 2 loop, and finally output from pin 20 to
drive the horizontal driver stage. The H-phase adjustment
is performed in the horizontal position control stage using
the IIC-bus.

1 HSYNC1 Horizontal sync from sync

processor

5 VSYNC1 Vertical sync from sync

processor

7 HOUT1 Horizontal sync for ADC and

IQTV2

9 CLK27_1 27 MHz main clock for FM1

and IQTV1
11 CLK13_5_1 13.5 MHz clock for ADC
13 VOUT1 Vertical sync for IQTV2
22 CLK27_2 27 MHz main clock for

deflection controller
24 HS_GSCART Horizontal sync from VGA

(DB700)
26 HSYNC2 Horizontal sync from VGA

(DB700)
27 VS_GSCART Vertical sync from VGA

(DB700)
28 CLK Format dependant clock for

FM1/2 and IQTV2
29 VSYNC2 Double frequency vert sync

from IQTV2
30 HOUT2 (HDFL) Hor sync for IQTV2 and

deflection controller
31 VOUT2 (VDFL) Vert sync for IQTV2 and

deflection controller
33 FORMAT_VGA Low by DB711/710, high by

DB700
35, 36 XTALCLK 27 MHz crystal (for main

clock)
37 FORMAT_MEM High by DB711, low by

DB700/710
40, 41 SDA / SCL IIC-bus, serial data and clock
42 ADC_OVFL Overflow data from ADC
43 PWM_REF Output of width modulated

pulses for ADC

Vertical drive signal

From the vertical detector stage, the vertical sync signal is
fed to the vertical place control, the vertical place genera­tor, the vertical geometry stage and finally the differential
current vertical drive signals are output from pins 10 and
11 to drive the vertical deflection circuit ICs1. Vertical am­plitude, S-correction and V-shift are controlled in the verti­cal geometry stage via the IIC-bus. The reference current
for both the vertical and E-W geometry processing is de­termined by resistor r68 on pin 8.

E-W drive signal

The E-W drive signal is a single ended current output and
it is taken out from pin 6. The control parameters: E-W
width, E-W parabola/width ratio, E-W corner/parabola, and
E-W trapezium are included in the E-W geometry process­ing stage. All of these controls can be set using the IIC­bus.

EHT compensation

Both the vertical and the E-W drive outputs are modulated
for EHT compensation via pin 7. The EHT information is
taken from DST pin 8 (“static” information) and from Ck31
/ Rk58 and Ch21 / Rh29 (dynamic information).

Sandcastle

The TDA9151 generates a two level display sandcastle pulse
(DSC). The 2.5 V level is used for horizontal and vertical
blanking, and the 4.5 V level for video clamping. The DSC
is output from pin 2 and it is used for the timing of the RGB
Video processor ICt1.
In addition, pin 2 operates as an input pin for the vertical
guard. The DSC pulse is connected to pin 1 of the vertical
deflection circuit. In possible fault cases, the vertical IC will
supply a voltage level of 2.5 V, which causes blanking of
the screen.

Deflection Controller TDA9151, IC17

The TDA9151 circuit is an IIC-bus controlled synchroniza­tion and deflection processor having horizontal and verti­cal drive outputs and an East-West correction drive circuit.

Input signals

The serial data (SDA) and serial clock (SCL) are connected
to pins 17 and 18.
The 27 MHz line locked clock pulse (CLK27_2) from the
DPLL1 is fed to pin 14. The internal synchronous logic uses
the LLC as a system clock. It is important to realise that the
circuit will not operate without the LLC, it will switch off
the outputs and will not perform any operations. The LLC
frequency is divided by two by connecting the line-locked
clock select input pin 5 (LLCS) to ground. This activates
the prescaler stage and creates a line duration of 32 µs.

12

Feature box
DB711 / 710 / 700

Y

U

V

VSA / VSYNC1
HSA / HSYNC1

A/D-C

YUV

INIT,CLP

CLK

A/D-C_REFV

Y

&

12

8

RSTR

FM1

3 Mb

ENW
ENR

RSTW

SWCK

SRCK

CLK

27 MHz

13.5 MHz

EEPROM

VCLK

DDC1
interface

SDA
SCL

In DB700 only

In DB700 and
DB710 only

YUV

12

FM_RST

D0...D11_FM1

12

FM1_ENW
FM1_ENR

2

&

FM1_RSTW

CLK13.5_I
OVFL
PWM_REF
VSYNC1
HSYNC1

HSYNC

VSYNC

VGA

VS_50

IIC-bus

3

FM2

3 Mb

YUV

IQTV2.1

DB711

UP-C, HFC, HEQ
CTI, LTI, Peaking
D/A-C

DB700/710

UP-C, FC, NR, HEQ
CTI, LTI, Peaking,
D/A-C

CLK_IPLL

CLK27_I

DPLL1.02

27 MHz

RGB VGA
to Xtpp

SWCK
SRCK

RSTW

RSTR

12

HS_IPLL

27 MHz

LLC

Deflection
controller

FM2_ENW
FM2_ENR

VS_50_100

CLK

VA

VA HA

CLK_OPLL

VS_50_100

FM_RST

AY

AU

AV

CLK_OPLL

IIC-bus

HS_OPLL

HSYNC_O

VSYNC_O

DSC

EHT, HFB

HD, VD, EW

IIC-bus

IIC-bus

Block diagram of the Feature boxes DB711, 710 and 700

Feature box DB710

The basic functions of the DB710 are similar in principle to
the DB711. The only visible difference is that the DB710 is
equipped with two field memories, FM1 and FM2. This al­lows noise reduction and vertical zoom (vertical format
conversion) functions to be implemented.
The upconversion from 50 to 100 Hz in the DB710 is based
on a median interpolation algorithm that reduces both the
field and line flicker. The median filter method uses a 7­point adaptive median interpolator, whose sampling win­dow consists of 7 samples, taken in horizontal, vertical and
temporal directions. The 7-point median output will be re­placed with 3-point vertical median output, if a difference
signal exceeds the externally determined threshold level.
The noise reduction system consists of an adaptive
weighted average post-filter, that is based on the so-called
motion adaptive temporal recursive averaging filter. The
system is used not only for noise reduction, but also to
reduce the cross effects. The noise reduction affects both
the luminance and chrominance components. As men­tioned above, the noise reduction function requires an ad­ditional field memory. This field memory, FM2 is identical
to FM1 and it is connected to the IQTV2 circuit in a similar
way.
The characteristics of the vertical format conversion of the
IQTV2 circuit make it possible to always display all vertical
zoom modes with a full vertical resolution of 576 active
lines. This is due to the digital signal processing and linear
vertical interpolation.

Feature box DB700

The functional features are similar to DB710; median inter­polation, noise reduction, full vertical resolution etc. In ad­dition to these features, the DB700 is equipped with a VGA
(video graphics array) interface in order to make it possi­ble to use the TV set as a monitor for a personal computer.
For this reason, an additional memory circuit is needed.
The memory circuit ic3 is a serial EEPROM, that is pre-pro­grammed with the data needed for automatic configura­tion of the display controller in the computer via the dis­play data channel 1 (DDC1).
The vertical and horizontal sync signals from the VGA con­nector are fed via inverting schmitt triggers and fed on­ward to pins 27 (vert sync) and 24/26 (hor sync) of the
DPLL1.
The analog RGB signals are fed through the module with­out any processing to the RGB video processor ICt1 via the
connector Xtpp on the main board, or via the PIP module,
if installed. If sound signals are also taken from the PC,
they are input via Scart3 + VGA audio module TA710.

The following VGA modes are available:

Resolution Line frequency Field frequency

640 x 480 31.5 kHz 60 Hz
640 x 350 31.5 kHz 70 Hz
640 x 400 31.5 kHz 70 Hz

Q101-3

t

t

t

Q101-3

Q101-4

Q101-4

Q101-1

Q101-1

Q101-2

Q101-2

Q101-5

Q101-5

Q101-11

Q101-11

Q101-9

Q101-9

Q101-16

Q101-16

Q101-8

Q101-8

Q101-7

Q101-7

Q101-6

Q101-6

Q101-14
Q101-13
Q101-12

Q101-10

Q101-10

Q104-1

Q104-2

Q104-3

Q104-4

Q104-5

Q104-6

Q104-7

Q104-8

Q104-9

Q104-10

Q104-11

Q104-12

Q104-13

Q104-14

Q104-15

O N LY D B 7 0 0

7 V f b

D

D

1 2 V p

D

D

8 V p

V i n

U i n

Y i n

SDA
SCL

HSNCI

D

VSNCI

D

C211
10n

D

VGA_R
VGA_G
VGA_B

L5

L5
10u

10u

C60

C60
22u

22u

C70

C70
22u

22u

C90

C90
22u

22u

R161
1k0

DB700/710 Feature module

7V

L1

L1
10u

10u

C210
10n

D

12V

12V

L3

L3
10u

10u

C43

C43

C44

C44

22u

22u

100n

100n

D

D

D

D

VCC8

VCC8

TP24

C50

C50

C49

C49

100n

100n

100u

100u

D

D

D

D

R5

R5

R7

R7

15k

15k

22R

22R

T2

T2
BFS20

BFS20

R8

R8

R6

R6

470R

470R

4k7

4k7

A

A

A

A

R15

R15

R17

R17
22R

22R

15k

15k

T4

T4
BFS20

BFS20

R16

R16

R18

R18
470R

470R

4k7

4k7

A

A

A

A

R25

R25

C80

C80
100u

100u

A

A

R209
R210
R211

DD

D

R193
1k0

R27

R27

15k

15k

22R

22R

T6

T6
BFS20

BFS20

R28

R28

R26

R26

470R

470R

3k9

3k9

A

A

A

A

C160
470n

0R0

0R0

C161

0R0

R108

R107

75R

75R

R191

1k0

1k0

R192

R194

1k0

DD

TP22

C33

C33

C34

C34

220u

220u

100n

100n

D

D

D

D

TP23

C45

C45
100n

100n

A

A

12V

12V

C61

C61
10n

10n

A

A

R9

R9
180R

180R

12V

12V

C71

C71
10n

10n

A

A

R19

R19
240R

240R

12V

12V

C81

C81
10n

10n

A

A

R29

R29
180R

180R

R G B O U TV G A - I N

470n

C162
470n
R109
75R

1

IC2-1
74F14

1

5 9 8

IC2-3
74F14

12V

12V

R73

R73
4k7

4k7

1
4

R75
4k7

D

PWM_REF

R10

R10

R12

R12

470R

470R

15k

15k

T3

T3
BFS20

BFS20

R11

R11

R13

R13
4k7

4k7

220R

220R

A

A

A

A

R22

R22

R20

R20

15k

15k

470R

470R

T5

T5
BFS20

BFS20

R21

R21

R23

R23

180R

180R

4k7

4k7

A

A

A

A

R32

R32

R30

R30

15k

15k

470R

470R

T7

T7
BFS20

BFS20

R33

R33

R31

R31
220R

220R

3k9

3k9

A

A

A

A

Q105-1
Q105-2
Q105-3
Q105-4
Q105-5
Q105-6

21 3 4

IC2-2
74F14

6

IC2-4
74F14

D

IC2-5
74F14

IC1

IC1
PQ05RF1

PQ05RF1
IN

ON/OFF

GND

R72

R72
100k

100k

A

A

A

A

R195

A

A

1

1

1

1011

3

C62

C62
100u

100u

C72

C72
100u

100u

0R0

C82

C82
100u

100u

D

D

OUT

VGA_HSYNC
VGA_VSYNC

A

A

A

A

A

A

A

A

2

C51

C51
47u

47u

C63

C63

100n

100n

C73

C73
100n

100n

C83

C83
100n

100n

T9

T9
BC847B

BC847B

R215

D

R212
100R

R213
100R

VCC

VCC

TP13

C35

C35

C36

C36

100n

100n

100u

100u

D

D

D

D

VCCA

R91

VCCA

VCCA

820R

R1

R1
820R

820R

R2

R2

C52

C52

820R

820R

100n

100n

A

A

A

A

L6

L6
33u

33u

C65

C65
6p8

6p8

C64

C64

C66

C66

180p

180p

82p

82p

A

A

A

A

L8

L8

33u

33u
C75

C75
6p8

6p8

C74

C74

C76

C76

82p

82p

180p

180p

A

A

A

A

L10
12u

C85

C85
5p6

5p6

C84

C84

C86

C86
82p

82p

33p

33p

A

A

A

A

IC3

IC3

24LC21

24LC21

1

NC.

2

NC.

TP60

10k

3

WP

D

D

TP58
TP59

L2

L2
10u

10u

VCLK

VCCA

L7

L7
27u

27u

L11
12u

VCC
SCL

SDA4VSS

C67

C67
22p

22p

L9

L9
27u

27u

C77

C77
22p

22p

C87

C87
27p

27p

T1
BC847B

R3
75R

R4
10R

A

VCCA

C37
100u

A

C53
1u0

A

C55

1u0

A

C68
68p

A

C78
68p

A

L12
12u

C115
22p

C88
68p

A

8
7
6
5

A

TP14

C38
100n

VCC

R14
470R

A

D

C153
100n

A

A

A

C54
100n

C56
100n

R24
470R

VCC

IC4

LD1117

IN OUT

GND

D

C58

C57

1n0

1n0

12V

12V

T15

T15
BC847B

BC847B

R99

R99
200R

200R

200R

200R

R98

R98

A

A

12V

T14
BC847B

R97
200R

200R

R96

A

12V

T13
BC847B

R95

200R

R34
560R

A
C114
18p

A

R214

R94
200R

A

TP18

10k

ECO2_VIDEO_SHIELD

VCCIQ3

VCCIQ3

L14
10u

TP51
C19

100n

TP4

REFH

C59
1n0

TP5

REFL

TP41

TP42

A101

2

4

1

3

D

D

D D

5

TP1

TP3

A

A

TP2

D D D

VCC

C18
100u

DD

C69
1u0

C79
1u0

C168

2n2

C169

2n2

C89
1u0

7

6

L30
10u

VCC

VCC

L4

L4
10u

10u

C46

C46

22u

22u

L13

L13
10u

10u

D

49

A

GND_B

50

BIN

51

B_AVCC

VCCA

52

RTB

REFH

53

CLPVB

R145

54

15k

CLP_OUTB

55

EXT_CLP

56

CLK

57

D

CLPEN

58

INIT

R146

59

15k

CLP_OUTA

60

CLPVA

61

RTA

REFH

62

A_AVCC

VCCA

63

AIN

64

A

GND_A

IC9

TLC5733

8

15

10

D DDD

D

D

17

12

14

16

13

D D

D

D

D D

VCC

VCCIQ5

L17

TP55

10u

C216

C217

100n

100u

D

D

VCCO

TP25

C47

C48

100n

100n

TP26

GNDO

D

D

D

D

38

44

39

45

40

46

41

47

42

48

43

CD5

CD4

CD3

OEB

CD2

RBB

CD1

MODE1

MODE0

QC_DGND

AD8

AD5

AD7

AD4

AD6

NT/PAL

TEST5QA_DGND

RBA

QEA

6

11

9

7

10

8

3

4

1

2

D

D

D

VCC

REFL REFL

5

IC28

74F30

20

19

21

D

D

D

461

12

11

13109

282233

24

26

23

271832

25

D

D

D D D

5VAC

C121

C122

100n

100u

D

D

VCC

34

35

36

37

33

QEC

CD8

CD7

CD6

QC_DVCC

CLP_OUTC

AD3

AD2

DGND14QA_DVDD

AD1

12

15

13

16

D

VCC

3

2

14

&

D

7

8

30

31

29

341139

D

D D D D D D D D D D D

VCC

VCC

REFL

RBC

GND_C

CIN

C_AVCC

RTC

CLPVC

DVDD

QB_DGND

BD1
BD2
BD3
BD4
BD5
BD6
BD7
BD8

QB_DVDD

VCC

VCC

35

36941

VCCDPL

L15

10u

L16

10u

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

38

37

TP54

C163

C164

100n

100u

D

D

VCCMEM

TP53

C165

C166

100n

100u

D

D

A

VCCA
REFH

R144

C167

15k

2n2

D

40

A

VCC

8

9
10
11

0

1

2

3
4

5

6
7

FM1DI(0:11)

C98

100n

D

CLK
2
0

VCC

1

CLK

0

1

2

3

4

5

6

7

8

9

10

11

IC2-6
74F14

14=

7=

13 12

CLK27_1

2
1

VCCMEM

0
3

CLK

VCC

C11

C17

C12

C8

D

D

D

D

F M 2

VCC

C112

18

14

SWCK

15

RSTW

16

W

17

IE

20

OE

21

R

22

RSTR

23

SRCK

13

D0

12

D1

11

D2

10

D3

9

D4

8

D5

7

D6

6

D7

5

D8

4

D9

3

D10

2

D11

IC24
TMS4C2970

O N LY D B 7 0 0 / D B 7 1 0

FM2CTR(0:2)

FM2DI(0:11)

F M 1

VCC

VCCMEM

D_GND

1

18

14

SWCK

15

RSTW

16

W

17

IE

20

OE

21

R

22

RSTR

23

SRCK

13

8

D0

12

9

D1

11

10

D2

10

11

D3

9

0

D4

8

1

D5

7

2

D6

6

3

D7

5

4

D8

4

5

D9

3

6

D10

2

7

D11

IC14

IC14
TMS4C2970

TMS4C2970

FM1CTR(0:3)

C22

C27

C20

C21

D

D

D

D

D

1

36

19

24

Q0

25

Q1

26

Q2

27

Q3

28

Q4

29

Q5

30

Q6

31

Q7

32

Q8

33

Q9

34

Q10

35

Q11

C3

D

1

36

19

24

Q0

25

Q1

26

Q2

27

Q3

28

Q4

29

Q5

30

Q6

31

Q7

32

Q8

33

Q9

34

Q10

35

Q11

C30

D

R118
220R

R119
330R

C23

D

8

9
10
11

0

1

2

3

4

5

6

7

VCC

D

VCCIQ3

C24

D

0
1
2
3
4
5
6
7
8

9
10
11

FM1DO(0:11)

CLK27_1

C5

C25

D

D

VCCDPL

C118

3p9

VCCIQ5

FM2DO(0:11)

VCCIQ3

11
10
9
8
11
10
9
8

VCCIQ5

7
6
5
4
3
2
1
0

TP56

C101

C101

VSNCI
HOUT1

D

C28

D

SDA

SCL

R117

33R

D

D

DPLL1

DPLL1

C29

D

Q15_FM2

81

3.3V

82

D15_FM2

83

D14_FM2

84

D13_FM2

85

D12_FM2

86

D11_FM2

87

D10_FM2

88

D9_FM2

89

D8_FM2

90

SYNC_SEL

91

D7_FM2

92

D6_FM2

93

D5_FM2

94

D4_FM2

95

D3_FM2

96

D2_FM2

97

D1_FM2

98

D0_FM2

99

D

GND

100

D15_FM1
D14_FM1

IC10
IQTV2

11 10

R81
100R

R80

100R

D

1

HSYNC1

2

VDDi3

3

ADD0

D

D

4

ADD1

5

VSYNC1

6

HINT_EXT1

D

D

7

HOUT1

8

test_scan

D

D

9

CLK27_1

10

VSSi1

D

D

11

CLK13_5_1

IC11

IC11

C105

D

5VAC

C39

C40

D

D

C103
100n

11

80

79

1

2

VCCIQ3

D

D

44

12

C41DC42

D

VCCO

VCCO

R152

R152

R155

22R

1k0

1k0

*

VDFL

T18

T18

BF599

BF599

GNDO

C212
10u

12V

HDFL
CLK27_2

SCL

SDA

GNDO

C120
100n

R153
100R

R69
100R

R70
100R

R154
100R

C201

47p

D

T19

GNDO

VCCO

*

R120

10k

BF824

R101
150R

GNDO

T16

2N7002

D

R68

D

39k

C119
100p

R103
10R

C202
12p

D

L26
1u5

GNDO

GNDO

T17

2N7002

16

1
3
5
7
8
12
13
14
18
2
17

IC17
TDA9151

C203
22p

VCC8

HFB
PROT
LLCS
EHT
RCONV
VA
HA
LLC
SCL
DSC
SDA

GNDO

R102
220R

R104
150R

LL4148

15 4

GNDO

GNDO

R178
100R
R179
100R

D9

D

R105

33R

C204

100p

D

EWOUT
VOUTA
VOUTB

OFCS
HOUT

C208
27p

C209
39p

C111
100p

Q102-1

GNDO

C205

39p

C206

10p
L27

3u3

C207
15p

L28
2u2

TP36

Q102-4

Q102-4

VOA

VOB

HA2

PROT

EHT

HFB

EW

VCC8

DSC

D

D

D

Q102-3

Q102-3

Q102-2

Q102-5

Q102-15
Q102-16

Q102-12

Q102-6

Q102-7
Q102-8
Q102-9

Q102-10

Q102-11
Q102-14
Q102-13

Q103-1
Q103-2
Q103-3
Q103-4
Q103-5
Q103-6

Y o u

U o u

V o u t

C150

R156

100p

1k0

GNDO

GNDO

TP37

C151

R157

82p

680R

GNDO

GNDO

TP38

C152

R158

120p

560R

GNDO

GNDO

SCL

SDA

R159
1k0

R160
1k0
R62

2k2
R63
39k

D

R66

15k

R67
10k

D

9

D

6
11
10
19

OFCS

R71
820R

20

R64
33k

R65
3k3

D

L29
2u2

D

NC

R151

R151
3k3

3k3

R150

R150

1k0

1k0

R100

R100
150R

150R

TP43
TP44

TP45
TP46

C200
150p

C215

1u0

3

0

2

1

C139

1

D

69

GND

D6_FM1

34

VSSi4

CLK27_2

68

DIG_OUT8

+5V(DCio)

13

VCCIQ5

DB711
R87

**

R106

R106

VDDi4
VOUT2
HOUT2

VSYNC2

HSYNC2

VSSi2

14

1M0

1M0

67

66

Q7_FM2

D5_FM1

15

VCCIQ3

C96
22p

C95

C95
22p

22p

CLK

D

2

3

65

64

63

62

Q6_FM2

Q5_FM2

Q4_FM2

Q3_FM2

D4_FM1

GND18D3_FM1

+3.3V(core)

19

17

16

D

D

D

D

D

33
32
31
30
29
28
27
26
25

D

D
24
23

D

D

5VAC

DD

61

60

+5V

GND

Q2_FM2

D2_FM1

D0_FM1

D1_FM1

21

20

22

DB700 0R * 0R *
DB710 * 0R 0R *
DB711 * 0R * 0R

D

C102

C102

VDFL
HDFL

R116

33R

VGA_HSYNC

VGA_VSYNC

87654

8

9

9

10

10

11

5VAC

VCCIQ5

77

76

75

74

73

72

71

Q14_FM2

D13_FM1

6

5

9

SCL41SDA

NANDTREE

15

16

VCCDPLVCCDPL

Q13_FM2

Q12_FM2

Q11_FM2

D10_FM1

D11_FM1

D12_FM1

8

7

81110

8

9

DB700/710

R86

**

VCCDPL

D

D

40

38

VSSe239VDDe2

VDDe1

VSSe1

nreset

17

18

D D

D

70

Q9_FM2

Q8_FM2

Q10_FM2

D7_FM1

D8_FM1

D9_FM1

9

12

11

10

7 6 5 4 3 2 1 0

TP47
TP48

VCC

D

Z1

27MHz

D

D

35

37

36

XTALCLK1

FORMAT_VGA

XTALCLK2

FORMAT_MEM

VS_GSCART
HINT_EXT2

HS_GSCART

CLK13_5_2

test_mod

VDDi2

19

20

21

22

C14

VCCDPL

C91
100n

78

+5V

+5V

GND

+5V4GND(ACio)

+3.3V

3

D

5VAC

PWM_REF

43

42

VSSi3

PWM_REF

ADC_OVFL

VDDi1

VOUT1

CLK27_SKEW

13

14

C104
D

VOUT1

330n

0

VCCIQ3

VCCIQ3

D

D

59

58

57

56

GND

Q1_FM2

Q0_FM2

FM1_RSTW

FM1_RNW

FM1_ENR

25

24

23

HOUT1

0 1 2

R84 R85 R86 R87

* N O T U S E D
* * V e r s i o n C o m p o n e n t

VCCDPL

C117

3p9

D

D

GNDO

D

55

54

52AU53

51

RST

GND

3.3V

VS_50_100

FM2_ENW

HS_IPLL

26

R115

33R

27

TEST_EN

FM2_ENR

5VAC

28

FM2_RST

HS_OPLL

CLK_OPLL
CLK_IPLL

+5V

GND

30

29

D

CLK27_1

R84

**

R85

**

C116
3p9

50

AV

49

GND

48

AY

47

GND

46

VREF

45

VT

44

GND

43

VBIAS

42

+5V

41

+3.3V

40

FSY

39

SCL

38

SDA

37

GND

36
35

HS32

34

+5V

33
32

VS_50

31

D

NO VGA DB710/711

R113

R113
220R

220R

TP57

R114
330R

D

VCC

C214

4u7

D

VGA DB700

VCC

CLK

GNDO

GNDO

VCCIQ3

VCCIQ5

1u0

R177

3k9

HDFL

VOUT1

CLK

GNDO

GNDO

C213

RGB Video Processor TDA4780, ICt1

g

13

Functional description

General

The TDA4780 circuit is an RGB Video Processor with an
automatic cut-off control, gamma adjustment, dynamic
black control, and blue stretch.
The IC contains a linear matrix to convert the luminance
and colour difference signals into RGB signals. The proc­essor is also able to process two external RGB signals.
All parameters and functions are controlled using the IIC­bus.

Y

26

Y

(Hue)

D/A
converters

Contrast
adjust

5

+8V

SDA

SCL

Sand­castle

Y

V
U

R
G
B
Fsw

R
G
B
Fsw

28

27

14

8

7
6

10
11
12
13

2
3
4
1

2

I C-bus
interface

Control
registers

0.45V/

1.4V
VBS

PAL/SECAM
NTSC
Matrix

Fast
signal
switch,
blanking

IIC bus data
and control

TDA4780

Sandcastle
detector

Y-Matrix

R

G

B

18

1st and 2nd
switch on
delays

Timin g
generator

Timing pulses

Adaptive
black
control

Gamma
adjust

Saturation
adjust

Supply

Peak dark
storage

Signal input stages

The luminance and colour difference signals from the Fea­ture box module are input to pins 8 (Y), 6 (U) and 7 (V). The
luminance signal input level is selectable (0.45 Vpp or 1.4
Vpp) using the IIC-bus (pins 27 and 28). 1.4 Vpp is used in
this application. The signals are fed to a linear matrix stage
to convert them into RGB signals.
RGB signals from the teletext circuit are fed to the input
pins 2 (R), 3 (G) and 4 ((B). RGB signals from the PIP mod­ule (or from the VGA connector) are fed to the input pins
10 (R), 11 (G) and 12 (B).
All input signals are clamped in order to have the same
black levels at the signal switch input.

3x6-bit

Peak drive
limiter,
6-bit D/A
converter

Brightness
adjust

9

Ground

Averag e
beam and
peak drive
limiting

R
G

Blue
stretch

reference
registers,
MUX, DAC

PDL

3x6-bit
DAC

Blanking,
measure­ment pulse
insertion,
white point
adjust

Cut-off
comparators

Peak
detector

Cut-off storage

Cut-of f
adjust,
output
stages

21
B

23 25

R

G

19

17

16

15

24
22
20

Leakage
and cut-off
current
input

Leakage
storage

Peak drive
limiting storage

Averag e
beam current

R
G
B

Signal switches

Fast signal source switches select RGB signals from one
of three input signal alternatives: the matrix stage, the tele­text circuit or the PIP module. This selection is controlled
using the IIC-bus or by using fast blanking signals FB on
pins 1 and 13. During the vertical and horizontal blanking
time, an artificial black level is inserted in order to clip off
the sync pulse of the luminance signal, to suppress hum
during the cut-off measurement time, and to eliminate
noise during these intervals.

Y -matrix and adaptive black level, gamma and satu­ration controls

Saturation control is performed by varying the amplitude
of the RGB signals relative to the luminance signal ampli­tude. For this reason the luminance signal has to be re­generated in the Y-matrix from the RGB signals.
After the Y-matrix, the luminance signal is fed to the adap­tive black level control stage. This detects the lowest volt-

Nom white
level

Nom black
level

Input si

nal Adaptive Black level Control Gamma Adjust

Principle of the adaptive black control and gamma adjust

age of the luminance component of the internal RGB sig­nal during the scanning time and moves it to the nominal
black level. In order to keep the nominal white level con­stant, the contrast is increased simultaneously. The proc­ess expands the dynamic range of the contrast.
Next, the luminance signal is processed in the gamma ad­justment stage. This has a non-linear transmission charac­teristic. The gamma adjustment stage amplifies the lower
levels of the signal using a higher gain. This process im­proves the separation of the dark parts of the picture from
each other. Finally the luminance signal is fed to the col­our saturation control stage.
The Y-signal is fed in addition to the adaptive black level
control stage through an internal switch to the output pin
26 and onwards to the SVM module.
The gamma and saturation adjustments are controlled
using the IIC-bus.

14

Contrast and brightness control

Both adjustment blocks consist of electronic potentiometers
and are controlled via the IIC-bus. The contrast control has
an influence on the amplitude of the RGB signals and the
brightness control on the DC level of the RGB signals rela­tive to the black level.

Blue stretch

The blue stretch channel gives additional amplification if
the blue signal is greater than 80% of the nominal signal
amplitude. In such cases, the white point is shifted towards
a higher colour temperature so that white parts of the pic­ture seem to be brighter.

ing generator includes a line counter which controls the
blanking and measurement pulse insertion stages.

Switch-on delay circuit

After switch on, all signals are blanked and a warm up test
pulse is fed to the outputs during the cut-off measurement
lines. If the voltage on the cut-off measurement input ex­ceeds an internal level, the cut-off control is enabled but
the signal still remains blanked. Signal blanking is stopped
when the cut-off control has stabilized.

CRT module

Measurement pulse insertion and blanking

During the horizontal and vertical blanking time and the
measurement period, the signals are blanked to an ultra
black level, so the leakage current of the picture tube can
be measured and compensated for automatically.
Measurement pulses are generated in the timing genera­tor and are inserted into the R channel during line 20, the
second is inserted into the G channel during line 21 and
the third is inserted into the B channel during line 22. These
measurement pulses are fed with the RGB signals to the
video output amplifiers (ICh1, ICh2 and ICh3), and feed back
the voltage levels to pin 19. During the cut-off measure­ment lines, the output signal levels are at the cut-off meas­urement level. The vertical blanking period is timed using
a sandcastle pulse. The measurement pulses are triggered
by the negative going edge of the vertical pulse of the
sandcastle pulse and start after the following horizontal
pulse.

White point adjust, automatic cut-off control and
output stages

The nominal signal amplitude can be varied ±50% by the
white point adjustment using the IIC-bus. During the leak­age measurement time, leakage is compensated in order
to get a reference voltage on the cut-off measurement in­put pin 19. This compensation value is stored in the exter­nal capacitor on pin 17. During cut-off current measure­ment times for the R, G and B channels, the voltage on this
pin is compared with the reference voltage, which is indi­vidually adjustable via the IIC-bus for each colour channel.
The control voltages so derived are stored in the external
feedback capacitors on pins 21, 23 and 25. Shift stages add
these voltages to the corresponding output signals. Finally,
the RGB signals are amplified to the nominal value of 2
Vpp and the signals are output on pins 24 (R), 22 (G) and
20 (B).

Beam current and peak drive limiting

The circuit is provided with two kinds of signal limiter. An
average beam limiter, which reduces the signal level if a
certain average value is exceeded and a peak drive limiter,
which is activated if one of the RGB signals even briefly
exceeds the IIC-bus determined threshold. The beam cur­rent limiting voltage is taken from the cathode current in­formation and fed via transistors tt4 / tt1 and capacitor Ct29
to pin 15. If the voltage on the pin 15 decreases below +4 V
due to the charge of capacitor Ct29, the internal limiter starts
to reduce the contrast. If the voltage decreases below +2.8
V, the limiter also starts to reduce the brightness.

Video output amplifiers ICh1, ICh2 and ICh3

The video output stage consists of three separate output
amplifiers, TDA6111. The circuit has a high slew rate and a
large 16 MHz bandwidth and is thus suitable for 100 Hz
applications. The circuit is protected against CRT flashovers
and electrostatic discharges (ESD).

The RGB signals from the RGB video processor are fed via
low pass filters to the inverting input pin 3 of the amplifi­ers. The non-inverting input pins 1 are connected to a volt­age level of +3 V. The amplifiers have two outputs for the
picture tube cathodes, pin 8 for the DC currents and pin 7
for the transient currents. After these output pins the am­plified RGB signals are fed to the picture tube cathodes.
The feedback information is output from pin 9 and con­nected via a resistor to input pin 3. Monitoring of the black
level of the cathodes is done via output pins 5. These out­puts are connected together via resistors and the final re­sult is fed to the RGB video processor, pins 19 (cut-off con­trol) and 15 (beam current). The required supply voltages
are fed to pins 2 (+12 Vp) and 6 (+200 V).
A negative flyback pulse from the diode split transformer
Mk1 (DST) is fed to the control grid G1 via connector Xh1­2, capacitor Ch19, and resistor Rh28. This intensifies the
horizontal blanking during the line flyback.
The blanking of the screen after switching off is done by
transistors Th1 and th2. During normal operation, capaci­tor Ch27 is charged to +12 V and capacitor Ch18 to +200 V.
When the set is switched off, Ch27 discharges to the base
of Th1. The transistor conducts and discharges Ch18 as
negative charge on to the control grid G1. Also, capacitor
Ch28 is charged to +12 V and when the set is switched off,
the base of th2 goes low and the transistor conducts. Ch28
discharges to the non-inverting input pin 1 momentarily
causing about +200 V to be fed to the outputs. This pre­vents the increase of the beam current until Th1 has had
time to block the picture tube.

Sandcastle detector and timing generator

The two level (2.5V / 4.5V) display sandcastle pulse (DSC)
from the deflection controller on the Feature box is fed to
input pin 14. The sandcastle detector separates the
sandcastle pulse into combined line, field pulses and clamp­ing pulses, which are fed to the timing generator. The tim-

Teletext

y

Megatext SDA5273, ICr1

The SDA5273 Megatext circuit is a single chip which com­bines data slicer, teletext processor, page / pixel memory,
and display controller. Digital signal processing is used to
eliminate external discrete components.
The memory can be extended using an external DRAM to
increase the teletext capacity.
The multistandard capability of the Megatext circuit en­sures its suitability for all countries which transmit the
World System Teletext (WST) level 1.5.
The Megatext circuit functions are the decoding and dis­play of teletext information from an analog source, CVBS
input, and the generation of On Screen Displays, which
can provide the TV user with status information or assist­ance. The RGB output of the Megatext IC is connected to
the RGB input of the RGB video processor together with
fast blanking information.
The Megatext IC is controlled through the M3L-bus which
has a maximum data rate of 1 Mbit/s.

Circuit description

The CVBS signal from the video matrix switch is fed to
input pin 9.
The basic principles of the signal handling are shown in
the block diagram below.
The analog RGB signals and fast blanking signal are out­put on pins 44 (R), 45 (G), 46 (B) and 47 (FB). The vertical
sync pulse (2V) is fed to pin 3 and the horizontal sync pulse
(2H) to pin 4. Sync pulses are taken from the Feature box
(VDFL and HDFL).
An external 20.48 MHz crystal is connected between pins 5
and 6. Pins 18...35 and 37 are the address and data lines
for the external DRAM (icr2). The +5 Vr supply voltage is
fed to pins 10, 11, 13, 15 and 17. A high level on pin 14
causes the chip to be reset.
A stabilized 3.3 V reference voltage for internal use, from
the zener diode Zdr1, is connected to pin 16.
The Megatext circuit communicates with the
microcontroller via the M3L-bus, using pins 49 (SCL), 50
(SDA) and 51 (IICENable).

15

Data Slicer separates the teletext data from

the digitized CVBS signal.

Acquisition Interface synchronizes the bytes, con-

verts serial bits to the parallel
bytes and detects the framing
code.

Processing Unit manages the interchange func-

tions between acquisition,
memory, display, and bus inter-

face.
Internal Memory Internal 24 Kbyte DRAM.
Ext DRAM Interface Interface between the megatext

and external DRAM.
Display Generator controls data transfer from

IRAM to DG, decodes the dis-

play words, controls the display

formats and generates special

cursors.
Character ROM Character pixel memory.
CLUT Colour look up tables.
Display clock and Timing generates the horizontal timing

signals for the display and a line

locked display clock.
FIFO speeds up the pixel rate from

normally 24 MHz to 32 MHz in

16:9 mode.
D/A converter produces analog RGB signals.
Bus Interface M3L-bus interface between the

Megatext and microcontroller.

Megatext Plus SDA5275, ICr1

The Megatext Plus circuit SDA5275 is based on the origi­nal Megatext circuit SDA5273. The main difference is in
the internal data processing, which enables the teletext data
processing in accordance with the level 2.5. The level 2.5
generates much better graphics (bitmap graphics), more
colours (4096) and an extension for the 16:9 format, which
enables a wider display page. Consequently, the level 2.5
can display 56 characters on each 25 lines (1400 charac­ters / page). The level 1.5 can display only 40 characters
per line (1000 characters / page).
Because of higher level pages, the Megatext Plus circuit
always requires an external memory circuit.

M3L-Bus RGB

CVBS

SDA 5273

Data
Slicer

A/D

Converter

Sync
Slicer &
Timing

Crystal

Oscillator

20.5 MHz
Cr

stal

Interface

Bus

Interface

Acq

PU

24-KByte DRAM

External DRAM-Interface

to external
DRAM

DAC

FIFO

CLUT

Display

Generator

Character
ROM

Display
Clock &
Timing

2V

2H

A/D Converter converts the CVBS signal to 7-

bit binary code.

Sync Slicer and Timing separates the hor/vert sync

from the digitized CVBS signal
and generates a line-locked 24
MHz acq clock.

Teletext memory DRAM, icr2

The external teletext memory is a 4 Mbit high-speed Dy­namic Random Access Memory (DRAM). It is organized as
1 048 576 four-bit words (4 194 304 bit). The circuit uses
CMOS silicon gate technology.
One teletext page takes 1 Kbyte (8 192 bit) of memory, so
the circuit is able in theory to store 512 teletext pages (4
194 304 : 8 192 = 512). This reduces the page access time
to virtually zero.
During the first cycle of the teletext transmission, the
memory circuit is formatted for the transmitted pages.
During the second cycle, transmitted pages are stored in
the memory.

16

CONTROL SYSTEM

The control system consists of the following circuits,

- Program memory, ICf1

- NV RAM, ICf2

- Microcontroller, icf3

- AND gate, icf4

- Reset circuit, icf5 and

- Remote control and local control

Program memory, ICf1

Depending on the receiver version, the chassis may be
equipped with either 4 Mbit or 8 Mbit program memory.
Both are high speed Ultraviolet erasable and Electrically
Programmable Read Only Memories (UV EPROM). Later,
also an OTP (One Time Programmable) ROM or just a ROM
can be used.
The 4 Mbit (512 kbyte) memory is organized as 524 288
eight-bit words. The microcontroller addresses this
memory using the address lines A0...A18.
The 8 Mbit (1024 kbyte) memory is organized as 1 048 576
eight-bit words. This memory needs extra banking. This is
carried out by icf4, which divides the address space into
four separate blocks, data bank 0, 1, 2, and 3. The basic
software is programmed into data banks 0 and 1. Data
banks 2 and 3 are used for the Menu text and Electrical
User Manual (EUM) text.
The program memory communicates with the
microcontroller via the address and data bus.

NV RAM, ICf2

The NV RAM is a low power CMOS, 16 kbit Electrically Eras­able and Programmable Read Only Memory (EEPROM). It
is organized as eight separate address blocks, each con­sisting of 256 eight-bit words (8 x 256 x 8 = 16 384 bits).
Data is transferred via the IIC-bus.
Settings which can be stored in NV RAM include TV pro­gram memory location information, IIC-bus controlled serv­ice adjustments, normalization settings, user settings, op­tion and configuration data, and teletext bank pages.

Microcontroller, icf3

The SDA30C264 is a low power CMOS circuit which in­cludes an eight-bit CPU, a 2048 byte + 256 byte data
memory (RAM), an oscillator and clock circuits, two 16-bit
timers / counters and a watchdog timer. The microcontroller
is connected to the program memory via address and data
bus and to the other circuits via the IIC-bus.
Depending on the size of the program memory (4 Mbit or
8 Mbit) and the picture ratio (4:3 or 16:9), some compo­nents (and gate icf4 and few jumpers) are either installed
or omitted. Consequently, some microcontroller pins have
different functions.
The pins marked by an asterisk (*) are explained in more
detail after the pin configuration table.

Pin configuration of the microcontroller SDA30C264

Pin Description

1 Headphone switch input, Hp connected = high
2 AV-link data out to scart pin 10, high pulses
3 * 4Mb/4:3 : TA700 status in, plug connected = high

All 8Mb and all 16:9 : picture tilt output, 0...5 V
4 M3L-bus, enable for Megatext, enable = low
5 Hor shift adjustment in VGA sets

(PWM -> Xo3-1 = 0...5 V)
6 * 4Mb/4:3 : RGB status in, status on = high

All 8Mb and all16:9 : RGB status in = high / TA700

status in, plug connected = high
7 Hold from service connector, hold = low
8 * Bank 1 / EPROM data bank selection control (8Mb)
9 * Bank 0 / EPROM data bank selection control (8Mb)
10 Ground
11 Supply voltage, +5 Vstb

12...13 Crystal 12 MHz
14 Reset input, reset by low
15 Not connected

16...28 Address bus for program memory (EPROM)

29...36 Data bus for program memory (EPROM)

37...39 Address bus for program memory (EPROM)
40 Ground
41 Supply voltage, +5 Vstb
42 Address bus for program memory (EPROM)
43 * EPROM data bank control (8Mb). Low = data

bank 0, high = data banks 1, 2 and 3
44 IIC-bus, serial clock
45 IIC-bus, serial data
46 Rec LED on by low / Local control read pulse out

(in to pins 61 or 62)
47 * Multistandard IF = strobe pulse (low) for data latch

Non multistandard IF = APSi filter driver, APSi

by high
48 * P_on, picture on voltages by low
49 * R_on, recording voltages by low
50 * Reset pulse (high) for MSP / Subwoofer

identification = low
51 * Audio mute by high / Identification of 16:9 (lower

voltage), 4:3 (higher voltage)
52 * Scart 3 identification / status in (off = 0 - 1.2V,

16:9 = 1.3 - 3.2V, 4:3 = 3.3 - 5V)

53...54 Scart 1, 2 status in (off = 0 - 1.2V, 16:9 = 1.3 - 3.2V,

4:3 = 3.3 - 5V)
55 Version identification of IF module. Reads the

resistor R556 (multi) / R526 (non multi)
56 GND
57 Address for program memory (EPROM)
58 Reference voltage of internal D/A-converters
59 M3L-bus, clock for Megatext
60 M3L-bus, data for Megatext
61 Local control 2 input
62 Local control 1 input
63 AV-link data in from scart pin 10, low pulses
64 Remote control input, high pulses

The list below gives more detailed information about each
pin marked *.

3 a) In 4:3 sets with 4 Mbit program memory, pin 3 inputs

status information (line out status) from the adjustable
audio module. It indicates whether the module is in use
or not, that is, whether the plug is connected or not. If
the plug is connected, transistor ta9 does not conduct
and pin 3 is high. This activates a three level mute se­lection: 1) TV’s speakers are muted, 2) TV’s speakers
and adjustable audio module are muted or 3) no mute.
The circuit icf4 is not installed and the link to the pic­ture tilt adjustment is disconnected.
b) In all 16:9 and all 8 Mbit program memory sets, pin 3
outputs a picture tilt adjustment. In these cases, infor­mation from audio module is disconnected. With the
tilt adjustment the picture declination caused by the
magnetic field of the earth can be compensated for.
Depending on the control voltage, transistors tt5, tt6
and tt7 drive the voltage either from +12 Vr via the can­celler coil to +5 Vr (low control voltage, tt6 conducts) or
from +5 Vr via the canceller coil to ground (high control
voltage, tt5 and tt7 conduct).

6 a) In 4:3 sets with 4 Mbit program memory, pin 6 oper-

ates as an indication of the RGB status (rf51 is installed).
If the RGB connection is in use, transistor tq4 does not
conduct and pin 6 is high.
b) In all 16:9 and all 8 Mbit program memory sets, pin 6
operates as an indication of the RGB status (= scart pin
16 high) and TA700 status via icf4 (rf51 is not installed).
The software periodically checks the status by feeding
out a high level from µC pin 9 to icf4-4 pin 13, and if
icf4-4 pin 12 is high (RGB status on), pin 11 feeds a high
level out to µC pin 6.
The same checking routine takes place for the TA700
status, but this uses µC pin 8 and icf4-3. During this
check, µC pin 43 (A18) is always low. This means that
the levels on pins 8 and 9 have no influence on the data
banking of the EPROM.

17

48 / P_on 49 / R_on Description

H H Micropower standby mode,

power supply does not operate

L L TV on mode, Vr, Vp and Vstb

available

H L Rec mode, Vr and Vstb available,

Vp not available

L H Service standby, Vstb available,

but not Vr neither Vp

The receiver is in service standby mode whenever it
has been set to service mode by pressing the -vol /
menu, TV and i buttons, but not yet switched on by
pushing the TV button twice. Service mode is indicated
by the rec LED (illuminated), as well as rec and service
standby modes.

50 a) During startup phase, pin 50 feeds out a positive

going reset pulse for the sound processor.
b) By sensing the load on the reset pulse, pin 50 de­tects whether or not the subwoofer is installed. If the
subwoofer is installed, resistor Ra107 is also present in
which case the amplitude of the reset pulse is smaller
than it is when Ra107 is absent. This check takes place
during the configuration phase (in service mode when
the red button is pressed).

51 a) During the configuration phase, pin 51 checks the

resistor ra10 via transistor ta10 (b-e) in order to identify
the picture tube ratio. Low resistance indicates 16:9 and
high resistance 4:3
b) During normal operation the audio amplifier can be
muted by a high level on this pin (central mute)

52 a) In the configuration phase, pin 52 checks the possi-

ble installation of a scart 3 module by checking the re­sistor ra26 (on the scart 3 module)
b) Pin 52 operates as a status input pin from scart 3

8/9 When µC pin 43 is high, these pins select, via icf4-1 and

icf4-2, the required data bank, either 1, 2 or 3.
When µC pin 43 is low, only data bank 0 is in use, thus
pins 8 and 9 have no influence on data banking, but
they can be used for other functions.

43 Pin 43 is an address line that is used for data banking of

the 8 Mbit program memory. When the pin is in a low
state, data bank 0 is selected, and when high, either 1,
2 or 3 are selected. For the 4 Mbit memory, pin 43 is a
normal address line (A18)

47 a) In multistandard sets, pin 47 feeds out a strobe pulse

(low) for the shift register on the IF block
b) In non multistandard sets, pin 47 drives the switch­ing transistor T501 on the IF block. During channel
search (APSi), pin 47 is high

48/49

The combination of levels on these pins determines the
working state of the receiver as follows:

AND gate, icf4

The AND gate icf4 operates as a function expander in all
16:9 sets (4 and 8 Mbit program memory) as well as in all
sets equipped with 8 Mbit program memory (4:3 and 16:9).
In these cases, the jumpers rf30 (program memory pin 31),
rf31 (program memory pin 1), rf48 (µC pin 3) and rf51 (µC
pin 6) are not installed.
In 4:3 sets with 4 Mbit program memory, the AND gate is
not installed, but the above mentioned jumpers are in­stalled.
For a more detailed description, refer to microcontroller
pins 6, 8, 9 and 43.

Reset circuit, icf5

The microcontroller is reset by a special reset circuit, icf5
(TL7705A). When the receiver is switched on, pin 5 feeds a
low level to pin 14 of the microcontroller until the +5 Vstb
on the monitoring pin 7 (sense) reaches a level of +4.55 V.
After that the reset continues for about 30 ms. Then pin 5
goes high and the microcontroller is reset. The reset delay
time of 30 ms is determined by capacitor Cf21 on pin 3.
If the +5 Vstb drops below the 4.55 V threshold level even
for a moment, reset takes place immediately and the
microcontroller is blocked causing the receiver to switch
to micropower standby mode.

18

Remote control

The remote control uses the NRC-17 coding system based
on a 17-bit biphase code. The infrared receiver / amplifier
Hfc1 receives pulse modulated infrared light. The receiver
converts the light into an electrical signal, which is demodu­lated, amplified, and fed out from pin 3. The signal is taken
to microcontroller pin 64 via transistor tfc3. During code
transmission, the microcontroller sends negative pulses
from pin 46. This causes LED Dfc4 to flash as an indication
of the accepted code.

Local control

The local control comprises only four primary daily use
functions: volume + / - and program stepping + / -. These
functions makes it possible to use the receiver without the
hand-held remote control unit. The information from func­tion switches SWfc1...SWfc4 is fed to microcontroller pins
61 and 62.
The LEDs on the local control unit indicate the receiver state
as follows:
In On-mode, the green LED Dfc17 lights due to the +12Vp.
In Stby-mode, the red LED Dfc16 (on the micropower block)
lights to indicate the mains voltage is connected.
In Rec-mode, the red LED Dfc4 lights due to the low level
on microcontroller pin 46.

DEFLECTION STAGES

- Vertical deflection

- Horizontal deflection

19

Vertical deflection

The TDA8354 is a DC-coupled Vertical Deflection output
circuit containing an internal vertical flyback generator and
a guard circuit. The output amplifiers and flyback genera­tor are fitted with power FETs. The IC is thermally protected
and in addition it is protected against short circuits between
the outputs and from the output pin to ground and to the
supply voltage.

Functional description

Symmetrical vertical pulses from the deflection processor
TDA9151 are fed via pins 11 and 12 to a current driven
differential input circuit. The current to voltage conversion
is carried out by resistor rs4 via input pin 3. The voltage on
pin 3 is compared with the feedback information on pin 2.
The feedback information is taken from the output current
through the deflection coil measured across resistors Rs2,
Rs3 and Rs5.

The signals are amplified using a vertical driver circuit in a
bridge configuration.
The deflection coil is connected between the phase oppo­sition driven amplifiers at output pins 5 and 9. The output
current is determined by the value of resistor rs4. The re­sistor network (VD6xx), connected in parallel with the de­flection coil, damps down the high frequency oscillation
which tends to be generated at the end of the flyback pe­riod. Resistor rs6 on pin 13 is added to compensate for the
current differences in the dumping resistors during the scan
and flyback period.

The operating supply voltage of +16 V on pins 4 and 10,
and the flyback supply voltage of +50 V on pin 7 are taken
from the diode split transformer Mk1. Operation with two
supply voltages (class G) makes it possible to set both sup­ply voltages independently to their optimum values. In this
way a very high efficiency is achieved. Due to the bridge
configuration, a decoupling capacitor is not necessary. Thus
almost the whole flyback supply voltage is available across
the deflection coil.

The output of an internal guard circuit is connected to pin

1. The sandcastle pulse (DSC) from the deflection proces­sor is also connected to the same pin.
The guard circuit is activated in possible fault situations,
such as short circuits at output pins, an open deflection
loop, or circuit overheating. In such cases the guard circuit
increases the DC level on pin 1 to 2.5 V. This is the same
DC level as the blanking level of the sandcastle pulse. This
causes blanking of the screen that protects the picture tube.

Horizontal deflection

The horizontal drive signal from the deflection processor
is fed to the driver transformer Mk2 via a pulse shaping
network consisting of transistors tk6, Tk1, Tk2, and associ­ated components. The circuit Dk5, Rk30 and Ck17 limits
the switching transients of Tk2. The +17 V supply voltage
for the transformer is taken from the power supply. The
secondary winding of the transformer is connected to the
base of the line output transistor Tk3, which drives the di­ode split transformer Mk1 and the line output stage.
The functional description of the line output stage starts
from the time t5 when the drive signal becomes negative,
the line scan period is stopped and the line flyback period
t1 starts (picture below).

t5

t2 t4 t5 t1t3Iscan

t1

Line flyback (t1...t3)

Due to the cut off of the Tk3 collector current, the energy
stored in the deflection coil at the end of the scan period
flows to flyback capacitor Ck24. The energy flow contin­ues until time t2, when all energy has been transferred and
the collector voltage reaches its maximum value. The cur­rent then changes direction and energy from the capacitor
flows back to the deflection coil. At time t3 the flyback ca­pacitor is discharged and the voltage across it is 0 V. It
then becomes negative as the deflection coil starts the scan
period by feeding its energy to capacitor Ck27 (and Ck33).

Line scan (t3...t5)

At time t3, when the deflection coil starts to feed its energy
to Ck27, current begins to flow via diode Dk7. At time t4,
which is the mid point of the line scan, the drive pulse on
the base of Tk3 becomes positive again and the deflection
current can flow via transistor Tk3 and diode Dk8. From
time t4 to t1, the deflection current changes direction and
energy moves from Ck27 into the deflection coil. At time
t5, that is the end of line scan, the drive signal of Tk3 be­comes negative and the flyback period begins again.
To achieve continuous operation, the energy from the
power supply is stored in the primary winding of Mk1 (pins
6 and 3) during the scan period when Tk3 is saturated. Some
of this energy is used to compensate for the deflection
losses.

Deflection corrections

The parabolic E-W correction pulse from the deflection
processor is fed through transistors ts1 and ts2 to the base
of transistor Tk4, which drives the E-W correction circuit
consisting of capacitors Ck26, Ck28, diode Dk8 and bridge
transformer Mk3.

20

n

The picture width, and E-W correction adjustments (pa­rabola, corner and trapezium) are carried out by modulat­ing the current across coil Lk1.
The circuit Ck38, Dk9, Rk49 and Rk52 in parallel with S­correction capacitor Ck27 eliminates the so-called “mouse
tooth” phenomena.

Dynamic focus, FO600

A dynamic focus adjustment is used in addition to the nor­mal focus adjustment. The dynamic focus improves the
focus on both sides of the screen. In order to have a higher
focus voltage at the beginning and end of the scan period,
an auxiliary voltage is needed. This voltage is taken from a
transformer, which is connected in series with the horizon­tal deflection coil. The parabolic voltage across the trans­former is fed via a capacitor to the dynamic focus
potentiometer and onwards to a discrete focus grid. The
dynamic focus is used only in larger picture tubes.

Horizontal scan shift and dynamic focus, FO7xx

Receivers with a VGA connection (Feature box DB700) are
equipped with a special FO7xx module which includes a
horizontal scan shift adjustment, and also, when needed,
dynamic focus.
The horizontal shift control voltage (0...+5 V) is taken from
microcontroller pin 5 to the module connector Xfo3-1. The
connector Xfo3-2 is connected to +12 Vp.
When the control voltage is low, transistor tfo5 conducts.
Due to resistors rfo4, rfo5 and rfo6 the base voltage on
transistors tfo3 and tfo4 is low, causing tfo3 and Tfo1 to
conduct. Diode Dfo2 conducts and capacitor Cfo7 is charged
to the positive voltage, which is fed onward to the deflec­tion path via resistor Rfo2 and transformer pins 2 and 4.
When the control voltage is high, transistor tfo5 is switched
off and resistors rfo4 and rfo5 are not in parallel connec­tion with rfo6. This means that the voltage level on the
bases of tfo3 and tfo4 is high, causing tfo4 and Tfo2 to
conduct. Diode Dfo1 conducts and capacitor Cfo6 is charged
to the negative voltage, which is fed to the deflection path.
By varying the control voltage between 0 and 5V, the de­flection path can be made more negative or more positive,
and thus the horizontal scanning can be shifted sideways.
Capacitors Cfo2 and Cfo3 operate as S-correction capaci­tors. This means that in VGA sets, the original S-correc­tion capacitors (Ck27 and Ck33) on the main board are short
circuited.

Capacitor Cfo4 and coils Lfo1 and Lfo2 apply an additional
correction to the linearity.

Diode split transformer Mk1

The primary winding (pin 6) of the diode split transformer
(DST) is connected to the +130 V supply voltage via FET
switch Tsw1. In order to protect the switching transistor in
the power supply, power consumption will be reduced
during the switch off phase by the FET. During normal op­eration, the FET conducts due to a high level on the gate.
When the TV set is switched off, the +12 Vp drops and tran­sistor Tsw2 conducts. Capacitor Csw1 discharges through
transistor Tsw3, which conducts and grounds the gate caus­ing the FET to switch off.
The DST produces the flyback pulses from the primary
winding (pins 6-3) to the secondary windings and gener­ates the following voltages:

- High voltage (30kV) for the picture tube anode

- Focus and screen grid (Ug2) for picture tube

- Filament voltages for the picture tube cathode from pins
10-11

- +200 V for the video output amplifiers from pins 12-4.
This voltage is rectified by diode Dk1

- +50 V from pins 1-5 or +46 V from pins 2-5 for the vertical
IC. This voltage is rectified by diode Dk2

- +16 V for the vertical IC from pins 7-5. This voltage is rec­tified by diode Dk3

- EHT information from pin 8 (and Ck21)

+30 V

U1

+12 Vp

+17 V

Hor
drive

ZDk1

Tsw1

Tk1

Rk11-14

Tk2

Mk2

+53 V

+16 V

E-W
drive

Dk2

Rk9

Dk3 Rk19

Tk3

Tk4

Mk1

Dk7

Dk8

Ck26

Ck28

Lk1

Rk2 Dk1

Ck24

Mk3

Ck27/33

Lk2

EHT 30 kV
Focus
Ug2

EHT compensatio
Filament 6.3 V
+200 V

Defl
coil

OPTIONS

Active Subwoofer
Comb Filter CF700
SVM module
Audio Feature AR700
Audio Feature AR701
Adjustable Audio TA700
Scart 3 + VGA-audio TA710
Scart 3 TA711
Picture in Picture PP700 / 710

Active Subwoofer

21

General

The active subwoofer system provides a clear improve­ment in stereo sound. The system consists of active filters,
power amplifiers, a subwoofer, and stereo speakers. The
active subwoofer stage is designed to be used with an in­ternal subwoofer box and stereo speakers in the TV set or
with small external front speakers.

Functional description

The left and right stereo channels are already added to­gether in the sound processor MSP3410D. The sound proc­essor also includes the required lowpass filters for the
subwoofer channel and highpass filters for the loudspeaker
channels.
The signal is taken from sound processor pin 31 and fed
onward to the high pass filter (40 Hz), consisting of transis­tor ta6 and associated components.
The filtered signal is then fed to the audio power amplifier,
ICa4. The amplifier can be muted by pulling pin 2 low. The
mute control signal is taken from microcontroller (pin 51)
via transistors ta10, ta4 and ta5. This mute function mutes
each of the audio power amplifiers in the set. However,
the subwoofer amplifier can also be muted separately. This
can be done via the audio processor. A high level on pin 5
drives transistor ta5 to conduct, which just mutes the
subwoofer amplifier. Due to the resistor network ra106,
ra105 and ra14, the central mute will be not activated in
this case.
The amplifier operates in a bridge configuration. The out­puts are internally inverse feedback connected to the in­puts of each other. The amplified, phase opposition sig­nals are output from pins 4 and 6 to the subwoofer speaker.

Comb Filter module, CF700

Functional description

Depending on the standard, the module either bypasses
or filters the input signal as follows:

PAL and NTSC 3.58

The signal is fed to comb filter IC and separated
for Y and C signals

NTSC 4.43 and SECAM

The signal is fed to comb filter IC, but it is not sepa­rated

S-VHS The signal is bypassed in the multiplexer IC

The standard is identified in the colour decoder Icd1. The
standard information is input to the microcontroller via the
IIC-bus and back to the colour decoder again. The infor­mation is output from pin 23 to comb filter module pin 1,
from pin 16 to module pin 2, and from pin 15 to module
pin 13.
Module pin 1 controls the multiplexer to bypass the video
signal (“L”) or to feed the signal to the comb filter IC (“H”).
When pin 1 is high, it inputs the colour subcarrier frequency
(Fsc) to an internal clock generator of the comb filter IC.
Module pin 2 defines the comb filtering method, PAL (“L”)
or NTSC 3.58 (“H”).
Module pin 13 drives the comb filter IC to be in comb filter­ing mode (“H”), at which time the IC performs Y / C sepa­ration. Or to be in a bypass mode (“L”), whereat the signal
is not separated, but fed only via an internal delay stage.
In addition, pin 13 informs the colour decoder the exist­ence of the module by transistor tc3 (base-collector joint).
Depending on which standard is in use, the logical high /
low level combinations are as follows:

General

The basic function of the comb filter is to separate the lu­minance (Y) and chrominance (C) signals from the CVBS
signal. The device minimizes problems caused during Y /
C separation such as dot-crawl and cross colour interfer­ence. In addition, it allows the input video signal to have
an extended frequency bandwidth. This is carried out us­ing a clock frequency of four times the colour subcarrier
frequency. The filter is capable of handling signals accord­ing to the PAL and NTSC 3.58 standards. The module con­tains two ICs, the multiplexer circuit, icc1 and the comb
filter circuit, icc2.

Standard module module module

pin 1 pin 2 pin 13

PAL “H“ + 4.43 “L” “H“
NTSC 3.58 “H“ + 3.58 “H“ “H“
NTSC 4.43 “H“ + 4.43 “L” “L”
SECAM “H“ + 4.28 “L” “L”
S-VHS “L” “L” “L”

22

PAL signal

The PAL CVBS signal from module pin 6 is input to multi­plexer pin 4. Due to the low level on control pin 9 (note
inverter tc10), the signal is output from pin 5, and onward
via an amplifier stage tc7 / tc8 to a low pass filter. After the
LPF and buffer transistor tc9, the signal is input to pin 15 of
the comb filter IC.
In the comb filter IC, the composite video is clamped to an
internal level and then converted by a high speed 8-bit A/D
converter. The conversion frequency is four times the col­our subcarrier frequency. Due to the PAL standard, the Fsc
on pin 45 is 4.43 MHz, thus the conversion frequency is

17.7 MHz.
A logical low on pin 41 drives the video data in to the comb
filter processing block and a logical low on pin 47 defines
the filtering method in accordance with the PAL standard.
The separate luminance and chrominance signal data is
then converted into analog form by two 8-bit D/A convert­ers. The conversion is carried out using the same clock
frequency of 17.7 MHz.
The luminance signal is output from pin 6, via the emitter
follower tc11 into multiplexer pin 12, out from pin 14, and
then on through the emitter follower tc6 to the module
output pin 10.
The chrominance signal is output from pin 8, via tc12 into
multiplexer pin 2 and output from pin 15, and then on
through tc4 to module output pin 11.

NTSC 3.58 signal

The signal routes are exactly the same as the PAL signal
routes. The only difference takes place in the comb filter­ing system inside the comb filter IC. Pin 47 is high, thus a
different filtering method is selected. The conversion fre­quency is now 14.3 MHz due to the Fsc of 3.58 MHz on pin

45.

NTSC 4.43 and SECAM signals

The signal route to the comb filter IC is the same as above.
However, now pin 41 is high and thus the comb filter IC is
in bypass mode. The signal is fed only via the A/D con­verter, memory block and D/A converter. The conversion
frequencies are 17.7 MHz (NTSC) and 17.1 MHz (SECAM).
The NTSC 4.43 and SECAM signals are fed via the comb
filter IC because the internal memory block imposes a two
line delay on the signal. If these signals were already by­passed in the multiplexer and the received standard
changed, for example, from SECAM to PAL, a momentary
loss of sync would occur.

Scan Velocity Modulation module, VM600

General

The purpose of the Scan Velocity Modulation (SVM) mod­ule is to increase the sharpness of the picture during inten­sity transients of the luminance signal.
The scan velocity modulation is carried out so that the lu­minance signal (a), which contains intensity transients, is
first differentiated and then amplified (b).
In this way the signal produced is fed to an auxiliary coil,
which is situated at the neck of picture tube. The current
which flows through the SVM coil during intensity tran­sients modulates the deflection field (c), and thus either
speeds up or slows down the scan velocity.

White

Luminance
signal

Black

SVM
signal

Deflection

Chess pattern

Scan velocity slower
Scan velocity faster

Basic principle of Scan Velocity Modulation

The luminance signal is first derived by two consecutive
differentiators consisting of cvm2/rvm2 and cvm1/rvm1/
rvm3.
The derived signal is preamplified by transistors tvm1 and
tvm2, and then fed to the limiter stage, which consists of a
differential amplifier, transistors tvm3 and tvm4.
The limited signal is then fed via a driver stage (tvm6 and
tvm7) to transistors Tvm8 and Tvm9, which form the out­put stage, and onwards to the SVM coil.

Grid pattern

a)

b)

c)

S-VHS signal

The S-VHS signal is input to module pins 6 (Y) and 7 (C)
and onward to the multiplexer, pins 4 and 1. Pin 1 of the
module is now low, and this causes control pin 9 to go
high, and the internal switches of the multiplexer change
to bypass mode. The luminance signal is output from pin
14 and chrominance signal from pin 15.
If the transmission is a pure monochrome signal or pure
noise, meaning that there is no burst, the signal is bypassed
like an S-VHS signal. This is because there is then no col­our subcarrier which is needed in the signal processing.