Hitachi HD-R161, HD-R081 Service Manual
SERVICE MANUAL
MANUEL D'ENTRETIEN
WARTUNGSHANDBUCH
CAUTION:
Before servicing this chassis, it is important that the service technician read the “Safety
Precautions” and “Product Safety Notices” in this service manual.
ATTENTION:
Avant d’effectuer l’entretien du châssis, le technicien doit lire les «Précautions de sécurité»
et les «Notices de sécurité du produit» présentés dans le présent manuel.
No. 0801
HDR081
HDR161
Data contained within this Service
manual is subject to alteration for
improvement.
Les données fournies dans le présent
manuel d’entretien peuvent faire l’objet
de modifications en vue de perfectionner
le produit.
VORSICHT:
Vor Öffnen des Gehäuses hat der Service-Ingenieur die „Sicherheitshinweise“ und „Hinweise
zur Produktsicherheit“ in diesem Wartungshandbuch zu lesen.
Die in diesem Wartungshandbuch
enthaltenen Spezifikationen können sich
zwecks Verbesserungen ändern.
SPECIFICATIONS AND PARTS ARE SUBJECT TO CHANGE FOR IMPROVEMENT
Digital Set Top Box
October 2007
SERVICE MANUAL
TERRESTRIAL STB MODEL
Page 2
SERVICE MANUAL
TERRESTRIAL STB MODEL................................................................................................................................................... 2
REVISION HISTORYREV 2.0 02/03/2007........................................................................................................................... 3
GENERAL DESCRIPTION........................................................................................................................................................ 4
T816 PROJECT HARDWARE BLOCK
16MB31-1 M
STI5100
DDRAM HYNIX 512MB
HY29LV320 32 M
16
TUT
STV0360/0361(COFDM
TUNER
16SC31-2
STV6414A
16PW810-2 P
16FP38-3
VFD D
USED IC LISTS.......................................................................................................................................................................... 22
MAINBOARD
POWER BOARD
SCART BOARD
FRONT BOARD
CONNECTORS.......................................................................................................................................................................... 23
AINBOARD
(IC101)........................................................................................................................................................................ 5
36-2
TUNER BOARD
(DTOS449IV241B-DTOS443PV241B).................................................................................................................. 15
SCART BOARD
UDIO/VIDEO SWİTCH MATRİX
OWER BOARD
FRONT BOARD
RİVER/CONTROLLER IC
............................................................................................................................................................... 5
İTS
.................................................................................................................................................. 11
BIT
(2M
X
16) L
......................................................................................................................................................... 13
DEMODULATORS IC FOR TERRESTRİAL TV SET-TOP BOX
............................................................................................................................................................ 17
...................................................................................................................................................... 18
........................................................................................................................................................... 19
PT6311(IC2) ....................................................................................................................... 19
(16MB31-1) ................................................................................................................................................... 22
(16PW810-2)............................................................................................................................................. 22
(16SC31-2).................................................................................................................................................. 22
(16FP38-3)................................................................................................................................................. 22
DIAGRAM ........................................................................................................... 4
OW VOLTAGE FLASH MEMORY
(IC200)................................................................................................................. 17
(IC1) ........................................................................... 12
) .......................................................... 13
SCART CONNECTION .......................................................................................................................................................... 24
TV S
CART SOCKET
VCR S
CART SOCKET
RS232 S
RCA (A
TECHNICAL SPECIFICATIONS........................................................................................................................................... 26
TROUBLE-SHOOTING ........................................................................................................................................................... 28
PARTS LIST............................................................................................................................................................................... 30
EXPLODED VIEW.................................................................................................................................................................... 31
SCHEMATİCS........................................................................................................................................................................... 32
16PW810-2 POWER BOARD SCHEMATIC.......................................................................................................................... 32
16MB31-1 MAINBOARD SCHEMATIC ............................................................................................................................... 33
16FP38-3 FRONT BOARD SCHEMATIC.............................................................................................................................. 41
16SC31-2 AV SCHEMATIC ................................................................................................................................................... 42
16TUT36-2 TUNER SCHEMATIC ........................................................................................................................................ 44
ERIAL PORT
UDIO AND COMPOSITE VIDEO) CONNECTOR
................................................................................................................................................................... 24
................................................................................................................................................................ 24
................................................................................................................................................................. 25
................................................................................................................ 25
Page 3
GENERAL DESCRIPTION
Major functional blocks are discussed briefly in this section. A more detailed description is contained later in the document.
BLOCK DIAGRAM
Page 4
16mb31-1 Mainboard
STI5100 (IC101)
1. Introduction
The STi5100 is a low-cost Omega2 (The STBus multipath unified interconnect provides high onchip bandwidth and low latency accesses between modules. The interconnect operates hierarchically, with
latency-critical modules placed at the top level. The multipath router allows simultaneous access paths
between modules, and simultaneous read and write phases from different transactions to and from the
modules. Split transactions maximize the use of the available bandwidth.) MPEG device that delivers high
performance and integrates features that provide an overall system cost reduction. The device implements
a fully unified DDR SDRAM based memory architecture and integrates the Omega2 video decoder cell
together with a blitter engine and a multichannel DMA controller to provide enhanced performance for
graphics and real-time stream transfers.
DVR applications are supported by a dual-stream deMUX and using an HDD connected either to
the FMI or USB 2.0 port.The STi5100 includes transport stream routing and strobe decoding logic for
DVB-CI and CableCard (formerly known as POD) modules to reduce implementation cost.
2. Technical Specification
• Features
• Enhanced ST20 32-bit VL-RISC CPU
¾ 243MHz, 8Kbyte ICache, 8Kbyte DCache, 4Kbyte SRAM
• Unified Memory Interface
• Dual Transport Stream Merger
¾ Supports DVB and DIRECTV .
¾ Integrated DES-ECB, DVB and ICAMdescramblers
¾ NDS RASP compliant
¾ Low cost DVB-CI and Cable Card support
• MPEG-2 MP@ML Video Decoder
¾ Trick modes including smooth fast forward andrewind
• Audio
¾ MPEG-1 layers I/II, MP3
¾ Dolby . Digital decoding
¾ Dolby Pro Logic . compatible output
¾ PCM input, mixing and sample rate conversion
¾ SRS/TruSurrondXT . virtual surround sound
¾ Simultaneous MPEG audio decode and outputof Dolby streams
• Graphics/Display
¾ 4 display planes
¾ 2, 4 and 8 bpp CLUT graphics, 256 x 30 bits(AYCBCr) CLUT entries
¾ 16 bpp true color graphics
¾ Alpha blending, antialiasing, antiflutter,antiflicker filters
• PAL/NTSC/SECAM encoder
¾ RGB, CVBS, Y/C and YUV outputs with 10-bitDACs
Page 5
SERVICE MANUAL
¾ CGMS, Teletext, WSS, VPS and close caption
• On-Chip Peripherals
¾ 4 ASCs (UARTS)
¾ 4 parallel 8-bit I/O banks
¾ 2 smartcard interfaces and clock generators
¾ 3 SSCs for I²C/SPI master/slave interfaces
¾ Silicon Labs line side (DAA) interface
¾ High-speed USB OHCI/EHCI compliant host interface
¾ DiSEqC interface
3. Architecture overview
The figure below shows the architecture of the Sti5100.
This chapter gives a brief overview of each of the functional blocks of the STi5100.
4. STi5100 functional modules
4.1 Memory subsystem
Page 6
SERVICE MANUAL
The STi5100 has a local memory interface (LMI) and a flash and peripheral interface (FMI). The
STi5100's local memory interface is used for all data requirements in unified memory applications,
including graphics, video and audio buffers. It provides 16-bit wide DDR SDRAM support only at up to
166 MHz. The FMI provides support for 16-bit wide peripherals, flash and synchronous flash.
Local memory interface (LMI)
The LMI is a 16-bit wide DDR SDRAM interface with a peak bandwidth of 664 Mbyte/s (166
MHz). It supports one bank of 128-Mbit, 256-Mbit, or 512-Mbit DDR SDRAM. The LMI provides a fully
cacheable address space for data and instructions, with data cacheability controlled in 512 Kbyte blocks
for up to 8 Mbytes.
Flash and peripheral memory interface (FMI)
The FMI provides a glueless interface to SRAM, flash, SFlash and peripherals, in up to four
configurable banks over a 16-bit wide interface. Bus cycle strobe timings can be programmed from 0 to 15
phases for slower peripherals. The FMI output drive of the STi5100/STi5101 is programmable on a busby-bus basis. Support is provided for connection to an ATAPI HDD.
4.2 Transport stream processing
The STi5100 supports dual independent transport stream inputs using an SRAM-based packet
merger and a single programmable transport interface (PTI). The merger buffers a packet pair per channel.
The incoming transport packets are tagged with a source ID and a time stamp.
Programmable transport interface (PTI)
The PTI performs transport-stream descrambling, demultiplexing and data filtering. PESdata is
transferred by DMA to audio and video decoders using circular buffers. Section data is transferred by
DMA to separate buffers for further processing by the CPU.
• DIRECTV and DVB transport streams can be handled by the PTI with data rates up to 138 Mbit/s.
• The PTI performs PID filtering to select audio, video and data packets to be processed. 96 PID
slots can be supported by the PTI.
• The PTI can descramble streams using the following ciphers:
¾ DES-ECB,
¾ DES-CBC including DVS-042 and cipher text stealing termination block handling,
¾ DVB-CSA,
¾ NDS specific streams can also be supported for integrated ICAM functionality.
• The PTI has a section filter core that filters DVB and DIRECTV standard sections. Four filtering
modes are available:
¾ wide match mode: 48x 16-byte filters,
¾ long match mode: 96x 8-byte filters,
¾ positive/negative mode: 48x 8-byte filters with positive/negative filtering at the bit level.
Matching sections are transferred to memory buffers for processing by software.
When the PTI is required to output a transport stream, it can output the entire transport stream or selected
packets filtered by PID. A latency counter is provided to ensure packet timing is preserved. Packet
substitution can also be performed.
4.3 Audio subsystem
The audio subsystem supports multichannel audio decoding and mixing with internal PCM files.
Decoding of MPEG-1 layers I, II, MP3 and Dolby Digital stereo are supported.Decoded multichannel
Page 7
SERVICE MANUAL
audio is downmixed before emerging as stereo or Dolby Pro Logic compatible encoded audio.
Simultaneous MPEG audio decoding and output of Dolby streams on the S/PDIF is also supported. SRS
Labs’ TruSurroundXT is also provided for two speaker virtual surround sound. The integrated DACs
provide analog stereo output directly from the device using a single-ended interface.Multichannel streams
can be passed through to the IEC958 output for external decoding. Audio sample rates of 32 kHz, 44.1
kHz and 48 kHz are supported.The audio digital-to-analog converter is a high performance stereo audio
converter operating at 256 Fs system clock using single-ended voltage. This DAC accepts a 24-bit input
data in I 2 S format from the audio decoder macro block and converts them into up to 2 Vrms output
voltage. Digitized analog audio can also be input to the STi5100 using the PCM input interface and
buffered in memory via DMA. 26/830 STMicroelectronics Confidential 7603604B The audio subsystem
consists of the following units.
¾ Audio datastream controller
The audio datastream controller receives, buffers and reformats audio data. It handles up to three audio
data flows concurrently.
It receives a raw PCM stream from an external source via the PCM input interface or receives a
compressed data stream from an internal source such as the PTI and stores this in a memory buffer via
DMA. This is used to buffer and play the main audio for the digital or analog program.
It receives a PCM file or stream from a memory buffer via DMA and delivers this to the audio decoder’s
second input for sample rate conversion and mixing with the main audio.
The router is able route either source to either input of the audio decoder.
¾ Audio decoder 24-bit audio digital signal processor
The digital signal processor processes audio streams sent to it by the CD player and PCM file player.
¾ S/PDIF player
The independent S/PDIF player can output a compressed Dolby Digital audio stream independently of the
stream being decoded.
Page 8
SERVICE MANUAL
¾ IEC958/IEC1937 formatted output
The audio decoder outputs IEC958/IEC1937 formatted CD or PCM audio received from the audio
decoder.
¾ 1-channel PCM output interface
The PCM output interface outputs PCM audio received from the audio decoder.
¾ Integrated 24-bit stereo audio DAC system
¾ Programmable tone generation for dish alignment
4.4 Internal peripherals
The STi5100 has many dedicated internal peripherals for digital TV receiver applications, including:
¾ 2 smartcard controllers,
¾ 4 ASCs (UARTs), two of which are generally used by the smartcard controllers, teletext serializer
and DMA,
¾ 3 SSCs for I 2 C master/slave interfaces, with SPI support,
¾ 4.5 GPIO ports, with a further 1.5 ports mapped to transport pins,
¾ 1 PWM module,
¾ a multichannel, infrared blaster/decoder interface module,
¾ a modem analog front-end interface (MAFE),
¾ DVB common interface support,
¾ CableCard support,
¾ fully integrated digital clock recovery for MPEG (replacement for VCXO),
¾ USB 2.0 host, OHCI/EHCI compliant,
¾ interface to SiLabs line side device (DAA),
¾ an interrupt level controller,
¾ a low-power/RTC/watchdog controller,
¾ DCU toolset support,
¾ a JTAG/TAP interface.
4.5 Clock generation
All system clocks are generated using the clock generator block. This contains two high-frequency PLLs
(600 MHz) that are divided down to produce a series of phase-related programmable clock channels. The
guaranteed phase relationship between these channels simplifies interconnect bridging between different
subsystem modules and gives lower latency compared to a fully asynchronous clocking scheme.
The STi5100 is a clock master. The flash clock output may be phase aligned to optimize the external bus
performance of the FMI.
Digital clock recovery for MPEG (DCO) has been integrated using a special purpose frequency
synthesizer, thus removing the need for an external varactor diode or VCXO module. An external VCXO
can still be used for genlocking applications.
4.6 System clock
External 27 MHz clock
Either a 27 MHz clock can be fed into CLK27IN, or a crystal pi network may be connected between
CLK27IN and CLK27OSC. The crystal option and internal VCO is the option recommended by
STMicroelectronics
.
Page 9
SERVICE MANUAL
Page 10
SERVICE MANUAL
DDRAM HYNIX 512MBits
The HY5DU12422C(L)TP, HY5DU12822C(L)TP and HY5DU121622C(L)TP are a 536,870,912-bit
CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications
which requires large memory density This Hynix 512Mb DDR SDRAMs offer fully synchronous
operations referenced to both rising and falling edges of the clock. While all addresses and control inputs
are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data
masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and
2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with
SSTL_2.
FEATURES
• VDD, VDDQ = 2.5V ± 0.2V for DDR200, 266, 333
VDD, VDDQ = 2.6V ± 0.1V for DDR400
• All inputs and outputs are compatible with SSTL_2
interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
• x16 device has two bytewide data strobes (UDQS,
LDQS) per each x8 I/O
• Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
• On chip DLL align DQ and DQS transition with CK
transition
• DM mask write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges of the clock
• Programmable CAS latency 2/2.5 (DDR200, 266,
333) and 3 (DDR400) supported
• Programmable burst length 2 / 4 / 8 with both
sequential and interleave mode
• Internal four bank operations with single pulsed /RAS
• Auto refresh and self refresh supported
• tRAS lock out function supported
• 8192 refresh cycles / 64ms
Page 11
SERVICE MANUAL
HY29LV320 32 Mbit (2M x 16) Low Voltage Flash Memory (IC1)
Low Voltage Single Supply Flash Memory
Single Power Supply Operation
– Read, program and erase operations from 2.7 to 3.6 volts
– Ideal for battery-powered applications
_ High Performance
– 70, 80, 90 and 120 ns access time versions for full voltage range operation
_ Ultra-low Power Consumption (Typical/ Maximum Values)
– Automatic sleep/standby current: 0.5/5.0 µA
– Read current: 9/16 mA (@ 5 MHz)
– Program/erase current: 20/30 mA
_ Top and Bottom Boot Block Versions
– Provide one 8 KW, two 4 KW, one 16 KW and sixty-three 32 KW sectors
_ Secured Sector
– An extra 128-word, factory-lockable sector available for an Electronic Serial Number and/or additional
secured data
_ Sector Protection
– Allows locking of a sector or sectors to prevent program or erase operations within that sector
– Temporary Sector Unprotect allows changes in locked sectors
_ Fast Program and Erase Times (typicals)
– Sector erase time: 0.5 sec per sector
– Chip erase time: 32 sec
– Word program time: 11 µs
– Accelerated program time per word: 7 µs
_ Automatic Erase Algorithm Preprograms and Erases Any Combination of Sectors or the Entire
Chip
_ Automatic Program Algorithm Writes and Verifies Data at Specified Addresses
_ Compliant With Common Flash Memory Interface (CFI) Specification
– Flash device parameters stored directly on the device
– Allows software driver to identify and use a variety of current and future Flash products
_ Minimum 100,000 Write Cycles per Sector
_ Compatible With JEDEC standards
– Pinout and software compatible with single-power supply Flash devices
– Superior inadvertent write protection
_ Data# Polling and Toggle Bits
– Provide software confirmation of completion of program and erase operations
_ Ready/Busy (RY/BY#) Pin
– Provides hardware confirmation of completion of program and erase operations
_ Write Protect Function (WP#/ACC pin)
- Allows hardware protection of the first or last 32 KW of the array, regardless of sector protect status
_ Acceleration Function (WP#/ACC pin)
- Provides accelerated program times
_ Erase Suspend/Erase Resume
– Suspends an erase operation to allow reading data from, or programming data to, a sector that is not
being erased
Page 12
SERVICE MANUAL
– Erase Resume can then be invoked to complete suspended erasure
_ Hardware Reset Pin (RESET#) Resets the Device to Reading Array Data
_ Space Efficient Packaging
– 48-pin TSOP and 63-ball FBGA packages
16tut36-2 tuner board
STV0360/0361(COFDM demodulators IC for terrestrial TV set-top box)
STMicroelectronics complements the world leading range of MPEG-2 decoders with a range of COFDM
demodulators for digital terrestrial applications. The STV0360 and STV0361 demodulators are high
performance COFDM (Coded Orthogonal Frequency Division Multiplex) demodulators with built in A/D
converters. They perform all the demodulation functions to extract the MPEG-2 transport stream from the
tuner input.
• DVB-T (ETS 300 744), NORDIG II and NORDIG Unified 1.0.1 compliant1
• Inputs for direct IF, eliminating the need for a down-converter in the tuner
• Adaptative channel correction in both time and frequency, providing excellent performance, event
in the presence of noise or significant Doppler shift.
• Dual Automatic Gain Controller (AGC) to seamlessly interface with all tuners characteristics
• Support for 2K/8K carrier detection modes
• PGA (Programmable Gain Amplifier) increasing flexibility to enhance tuner power matching
• Additional A/D converter to directly monitor the input level of the new generation of tuners
Page 13
SERVICE MANUAL
Page 14
Loading...