HITACHI HD74HCT563, HD74HCT573 User Manual
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HD74HCT563/HD74HCT573
Octal Transparent Latches (with 3-state outputs)
Description
When the latch enable (LE) input is high, the Q outputs of HD74HCT563 will follow the inversion of the D
inputs and the Q outputs of HD74HCT573 will follow the D inputs.
When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enabled
returns high again. When a high logic level is applied to the output control input, all outputs go to a high
impedance state, regardless of what signals are present at the other inputs and the state of the storage
elements.
Features
• LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
• High Speed Operation: tpd (D to Q, Q) = 13 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 4.5 to 5.5 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Outputs
Output Control Latch Enable Data HD74HCT563 HD74HCT573
LH H L H
LH L H L
LL X Q
HX X Z Z
0
Q
0
HD74HCT563/HD74HCT573
Pin Arrangement
HD74HCT563
Output
Control
1D
2D
3D
4D
5D
6D
7D
8D
GND
10
V
OE
OE
OE
OE
20
CC
19
18
17
16
15
14
13
12
11
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
Latch
Enable
QD
QD
QD
QD
1
2
OE
3
QD
4
OE
5
QD
6
OE
7
QD
8
OE
9
QD
(Top view)
2
HD74HCT573
HD74HCT563/HD74HCT573
Output
Control
1D
2D
3D
4D
5D
6D
7D
8D
GND
10
V
OE
OE
OE
OE
20
CC
19
18
17
16
15
14
13
12
11
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
Latch
Enable
QD
QD
QD
QD
1
2
OE
3
QD
4
OE
5
QD
6
OE
7
QD
8
OE
9
QD
(Top view)
3
HD74HCT563/HD74HCT573
Block Diagram
HD74HCT563
Enable C
OC
1D
2D
3D
4D
5D
6D
7D
8D
D
C Q
C
D
C Q
C
D
C Q
C
D
C Q
C
D
C Q
C
D
C Q
C
D
C Q
C
D
C Q
C
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
4
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