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查询HD74ALVCH16831供应商
1-to 4 Address Register / Driver with 3-state Outputs
Description
This 1-bit to 4-bit address register / driver is designed for 2.3 V to 3.6 V VCC operation. The device is ideal
for use in applications in which a single address bus is driving four separate memory locations. The
HD74ALVCH16831 can be used as a buffer or a register, depending on the logic level of the select (SEL)
input. When SEL is logic high, the device is in the buffer mode. The outputs follow the inputs and are
controlled by the two output enable (OE) controls. Each OE controls two groups of nine outputs. When
SEL is logic low, the device is in the register mode. The register is an edge triggered D-type flip flop. On
the positive transition of the clock (CLK) input, data set up at the A inputs is stored in the internal registers.
OE controls operate the same as in buffer mode. When OE is logic low, the outputs are in a normal logic
state (high or low logic level). When OE is logic high, the outputs are in the high impedance state. To
ensure the high impedance state during power up or power down, OE should be tied to VCC through a
pullup registor; the minimum value of the registor is determined by the current sinking capability of the
driver. SEL and OE do not affect the internal operation of the flip flops. Old data can be retained or new
data can be entered while the outputs are in the high impedance state. Active bus hold circuitry is provided
to hold unused or floating data inputs at a valid logic level.
HD74ALVCH16831
ADE-205-194 (Z)
Preliminary
1st. Edition
March 1998
Features
• VCC = 2.3 V to 3.6 V
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±24 mA (@VCC = 3.0 V)
• Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
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HD74ALVCH16831
Function Table
Inputs Output Y
OE SEL CLK A
HXXXZ
LHXLL
LHXHH
LL↑LL
LL↑HH
H : High level
L : Low level
X : Immaterial
Z : High impedance
↑ : Low to high transition
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Pin Arrangement
HD74ALVCH16831
14Y1
23Y1
3GND
42Y1
51Y1
V
6
CC
7NC
8A1
9GND
10NC
11A2
12GND
13NC
14A3
V
15
CC
16NC
17A4
18GND
19CLK
20OE1
21OE2
22SEL
23GND
24A5
25A6
V
26
CC
27A7
28NC
29GND
30A8
31NC
32GND
33A9
34NC
V
35
CC
364Y9
373Y9
38GND
392Y9
401Y9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1Y2
2Y2
GND
3Y2
4Y2
V
CC
1Y3
2Y3
GND
3Y3
4Y3
GND
1Y4
2Y4
V
CC
3Y4
4Y4
GND
1Y5
2Y5
3Y5
4Y5
GND
1Y6
2Y6
V
CC
3Y6
4Y6
GND
1Y7
2Y7
GND
3Y7
4Y7
V
CC
1Y8
2Y8
GND
3Y8
4Y8
(Top view)
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HD74ALVCH16831
Absolute Maximum Ratings
Item Symbol Ratings Unit Conditions
Supply voltage V
Input voltage
Output voltage
*1
*1, 2
Input clamp current I
Output clamp current I
Continuous output current I
VCC, GND current / pin ICC or I
Maximum power dissipation
at Ta = 55°C (in still air)
*3
Storage temperature T
CC
V
I
V
O
IK
OK
O
GND
P
T
stg
Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage
to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C
and a board trace length of 750 mils.
–0.5 to 4.6 V
–0.5 to 4.6 V
–0.5 to VCC +0.5 V
–50 mA VI < 0
±50 mA VO < 0 or VO > V
±50 mA VO = 0 to V
CC
±100 mA
1 W TVSOP
–65 to 150 °C
CC
Recommended Operating Conditions
Item Symbol Min Max Unit Conditions
Supply voltage V
Input voltage V
Output voltage V
High level output current I
Low level output current I
CC
I
O
OH
OL
Input transition rise or fall rate ∆t / ∆v 0 10 ns / V
Operating temperature T
a
Note: Unused control inputs must be held high or low to prevent them from floating.
2.3 3.6 V
0VCCV
0VCCV
— –12 mA VCC = 2.3 V
— –12 VCC = 2.7 V
— –24 VCC = 3.0 V
—12mAV
—12 V
—24 V
= 2.3 V
CC
= 2.7 V
CC
= 3.0 V
CC
–40 85 °C
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Logic Diagram
g
OE1
OE2
CLK
A1
SEL
HD74ALVCH16831
20
5
21
19
8
22
CLK
DQ
ht other channels
To ei
1Y1
4
2Y1
2
3Y1
1
4Y1
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HD74ALVCH16831
Electrical Characteristics (Ta = –40 to 85°C)
Item Symbol V
Input voltage V
IH
(V) Min Max Unit Test Conditions
CC
2.3 to 2.7 1.7 — V
2.7 to 3.6 2.0 —
V
IL
2.3 to 2.7 — 0.7
2.7 to 3.6 — 0.8
Output voltage V
OH
2.3 to 3.6 VCC–0.2 — V IOH = –100 µA
2.3 2.0 — IOH = –6 mA, VIH = 1.7 V
2.3 1.7 — IOH = –12 mA, VIH = 1.7 V
2.7 2.2 — IOH = –12 mA, VIH = 2.0 V
3.0 2.4 — IOH = –12 mA, VIH = 2.0 V
3.0 2.0 — IOH = –24 mA, VIH = 2.0 V
V
OL
2.3 to 3.6 — 0.2 IOL = 100 µA
2.3 — 0.4 IOL = 6 mA, VIL = 0.7 V
2.3 — 0.7 IOL = 12 mA, VIL = 0.7 V
2.7 — 0.4 IOL = 12 mA, VIL = 0.8 V
3.0 — 0.55 IOL = 24 mA, VIL = 0.8 V
Input current I
IN
I
IN (hold)
3.6 — ±5 µAVIN = VCC or GND
2.3 45 — VIN = 0.7 V
2.3 –45 — VIN = 1.7 V
3.0 75 — VIN = 0.8 V
3.0 –75 — VIN = 2.0 V
*1
or GND
CC
Off state output current I
Quiescent supply current I
∆I
3.6 — ±500 VIN = 0 to 3.6 V
OZ
CC
CC
3.6 — ±10 µAV
3.6 — 40 µAVIN = VCC or GND
3.0 to 3.6 — 750 µAVIN = one input at (VCC–0.6) V,
= VCC or GND
OUT
other inputs at V
Note: 1. This is the bus hold maximum dynamic current required to switch the input from one state to
another.
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Switching Characteristics (Ta = –40 to 85°C)
HD74ALVCH16831
Item Symbol VCC (V) Min Typ Max Unit FROM
(Input)
Maximum clock frequency f
max
2.5±0.2 150 — — MHz
2.7 150 — —
3.3±0.3 150 — —
Propagation delay time t
PLH
t
PHL
2.5±0.2 1.2 — 4.0 ns A Y
2.7 — — 4.1
3.3±0.3 1.6 — 3.6
2.5±0.2 1.1 — 4.5 CLK Y
2.7 — — 4.4
3.3±0.3 1.5 — 3.9
2.5±0.2 1.3 — 5.2 SEL Y
2.7 — — 5.2
3.3±0.3 1.7 — 4.4
Output enable time t
ZH
t
ZL
2.5±0.2 1.1 — 5.1 ns OE Y
2.7 — — 5.0
3.3±0.3 1.2 — 4.3
Output disable time t
HZ
t
LZ
2.5±0.2 1.4 — 5.5 ns OE Y
2.7 — — 4.7
3.3±0.3 1.6 — 4.5
Setup time t
su
2.5±0.2 2.0 — — ns
2.7 2.0 — —
3.3±0.3 1.6 — —
Hold time t
h
2.5±0.2 0.7 — — ns
2.7 0.5 — —
3.3±0.3 1.1 — —
Pulse width t
w
2.5±0.2 3.3 — — ns
2.7 3.3 — —
3.3±0.3 3.3 — —
Input capacitance C
IN
3.3 — 4.5 — pF Control inputs
3.3 — 5.0 — Data inputs
Output capacitance C
O
3.3 — 7.5 — pF
TO
(Output)
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HD74ALVCH16831
Test Circuit
See under table
500 Ω
S1
OPEN
GND
*1
L
500 ΩC
Load Circuit for Outputs
Symbol
t / t
PLH PHL
t / t / t
su h w
t / t
ZH HZ
t / t
ZL LZ
C
Vcc=2.5±0.2V
2 × V 6.0 V
L
Note: 1. CL includes probe and jig capacitance.
Vcc=2.7V,
3.3±0.3V
OPEN
GND
OPEN
GND
CC
30 pF 50 pF
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Waveforms – 1
HD74ALVCH16831
Input
Output
Waveforms – 2
Timing Input
Data Input
10 %
t
rf
90 %
V
ref
t
90 %
V
ref
10 %
t
PLH
V
ref
t
r
t
PHL
V
ref
90 %
V
ref
10 %
t
su
V
ref
t
h
V
ref
V
IH
GND
V
OH
V
OL
V
IH
GND
V
IH
GND
Input
t
w
V
IH
V
ref
V
ref
GND
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HD74ALVCH16831
Waveforms – 3
t
r
90 %
V
ref
t
LZ
V
ref1
t
HZ
V
ref2
CC
Vcc=2.7V,
3.3±0.3V
V +0.3 V
OL
V –0.3 V
OH
TEST
V
IH
V
ref
V
ref1
V
ref2
V
OH1
V
OL1
Vcc=2.5±0.2V
V
CC
1/2 V 1.5 V
V +0.15 V
OL
V –0.15 V
OH
V
CC
GND
Output
Control
Waveform - A
Waveform - B
90 %
t
f
V
ref
10 % 10 %
t
ZL
V
ref
t
ZH
V
ref
Notes: 1. All input pulses are supplied by generators having the following characteristics :
PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.0 ns, tf ≤ 2.0 ns. (VCC = 2.5±0.2 V)
PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. (VCC = 2.7 V, 3.3±0.3 V)
2. Waveform – A is for an output with internal conditions such that the output is low except
when disabled by the output control.
3. Waveform – B is for an output with internal conditions such that the output is high except
when disabled by the output control.
4. The output are measured one at a time with one transition per measurement.
V
GND
≈V
V
V
≈V
2.7 V
3.0 V
GND
IH
OH1
OL
OH
OL1
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Package Dimensions
140
0.23 Max
17.10 Max
0.40
0.07
0.08
HD74ALVCH16831
Unit : mm
4180
6.20 Max
M
8.40 Max
0.16 Typ
12° Max
0.75 Max
0.15 Min
1.20 max
Hitachi code
EIAJ code
JEDEC code
—
—
—
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Cautions
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intellectual property rights, in connection with use of the information contained in this document.
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received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
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5. This product is not designed to be radiation resistant.
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