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Hitachi Single-Chip Microcomputer
H8/3672 Series
H8/3672F-ZTAT
HD64F3672
H8/3670F-ZTAT
HD64F3670
Hardware Manual
TM
TM
ADE-602-239
Rev. 1.0
03/20/01
Hitachi, Ltd.
Page 2
Rev. 2.0, 03/01, page ii of xxiv
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Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no respon sibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.
Rev. 2.0, 03/01, Page
of xxiv
iii
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Rev. 2.0, 03/01, page iv of xxiv
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Preface
This LSI is a single-chip microprocessor made up of the high-speed H8/300H CPU as its core, and
the peripheral functions required to configure a system. The H8/300H CPU has an instruction set
that is compatible with the H8/300 CPU
This LSI is equipped with ROM, RAM, an 8-bit timer (TMR), a 16-bit timer, a watchdog timer
(WDT), two types of serial communication interfaces (SCIs), a 10-bit A/D converter, and I/O
ports as on-chip peripheral modules. This LSI is suitable for use as an embedded processor for
high-level control systems. Its on-chip ROM is flash memory (F-ZTAT
flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of
mass production to full-scale mass production. This is particularly applicable to application
devices with specifications that will most pro bably change.
TM
*) that provides
Note: * F-ZTAT
TM
is a trademark of Hitachi, Ltd.
Target Users: This manual was written for users who will be using the H8/3672 Series in the
design of application systems. Members of this audience are expected to
understand the fundamentals of electrical circuits, logical circuits, and
microcomputers.
Objective: This manual was written to explain the hardware func tions and electrical
characteristics of the H8/3672 Series to the above audience.
Refer to the H8/300H Series Programming Manual for a detailed description of the
instruction set.
Notes on reading this manual:
In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
In order to understand the details of the CPU's functions
Read the H8/300 Series Programming Manual.
In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in Appendix A,
On-Chip I/O Registers.
Examples: Register name: The following notation is used for cases when the same or a
similar function, e.g. serial communication, is implemented
on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order: The MSB is on the left and the LSB is on the right.
Rev. 2.0, 03/01, Page v of xxiv
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Related Manuals: The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.hitachi.co.jp/Sicd/English/Products/micome.htm
H8/3672 Series manuals:
Manual Title ADE No.
H8/3672 Series Hardware Manual This manual
H8/300H Series Programming Manual ADE-602-053
Users manuals for development tools:
Manual Title ADE No.
C/C++ Compiler, Assembler, Optimized Linkage Editor User's Manual ADE-702-246
Hitachi Debugging Interface User's Manual ADE-702-212
Hitachi Embedded Workshop User's Manual ADE-702-201
Hitachi Embedded Workshop, Hitachi Debugging Interface Tutorial ADE-702-231
F-ZTAT Microcomputer On-Board Writing Program User's Manual ADE-702-227
Application Notes:
Manual Title ADE No.
C/C++ Compiler Guide ADE-502-044
F-ZTAT Technical Q & A ADE-502-046
Rev. 2.0, 03/01, page vi of xxiv
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Contents
Section 1 Overview....................................................................................................................1
1.1 Overview...........................................................................................................................1
1.2 Internal Block Diagram.....................................................................................................2
1.3 Pin Arrangement...............................................................................................................3
1.4 Pin Functions ....................................................................................................................5
Section 2 CPU................................................................................................... 7
2.1 Address Space and Memory Map.....................................................................................8
2.2 Register Configuration......................................................................................................9
2.2.1 General Registers.....................................................................................................10
2.2.2 Program Counter (PC) .............................................................................................11
2.2.3 Condition - Co d e Reg ister (CCR)..............................................................................11
2.3 Data Formats.....................................................................................................................13
2.3.1 General Register Data Formats................................................................................13
2.3.2 Memory Data Formats .............................................................................................15
2.4 Instruction Set...................................................................................................................16
2.4.1 Table of Instructions Classified by Function...........................................................16
2.4.2 Basic Instruction Formats ........................................................................................25
2.5 Addressing Modes and Effective Address Calculation.....................................................27
2.5.1 Addressing Modes ...................................................................................................27
2.5.2 Effective Address Calculation .................................................................................29
2.6 Basic Bus Cycle................................................................................................................32
2.6.1 Access to On-Chip Memory (RAM, ROM).............................................................32
2.6.2 On-Chip Peripheral Modules ...................................................................................33
2.7 CPU States ........................................................................................................................34
2.8 Usage Notes ......................................................................................................................35
2.8.1 Notes on Data Access to Empty Areas ....................................................................35
2.8.2 EEPMOV Instruction...............................................................................................35
2.8.3 Bit Manipulation Instruction....................................................................................35
Section 3 Exception Handling .......................................................................... 41
3.1 Exception Sources and Vector Address............................................................................41
3.2 Register Descriptions........................................................................................................43
3.2.1 Interrupt Edge Select Register 1(IEGR1) ................................................................43
3.2.2 Interrupt Edge Select Register 2(IEGR2) ................................................................44
3.2.3 Interrupt Enable Register 1(IENR1) ........................................................................45
3.2.4 Interrupt Flag Register 1(IRR1)...............................................................................46
3.2.5 Wakeup Interrupt Flag Register(IWPR) ..................................................................47
3.3 Reset .................................................................................................................................48
3.4 Interrupt Exception Handling............................................................................................48
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3.4.1 External Interrupts ...................................................................................................48
3.4.2 Internal Interrupts ....................................................................................................49
3.4.3 Interrupt Handling Sequence ...................................................................................49
3.4.4 Interrupt Response Time..........................................................................................51
3.5 Usage Notes......................................................................................................................53
3.5.1 Interrupts after Reset................................................................................................53
3.5.2 Notes on Stack Area Use .........................................................................................53
3.5.3 Notes on Rewriting Port Mode Registers ................................................................53
Section 4 Address Break....................................................................................55
4.1 Register Descriptions........................................................................................................55
4.1.1 Address Break Control Register(ABRKCR) ...........................................................56
4.1.2 Address Break Status Register(ABRKSR) .............................................................. 57
4.1.3 Break Address Registers (BARH, BARL)...............................................................57
4.1.4 Break Data Registers (BDRH, BDRL) ....................................................................58
4.2 Operation ..........................................................................................................................58
Section 5 Clock Pulse Generators .....................................................................61
5.1 System Clock Generator ...................................................................................................61
5.1.1 Connecting a Crystal Oscillator...............................................................................61
5.1.2 Connecting a Ceramic Oscillator.............................................................................62
5.1.3 External Clock Input Method...................................................................................62
5.2 Prescalers ..........................................................................................................................63
5.2.1 Prescaler S ...............................................................................................................63
5.3 Usage Notes......................................................................................................................63
5.3.1 Note on Oscillators ..................................................................................................63
5.3.2 Notes on Board Design............................................................................................64
Section 6 Power-down Modes...........................................................................65
6.1 Register Descriptions........................................................................................................65
6.1.1 System Control Register 1(SYSCR1)......................................................................65
6.1.2 System Control Register 2(SYSCR2)......................................................................66
6.1.3 Module Standby Control Register 1(MSTCR1)......................................................67
6.1.4 Module Standby Control Register 2(MSTCR2)......................................................68
6.2 Mode Transitions and States of the LSI............................................................................69
6.2.1 Sleep Mode ..............................................................................................................71
6.2.2 Standby Mode..........................................................................................................71
6.2.3 Subsleep Mode.........................................................................................................71
6.3 Operating Frequency in the Active Mode.........................................................................72
6.4 Direct Transition...............................................................................................................72
6.5 Module Standby Function.................................................................................................72
Section 7 ROM..................................................................................................73
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7.1 Block Configuration..........................................................................................................73
7.2 Register Descriptions........................................................................................................74
7.2.1 Flash Memory Control Register 1 (FLMCR1).........................................................75
7.2.2 Flash Memory Control Register 2 (FLMCR2).........................................................76
7.2.3 Erase Block Register 1 (EBR1) ...............................................................................76
7.2.4 Flash Memory Enable Register(FENR)...................................................................77
7.3 On-Board Programming Modes........................................................................................77
7.3.1 Boot Mode ...............................................................................................................78
7.3.2 Programming/Erasing in User Program Mode.........................................................80
7.4 Flash Memory Programming/Erasing...............................................................................81
7.4.1 Program/Program-Verify.........................................................................................81
7.4.2 Erase/Erase-Verify...................................................................................................84
7.4.3 Interrupt Handling when Programming/Erasing Flash Memory..............................84
7.5 Program/Erase Protection .................................................................................................86
7.5.1 Hardware Protection ................................................................................................86
7.5.2 Software Protection ..................................................................................................86
7.5.3 Error Protection........................................................................................................86
Section 8 RAM ................................................................................................. 87
Section 9 I/O Ports............................................................................................ 89
9.1 Port 1.................................................................................................................................89
9.1.1 Port Mode Register 1(PMR1) ..................................................................................90
9.1.2 Port Control Register 1(PCR1) ................................................................................91
9.1.3 Port Data Register 1(PDR1).....................................................................................91
9.1.4 Port Pull-Up Control Register 1(PUCR1)................................................................92
9.1.5 Pin Functions ...........................................................................................................92
9.2 Port 2.................................................................................................................................94
9.2.1 Port Control Register 2(PCR2) ................................................................................94
9.2.2 Port Data Register 2(PDR2).....................................................................................95
9.2.3 Pin Functions ...........................................................................................................95
9.3 Port 5.................................................................................................................................96
9.3.1 Port Mode Register 5(PMR5) ..................................................................................97
9.3.2 Port Control Register 5(PCR5) ................................................................................98
9.3.3 Port Data Register 5(PDR5).....................................................................................98
9.3.4 Port Pull-up Control Register 5(PUCR5).................................................................9 9
9.3.5 Pin Functions ...........................................................................................................99
9.4 Port 7.................................................................................................................................101
9.4.1 Port Control Register 7(PCR7) ................................................................................102
9.4.2 Port Data Register 7(PDR7).....................................................................................102
9.4.3 Pin Functions ...........................................................................................................103
9.5 Port 8.................................................................................................................................104
9.5.1 Port Control Register 8(PCR8) ................................................................................104
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9.5.2 Port Data Register 8(PDR8).....................................................................................105
9.5.3 Pin Functions ...........................................................................................................105
9.6 Port B................................................................................................................................107
9.6.1 Port Data Register B(PDRB) ...................................................................................108
Section 10 Timer V............................................................................................109
10.1 Features ................................................................................................................... .......... 109
10.2 Input/Output Pins..............................................................................................................110
10.3 Register Descriptions........................................................................................................111
10.3.1 Timer Counter V (TCNTV).................................................................................111
10.3.2 Time Constant Registers A and B (TCORA, TCORB)........................................111
10.3.3 Timer Control Register V0(TCRV0)...................................................................112
10.3.4 Timer Control/Status Register V(TCSRV)..........................................................114
10.3.5 Timer Control Register V1(TCRV1)...................................................................115
10.4 Operation ..........................................................................................................................115
10.4.1 Timer V operation................................................................................................115
10.5 Timer V application examples..........................................................................................119
10.5.1 Pulse Output with Arbitrary Duty Cycle..............................................................119
10.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input.............120
10.6 Usage Notes................................................................................................................ ...... 121
Section 11 Timer W...........................................................................................123
11.1 Features ................................................................................................................... .......... 123
11.2 Input/Output Pins..............................................................................................................125
11.3 Register Descriptions........................................................................................................126
11.3.1 Timer Mode Register W(TMRW).......................................................................126
11.3.2 Timer Control Register W(TCRW).....................................................................128
11.3.3 Timer Interrupt Enable Register W(TIERW).......................................................129
11.3.4 Timer Status Register W(TSRW)........................................................................129
11.3.5 Timer I/O Control Register 0(TIOR0).................................................................131
11.3.6 Timer I/O Control Register 1(TIOR1).................................................................132
11.3.7 Timer Counter (TCNT)........................................................................................133
11.3.8 General Registers A to D (GRA to GRD)............................................................133
11.4 Operation ..........................................................................................................................134
11.4.1 Normal Operation................................................................................................134
11.4.2 PWM Operation...................................................................................................138
11.5 Operation Timing..............................................................................................................142
11.5.1 TCNT Count Timing ...........................................................................................142
11.5.2 Output Compare Timing......................................................................................142
11.5.3 Input Capture Timing...........................................................................................143
11.5.4 Timing of Counter Clearing by Compare Match.................................................144
11.5.5 Buffer Operation Timing.....................................................................................144
11.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match ................................145
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11.5.7 Timing of IMFA to IMFD Setting at Input Capture ............................................146
11.6 Usage Notes......................................................................................................................147
Section 12 Watchdog Timer ............................................................................. 149
12.1 Features.............................................................................................................................149
12.2 Register Descriptions........................................................................................................149
12.2.1 Timer Control/Status Register WD(TCSRWD)...................................................150
12.2.2 Timer Counter WD(TCWD)................................................................................151
12.2.3 Timer Mode Register WD(TMWD) ....................................................................151
12.3 Operation...........................................................................................................................152
Section 13 Serial Communication Interface3 (SCI3) ....................................... 153
13.1 Features.............................................................................................................................153
13.2 Input/Output Pins..............................................................................................................155
13.3 Register Descriptions........................................................................................................155
13.3.1 Receive Shift Register (RSR)...............................................................................156
13.3.2 Receive Data Register (RDR)..............................................................................156
13.3.3 Transmit Shift Register (TSR).............................................................................156
13.3.4 Transmit Data Register (TDR).............................................................................156
13.3.5 Serial Mode Register (SMR)................................................................................157
13.3.6 Serial Control Register 3 (SCR3).........................................................................158
13.3.7 Serial Status Register (SSR)................................................................................. 160
13.3.8 Bit Rate Register (BRR) ......................................................................................162
13.4 Operation in Asynchronous Mode ....................................................................................167
13.4.1 Clock....................................................................................................................168
13.4.2 SCI3 Initialization................................................................................................169
13.4.3 Data Transmission ...............................................................................................170
13.4.4 Serial Data Reception...........................................................................................172
13.5 Operation in Clocked Synchronous Mode........................................................................176
13.5.1 Clock....................................................................................................................176
13.5.2 SCI3 Initialization................................................................................................176
13.5.3 Serial Data Transmission.....................................................................................177
13.5.4 Serial Data Reception (Clocked Synchronous Mode)..........................................179
13.5.5 Simultaneous Serial Data Transmission and Reception.......................................181
13.6 Multiprocessor Communication Function.........................................................................183
13.6.1 Multiprocessor Serial Data Transmission............................................................185
13.6.2 Multiprocessor Serial Data Reception .................................................................186
13.7 Interrupts...........................................................................................................................190
13.8 Usage Notes......................................................................................................................191
13.8.1 Break Detection and Processing ..........................................................................191
13.8.2 Mark State and Break Detection..........................................................................191
13.8.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
191
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13.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 192
Section 14 A/D Converter .................................................................................193
14.1 Features ................................................................................................................... .......... 193
14.2 Input/Output Pins..............................................................................................................195
14.3 Register Description..........................................................................................................196
14.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................196
14.3.2 A/D Control/Status Register (ADCSR) ...............................................................197
14.3.3 A/D Control Register (ADCR) ............................................................................198
14.4 Operation ..........................................................................................................................199
14.4.1 Single Mode......................................................................................................... 199
14.4.2 Scan Mode...........................................................................................................199
14.4.3 Input Sampling and A/D Conversion Time .........................................................200
14.4.4 External Trigger Input Timing.............................................................................201
14.5 A/D Conversion Precision Definitions..............................................................................202
14.6 Usage Notes................................................................................................................ ...... 203
14.6.1 Permissible Signal Source Impedance.................................................................203
14.6.2 Influences on Absolute Precision.........................................................................203
Section 15 Power Supply Circuit ......................................................................205
15.1 When Using the Internal Power Supply Step-Down Circuit.............................................205
15.2 When Not Using the Internal Power Supply Step-Down Circuit......................................206
Section 16 Electrical Characteristics.................................................................207
16.1 Absolute Maximum Ratings.............................................................................................207
16.2 Electrical Characteristics...................................................................................................207
16.2.1 Power Supply Voltage and Operating Ranges.....................................................207
16.2.2 DC Characteristics...............................................................................................209
16.2.3 AC Characteristics...............................................................................................214
16.2.4 A/D Converter Characteristics ............................................................................. 217
16.2.5 Watchdog Timer..................................................................................................218
16.2.6 Flash Memory Characteristics (Preliminary).......................................................219
16.3 Operation Timing..............................................................................................................221
16.4 Output Load Circuit..........................................................................................................223
Appendix A Instruction Set...............................................................................225
A.1 Instruction List..................................................................................................................225
A.2 Operation Code Map.........................................................................................................240
A.3 Number of Execution States .............................................................................................243
A.4 Combinations of Instructions and Addressing Modes ......................................................250
Appendix B Internal I/O Registers....................................................................251
B.1 Register Addresses............................................................................................................251
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B.2 Register Bits......................................................................................................................254
B.3 Registers States in Each Operating Mode.........................................................................257
Appendix C I/O Port Block Diagrams.............................................................. 260
C.1 I/O Port Block...................................................................................................................260
C.2 Port States in Each Operating State...................................................................................275
Appendix D Product Code Lineup.................................................................... 276
Appendix E Package Dimensions..................................................................... 277
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Figures of Contents
Section 1 Overview
Figure 1-1 Internal Block Diagram.................................................................................................2
Figure 1-2 Pin Arrangement (FP-64E) ...........................................................................................3
Figure 1-3 Pin Arrangement (FP-48F)............................................................................................4
Section 2 CPU
Figure 2-1 Memory Map.................................................................................................................8
Figure 2-2 CPU Registers...............................................................................................................9
Figure 2-3 Usage of General Registers.........................................................................................10
Figure 2-4 Relationship between Stack Pointer and Stack Area...................................................11
Figure 2-5 General Register Data Formats (1)..............................................................................13
Figure 2-5 General Register Data Formats (2)..............................................................................14
Figure 2-6 Memory Data Formats................................................................................................15
Figure 2-7 Instruction Formats.....................................................................................................26
Figure 2-8 Branch Address Specification in Memory Indirect Mode...........................................29
Figure 2-9 On-Chip Memory Access Cycle.................................................................................32
Figure 2-10 On-Chip Peripheral Module Access Cycle (3-State Access) ....................................33
Figure 2-11 CPU Operation States ...............................................................................................34
Figure 2-12 State Transitions........................................................................................................35
Figure 2-13 Example of Timer Configuration with Two Registers Allocated to Same Address..36
Section 3 Exception Handling
Figure 3-1 Reset Sequence............................................................................................................49
Figure 3-2 Stack Status after Exception Handling........................................................................50
Figure 3-3 Interrupt Sequence ......................................................................................................52
Figure 3-4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure..............53
Section 4 Address Break
Figure 4-1 Block Diagram of an Address Break...........................................................................55
Figure 4-2 Address Break Interrupt Operation Example (1).........................................................58
Figure 4-2 Address Break Interrupt Operation Example (2).........................................................59
Figure 4-2 Address Break Interrupt Operation Example (3).........................................................60
Section 5 Clock Pulse Generators
Figure 5-1 Block Diagram of Clock Pulse Generators.................................................................61
Figure 5-2 Typical Connection to Crystal Oscillator....................................................................61
Figure 5-3 Equivalent Circuit of Crystal Oscillator......................................................................62
Figure 5-4 Typical Connection to Ceramic Oscillator ..................................................................62
Figure 5-5 Example of External Clock Input................................................................................62
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Figure 5-6 Example of Incorrect Board Design............................................................................64
Section 6 Power-down Modes
Figure 6-1 Mode Transition Diagram...........................................................................................69
Section 7 ROM
Figure 7-1 Flash Memory Block Configuration............................................................................74
Figure 7-2 Programming/Erasing Flowchart Example in User Program Mode............................80
Figure 7-3 Program/Program-Verify Flowchart ...........................................................................82
Figure 7-4 Erase/Erase-Verify Flowchart.....................................................................................85
Section 9 I/O Ports
Figure 9-1 Port 1 Pin Configuration.............................................................................................89
Figure 9-2 Port 2 Pin Configuration.............................................................................................94
Figure 9-3 Port 5 Pin Configuration.............................................................................................96
Figure 9-4 Port 7 Pin Configuration...........................................................................................101
Figure 9-5 Port 8 Pin Configuration...........................................................................................104
Figure 9-6 Port B Pin Configuration...........................................................................................107
Section 10 Timer V
Figure 10-1 Block Diagram of Timer V.....................................................................................110
Figure 10-2 Increment Timing with Internal Clock....................................................................116
Figure 10-3 Increment Timing with External Clock...................................................................116
Figure 10-4 OVF Set Timing......................................................................................................117
Figure 10-5 CMFA and CMFB Set Timing................................................................................117
Figure 10-6 TMOV Output Timing............................................................................................117
Figure 10-7 Clear Timing by Compare Match............................................................................117
Figure 10-8 Clear Timing by TMRIV Input...............................................................................118
Figure 10-9 Pulse Output Example.............................................................................................119
Figure 10-10 Example of Pulse Output Synchronized to TRGV Input ......................................120
Figure 10-11 Contention between TCNTV Write and Clear......................................................121
Figure 10-12 Contention between TCORA Write and Compare Match.....................................122
Figure 10-13 Internal Clock Switching and TCNTV Operation.................................................122
Section 11 Timer W
Figure 11-1 Timer W Block Diagram.........................................................................................125
Figure 11-2 Free-Running Counter Operation............................................................................134
Figure 11-3 Periodic Counter Operation.....................................................................................135
Figure 11-4 0 and 1 Output Example(TOA = 0, TOB = 1).........................................................135
Figure 11-5 Toggle Output Example (TOA = 0, TOB = 1)........................................................136
Figure 11-6 Toggle Output Example (TOA = 0, TOB = 1)........................................................136
Figure 11-7 Input Capture Operating Example...........................................................................137
Figure 11-8 Buffer Operation Example (Input Capture).............................................................137
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Figure 11-9 PWM Mode Example (1)........................................................................................138
Figure 11-10 PWM Mode Example (2)......................................................................................139
Figure 11-11 Buffer Operation Example (Output Compare)......................................................139
Figure 11-12 PWM Mode Example
(TOB=0, TOC=0, TOD=0: initial output values are set to 0)...............................140
Figure 11-13 PWM Mode Example
(TOB=1, TOC=1,and TOD=1: initial output values are set to 1).........................141
Figure 11-14 Count Timing for Internal Clock Source...............................................................142
Figure 11-15 Count Timing for External Clock Source..............................................................142
Figure 11-16 Output Compare Output Timing...........................................................................143
Figure 11-17 Input Capture Input Signal Timing .......................................................................143
Figure 11-18 Timing of Counter Clearing by Compare Match...................................................144
Figure 11-19 Buffer Operation Timing (Compare Match) .........................................................144
Figure 11-20 Buffer Operation Timing (Input Capture).............................................................145
Figure 11-21 Timing of IMFA to IMFD Flag Setting at Compare Match..................................145
Figure 11-22 Timing of IMFA to IMFD Flag Setting at Input Capture......................................146
Figure 11-23 Timing of Status Flag Clearing by the CPU..........................................................146
Figure 11-24 Contention between TCNT Write and Clear.........................................................147
Figure 11-25 Internal Clock Switching and TCNT Operation....................................................148
Section 12 Watchdog Timer
Figure 12-1 Block Diagram of WDT..........................................................................................149
Figure 12-2 Watchdog Timer Operation Example......................................................................152
Section 13 Serial Communication Interface3 (SCI3)
Figure 13-1 Block Diagram of SCI3...........................................................................................154
Figure 13-2 Data Format in Asynchronous Communication......................................................167
Figure 13-3 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode)(Example with 8-Bit Data, Parity, Two Stop Bits)..............168
Figure 13-4 Sample SCI3 Initialization Flowchart.....................................................................169
Figure 13-5 Example SCI3 Operation in Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)...........................................................................170
Figure 13-6 Sample Serial Transmission Flowchart...................................................................171
Figure 13-7 Example SCI3 Operation in Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)...........................................................................172
Figure 13-8 Sample Serial Reception Data Flowchart (Asynchronous mode)(1).......................174
Figure 13-8 Sample Serial Reception Data Flowchart (2)..........................................................175
Figure 13-9 Data Format in Synchronous Communication........................................................176
Figure 13-10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode.....177
Figure 13-11 Sample Serial Transmission Flowchart(Clocked Synchronous Mode).................178
Figure 13-12 Example of SCI3 Reception Operation in Clocked Synchronous Mode...............179
Figure 13-13 Sample Serial Reception Flowchart(Clocked Synchronous Mode) ......................180
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Figure 13-14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
(Clocked Synchronous Mode) ...............................................................................182
Figure 13-15 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)...........................................184
Figure 13-16 Sample Multiprocessor Serial Transmission Flowchart........................................185
Figure 13-17 Sample Multiprocessor Serial Reception Flowchart (1)........................................187
Figure 13-17 Sample Multiprocessor Serial Reception Flowchart (2)........................................188
Figure 13-18 Example of SCI3 Operation in Reception Using Multiprocessor Format
(Example with 8-Bit Data, MultiprocessorBit, One Stop Bit) ...............................189
Figure 13-19 Receive Data Sampling Timing in Asynchronous Mode......................................192
Section 14 A/D Converter
Figure 14-1 Block Diagram of A/D Converter...........................................................................194
Figure 14-2 A/D Conversion Timing..........................................................................................200
Figure 14-3 External Trigger Input Timing................................................................................201
Figure 14-4 A/D Conversion Precision Definitions (1)..............................................................202
Figure 14-5 A/D Conversion Precision Definitions (2)..............................................................203
Figure 14-6 Analog Input Circuit Example................................................................................204
Section 15 Power Supply Circuit
Figure 15-1 Power Supply Connection when Internal Step-Down Circuit Is Used....................205
Figure 15-2 Power Supply Connection when Internal Step-Down Circuit Is Not Used.............206
Section 16 Electrical Characteristics
Figure 16-1 System Clock Input Timing....................................................................................221
Figure 16-2 RES Low Width Timing.........................................................................................221
Figure 16-3 Input Timing ...........................................................................................................221
Figure 16-4 SCK3 Input Clock Timing......................................................................................222
Figure 16-5 Serial Interface 3 Synchronous Mode Input/Output Timing...................................222
Figure 16-6 Output Load Condition ...........................................................................................223
Appendix C I/O Port Block Diagrams
Figure C.1 Port 1 Block Diagram (P17).....................................................................................260
Figure C.2 Port 1 Block Diagram (P14).....................................................................................261
Figure C.3 Port 1 Block Diagram (P16, P15, P12, P10).............................................................262
Figure C.4 Port 1 Block Diagram (P11).....................................................................................263
Figure C.5 Port 2 Block Diagram (P22).....................................................................................264
Figure C.6 Port 2 Block Diagram (P21).....................................................................................265
Figure C.7 Port 2 Block Diagram (P20).....................................................................................266
Figure C.8 Port 5 Block Diagram (P57, P56).............................................................................267
Figure C.9 Port 5 Block Diagram (P55).....................................................................................268
Figure C.10 Port 5 Block Diagram (P54 to P50)........................................................................269
Figure C.11 Port 7 Block Diagram (P76)...................................................................................270
Rev. 1.0, 03/01, page xviii of xxiv
Page 19
Figure C.12 Port 7 Block Diagram (P75)...................................................................................271
Figure C.13 Port 7 Block Diagram (P74)...................................................................................272
Figure C.14 Port 8 Block Diagram (P84 to P81)........................................................................273
Figure C.15 Port 8 Block Diagram (P80)...................................................................................274
Figure C.16 Port B Block Diagram (PB3 to PB0)......................................................................275
Appendix E Package Dimensions
Figure E.1 FP-64E Package Dimensions....................................................................................277
Figure E.2 FP-48F Package Dimensions....................................................................................278
Rev. 1.0, 03/01, page xix of xxiv
Page 20
Rev. 1.0, 03/01, page xx of xxiv
Page 21
Tables of Contents
Section 1 Overview
Table 1-1 Pin Functions..................................................................................................................5
Section 2 CPU
Table 2-1 Operation Notation.......................................................................................................16
Table 2-2 Data Transfer Instructions............................................................................................17
Table 2-3 Arithmetic Operations Instructions (1).........................................................................18
Table 2-3 Arithmetic Operations Instructions (2).........................................................................19
Table 2-4 Logic Operations Instructions ......................................................................................20
Table 2-5 Shift Instructions..........................................................................................................20
Table 2-6 Bit Manipulation Instructions (1).................................................................................21
Table 2-6 Bit Manipulation Instructions (2).................................................................................22
Table 2-7 Branch Instructions.......................................................................................................23
Table 2-8 System Control Instructions.........................................................................................24
Table 2-9 Block Data Transfer Instructions..................................................................................25
Table 2-10 Addressing Modes......................................................................................................27
Table 2-11 Absolute Address Access Ranges...............................................................................28
Table 2-12 Effective Address Calculation (1)..............................................................................30
Table 2-12 Effective Address Calculation (2)..............................................................................31
Section 3 Exception Handling
Table 3-1 Exception Sources and Vector Address........................................................................42
Table 3-2 Interrupt Wait States.....................................................................................................51
Section 4 Address Break
Table 4-1 Access and Data Bus Used...........................................................................................57
Section 5 Clock Pulse Generators
Table 5-1 Crystal Oscillator Parameters.......................................................................................62
Section 6 Power-down Modes
Table 6-1 Operating Frequency and Waiting Time ...................................................................... 66
Table 6-2 Transition Mode after the SLEEP Instruction Execution and Interrupt Handling........70
Table 6-3 Internal State in Each Operating Mode ........................................................................70
Section 7 ROM
Table 7-1 Setting Programming Modes........................................................................................77
Table 7-2 Boot Mode Operation...................................................................................................79
Rev. 1.0, 03/01, page xxi of xxiv
Page 22
Table 7-3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is
Possible.........................................................................................................................79
Table 7-4 Reprogram Data Computation Table............................................................................82
Table 7-5 Additional-Program Data Computation Table..............................................................83
Table 7-6 Programming Time.......................................................................................................83
Section 10 Timer V
Table 10-1 Pin Configuration.....................................................................................................110
Table 10-2 Clock signals to input to TCNTV and the counting conditions................................113
Section 11 Timer W
Table 11-1 Timer W Functions...................................................................................................124
Table 11-2 Timer W Pins............................................................................................................125
Section 13 Serial Communication Interface3 (SCI3)
Table 13-1 Pin Configuration.....................................................................................................155
Table 13-2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode)(1)...........163
Table 13-2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)..........164
Table 13-2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3)..........165
Table 13-3 Maximum Bit Rate for Each Frequency (Asynchronous Mode)..............................165
Table 13-4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ........................166
Table 13-5 SSR Status Flags and Receive Data Handling..........................................................173
Table 13-6 SCI3 Interrupt Requests............................................................................................190
Section 14 A/D Converter
Table 14-1 Pin Configuration.....................................................................................................195
Table 14-2 Analog Input Channels and Corresponding ADDR Registers..................................196
Table 14-3 A/D Conversion Time (Single Mode) ......................................................................201
Section 16 Electrical Characteristics
Table 16-1 Absolute Maximum Ratings.....................................................................................207
Table 16-2 DC Characteristics (1)..............................................................................................209
Table 16-2 DC Characteristics (2)..............................................................................................213
Table 16-3 AC Characteristics....................................................................................................214
Table 16-4 Serial Interface (SCI3) Timing .................................................................................216
Table 16-5 A/D Converter Characteristics..................................................................................217
Table 16-6 Watchdog Timer Characteristics ..............................................................................218
Table 16-7 Flash Memory Characteristics (Preliminary)............................................................219
Appendix A Instruction Set
Table A.1 Instruction Set............................................................................................................227
Table A.2 Operation Code Map (1)............................................................................................240
Table A.2 Operation Code Map (2)............................................................................................241
Rev. 1.0, 03/01, page xxii of xxiv
Page 23
Table A.2 Operation Code Map (3)............................................................................................242
Table A.3 Number of Cycles in Each Instruction.......................................................................244
Table A.4 Number of Cycles in Each Instruction.......................................................................245
Table A.5 Combinations of Instructions and Addressing Modes ...............................................250
Rev. 1.0, 03/01, page xxiii of xxiv
Page 24
Rev. 1.0, 03/01, page xxiv of xxiv
Page 25
Section 1 Overview
1.1 Overview
High-speed H8/300H central processing unit with an internal 16-bit architecture
•
Upward-compatible with H8/300 CPUs on an object leve l
Sixteen 16-bit general registers
62 basic instructions
Various peripheral functions
•
Timer V (8-bit timer)
Timer W (16-bit timer)
Watchdog timer
SCI3 (Asynchronous or clocked synchronous serial communication interface)
10-bit A/D converter
On-chip memory
•
ROM Model ROM RAM
F-ZTAT Version HD64F3672 16k 2,048 bytes
HD64F3670 8k 2,048 bytes
General I/O ports
•
I/O pins: 26 I/O pins, including 5 large current ports (I
•
Input-only pins: 4 input pins (also used for analog input)
•
Supports various power-down states
•
Compact package
•
Package (Code) Body Size Pin Pitch
LQFP-64 (FP-64E) 10.0 × 10.0 mm 0.5 mm
LQFP-48 (FP-48F) 10.0 × 10.0 mm 0.65 mm
= 20mA, @VOL = 1.5V)
OL
Rev. 1.0, 03/01, page 1 of
280
Page 26
1.2 Internal Block Diagram
VCLVSSVCCTEST
P17/ /TRGV
P14/
P22/TXD
P21/RXD
P20/SCK3
P55/
/
P54/
P53/
P52/
P51/
P50/
P16
P15
P12
P11
P10
P57
P56
Port 1
Port 2Port 5
OSC1
System
clock
generator
OSC2
CPU
H8/300H
Data bus (lower)
ROM
Timer W
Timer V
A/D converter
RAM
SCI3
Watchdog
timer
Address bus
Data bus (upper)
Port 7Port 8
EIOT_0
EIOT_1
EIOT_2
P76/TMOV
P75/TMCIV
P74/TMRIV
P84/FTIOD
P83/FTIOC
P82/FTIOB
P81/FTIOA
P80/FTCI
= 1.5 V
OL
= 20 mA @ V
OL
CMOS large current port
I
Rev. 1.0, 03/01, page 2 of
Port B
CC
AV
PB3/AN3
PB2/AN2
PB1/AN1
PB0/AN0
Figure 1-1 Internal Block Diagram
280
Page 27
1.3 Pin Arrangement
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
NC
50
NC
NC
NC
NC
NC
NC
NC
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1 2 3 4 5 6 7 8 910111213141516
P14/
P15
P16
P17/
/TRGV
PB3/AN3
PB2/AN2
PB1/AN1
PB0/AN0
Note: Do not connect NC pins.
NCNCP22/TXD
NC
NC
CC
AV
P21/RXD
P20/SCK3
NC
NC
EIOT_2
EIOT_1
H8/3672
Top view
CL
V
EIOT_0
P84/FTIOD
SS
V
TEST
P83/FTIOC
P82/FTIOB
P81/FTIOA
CC
V
OSC2
OSC1
P80/FTCINCNC
P50/
P51/
Figure 1-2 Pin Arrangement (FP-64E)
NC
NC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
NC
P76/TMOV
P75/TMCIV
P74/TMRIV
P57
P56
P12
P11
P10
P55/
P54/
P53/
P52/
NC
NC
/
Rev. 1.0, 03/01, page 3 of
280
Page 28
P17/
P14/
/TRGV
PB3/AN3
PB2/AN2
PB1/AN1
PB0/AN0
P15
P16
NC
NC
NC
NC
P22/TXD
P21/RXD
P20/SCK3
EIOT_2
EIOT_1
EIOT_0
P84/FTIOD
P83/FTIOC
P82/FTIOB
P81/FTIOA
P80/FTCI
36 35 34 33 32 31 30 29 28 27 26 25
Vcc
P50/
24
23
22
21
20
19
18
17
16
15
14
13
P51/
37
38
39
40
41
42
43
44
45
46
47
48
123456789101112
NC
AVcc
NC
H8/3672
Top view
CL
V
TEST
Vss
OSC2
OSC1
Figure 1-3 Pin Arrangement (FP-48F)
P76/TMOV
P75/TMCIV
P74/TMRIV
P57
P56
P12
P11
P10
P55/
P54/
P53/
P52/
/
Rev. 1.0, 03/01, page 4 of
280
Page 29
1.4 Pin Functions
Table 1-1 Pin Functions
Pin No.
Type Symbol FP-64E FP-48F I/O Functions
Power
source pins
Clock pins OSC1 11 9 Input
System
control
Interrupt
pins
V
CC
12 10 Input Power supply pin. Connect this pin
to the system power supply.
V
SS
9 7 Input Ground pin. Connect all these pins
to the system power supply(0V).
AV
CC
3 1 Input Analog power supply pin for the A/D
converter. When the A/D converter
is not used, connect all this pin to
the system power supply.
V
CL
6 4 Input Internal step-down power supply
pin. Connect a capacitor of around
0.1µF between this pin and the Vss
pin for stabilization.
These pins connect to a crystal or
OSC2 10 8 Output
ceramic oscillator for system clocks,
or can be used to input an external
clock.
These pins can be used to input an
external clock. See section 5, Clock
Pulse Generators, for a typical
connection.
RES 7 5 Input Reset pin. When this driven low, the
chip is reset.
TEST 8 6 Input Test pin. Connect this pin to Vss.
NMI 35 25 Input Non-maskable interrupt request
input pin.
IRQ0,
IRQ3
51, 54 37, 40 Input External interrupt request input
pins. Can select the rising or falling
edge.
WKP0 to
WKP5
13, 14,
19 to 22
11 to 16 Input External interrupt request input
pins. Can select the rising or falling
edge.
Rev. 1.0, 03/01, page 5 of
280
Page 30
Pin No.
Type Symbol FP-64E FP-48F I/O Functions
Timer V TMOV 30 24 Output This is an output pin for waveforms
generated by the output compare
function.
TMCIV 29 23 Input External event input pin.
TMRIV 28 22 Input Counter reset input pin.
TRGV 54 40 Input Counter start trigger input pin.
Timer W FTCI 36 26 Input External event input pin.
FTIOA to
FTIOD
EIOT EIOT-0,
EIOT-1,
EIOT-2
Serial communication
interface
(SCI)
A/D
converter
I/O ports PB3 to PB0 59 to 62 45 to 48 Input 4-bit input port.
Other NC These pins must be left
TXD 46 36 Output Transmit data output pin
RXD 45 35 Input Receive data input pin
SCK3 44 34 Output Clock I/O pin
AN3 to AN0 59 to 62 45 to 48 Input Analog input pin
ADTRG 22 16 Input A/D converter trigger input pin.
P17 to P14,
P12 to P10
P22 to P20 46 to 44 36 to 34 I/O 3-bit I/O port.
P57 to P50 27, 26,
P76 to P74 30 to 28 24 to 22 I/O 3-bit I/O port
P84 to P80 40 to 36 30 to 26 I/O 5-bit I/O port.
37 to 40 29 to 30 I/O Output compare output/ input
capture input/ PWM output pin
41, 42, 43 31, 32, 33 I/O Interface pin for EIOT emulator
54 to 51,
25 to 23
22 to 19,
14, 13
40 to 37,
19 to 17
21, 20,
16 to 11
I/O 7-bit I/O port.
I/O 8-bit I/O port
unconnected.
Rev. 1.0, 03/01, page 6 of
280
Page 31
Section 2 CPU
This LSI has an H8/300H CPU with an internal 3 2-bit architecture that is upword-compatible with
the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space.
Upward-compatible with H8/300 CPUs
•
Can execute H8/300 CPUs object programs
Additional eight 16-bit extended registers
32-bit transfer and arithmetic and logic instructions are added
Signed multiply and divide instructio ns are added.
General-register architecture
•
Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers
Sixty-two basic instructions
•
8/16/32-bit data transfer and arithmetic and log ic in structions
Multiply and divide instructions
Powerful bit-manipulation instructions
Eight addressing modes
•
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, @aa:24]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Memory indirect [@@aa:8]
64-kbyte address space
•
High-speed operation
•
All frequently-used instructions execute in one or two states
8/16/32-bit register-register add/subtract : 2 state
8 × 8-bit register-register multiply : 14 states
16 ÷ 8-bit register-register divide : 14 states
16 × 16-bit register-register multiply : 22 states
32 ÷ 16-bit register-register divide : 22 states
Power-down state
•
Transition to power-down state by SLEEP instruction
Rev. 1.0, 03/01, page 7 of
280
Page 32
2.1 Address Space and Memory Map
The address space of this LSI is 64 kbytes, which includes the program area and the data area.
Figure 2-1 show the memory map.
(Flash memory version)
H'0000
H'0033
H'0034
H'3FFF
H'4000
H'4FFF
HD64F3672
Interrupt vector
On-chip ROM
(16 kbytes)
EIOT control
program area
(4 kbytes)
Not used
(Flash memory version)
H'0000
H'0033
H'0034
H'1FFF
H'4000
H'4FFF
HD64F3670
Interrupt vector
On-chip ROM
(8 kbytes)
Not used
EIOT control
program area
(4 kbytes)
Not used
H'F780
H'FB7F
H'FB80
H'FF7F
H'FF80
H'FFFF
Rev. 1.0, 03/01, page 8 of
(1-kbyte work area
for flash memory
programming&EIOT)
On-chip RAM
(2 kbytes)
(1-kbyte user area)
Internal I/O register
Figure 2-1 Memory Map
280
H'F780
H'FB7F
H'FB80
H'FF7F
H'FF80
H'FFFF
(1-kbyte work area
for flash memory
programming&EIOT)
On-chip RAM
(2 kbytes)
(1-kbyte user area)
Internal I/O register
Page 33
2.2 Register Configuration
The H8/300H CPU has the internal registers shown in figure 2-2. There are two types of registers;
general registers and control registers. The control registers are a 24-bit program counter (PC), and
an 8-bit condition code register (CCR).
General Registers (ERn)
15 0 7 0 7 0
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7 (SP)
E0
E1
E2
E3
E4
E5
E6
E7
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
Control Registers (CR)
Legend
SP
:Stack pointer
PC
:Program counter
CCR
:Condition-code register
I
:Interrupt mask bit
UI
:User bit
23 0
PC
76543210
CCR
IUIHUNZVC
:Half-carry flag
H
:User bit
U
:Negative flag
N
:Zero flag
Z
:Overflow flag
V
:Carry flag
C
Figure 2-2 CPU Registers
Rev. 1.0, 03/01, page 9 of
280
Page 34
2.2.1 General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally
identical and can be used as both address registers and data registers. When a general register is
used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2-3 illustrates
the usage of the general registers. When the general registers are used as 32-bit registers or address
registers, they are designated by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit registers designated by the letters RH (R0H to R7H) and RL (R0L
to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8-bit
registers.
The usage of each register can be selected independently.
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2-4 shows th e
stack.
• Address registers
• 32-bit registers
ER registers
(ER0 to ER7)
Rev. 1.0, 03/01, page 10 of
• 16-bit registers • 8-bit registers
E registers (extended registers)
(E0 to E7)
RH registers
(R0H to R7H)
R registers
(R0 to R7)
RL registers
(R0L to R7L)
Figure 2-3 Usage of General Registers
280
Page 35
Free area
SP (ER7)
Stack area
Figure 2-4 Relationship between Stack Pointer and Stack Area
2.2.2 Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is regarded as 0) . The PC is initialized when the
start address is loaded by the vector address generated during reset exception-handling sequence.
2.2.3 Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The I bit is initialized to 1
by reset exception-handling sequence, but other bits are not initialized.
Some instructions leave flag bits unchanged. Operation s can be performed on the CCR bits by the
LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching
conditions for conditional branch (Bcc) instructions.
For the action of each instruction on the flag bits, see appendix A.1 Instruction List.
Rev. 1.0, 03/01, page 11 of
280
Page 36
Bit Bit Name Initial Value R/W Description
7 I 1 R/W Interrupt Mask Bit
Masks interrupts other than NMI when set to 1.
NMI is accepted regardless of the I bit setting.
The I bit is set to 1 at the start of an exceptionhandling sequence.
6 UI undefined R/W User Bit
Can be written and read by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
5 H undefined R/W Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B,
CMP.B, or NEG.B instruction is executed, this
flag is set to 1 if there is a carry or borrow at bit 3,
and cleared to 0 otherwise. When the ADD.W,
SUB.W, CMP.W, or NEG.W instruction is
executed, the H flag is set to 1 if there is a carry
or borrow at bit 11, and cleared to 0 otherwise.
When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 27, and cleared to
0 otherwise.
4 U undefined R/W User Bit
Can be written and read by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
3 N undefined R/W Negative Flag
Stores the value of the most significant bit of data
as a sign bit.
2 Z undefined R/W Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
1 V undefined R/W Overflow Flag
Set to 1 when an arithmetic overflow occurs, and
cleared to 0 at other times.
0 C undefined R/W Carry Flag
Set to 1 when a carry occurs, and cleared to 0
otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to indicate a
carry
The carry flag is als o used as a bit accumulator
by bit manipulation instructions.
Rev. 1.0, 03/01, page 12 of
280
Page 37
2.3 Data Formats
The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.
2.3.1 General Register Data Formats
Figure 2-5 shows the data formats in general registers.
Data Type General Register Data Format
70
65432710
Don't care
7043
Upper Lower
Don't care
70
65432710
Don't care
1-bit data
1-bit data
4-bit BCD data
RnH
RnL
RnH
4-bit BCD data
Byte data
Byte data
RnL
RnH
RnL
Don't care
70
MSB LSB
Don't care
7043
Upper Lower
70
MSB LSB
Figure 2-5 General Register Data Formats (1)
Rev. 1.0, 03/01, page 13 of
Don't care
280
Page 38
Data Type Data FormatGeneral
Register
Word data
Word dataRnEn
Longword
ERn
data
Legend
ERn
: General register ER
En
: General register E
Rn
: General register R
RnH
: General register RH
RnL
: General register RL
MSB
: Most significant bit
LSB
: Least significant bit
15 0
MSB LSB
15 0
MSB LSB
31 16
MSB
15 0
Figure 2-5 General Register Data Formats (2)
LSB
Rev. 1.0, 03/01, page 14 of
280
Page 39
2.3.2 Memory Data Formats
Figure 2-6 shows the data formats in memory. The H8/300H CPU can access word data and
longword data in memory, however word or longword data must begin at an even address. If an
attempt is made to access word or longword data at an odd address, an address error does not
occur, however the least significant bit of the address is regarded as 0, so access begins the
preceding address. This also applies to instruction fetches.
When ER7(SP)is used as an address register to access the stack, the operand size should be word
or longword.
Data T ype Address
1-bit data
Byte data
Word data
Longword data Address 2N
Address L
Address L
Address 2M
Address 2M+1
Address 2N+1
Address 2N+2
Address 2N+3
MSB
MSB
MSB
Figure 2-6 Memory Data Formats
Data Format
70
76 543210
LSB
LSB
LSB
Rev. 1.0, 03/01, page 15 of
280
Page 40
2.4 Instruction Set
2.4.1 Table of Instructions Classified by Function
The H8/300H CPU has 62 instructions. Tables 2-2 to 2-9 summarizes the instructions in each
functional category. The notation used in tables 2-2 to 2-9 is defined below.
Table 2-1 Operation Notation
Symbol Description
Rd General register (destination)
Rs General register (source)
Rn General register
ERn General register (32-bit register or address register)
(EAd) Destination operand
(EAs) Source operand
CCR Condition-code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Addition
– Subtraction
× Multiplication
÷ Division
∧ Logical AND
∨ Logical OR
⊕ Logical XOR
→ Move
¬ NOT (logical complement)
:3/:8/:16/:24 3-, 8-, 16-, or 24-bit length
Note: *General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to
R7, E0 to E7), and 32-bit registers/address registers (ER0 to ER7).
*
*
*
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Table 2-2 Data Transfer Instructions
Instruction Size
MOV B/W/L (EAs) → Rd, Rs → (EAd)
MOVFPE B (EAs) → Rd, Cannot be used in this LSI.
MOVTPE B Rs → (EAs) Cannot be used in this LSI.
POP W/L @SP+ → Rn
PUSH W/L Rn → @–SP
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
Function
*
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
Pops a general register from the stack. POP.W Rn is identical to MOV.W
@SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP.
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Table 2-3 Arithmetic Operations Instructions (1)
Instruction Size
ADD
SUB
ADDX
SUBX
INC
DEC
ADDS
SUBS
DAA
DAS
MULXU B/W Rd × Rs → Rd
MULXS B/W Rd × Rs → Rd
DIVXU B/W Rd ÷ Rs → Rd
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd
B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd
L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
B Rd decimal adjust → Rd
Function
*
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register (immediate byte data
cannot be subtracted from byte data in a general register. Use the SUBX
or ADD instruct ion.)
Performs addition or subtraction with carry on byte data in two general
registers, or on immediate data and data in a general register.
Increments or decrements a general register by 1 or 2. (Byte operands
can be incremented or decremented by 1 only.)
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 4-bit BCD data.
Performs unsigned multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
Performs signed multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
Performs unsigned division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
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Table 2-3 Arithmetic Operations Instructions (2)
Instruction Size
DIVXS B/W Rd ÷ Rs → Rd
CMP B/W/L Rd – Rs, Rd – #IMM
NEG B/W/L 0 – Rd → Rd
EXTU W/L Rd (zero extension) → Rd
EXTS W/L Rd (sign extension) → Rd
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
Function
*
Performs signed division on data in two general registers: either 16 bits ÷
8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.
Compares data in a general register with data in another general register
or with immediate data, and sets CCR bits according to the result.
Takes the two's complement (arithmetic complement) of data in a
general register.
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.
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Table 2-4 Logic Operations Instructions
Instruction Size
AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
NOT B/W/L ¬ (Rd) → (Rd)
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
Function
*
Performs a logical AND operation on a general register and another
general register or immediate data.
Performs a logical OR operation on a general register and another
general register or immediate data.
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
Takes the one's complement of general register contents.
Table 2-5 Shift Instructions
Instruction Size
SHAL
SHAR
SHLL
SHLR
ROTL
ROTR
ROTXL
ROTXR
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
B/W/L Rd (shift) → Rd
B/W/L Rd (shift) → Rd
B/W/L Rd (rotate) → Rd
B/W/L Rd (rotate) → Rd
Function
*
Performs an arithmetic shift on general register contents.
Performs a logical shift on general register contents.
Rotates general register contents.
Rotates general register contents through the carry flag.
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Table 2-6 Bit Manipulation In structions (1)
Instruction Size
BSET B 1 → (<bit-No.> of <EAd>)
BCLR B 0 → (<bit-No.> of <EAd>)
BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
BTST B ¬ (<bit-No.> of <EAd>) → Z
BAND
BIAND
BOR
BIOR
Note: * Refers to the operand size.
B: Byte
B
B
B
B
Function
*
Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
Clears a specified bit in a general register or memory operand to 0. The
bit number is specified by 3-bit immediate data or the lower three bits of a
general register.
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
Tests a specified bit in a general register or memory operand and sets or
clears the Z flag accordingly. The bit number is specif ied by 3-bi t
immediate data or the lower three bits of a general register.
C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
C ∧ ¬ (<bit-No.> of <EAd>) → C
ANDs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
C ∨ ¬ (<bit-No.> of <EAd>) → C
ORs the carry flag with the inverse of a specified bit in a general register
or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
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Table 2-6 Bit Manipulation In structions (2)
Instruction Size
BXOR
BIXOR
BLD
BILD
BST
BIST
Note: * Refers to the operand size.
B: Byte
B
B
B
B
B
B
Function
*
C ⊕ (<bit-No.> of <EAd>) → C
XORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
C ⊕ ¬ (<bit-No.> of <EAd>) → C
XORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the
carry flag.
¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
¬ C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a general
register or memory operand.
The bit number is specified by 3-bit immediate data.
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Table 2-7 Branch Instructions
Instruction Size Function
Bcc — Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic Description Condition
BRA(BT) Always (true) Always
BRN(BF) Never (false) Never
BHI High C ∨ Z = 0
BLS Low or same C ∨ Z = 1
BCC(BHS) Carry clear
(high or same)
BCS(BLO) Carry set (low) C = 1
BNE Not equal Z = 0
BEQ Equal Z = 1
BVC Overflow clear V = 0
BVS Overflow set V = 1
BPL Plus N = 0
BMI Minus N = 1
BGE Greater or equal N ⊕ V = 0
BLT Less than N ⊕ V = 1
BGT Greater than Z∨(N ⊕ V) = 0
BLE Less or equal Z∨(N ⊕ V) = 1
C = 0
JMP — Branches unconditionally to a specified address.
BSR — Branches to a subroutine at a specified address.
JSR — Branches to a subroutine at a specified address.
RTS — Returns from a subroutine
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Table 2-8 System Control Instructions
Instruction Size
TRAPA — Starts trap-instruction exception handling.
RTE — Returns from an exception-handling routine.
SLEEP — Causes a transition to a power-down state.
LDC B/W (EAs) → CCR
STC B/W CCR → (EAd), EXR → (EAd)
ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR
XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
NOP — PC + 2 → PC
Note: * Refers to the operand size.
B: Byte
W: Word
Function
*
Moves the source operand contents to the CCR. The CCR size is one
byte, but in transfer from memory, data is read by word access.
Transfers the CCR contents to a destination loca tion. The condition code
register size is one byte, but in transfer to memory, data is written by
word access.
Logically ANDs the CCR with immediate data.
Logically ORs the CCR with immediate data.
Logically XORs the CCR with immediate data.
Only increments the program counter.
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Table 2-9 Block Data Transfer Instructions
Instruction Size Function
EEPMOV.B — if R4L ≠ 0 then
Repeat @ER5+ → @ER6+,
R4L–1 → R4L
Until R4L = 0
else next;
EEPMOV.W — if R4 ≠ 0 then
Repeat @ER5+ → @ER6+,
R4–1 → R4
Until R4 = 0
else next;
Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location set
in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
2.4.2 Basic Instruction Formats
H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op field), a register field (r field), an effective address extension (EA field), and a
condition field (cc).
Figure 2-7 shows examples of instruction formats.
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• Operation Field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
• Register Field
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3
bits or 4 bits. Some instructions have two register fields. Some have no register field.
• Effective Address Extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A24-bit
address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00).
• Condition Field
Specifies the branching condition of Bcc instructions.
(1) Operation field only
op
(2) Operation field and register fields
op
(3) Operation field, register fields, and effective address extension
op
EA(disp)
rn
rn rm
rm
NOP, RTS, etc.
ADD.B Rn, Rm, etc.
MOV.B @(d:16, Rn), Rm
(4) Operation field, effective address extension, and condition field
op cc EA(disp) BRA d:8
Rev. 1.0, 03/01, page 26 of
Figure 2-7 Instruction Formats
280
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2.5 Addressing Modes and Effective Address Calculation
2.5.1 A ddressing Modes
The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the
generated 24-bit address, so the effective address is 16 bits.
The H8/300H CPU supports the eight addressing modes listed in table 2-10. Each instruction uses
a subset of these addressing modes. Addressing modes that can be used differ depending on the
instruction. For details, refer to appendix A.4, Combinations of Instructions and Addressing
Modes.
Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer
instructions can use all addressing modes except program-counter relative and memory indirect.
Bit manipulation instructions use register direct, register indirect, or the absolute addressing mode
to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or
immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2-10 Addressing Modes
No. Addressing Mode Symbol
1 Register direct Rn
2 Register indirect @ERn
3 Register indirect with displacement @(d:16,ERn)/@(d:24,ERn)
4 Register indirect with post-increment
Register indirect with pre-decrement
5 Absolute address @aa:8/@aa:16/@aa:24
6 Immediate #xx:8/#xx:16/#xx:32
7 Program-counter relative @(d:8,PC)/@(d:16,PC)
8 Memory indirect @@aa:8
@ERn+
@–ERn
Register Direct—Rn
The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the
operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7
can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
Register Indirect—@ERn
The register field of the instruction code specifies an address register (ERn), the lower 24 bits of
which contain the address of the operand on memory.
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Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn)
A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction, and the lower 24 bits of the sum the address of a
memory operand. A 16-bit displacement is sign-extended when added.
Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn
• Register indirect with post-increment—@ERn+
The register field of the instruction code specifies an address register (ERn) the lower 24 bits
of which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is
added to the address register contents (32 bits) and the sum is stored in the address register.
The value added is 1 for byte access, 2 for word access, or 4 for longword access. For the word
or longword access, the register value should be even.
• Register indirect with pre-decrement—@-ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the lower 24 bits of the result is the ad dress of a memory operand.
The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for
word access, or 4 for longword access. For the word or longword access, the register value
should be even.
Absolute Address—@aa:8, @aa:16, @aa:24
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24)
For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit
absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the
entire address space.
The access ranges of absolute addresses for the series of this LSI are those shown in table 2-11,
because the upper 8 bits are ignored.
Table 2-11 Absolute Address Access Ranges
Absolute Address Access Range
8 bits (@aa:8) H'FF00 to H'FFFF
16 bits (@aa:16) H'0000 to H'FFFF
24 bits (@aa:24) H'0000 to H'FFFF
Immediate—#xx:8, #xx:16, or #xx:32
The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an
operand.
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The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. So me bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a
vector address.
Program-Counter Relative—@(d:8, PC) or @(d:16, PC)
This mode is used in the BSR instruction. An 8-bit or 16-bit displacement contained in the
instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. The
PC value to which the displacement is added is the address of the first byte of the next instruction,
so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768
bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an
even number.
Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The memory operand is accessed by longword access. The first byte of the memory operand is
ignored, generating a 24-bit branch address. Figure 2-8 shows how to specify branch address for in
memory indirect mode. The upper bits of the absolute address are all assumed to be 0, so the
address range is 0 to 255 (H'0000 to H'00FF).
Note that the first part of the address range is also the exception vector area.
Specified
by @aa:8
Dummy
Branch address
Figure 2-8 Branch Address Specification in Memory Indirect Mode
2.5.2 Effective Address Calculation
Table 2-12 indicates how effective addresses are calculated in each addressing mode. In this LSI
the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address.
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Table 2-12 Effective Address Calculation (1 )
No
Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)
1
Register direct(Rn)
op
2
Register indirect(@ERn)
op
3 Register indirect with displacement
@(d:16,ERn) or @(d:24,ERn)
op
Register indirect with post-increment or
4
pre-decrement
•Register indirect with post-increment @ERn+
op
•Register indirect with pre-decrement @-ERn
op
rn
rm
r
r
r
r
disp
31
General register contents
31
General register contents
31
Sign extension
31
General register contents
31
General register contents
The value to be added or subtracted is 1 when the
operand is byte size, 2 for word size, and 4 for
longword size.
disp
1, 2, or 4
1, 2, or 4
Operand is general register contents.
0
0
0
0
0
23
23
23
23
0
0
0
0
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Table 2-12 Effective Address Calculation (2 )
Addressing Mode and Instruction Format
No
5
@aa:8
Absolute address
op
abs
Effective Address Calculation Effective Address (EA)
23 0
H'FFFF
8
7
@aa:16
@aa:24
6
Immediate
#xx:8/#xx:16/#xx:32
7
Program-counter relative
@(d:8,PC)
8
Memory indirect @@aa:8
op
Legend
Register field
r, rm,rn :
Operation field
op :
Displacement
disp :
Immediate data
IMM :
Absolute address
abs :
op
op
op
@(d:16,PC)
op
abs
abs
abs
IMM
disp
23
Sign extension
23 0
Operand is immediate data.
23
PC contents
23
Sign
extension
23
H'0000
disp
Memory contents
0
0
23
0
78
abs
015
23
H'00
15
16
16
15
0
0
0
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2.6 Basic Bus Cycle
CPU operation is synchronized by a system clock (ø) or a subclock (ø
edge of ø or ø
to the next rising edge is called one state. A bus cycle consists of two states or
SUB
). The period from a rising
SUB
three states. The cycle differs depending on whether access is to on-chip memory or to on-chip
peripheral modules.
2.6.1 Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2-9 shows the on-chip memory access cycle.
Bus cycle
ø or ø
SUB
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
T1 state
Address
T2 state
Read data
Internal data bus
(write access)
Rev. 1.0, 03/01, page 32 of
Write data
Figure 2-9 On-Chip Memory Access Cycle
280
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2.6.2 On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits
or 16 bits depending on the register. For description on the data bus width and number of
accessing states of each register, refer to appendix B, Register Addresses. Registers with 16-bit
data bus width can be accessed by word size only. Registers with 8-bit data bus width can be
accessed by byte or word size. When a register with 8-bit data bus width is accessed by word size,
access is completed in two cycles. In two-state access, the operation timing is the same as that for
on-chip memory.
Figure 2-10 shows the operation timing in the case of three-state access to an on-chip peripheral
module.
Bus cycle
ø or ø
T1 state
SUB
T2 state T3 state
Internal
address bus
Internal
read signal
Internal
data bus
(read access)
Internal
write signal
Internal
data bus
(write access)
Address
Read data
Write data
Figure 2-10 On-Chip Peripheral Module Access Cycle (3-State Access)
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2.7 CPU States
There are four CPU states: the reset state, program execution state, program halt state, and
exception-handling state. The program execution state includes active mode. In the program halt
state there are a sleep mode, and standby mode. These states are shown in figure 2-11, Figure 2-12
shows the state transitions. For details on program execution state and program halt state, refer to
section 6, Power-Down Modes. For details on exception processing, refer to section 3, Exception
Handling.
CPU state Reset state
The CPU is initialized
Program
execution state
The CPU executes successive program
instructions at high speed,
synchronized by the system clock
The CPU executes
successive program
instructions at reduced
speed, synchronized
by the subclock
Active
(high speed) mode
Rev. 1.0, 03/01, page 34 of
Program halt state
A state in which some
or all of the chip
functions are stopped
to conserve power
Exception-
handling state
A transient state in which the CPU changes
the processing flow due to a reset or an interrupt
Sleep mode
Standby mode
Figure 2-11 CPU Operation States
280
Power-down
modes
Page 59
Reset state
Reset cleared
Exception-handling state
Reset occurs
Reset
occurs
Program halt state
Reset
occurs
SLEEP instruction executed
Interrupt
source
Interrupt
source
Program execution state
Exceptionhandling
complete
Figure 2-12 State Transitions
2.8 Usage Notes
2.8.1 Notes on Data Access to Empty Areas
The address space of this LSI includes empty areas in addition to the ROM, RAM, and on- chip
I/O registers areas available to the user. When data is transferred from CPU to empty areas, the
transferred data will be lost. This action may also cause the CPU to malfunction. When data is
transferred from an empty area to CPU, the contents of the data cannot be guaranteed.
2.8.2 EEPMOV Instruction
EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L,
which starts from the address indicated by R5, to the address indicated by R6. Set R4L and R6 so
that the end address of the destination address (value of R6 + R4L) does not exceed H'FFFF (the
value of R6 must not change from H'FFFF to H'0000 during execution).
2.8.3 Bit Manipulation Instruction
The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in
byte units, manipulate the data of the target bit, and write da ta to the same address again in byte
units. Special care is required when using these instructions in cases where two registers are
assigned to the same address or when a bit is directly manipulated for a port, because this may
rewrite data of a bit other than the bit to be manipulated.
Bit manipulation for two registers assigned to the same address
Example: Bit manipulation for the timer load register and timer counter
(Applicable for timer B and timer C, not for the series of this LSI.)
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Figure 2-13 shows an example of a timer in which two timer registers are assigned to the same
address. When a bit manipulation instruction accesses the timer load register and timer counter of
a reloadable timer, since these two registers share the same address, the following operations takes
place.
1. Data is read in byte units.
2. The CPU sets or resets the bit to be manipulated with the bit manipulation instruction.
3. The written data is written again in byte units to the timer load reg ister.
The timer is counting, so the value read is not necessarily the same as th e value in th e timer load
register. As a result, bits other than the intended bit in the timer counter may be modified and the
modified value may be written to the timer load register.
Count clock Timer counter
Reload
Timer load register
Read
Write
Internal bus
Figure 2-13 Example of Timer Configuration with Two Registers Allocated to Same
Address
Example 2: The BSET instruction is executed for port 5.
P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level
signal at P50 with a BSET instruction is shown below.
Rev. 1.0, 03/01, page 36 of
280
Page 61
Prior to executing BSET
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
PCR5 00111111
PDR5 10000000
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
BSET instruction executed
BSET #0, @PDR5
The BSET instruction is executed for port 5.
After executing BSET
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
PCR5 00111111
PDR5 0 1 000001
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
Description on operation
When the BSET instruction is executed, first the CPU reads p ort 5.
Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level input).
P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a
value of H'80, but the value read by the CPU is H'40.
Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41.
Finally, the CPU writes H'41 to PDR5, completin g execution of BSET.
As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal.
However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy
of the PDR5 data in a work area in memory. Perform the bit manipulation on the data in the work
area, then write this data to PDR5.
Rev. 1.0, 03/01, page 37 of
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Page 62
Prior to executing BSET
MOV.B #80, R0L
MOV.B R0L, @RAM0
MOV.B R0L, @PDR5
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
PCR5 00111111
PDR5 10000000
RAM0 10000000
High
level
The PDR5 value (H'80) is written to a work area in
memory (RAM0) as well as to PDR5.
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
BSET instruction executed
BSET #0, @RAM0
The BSET instruction is executed designating the PDR5
work area (RAM0).
After executing BSET
MOV.B @RAM0, R0L
The work area (RAM0) value is written to PDR5.
MOV.B R0L, @PDR5
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
PCR5 00111111
PDR5 10000001
RAM0 10000001
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
Bit Manipulation in a Register Co ntaining a Write-Only Bit
Example 3: BCLR instruction executed designating port 5 control register PCR5
P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as
an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be
input to this input pin.
Rev. 1.0, 03/01, page 38 of
280
Page 63
Prior to executing BCLR
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
PCR5 00111111
PDR5 10000000
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
BCLR instruction executed
BCLR #0, @PCR5
The BCLR instruction is executed for PCR5.
After executing BCLR
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Output Output Output Output Output Output Output Input
Pin state Low
level
PCR5 1 1111110
PDR5 10000000
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
Description on operation
When the BCLR instruction is executed, first the CPU reads PCR5. Since PCR5 is a write-only
register, the CPU reads a value of H'FF, even though the PCR5 value is actually H'3F.
Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE.
Finally, H'FE is written to PCR5 and BCLR instruction execution ends.
As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However, bits 7
and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins. To prevent
this problem, store a copy of the PCR5 data in a work area in memory and manipulate data of the
bit in the work area, then write this data to PCR5.
Rev. 1.0, 03/01, page 39 of
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Page 64
Prior to executing BCLR
MOV.B #3F, R0L
MOV.B R0L, @RAM0
MOV.B R0L, @PCR5
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
PCR5 00111111
PDR5 10000000
RAM0 00111111
High
level
The PCR5 value (H'3F) is written to a work area in
memory (RAM0) as well as to PCR5.
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
BCLR instruction executed
BCLR #0, @RAM0
The BCLR instructions executed for the PCR5 work area
(RAM0).
After executing BCLR
MOV.B @RAM0, R0L
The work area (RAM0) value is written to PCR5.
MOV.B R0L, @PCR5
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
PCR5 00111110
PDR5 10000000
RAM0 00111110
Rev. 1.0, 03/01, page 40 of
High
level
280
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
Page 65
Section 3 Exception Handling
Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts.
Reset
•
A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared
by the
starts. Exception handling is the same as ex ception handling by the
Trap Instruction
•
Exception handling starts when a trap instruction (TRAPA) is executed. The TRAPA instruction
generates a vector address corresponding to a vector number from 0 to 3, as specified in the
instruction code. Exception handling can be executed at all times in the program execution state.
Interrupts
•
External interrupts other than NMI and internal interrupts other than address break are masked by
the I bit in CCR, and k e pt masked while the I bit is set to 1 . Exception handling starts wh en the
current instruction or exception handling ends, if an interrupt request has been issued.
3.1 Exception Sources and Vector Address
Table 3-1 shows the vector addresses and priority of each exception handling. When more than
one interrupt is requested, handling is performed from the interrupt with the highest priority.
pin. The chip is also reset when the watchdog timer overflows, and exception handling
RES
pin.
RES
Rev. 1.0, 03/01, page 41 of 280
Page 66
Table 3-1 Exception Sources and Vector Address
Vector
Exception Sources Number Vector Address
Reset 0 H'0000 to H'0001
Reserved for system use 1 to 6 H'0002 to H'000D
NMI 7 H'000E to H'000F
Trap instruction (#0) 8 H'0010 to H'0011
(#1) 9 H'0012 to H'0013
(#2) 10 H'0014 to H'0015
(#3) 11 H'0016 to H'0017
Break conditions satisfied 12 H'0018 to H'0019
Direct transition by executing the SLEEP instruction 13 H'001A to H'001B
IRQ0 14 H'001C to H'001D
IRQ3 17 H'0022 to H'0023
WKP 18 H'0024 to H'0025
Reserved for system use 20 H'0028 to H'0029
Timer W Input capture A/compare match A
Input capture B/compare match B
Input capture C/compare match C
Input capture D/compare match D
Timer W overflow
Timer V Timer V compare match A
Timer V compare match B
Timer V overflow
SCI3 SCI3 receive data full
SCI3 transmit data empty
SCI3 transmit end
SCI3 receive error
A/D conversion end 25 H'0032 to H'0033
21 H'002A to H'002B
22 H'002C to H'002D
23 H'002E to H'002F
Rev. 1.0, 03/01, page 42 of 280
Page 67
3.2 Register Descriptions
Interrupts are controlled by the following registers. For details on register addresses and register
states during each processing, refer to appendix B, Internal I/O Register.
• Interrupt Edge Select Register 1(IEGR1)
• Interrupt Edge Select Register 2(IEGR2)
• Interrupt Enable Register 1(IENR1)
• Interrupt Flag Register 1(IRR1)
• Wakeup Interrupt Flag Register(IWPR)
3.2.1 Interrupt Edge Select Register 1(IEGR1)
IEGR1 selects the direction of an edge that generates interrupt requests of pins and IRQ3 and
IRQ0.
Bit Bit Name Initial Value R/W Description
7 − 0 − Reserved
This bit is always read as 0, and cannot be modified.
6
−
5
−
4
−
3 IEG3 0 R/W IRQ3 Edge Select
2 − 0 − Reserved
1 − 0 − Reserved
0 IEG0 0 R/W IRQ0 Edge Select
1
1
1
−
−
−
Reserved
These bits are always read as 1, and cannot be modified.
0: Falling edge of IRQ3 pin input is detected
1: Rising edge of IRQ3 pin input is detected
This bit is always read as 0, and cannot be modified.
This bit is always read as 0, and cannot be modified.
0: Falling edge of IRQ0 pin input is detected
1: Rising edge of IRQ0 pin input is detected
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Page 68
3.2.2 Interrupt Edge Select Register 2(IEGR2)
IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and
WKP5 to WKP0.
Bit Bit Name Initial Value R/W Description
7
−
6
−
5 WPEG5 0 R/W WKP5 Edge Select
4 WPEG4 0 R/W WKP4 Edge Select
3 WPEG3 0 R/W WKP3 Edge Select
2 WPEG2 0 R/W WKP2 Edge Select
1 WPEG1 0 R/W WKP1Edge Select
0 WPEG0 0 R/W WKP0 Edge Select
1
1
−
−
Reserved
These bits are always read as 1, and cannot be modified.
0: Falling edge of WKP5(ADTRG) pin input is detected
1: Rising edge of WKP5(ADTRG) pin input is detected
0: Falling edge of WKP4 pin input is detected
1: Rising edge of WKP4 pin input is detected
0: Falling edge of WKP3 pin input is detected
1: Rising edge of WKP3 pin input is detected
0: Falling edge of WKP2 pin input is detect ed
1: Rising edge of WKP2 pin input is detected
0: Falling edge of WKP1 pin input is detected
1: Rising edge of WKP1 pin input is detected
0: Falling edge of WKP0 pin input is detected
1: Rising edge of WKP0 pin input is detected
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Page 69
3.2.3 Interrupt Enable Register 1(IENR1)
IENR1 enables direct transition interrupts, and external pin interrupts.
Bit Bit Name Initial Value R/W Description
7 IENDT 0 R/W Direct Transfer Interrupt Enable
When this bit is set to 1, direct transition interrupt requests
are enabled.
6 − 0 − Reserved
This bit is always read as 0, and cannot be modified.
5 IENWP 0 R/W Wakeup Interrupt Enable
This bit is an enable bit, which is common to the pins
WKP5 to WKP0. When the bit is set to 1, interrupt
requests are enabled.
4 − 1 − Reserved
This bit is always read as 1, and cannot be modified.
3 IEN3 0 R/W IRQ3 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ3 pin
are enabled.
2 − 0 − Reserved
This bit is always read as 0, and cannot be modified.
1 − 0 − Reserved
This bit is always read as 0, and cannot be modified.
0 IEN0 0 R/W IRQ0 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ0 pin
are enabled.
When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in
an interrupt flag register, always do so while interrupts are masked(I=1). If the above clear
operations are performed while I=0, and as a result a conflict arises between the clear instruction
and an interrupt request, exception handling for the interrupt will be executed after the clear
instruction has been executed.
Rev. 1.0, 03/01, page 45 of 280
Page 70
3.2.4 Interrupt Flag Register 1(IRR1)
IRR1 is a status flag register for direct transition interrupts, and IRQ3 and IRQ0 interrupt requests.
Bit Bit Name Initial Value R/W Description
7 IRRDT 0 R/W Direct Transfer Interrupt Request Flag
[Setting condition]
When a direct transfer is made by executing a SLEEP
instruction while DTON in SYSCR2 is set to 1.
[Clearing condition]
When IRRDT is cleared by writing 0
6
− 0 − Reserved
This bit is always read as 0, and cannot be modified.
54−
−
3 IRRI3 0 R/W IRQ3 Interrupt Request Flag
2
− 0 − Reserved
1
− 0 − Reserved
0 IRRl0 0 R/W IRQ0 Interrupt Request Flag
1
1
−
−
Reserved
These bits are always read as 1, and cannot be modified.
[Setting condition]
When IRQ3 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IRRI3 is cleared by writing 0
This bit is always read as 0, and cannot be modified.
This bit is always read as 0, and cannot be modified.
[Setting condition]
When IRQ0 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IRRI0 is cleared by writing 0
Rev. 1.0, 03/01, page 46 of 280
Page 71
3.2.5 Wakeup Interrupt Flag Register(IWPR)
IWPR is a status flag register for WKP5 to WKP0 interrupt requests.
Bit Bit Name Initial Value R/W Description
76−
−
5 IWPF5 0 R/W WKP5 Interrupt Request Flag
4 IWPF4 0 R/W WKP4 Interrupt Request Flag
3 IWPF3 0 R/W WKP3 Interrupt Request Flag
2 IWPF2 0 R/W WKP2 Interrupt Request Flag
1 IWPF1 0 R/W WKP1 Interrupt Request Flag
0 IWPF0 0 R/W WKP0 Interrupt Request Flag
1
1
−
−
Reserved
These bits are always read as 1, and cannot be modified.
[Setting condition]
When WKP5 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF5 is cleared by writing 0.
[Setting condition]
When WKP4 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF4 is cleared by writing 0.
[Setting condition]
When WKP3 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF3 is cleared by writing 0.
[Setting condition]
When WKP2 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF2 is cleared by writing 0.
[Setting condition]
When WKP1 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF1 is cleared by writing 0.
[Setting condition]
When WKP0 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF0 is cleared by writing 0.
Rev. 1.0, 03/01, page 47 of 280
Page 72
3.3 Reset
When the RES pin goes low, all processing halts and this LSI enters the reset. Th e internal state of
the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure
that this LSI is reset at power-up, hold the RES pin low until the clock pulse generator output
stabilizes. To reset the chip during operation, hold the RES pin low for at least 10 system clock
cycles. When the RES pin goes high after being held low for the necessary time, this LSI starts
reset exception handling. The reset exception handling sequence is shown in figure 3-1. The reset
exception handling sequence is as follows:
1. Set the I bit in the condition code register (CCR) to 1.
2. The CPU generates a reset exception handling vector address (from H'0000 to H'0001), the
data in that address is sent to the program counter (PC) as the start address, and program
execution starts from that address.
3.4 Interrupt Exception Handling
3.4.1 External Interrupts
There are external interrupts, NMI, IRQ3, IRQ0, and WKP.
NMI
NMI interrupt is requested by input falling edge to pin NMI.
NMI is the highest interrupt, and can always be accepted without depending on the I bit value
in CCR.
IRQ3 to IRQ0 Interrupts
IRQ3 to IRQ0 interrupts are requested by input signals to pins IRQ3 to IRQ0. These four
interrupts are given different vector addresses, and are detected individually by either rising
edge sensing or falling edge sensing, depending on the settings of bits IEG3 to IEG0 in
IEGR1.
When pins IRQ3 to IRQ0 are designated for interrupt input in PMR1 and the designated signal
edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt.
When IRQ3 to IRQ0 interrupt is accepted, the I bit is set to 1 in CCR. These in terrupts can be
masked by setting bits IEN3 to IEN0 in IENR1.
Rev. 1.0, 03/01, page 48 of 280
Page 73
WKP5 to WKP0 Interrupts
WKP5 to WKP0 interrupts are requested by input signals to pins WKP5 to WKP0. These six
interrupts have the same vector addresses, and are detected individually by either rising edge
sensing or falling edge sensing, depending on the settings of bits WPEG5 to WPEG0 in
IEGR2.
When pins WKP5 to WKP0 are designated for interrupt input in PMR5 and the designated
signal edge is input, the corresponding bit in IWPR is set to 1, requesting the CPU of an
interrupt. These interrupts can be masked by setting bit IENWP in IENR1.
Reset cleared
Initial program
Vector fetch
ø
Internal
processing
instruction prefetch
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus (16 bits)
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) Initial program instruction
(1)
(2) (3)
(2)
Figure 3-1 Reset Sequence
3.4.2 Internal Interrupts
Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to
enable or disable the interrupt. For direct transfer interrupt requests generated by execution of a
SLEEP instruction, this function is included in IRR1 and IENR1.
When an on-chip peripheral module requests an interrupt, the corresponding interrupt request
status flag is set to 1, requesting the CPU of an interrupt. When this interrupt is accepted, the I bit
is set to 1 in CCR. These interrup ts can be masked by writing 0 to clear the corresponding enable
bit.
Rev. 1.0, 03/01, page 49 of 280
Page 74
3.4.3
Interrupts are controlled by an interrupt controller.
Interrupt operation is described as follows.
1. If an interrupt occurs while the NMI or interrupt enable bit is set to 1, an interrupt request
2. When multiple interrupt requests are generated, the interrupt contro ller requests to the CPU for
3. The CPU accepts the NMI or address break without depending on the I bit value. Other
4. If the CPU accepts the interrupt after processing of the current instruction is completed,
5. Then, the I bit of CCR is set to 1, masking further interrupts exclu ding the NMI and address
6. Next, the CPU generates the vector address corresponding to the accepted interrupt, and
Interrupt Handling Sequence
signal is sent to the interrupt controller.
the interrupt handling with the highest priority at that time according to table 3-1. Other
interrupt requests are held pending.
interrupt requests are accepted, if the I bit is cleared to 0 in CCR; if the I bit is set to 1, the
interrupt request is held pending.
interrupt exception handling will begin. First, both PC and CCR are p ushed onto the stack. The
state of the stack at this time is shown in figure 3-2. The PC value pushed onto the stack is the
address of the first instruction to be executed upon return from interrupt handling.
break. Upon return from interrupt handling, the values of I bit and other bits in CCR will be
restored and returned to the values prior to the start of interru pt exception handling.
transfers the address to PC as a start address of the interrupt handling-routine. Then a program
starts executing from the address indicated in PC.
Figure 3-3 shows a typical interrupt sequence where the program area is in the on-chip ROM and
the stack area is in the on-chip RAM.
Rev. 1.0, 03/01, page 50 of 280
Page 75
SP – 4
SP – 3
SP – 2
SP – 1
SP (R7)
Stack area
SP (R7)
SP + 1
SP + 2
SP + 3
SP + 4
CCR
CCR
PCH
PCL
*3
Even address
Prior to start of interrupt
exception handling
Legend:
PC
Upper 8 bits of program counter (PC)
:
H
Lower 8 bits of program counter (PC)
PC
:
L
Condition code register
CCR:
Stack pointer
SP:
1.2.PC shows the address of the first instruction to be executed upon return from the interrupt
Notes:
handling routine.
Register contents must always be saved and restored by word length, starting from
an even-numbered address.
3. Ignored when returning from the interrupt handling routine.
PC and CCR
saved to stack
After completion of interrupt
exception handling
Figure 3-2 Stack Status after Exception Handling
3.4.4 Interrupt Response Time
Table 3-2 shows the number of wait states after an interrupt requ est flag is set until the first
instruction of the interrupt handling-routine is executed.
Table 3-2 Interrupt Wait States
Item States Total
Waiting time for completion of executing instruction
*
Saving of PC and CCR to stack 4
Vector fetch 2
Instruction fetch 4
Internal processing 4
Note: * Not including EEPMOV instruction.
1 to 13 15 to 27
Rev. 1.0, 03/01, page 51 of 280
Page 76
Prefetch instruction of
interrupt-handling routine
Internal
processing
Vector fetch
Stack access
Internal
processing
Instruction
prefetch
(9)
(3) (9)(8)(6)(5)
(4) (1) (7) (10)
Interrupt is
accepted
Interrupt level
decision and wait for
end of instruction
Interrupt
request signal
Rev. 1.0, 03/01, page 52 of 280
(1)
ø
Internal
address bus
Internal read
signal
(2)
Internal write
signal
Internal data bus
Figure 3-3 Interrupt Sequence
(1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.)
(2)(4) Instruction code (not executed)
(3) Instruction prefetch address (Instruction is not executed.)
(5) SP – 2
(6) SP – 4
(7) CCR
(8) Vector address
(9) Starting address of interrupt-handling routine (contents of vector)
(16 bits)
(10) First instruction of interrupt-handling routine
Page 77
3.5 Usage Notes
3.5.1 Interrupts after Reset
If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instructio n initializes
the stack pointer (example: MOV.W #xx: 16, SP).
3.5.2 Notes on Stack Area Use
When word data is accessed, the least significant bit of the address is regarded as 0. Access to the
stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd
address. Use PUSH Rn (MOV.W Rn, @–SP) or POP Rn ( MOV.W @SP+, Rn) to save o r restore
register values.
3.5.3 Notes on Rewriting Port Mode Registers
When a port mode register is rewritten to switch the functions of external interrupt pins, IRQ3 to
IRQ0, and WKP5 to WKP0, the interrupt request flag may be set to 1.
Figure 3-4 shows a port mode register setting and interrupt request flag clearing procedure.
When switching a pin function, mask the interrupt before setting the bit in the port mode register.
After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the
interrupt request flag from 1 to 0.
Interrupts masked. (Another possibility
CCR I bit 1
Set port mode register bit
Execute NOP instruction
Clear interrupt request flag to 0
CCR I bit 0
←
←
is to disable the relevant interrupt in
interrupt enable register 1.)
After setting the port mode register bit,
first execute at least one instruction
(e.g., NOP), then clear the interrupt
request flag to 0
Interrupt mask cleared
Figure 3-4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure
Rev. 1.0, 03/01, page 53 of 280
Page 78
Rev. 1.0, 03/01, page 54 of 280
Page 79
Section 4 Address Break
The address break simplifies on-board program debugging. It requests an address break interrupt
when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR.
Break conditions that can be set include instruction execution at a specific address and a
combination of access and data at a specific address. With the address break function, the
execution start point of a program containing a bug is detected and execution is branched to the
correcting program. Figure 4-1 shows a block diagram of the address break.
Internal address bus
Comparator
BARH BARL
Interrupt
generation
control circuit
BDRH BDRL
Comparator
Legend:
BARH, BARL: Break address register
BDRH, BDRL: Break data register
ABRKCR: Address break control register
ABRKSR: Address break status register
ABRKCR
ABRKSR
Internal data bus
Interrupt
Figure 4-1 Block Diagram of an Address Break
4.1 Register Descriptions
Address break has the following registers. For details on register addresses and register states
during each processing, refer to appendix B, Internal I/O Register.
Address break control register(ABRKCR)
•
Address break status register(ABRKSR)
•
Break address register(BARH, BARL)
•
Break data register (BDRH, BDRL)
•
Rev. 1.0, 03/01, page 55 of 280
Page 80
4.1.1 Address Break Control Register(ABRKCR)
ABRKCR sets address break conditions.
Bit Bit Name Initial Value R/W Description
7 RTINTE 1 R/W RTE Interrupt Enable
When this bit is 0, the interrupt immediately after
executing RTE is masked and then one instruction must
be executed. When this bit is 1, the interrupt is not
masked.
65CSEL1
CSEL0
4
ACMP2
3
ACMP1
2
ACMP0
10DCMP1
DCMP000
Legend
: X: Don't care.
0
0
0
0
0
R/W
Condition Select 1 and 0
R/W
These bits set address break conditions.
00: Instruction execution cycle
01: CPU data read cycle
10: CPU data write cycle
11: CPU data read/write cycle
R/W
Address Compare Condition Select 2 to 0
R/W
These bits comparison condition between the address set
in BAR and the internal address bus.
R/W
000: Compares 16-bit addresses
001: Compares upper 12-bit addresses
010: Compares upper 8-bit addresses
011: Compares upper 4-bit addresses
1XX: Reserved
R/W
Data Compare Condition Select 1 and 0
R/W
These bits set the comparison condition between the data
set in BDR and the internal data bus.
00: No data comparison
01: Compares lower 8-bit data between BDRL and data
bus
10: Compares upper 8-bit data between BDRH and data
bus
11: Compares 16-bit data between BDR and data bus
When an address break is set in the data read cycle or data write cycle, the data bus used will
depend on the combination of the byte/word access and address. Table 4-1 shows the access and
data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a
byte access is generated twice. For details on data widths of each register, see appendix B.1,
Register Addresses.
Rev. 1.0, 03/01, page 56 of 280
Page 81
Table 4-1 Access and Data Bus Used
Word Access Byte Access
Even Address Odd Address Even Address Odd Address
ROM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits
RAM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits
I/O register with 8-bit data bus
width
I/O register with 16-bit data
bus width
Upper 8 bits Upper 8 bits Upper 8 bits Upper 8 bits
Upper 8 bits Lower 8 bits — —
4.1.2
Address Break Status Register(ABRKSR)
ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit.
Bit Bit Name Initial Value R/W Description
7 ABIF 0 R/W Address Break Interrupt Flag
[Setting condition]
When the condition set in ABRKCR is satisfied
[Clearing condition]
When 0 is written after ABIF=1 is read
6 ABIE 0 R/W Address Break Interrupt Enable
When this bit is 1, an address break interrupt request is
enabled.
5
−
4
−
3
−
2
−
1
−
0
−
0
0
0
0
0
0
−
Reserved
−
These bits are always read as 1 and cannot be modified.
−
−
−
−
4.1.3 Break Address Registers (BARH, BARL)
BARH, BARL are 16-bit read/write registers that set the address for generating an address break
interrupt. When setting the address break condition to the instruction execution cycle, set the first
byte address of the instruction. The initial value o f this register is H'FFFF.
Rev. 1.0, 03/01, page 57 of 280
Page 82
4.1.4 Break Data Registers (BDRH, BDRL)
BDRH, BDRL are 16-bit read/write registers that set the data for generating an address break
interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the lower 8bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for
even and odd addresses in the data transmission. Therefore, comparison data must be set in
BDRH for byte access. For word access, the data bus used depends on the address. See section
4.1.1, Address Break Control Register, for details. The initial value of this register is undefined.
4.2 Operation
When the ABIE bit in ABRKSR is set to 1, if the ABIF bit in ABRKSR is set to 1 by the
combination of the address set in BAR, the data set in BDR, and the conditions set in ABRKCR,
the address break function generates an interrupt request to the CPU. When the interrupt request
is accepted, interrupt exception handling starts after the instruction being executed ends. The
address break interrupt is not masked because of the I bit in CCR of the CPU.
Figures 4-2 show the operation examples of the address break interrupt setting.
When the address break is specified in instruction execution cycle
Register setting
• ABRKCR = H'80
• BAR = H'025A
NOP
instruc-
tion
prefetch
φ
Address
bus
Interrupt
request
0258
Program
NOP
instruc-
prefetch
025A 025C 025E SP-2 SP-4
NOP
0258
*
NOP
025A
MOV.W @H'025A,R0
025C
NOP
0260
NOP
0262
:
:
MOV
instruc-
tion
tion 1
prefetch
Interrupt acceptance
MOV
instruc-
tion 2
prefetch
Internal
processing Stack save
Underline indicates the address
to be stacked.
Figure 4-2 Address Break Interrupt Operation Example (1)
Rev. 1.0, 03/01, page 58 of 280
Page 83
When the address break is specified in the data read cycle
Register setting
• ABRKCR = H'A0
• BAR = H'025A
Program
NOP
0258
NOP
025A
MOV.W @H'025A,R0
*
025C
NOP
0260
NOP
0262
:
:
Underline indicates the address
to be stacked.
φ
Address
bus
Interrupt
request
MOV
instruc-
tion 1
prefetch
025C
MOV
instruc-
tion 2
prefetch
NOP
instruc-
prefetch
025E 0260 025A 0262 0264 SP-2
tion
MOV
instruc-
tion
execution
NOP
instruc-
tion
prefetch
Interrupt acceptance
Next
instru-
ction
prefetch
Internal
processing
Figure 4-2 Address Break Interrupt Operation Example (2)
Stack
save
Rev. 1.0, 03/01, page 59 of 280
Page 84
When the interrupt acceptance is prohibited after the RTE (RTB) instruction
Register setting
• ABRKCR = H'10
Interrupt
Interrupt
RTE
instruc-
tion
prefetch
φ
Address
bus
Interrupt
request
φ
Address
bus
Interrupt
request
039C
MOV
instruc-
tion
execution
025A
Interrupt acceptance
Program
NOP
0258
NOP
025A
MOV.W @H'025A,R0
025C
NOP
0260
NOP
0262
:
:
NOP
instruc-
tion
prefetch
039E SP SP+2 025C 025E
NOP
instruc-
tion
prefetch
Stack
resumption
Internal
processing
0262 SP-2 SP-4 XXXX
Internal
processing
Underline indicates the
address to be stacked.
:
:
NOP
039A
RTE
039C
NOP
039E
:
:
MOV
instruc-
tion 1
prefetch
Vector
fetch
processingStack restore
MOV
instruc-
prefetch
Internal
instruc-
tion 2
prefetch
Interrupt request
is prohibited
NOP
tion
0260
Continues
to the
lower
Figure 4-2 Address Break Interrupt Operation Example (3)
Rev. 1.0, 03/01, page 60 of 280
Page 85
Section 5 Clock Pulse Generators
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including a system
clock pulse generator. The system clock pulse generator consists of a system clock o scillato r, a
duty correction circuit, and system clock dividers.
Figure 5-1 shows a block diagram of the clock pulse generators.
ø
OSC
ø
OSC
OSC
1
2
System
clock
oscillator
System clock pulse generator
ø
OSC
(f
OSC
)
Duty
correction
circuit
ø
(f
OSC
OSC
System
clock
)
divider
/8
OSC
ø
/16
OSC
/32
ø
OSC
ø
/64
OSC
Figure 5-1 Block Diagram of Clock Pulse Generators
The basic clock signals that drive the CPU and on-chip peripheral modules are ø.
The system clock is divided into ø/8192 to ø/2 by prescaler S and they are supplied to respective
peripheral modules.
ø
Prescaler S
(13 bits)
ø/2
to
ø/8192
5.1 System Clock Generator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic
oscillator, or by providing external clock inp ut.
5.1.1 Connecting a Crystal Oscillator
Figure 5-2 shows a typical method of connecting a crystal oscillator. An AT-cut parallelresonance crystal resonator should be used. Figure 5-3 shows the equivalent circuit of a crystal
oscillator. An oscillator having the characteristics given in table 5-1 should be used.
C
OSC
1
OSC
2
Figure 5-2 Typical Connection to Crystal Oscillator
1
C
2
C = C = 12 pF ±20%
12
Rev. 1.0, 03/01, page 61 of 280
Page 86
L
S
C
S
R
S
OSC
1
C
0
OSC
2
Figure 5-3 Equivalent Circuit of Crystal Oscillator
Table 5-1 Crystal Oscillator Parameters
Frequency(MHz) 2481016
R
(max) 500 Ω 120 Ω 80 Ω 60 Ω 50 Ω
S
C0 (max) 7 pF 7 pF 7 pF 7 pF 7 pF
5.1.2 Connecting a Ceramic Oscillator
Figure 5-4 shows a typical method of connecting a ceramic oscillator.
C
OSC
OSC
1
2
1
C
2
C1 = 30 pF ±10%
C
= 30 pF ±10%
2
Figure 5-4 Typical Connection to Ceramic Oscillator
5.1.3 External Clock Input Method
Connect an external clock signal to pin OSC
, and leave pin OSC2 open. Figure 5-5 shows a
1
typical connection. The duty cycle of the external clock signal must be 45 to 55%.
OSC
OSC
1
2
Open
External clock input
Figure 5-5 Example of External Clock Input
Rev. 1.0, 03/01, page 62 of 280
Page 87
5.2 Prescalers
5.2.1 Prescaler S
Prescaler S is a 13-bit counter using the system clock (ø) as its input clock. It is incremented once
per clock period.
Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state.
In standby mode and subsleep mode, the system clock pulse generator stops. Prescaler S also stops
and is initialized to H'0000.
The CPU cannot read or write prescaler S.
The output from prescaler S is shared by the on-chip peripheral modules. The divider ratio can be
set separately for each on-chip peripheral function.
In active mode the clock input to prescaler S is determined by the division factor designated by
MA2 and MA0 in SYSCR2.
5.3 Usage Notes
5.3.1 Note o n O scillators
Oscillator characteristics are closely related to board design and should be carefully evaluated by
the user, referring to the examples shown in this section. Oscillator circuit constants will differ
depending on the oscillator element, stray capacitance in its interconnecting circuit, and other
factors. Suitable constants should be determined in consultation with the oscillator element
manufacturer. Design the circuit so that the oscillator element never receives voltages exceeding
its maximum rating.
Rev. 1.0, 03/01, page 63 of 280
Page 88
5.3.2 Notes on Board Design
When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as
close as possible to the OSC
and OSC2 pins. Other signal lines should be routed away from the
1
oscillator circuit to prevent induction from interfering with correct oscillation (see figure 5-6).
Signal A Signal BAvoid
C
OSC
OSC
1
2
1
C
2
Figure 5-6 Example of Incorrect Board Design
Rev. 1.0, 03/01, page 64 of 280
Page 89
Section 6 Power-down Modes
This LSI has six modes of operation after a reset. These include a normal active mode and four
power-down modes, in which power dissipation is significantly reduced. The module standby
mode reduces power dissipation by selectively halting on-chip module functions.
Active mode
•
The CPU and all on-chip peripheral modules are operable on the system clock. The system
clock frequency can be selected from øosc, øosc/8, øosc/16, øosc/32, and øosc/64.
Sleep mode
•
The CPU halts. On-chip peripheral functions are operable on the system clock.
Standby mode
•
The CPU and all on-chip peripheral modules halt.
Subsleep mode
•
The CPU and all on-chip peripheral modules halt.
I/O ports keep the same states as before the transition.
Module standby mode
•
Independent of the above modes, power dissipation can be reduced by halting on-chip modules
that are not used in module units.
6.1 Register Descriptions
The registers related to power-down modes are listed below. For details on register addresses and
register states during each processing, refer to appendix B, Internal I/O Register.
System control register 1(SYSCR1)
•
System control register 2(SYSCR2)
•
Module standby control register 1(MSTCR1)
•
Module standby control register 2(MSTCR2)
•
6.1.1 System Control Register 1(SYSCR1)
The SYSCR1 register controls the power-down modes, as well as SYSCR2.
Rev. 1.0, 03/01, page 65 of 280
Page 90
Bit Bit Name Initial Value R/W Description
7 SSBY 0 R/W Software Standby
This bit selects the mode to transit after the execution of
the SLEEP instruction.
0: a transition is made to the sleep mode
1: a transition is made to the standby mode.
For details, see table 6-2.
6
STS2
5
STS1
4
STS0
0
0
0
R/W
Standby Timer Select 2 to 0
R/W
These bits designate the time the CPU and peripheral
modules wait for stable clock operation after exiting from
R/W
the standby mode, to the active mode or sleep mode due
to an interrupt. The designation should be made according
to the clock frequency so that the waiting time is at least
10 ms. The relationship between the spe cif ied value and
the number of wait states is shown in table 6-1. When an
external clock is to be used, the minimum value (STS2 =
STS1 = STS0 =1) is recommended.
3to0 − 0 − Reserved
These bits are always read as 0 and cannot be modified.
Table 6-1 Operating Frequency and Waiting Time
STS2 STS1 STS0 Waiting Time 16 MHz 10 MHz 8 MHz 4 MHz 2 MHz 1 MHz 0.5 MHz
0
0
0
100
1
1
0
1
1
10
1
Note: Time unit is ms
8,192 states
16,384 states
32,768 states
65,536 states
131,072 states 8.2
1,024 states
128 states
16 states
0.5
1.0
2.0
4.1
0.06
0.00
0.00
0.8
1.6
3.3
6.6
13.1
0.10
0.01
0.00
1.0
2.0
4.1
8.2
16.4
0.13
0.02
0.00
2.0
4.1
8.2
16.4
32.8
0.26
0.03
0.00
4.1
8.2
16.4 32.8 65.5
32.8 65.5 131.1
65.5 131.1 262.1
0.51 1.02 2.05
0.06 0.13 0.26
0.01 0.02 0.03
8.1
16.4 32.8
16.4
6.1.2 System Control Register 2(SYSCR2)
The SYSCR2 register controls the power-down modes, as well as SYSCR1.
Rev. 1.0, 03/01, page 66 of 280
Page 91
Bit Bit Name Initial Value R/W Description
7 SMSEL 0 R/W Sleep Mode Selection
This bit selects the mode to transit after the execution of a
SLEEP instruction, as well as bit SSBY of SYSCR1.
For details, see table 6-2.
6 − 0 − Reserved
This bit is always read as 0, and cannot be modieied
5 DTON 0 R/W Direct Transfer on Flag
This bit selects the mode to transit after the execution of a
SLEEP instruction, as well as bit SSBY of SYSCR1.
For details, see table 6-2.
4
MA2
3
MA1
2
MA0
0
0
0
R/W
Active Mode Clock Select 2 to 0
R/W
These bits select the operating clock frequency in the
active and sleep modes. The operating clock fr eque nc y
R/W
changes to the set frequency after the SLEEP instruction
is execu ted.
0XX: φ
OSC
100: φ
101: φ
110: φ
111: φ
1
−
0
−
0
0
−
Reserved
−
These bits are always read as 0, and cannot be modified.
OSC
OSC
OSC
OSC
/8
/16
/32
/64
Legend X: Don't care.
6.1.3
Module Standby Control Register 1(MSTCR1)
MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units.
Rev. 1.0, 03/01, page 67 of 280
Page 92
Bit Bit Name Initial Value R/W Description
7 − 0 − Reserved
This bit is always read as 0 and cannot be modified
6 − 0 − Reserved
This bit is always read as 0 and cannot be modified
5 MSTS3 0 R/W SCI3 Module Standby
SCI3 enters the standby mode when this bit is set to 1
4 MSTAD 0 R/W A/D Converter Module Standby
A/D converter enters the standby mode when this bit is set
to 1
3 MSTWD 0 R/W Watchdog Timer Module Standby
Watchdog timer enters the standby mode when this bit is
set to 1.When the internal oscillator is selected for the
watchdog timer clock, the watchdog timer operates
regardless of the setting of this bit
2 MSTTW 0 R/W Timer W Module Standby
Timer W enters the standby mode when this bit is set to 1
1 MSTTV 0 R/W Timer V Module Standby
Timer V enters the standby mode when this bit is set to 1
0 − 0 − Reserved
This bit is always read as 0 and cannot be modified
6.1.4 Module Standby Control Register 2(MSTCR2)
MSTCR2 allows the on-chip peripheral modules to enter a standby state in module units.
Bit Bit Name Initial Value R/W Description
7to1 − 0 − Reserved
These bit are always read as 0 and cannot be modified
0 MSTPWM 0 R/W PWM Module Standby
PWM enters the standby mode hen this bit is set to 1
Rev. 1.0, 03/01, page 68 of 280
Page 93
6.2 Mode Transitions and States of the LSI
Figure 6-1 shows the possible transitions among these operating modes. A transition is made from
the program execution state to the program halt state of the program by executing a SLEEP
instruction. Interrupts allow for returning from th e program halt state to the program execution
state of the program. A direct transition between the active mode and subactive mode, which are
both program execution states, can be made without halting the program. The operating frequency
can also be changed in the same modes by making a transition directly from active mode to active
mode, and from subactive mode to subactive mode. RES input enables transitions from a mode to
the reset state. Table 6-2 shows the transition conditions of each mode after the SLEEP instruction
is executed and a mode to return by an interrupt. Table 6-3 shows the internal states of the LSI in
each mode.
Reset state
Program halt state Program execution state Program halt state
SLEEP
Standby mode
instruction
Interrupt
Active mode
Direct transition
interrupt
SLEEP
instruction
Interrupt
SLEEP
instruction
Sleep mode
Interrupt
Subsleep mode
Notes: 1. To make a transition to another mode by an interrupt, make sure interrupt handling is after the interrupt
is accepted.
2. Details on the mode transition conditions are given in table 6-2.
Figure 6-1 Mode Transition Diagram
Rev. 1.0, 03/01, page 69 of 280
Page 94
Table 6-2 Transition Mode after the SLEEP Instruction Execution and Interrupt Handling
DTON SSBY SMSEL
Transition Mode after SLEEP
Instruction Execution
Transition Mode due to
Interrupt
0 0 0 Sleep mode Active mode
0 1 Sleep mode Active mode
1 X Standby mode Active mode
1X0*Active mode(direct transition) —
Legend: X : Don’t care.
• When a state transition is performed while SMSEL is 1, timer V, SCI3, and the A/D converter
are reset, and all registers are set to their initial values. To use these functions after entering
active mode, reset the registers.
Table 6-3 Internal State in Each Operating Mode
Function Active Mode Sleep Mode Subsleep Mode Standby Mode
System clock oscillator Functioning Functioning Halted Halted
Instructions Func tioning Halt ed Halted Hal t edCPU
operations
RAM Functioning Retained Retained Retained
IO ports Functioning Retained Retained Register contents are
interrupts
functions
Registers Functioning Retained Retained Retained
retained, but output is the
high-impedance state.
IRQ3, IRQ0 Functioning Functioning Functioning FunctioningExternal
WKP5 to WKP0 Functioning F unctioning Functioning Functioning
Timer V Functioning Functioning Reset ResetPeripheral
Timer W Functioning Functioning Retained Retained(if internal clock
is selected as a count
clock, the counter is
incremented by a subclock)
Watchdog timer Functioning Functioning Retained Retained(functioning if the
internal oscillator is
selected as a count clock)
SCI3 Functioning Functioning Reset
A/D converter Functioning Functioning Reset Reset
φ
Rev. 1.0, 03/01, page 70 of 280
Page 95
6.2.1 Sleep Mode
In the sleep mode, CPU operation is halted but the on-chip peripheral modules function at the
clock frequency set by the MA2 to MA0 bits in SYSCR2. CPU register contents are retained.
When an interrupt is requested, the sleep mode is cleared and interrupt exception handling starts.
The sleep mode is not cleared if the I bit o f the condition code register (CCR) is set to 1 or the
requested interrupt is disabled in the interrupt enable register. a transition is made to sub active
mode when the bit is 1.
When the RES pin goes low, the CPU goes into the reset state and the sleep mode is cleared.
6.2.2 Standby Mode
In the standby mode, the clock pulse generator stops, so the CPU and on-chip peripheral modules
stop functioning. However, as long as the rated voltage is supplied, the contents of CPU registers,
on-chip RAM, and some on-chip peripheral module registers are retained. On-chip RAM contents
will be retained as long as the voltage set by the RAM data retention voltage is provided. The I/O
ports go to the high-impedance state.
The standby mode is cleared by an interrupt. When an interrupt is requested, the system clock
pulse generator starts. After the time set in bits STS2–STS0 in SYSCR1 has elapsed, and interrupt
exception handling starts. The standby mode is not cleared if the I bit of CCR is set to 1 or the
requested interrupt is disabled in the interrupt enable register.
When the RES pin goes low, the system clock pulse generator starts. Since system clock signals
are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the
RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator
output has stabilized, the CPU starts reset exception handling if the RES pin is driven high.
6.2.3 Subsleep Mode
In the subsleep mode, the system clock oscillator is h alted, and operation of the CPU and on-chip
peripheral modules is halted. As long as a required voltage is applied, the contents of CPU
registers, the on-chip RAM, and some registers of the on-chip peripheral modules are retained. I/O
ports keep the same states as before the transition.
The subsleep mode is cleared by an interrupt. When an interrupt is requested, the system clock
oscillator starts to oscillate.
The subsleep mode is cleared and an interrupt exception handling starts when the time set in bits
STS2 to STS0 in SYSCR1 elapses.
The subsleep mode is not cleared if the I bit of CCR is 1 or the interrupt is disabled in the interrupt
enable bit.
Rev. 1.0, 03/01, page 71 of 280
Page 96
6.3 Operating Frequency in the Active Mode
Operation in the active mode is clocked at the frequency designated by the MA2, to MA0 bits in
SYSCR2. The operating frequency changes to the set frequency after SLEEP instruction
execution.
6.4 Direct Transition
The CPU can execute programs in active mode.The operating freuncy can be changed by making
a transition directly from active mode to active mode. A direct transition can be made by
executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. The direct transition
also enables operating frequency mod ification in the active mode. After the mode transition, direct
transition interrupt exception handling starts.
If the direct transition interrupt is disabled in interrupt enable register 1, a transition is made
instead to the sleep mode. Note that if a direct transition is attem pted while the I bit in CCR is set
to 1, the sleep mode will be entered, and the resulting mode cannot be cleared by means o f an
interrupt.
6.5 Module Standby Function
The module-standby function can be set to any peripheral module. In the module standby mode,
the clock supply to modules stops to enter the power-down mode. The module standby mode
enables each on-chip peripheral module to enter the standby state by setting a bit that corresponds
to each module in MSTCR1 and MSTCR2 to 1 and cancels the mode by clearing the bit to 0.
Rev. 1.0, 03/01, page 72 of 280
Page 97
Section 7 ROM
The features of the 20-kbyte (4 kbytes of them are the EIOT control program area) flash memory
built into HD64F3672 are summarized below.
Programming/erase methods
•
The flash memory is programmed 128 bytes at a time. Erase is performed in single-block
units. The flash memory is configured as follows: 1 kbyte × 4 blocks, 16 kbytes × 1 block.
To erase the entire flash memory, each block must be erased in turn.
Reprogramming capability
•
The flash memory can be reprogrammed up to 100 times.
On-board programming
•
On-board programming/erasing can be done in boot mode, in which the boot program built
into the chip is started to erase or program of the entire flash memory. In normal user
program mode, individual blocks can be erased or programmed.
Automatic bit rate adjustment
•
For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match
the transfer bit rate of the host.
Programming/erasing protection
•
Sets software protection against flash memory programming/erasing.
Power-down mode
•
The power supply circuit is partly halted in the subactive mode and can be read in the
power-down mode.
7.1 Block Configuration
Figure 7-1 shows the block configuration of 16-kbyte flash memory. The thick lines indicate
erasing units, the narrow lines indicate programming units, and the values are addresses. The
flash memory is divided into 1 kbyte × 4 blocks and 16 kbytes × 1 block. Erasing is performed in
these units. Programming is performed in 128-byte units starting from an address with lower eight
bits H'00 or H'80.
Rev. 1.0, 03/01, page 73 of 280
Page 98
Erase unit
1kbyte
H'0000 H'0001 H'0002
H'0080 H'0081 H'0082
Programming unit: 128 bytes
H'007F
H'00FF
Erase unit
1kbyte
Erase unit
1kbyte
Erase unit
1kbyte
Erase unit
16 kbytes
H'0380 H'0381 H'0382
H'0400 H'0401 H'0402
H'0480 H'0481 H'0481
H'0780 H'0781 H'0782
H'0800 H'0801 H'0802
H'0880 H'0881 H'0882
H'0B80 H'0B81 H'0B82
H'0C00 H'0C01 H'0C02
H'0C80 H'0C81 H'0C82
H'0F80 H'0F81 H'0F82
H'1000 H'1001 H'1002
H'1080 H'1081 H'1082
H'4F80 H'4F81 H'4F82
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Figure 7-1 Flash Memory Block Configuration
H'03FF
H'047F
H'04FF
H'07FF
H'087F
H'08FF
H'0BFF
H'0C7F
H'0CFF
H'0FFF
H'107F
H'10FF
H'4FFF
7.2 Register Descriptions
The flash memory has the following registers. For details on register addresses and register states
during each processing, refer to appendix B, Internal I/O Register.
• Flash memory control register 1 (FLMCR1)
• Flash memory control register 2 (FLMCR2)
• Erase block register 1 (EBR1)
• Flash memory enable register (FENR)
Rev. 1.0, 03/01, page 74 of 280
Page 99
7.2.1 Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is a register that makes the flash memory change to program mode, program-verify
mode, erase mode, or erase-verify mode. For details on register setting, refer to section 7.4, Flash
Memory Programming/Erasing.
Bit Bit Name Initial Value R/W Description
7— 0 — Reserved
This bit is always read as 0 and cannot be modified.
6 SWE 0 R/W Software Write Enable
When this bit is set to 1, flash memory
programming/erasing is enabled. When this bit is
cleared to 0, other FLMCR1 register bits and all
EBR1 bits cannot be set.
5 ESU 0 R/W Erase Setup
When this bit is set to 1, the flash memory changes to
the erase setup state. When it is cleared to 0, the
erase setup state is cancelled. Set this bit to 1 before
setting the E bit to 1 in FLMCR1.
4 PSU 0 R/W Program Setup
When this bit is set to 1, the flash memory changes to
the program setup state. When it is cleared to 0, the
program setup state is cancelled. Set this bit to 1
before setting the P bit in FLMCR1.
3 EV 0 R/W Erase-Verify
When this bit is set to 1, the flash memory changes to
erase-verify mode. When it is cleared to 0, eraseverify mode is cancelled.
2 PV 0 R/W Program-Verify
When this bit is set to 1, the flash memory changes to
program-verify mode. When it is cleared to 0,
program-verify mode is cancelled.
1 E 0 R/W Erase
When this bit is set to 1, and while the SWE=1 and
ESU=1 bits are 1, the flash memory changes to erase
mode. When it is cleared to 0, erase mode is
cancelled.
0 P 0 R/W Program
When this bit is set to 1, and while the SWE=1 and
PSU=1 bits are 1, the flash memory changes to
program mode. When it is cleared to 0, program
mode is cancelled.
Rev. 1.0, 03/01, page 75 of 280
Page 100
7.2.2 Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a
read-only register, and should not be written to.
Bit Bit Name Initial Value R/W Description
7 FLER 0 R Flash Memory Error
Indicates that an error has occurred during an
operation on flash memory (programming or erasing).
When FLER is set to 1, flash memory goes to the
error-protection state.
See 7.5.3, Error Protection, for details.
6
—
5
—
4
—
3
—
2
—
1
—
0
—
0
0
0
0
0
0
0
—
—
—
—
—
—
—
Reserved
These bits are always read as 0 and cannot be
modified.
7.2.3 Erase Block Register 1 (EBR1)
EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit
in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to
be automatically cleared to 0.
Bit Bit Name Initial Value R/W Description
7
—
6
—
5
—
4 EB4 0 R/W When this bit is set to 1, 16 kbytes of H'1000 to
3 EB3 0 R/W When this bit is set to 1, 1 kbyte of H'0C00 to H'0FFF
2 EB2 0 R/W When this bit is set to 1, 1 kbyte of H'0800 to H'0BFF
1 EB1 0 R/W When this bit is set to 1, 1 kbyte of H'0400 to H'07FF
0 EB0 0 R/W When this bit is set to 1, 1 kbyte of H'0000 to H'03FF
Rev. 1.0, 03/01, page 76 of 280
0
0
0
—
—
—
Reserved
These bits are always read as 0 and cannot be
modified.
H'4FFF will be erased.
will be erased.
will be erased.
will be erased.
will be erased.
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