Hitachi Single-Chip Microcomputer
H8/3664 Series
H8/3664
HD6433664
H8/3663
HD6433663
H8/3662
HD6433662
H8/3661
ADE-602-202A
HD6433661
H8/3660
HD6433660
H8/3664F-ZTAT™
HD64F3664
Hardware Manual
Rev. 2.0
9/25/00
Hitachi, Ltd.
Cautions
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life support.
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particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
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consider normally foreseeable failure rates or failure modes in semiconductor devices and
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Preface
The H8/3664 Series of single-chip microcomputers has the high-speed H8/300H CPU at its core,
with many necessary peripheral functions on-chip. The H8/300H CPU instruction set is
compatible with the H8/300 CPU.
The H8/3664 Series includes such peripheral functions as four timers, an I2C bus interface, a serial
communication interface, and a 10-bit A/D converter, so that they can be used as an embedded
microcomputer for a sophisticated control system.
This manual describes the hardware of the H8/3664 Series. For details on the H8/3664 Series
instruction set, refer to the H8/300H Series Programming Manual.
Notes:
When using an on-chip emulator (E10T) for H8/3664 program development and debugging, the
following restrictions must be noted.
1. The NMI pin is reserved for the E10T, and cannot be used.
2. Pins P85, P86, and P87 cannot be used. (In order to use these pins, additional hardware must
be provided on the user board.)
3. Area H'7000 to H'7FFF is used by the E10T, and is not available to the user.
4. Area H'F780 to H'FB7F must on no account be accessed.
5. When the E10T is used, address breaks can be set as available to the user, or for use by the
E10T. If address breaks are set as being used by the E10T, the address break control registers
must not be accessed.
6. When the E10T is used, NMI is an input/output pin (open-drain in output mode), P85 and P87
are input pins, and P86 is an output pin.
Main Revisions and Additions in this Edition
Page Item Description
4 Figure 1.1 Block Diagram TEST pin is amended to TEST pin
43 2.9.2 Notes on Bit Manipulation Example 1 description added
54 3.4.2 Interrupt Edge Select Register 2 (IEGR2) Bit 5 description amended
79 Figure 5.9 Pin Connection when not Using
Subclock
88 Table 6.3 Transition Mode after the SLEEP
Instruction Execution and Interrupt Handling
102 Figure 7.4 User Program Mode Figure amended
122 7.9 Flash Memory and Power-Down States
Table 7.10 Flash Memory Operating States
179 Figure 11.2 Increment Timing with Internal Clock Figure amended
281 14.5.1 Data Transfer Format 1st line, reference figure No.
322 Figure 15.5 I2C Bus Timing R/W is amended to R/W
322 to
324
324 to
326
15.3.2 Master Transmit Operation
Figure 15.6 Example of Master Transmit Mode
Operation Timing (MLS = WAIT = 0)
15.3.3 Master Receive Operation
Figure 15.7 Example of Master Receive Mode
Operation Timing (1) (NLS = ACKB = 0, WAIT = 1)
Figure amended
*1 description changed
Description amended
amended
Description changed
Figure amended
Description changed
Figure amended
Figure 15.7 Example of Master Receive Mode
Operation Timing (2) (NLS = ACKB = 0, WAIT = 1)
326 15.3.4 Slave Receive Operation R/W is amended to R/W
327 Figure 15.8 Example of Slave Receive Mode
Operation Timing (1) (MLS = ACKB = 0)
328 15.3.5 Slave Transmit Operation Description amended
329 Figure 15.10 Example of Slave Transmit Mode
Operation Timing (MLS = 0)
332 Figure 15.13 Flowchart for Master Transmit Mode
(Example)
333 Figure 15.14 Flowchart for Master Receive Mode
(Example)
R/W is amended to R/W
R/W is amended to R/W
Flowchart changed
Flowchart changed
Page Item Description
339,
340
15.4 Usage Notes
• Notes on Start Condition Issuance for
Description added
Retransmission
Figure 15.17 Flowchart and Timing of Start
Condition Instruction Issuance for Retransmission
348 16.2.3 A/D Control Register (ADCR) Bit 7 Note added
367 Table 18.2 DC Characteristics (2) Conditions changed
370 Table 18.4 I2C Bus Interface Timing Symbol in SCL and SDA output fall
time amended
372,
373
Table 18.6 A/D Converter Characteristics Min Value in AVcc amended
Test Condition of Conversion time
(single mode) amended
373 Table 18.7 Watchdog Timer Characteristics Unit amended
376 to
18.3 Electrical Characteristics (Mask ROM Version) Added
388
411 to
A.3 Number of Execution States Added
417
423 B.2 Register Bits Bit name in ABRKSR amended
Contents
Section 1 Overview............................................................................................................ 1
1.1 Features .............................................................................................................................. 1
1.2 Internal Block Diagram......................................................................................................4
1.3 Pin Arrangement ................................................................................................................ 5
1.4 Pin Functions...................................................................................................................... 7
Section 2 CPU...................................................................................................................... 11
2.1 Features .............................................................................................................................. 11
2.2 Address Space and Memory Map ...................................................................................... 12
2.3 Register Configuration ....................................................................................................... 15
2.3.1 General Registers.................................................................................................. 16
2.3.2 Program Counter (PC) .......................................................................................... 17
2.3.3 Condition Code Register (CCR) ........................................................................... 17
2.4 Data Formats ...................................................................................................................... 19
2.4.1 General Register Data Formats ............................................................................. 19
2.4.2 Memory Data Formats .......................................................................................... 21
2.5 Instruction Set .................................................................................................................... 22
2.5.1 Instruction Set Overview ...................................................................................... 22
2.5.2 Basic Instruction Formats...................................................................................... 32
2.6 Addressing Modes and Effective Address Calculation...................................................... 33
2.6.1 Addressing Modes................................................................................................. 33
2.6.2 Effective Address Calculation............................................................................... 35
2.7 Basic Bus Cycle.................................................................................................................. 39
2.7.1 Access to On-Chip Memory (RAM, ROM).......................................................... 39
2.7.2 Access to On-Chip Peripheral Modules................................................................ 40
2.8 CPU States.......................................................................................................................... 41
2.8.1 Overview............................................................................................................... 41
2.9 Application Notes............................................................................................................... 42
2.9.1 Notes on Data Access to Empty Areas.................................................................. 42
2.9.2 Notes on Bit Manipulation.................................................................................... 43
2.9.3 Notes on Use of the EEPMOV Instruction ........................................................... 48
Section 3 Exception Handling........................................................................................ 49
3.1 Overview............................................................................................................................ 49
3.1.1 Exception Handling Types.................................................................................... 49
3.2 Reset................................................................................................................................... 49
3.2.1 Reset Sequence...................................................................................................... 49
3.2.2 Reset by Watchdog Timer..................................................................................... 50
3.2.3 Interrupt Immediately after Reset ......................................................................... 50
i
3.3 Interrupts ............................................................................................................................ 51
3.3.1 Interrupt and Vector Address................................................................................ 51
3.4 Interrupt Control Registers.................................................................................................53
3.4.1 Interrupt Edge Select Register 1 (IEGR1) ............................................................ 53
3.4.2 Interrupt Edge Select Register 2 (IEGR2) ............................................................ 54
3.4.3 Interrupt Enable Register 1 (IENR1) .................................................................... 55
3.4.4 Interrupt Flag Register 1 (IRR1)........................................................................... 56
3.4.5 Wakeup Interrupt Flag Register (IWPR) .............................................................. 57
3.5 Interrupt Sources ................................................................................................................ 58
3.5.1 External Interrupts................................................................................................. 58
3.5.2 Internal Interrupts.................................................................................................. 58
3.5.3 Interrupt Operations.............................................................................................. 59
3.5.4 Interrupt Response Time....................................................................................... 62
3.6 Trap Instruction.................................................................................................................. 62
3.7 Application Notes............................................................................................................... 62
3.7.1 Notes on Stack Area Use ...................................................................................... 62
3.7.2 Notes on Rewriting Port Mode Registers.............................................................. 63
Section 4 Address Break.................................................................................................. 67
4.1 Overview............................................................................................................................ 67
4.1.1 Block Diagram...................................................................................................... 67
4.1.2 Register Configuration.......................................................................................... 68
4.2 Register Descriptions.......................................................................................................... 68
4.2.1 Address Break Control Register (ABRKCR)........................................................ 68
4.2.2 Address Break Status Register (ABRKSR) .......................................................... 70
4.2.3 Break Address Registers (BARH, BARL)............................................................ 71
4.2.4 Break Data Registers (BDRH, BDRL) ................................................................. 72
4.3 Operation............................................................................................................................ 72
Section 5 Clock Pulse Generators.................................................................................. 75
5.1 Overview............................................................................................................................ 75
5.1.1 Block Diagram...................................................................................................... 75
5.1.2 System Clock and Subclock.................................................................................. 75
5.2 System Clock Generator..................................................................................................... 76
5.3 Subclock Generator............................................................................................................ 78
5.4 Prescalers............................................................................................................................ 79
5.5 Usage Notes........................................................................................................................ 80
5.5.1 Note on Oscillators................................................................................................ 80
5.5.2 Notes on Board Design ......................................................................................... 80
Section 6 Power-down Modes........................................................................................ 81
6.1 Overview............................................................................................................................ 81
6.1.1 Register Configuration.......................................................................................... 81
ii
6.2 Register Descriptions.......................................................................................................... 82
6.2.1 System Control Register 1 (SYSCR1).................................................................. 82
6.2.2 System Control Register 2 (SYSCR2).................................................................. 83
6.2.3 Module Standby Control Register 1 (MSTCR1) .................................................. 85
6.3 Mode Transition Conditions............................................................................................... 87
6.4 Sleep Mode......................................................................................................................... 90
6.4.1 Transition to the Sleep Mode................................................................................ 90
6.4.2 Clearing the Sleep Mode....................................................................................... 90
6.5 Standby Mode .................................................................................................................... 90
6.5.1 Transition to the Standby Mode............................................................................ 90
6.5.2 Clearing the Standby Mode................................................................................... 91
6.5.3 Oscillator Settling Time after the Standby Mode is Cleared ................................ 91
6.6 Subsleep Mode ................................................................................................................... 92
6.6.1 Transition to the Subsleep Mode .......................................................................... 92
6.6.2 Clearing the Subsleep Mode ................................................................................. 92
6.7 Subactive Mode.................................................................................................................. 93
6.7.1 Transition to the Subactive Mode ......................................................................... 93
6.7.2 Clearing the Subactive Mode................................................................................ 93
6.8 Active Mode....................................................................................................................... 94
6.8.1 Transition to the Active Mode .............................................................................. 94
6.8.2 Transition from the Active Mode to Other Modes................................................ 94
6.8.3 Operating Frequency in the Active Mode............................................................. 94
6.9 Direct Transition ................................................................................................................ 95
6.9.1 Direct Transition Time.......................................................................................... 95
6.10 Module Standby Mode ....................................................................................................... 96
Section 7 ROM.................................................................................................................... 97
7.1 Features .............................................................................................................................. 97
7.2 Overview............................................................................................................................ 98
7.2.1 Block Diagram...................................................................................................... 98
7.2.2 On-board Programming Mode.............................................................................. 99
7.2.3 Block Configuration.............................................................................................. 103
7.2.4 Pin Configuration.................................................................................................. 103
7.2.5 Register Configuration.......................................................................................... 104
7.3 Register Descriptions.......................................................................................................... 104
7.3.1 Flash Memory Control Register 1 (FLMCR1)...................................................... 104
7.3.2 Flash Memory Control Register 2 (FLMCR2)...................................................... 106
7.3.3 Erase Block Register 1 (EBR1) ............................................................................ 107
7.3.4 Flash Memory Power Control Register (FLPWCR)............................................. 108
7.3.5 Flash Memory Enable Register (FENR)............................................................... 108
7.4 Boot Mode.......................................................................................................................... 109
7.4.1 Automatic SCI Bit Rate Adjustment..................................................................... 111
7.4.2 Programming Control Program Area.................................................................... 111
iii
7.4.3 Notes on Use of Boot Mode.................................................................................. 112
7.5 User Program Mode ........................................................................................................... 112
7.6 Programming/Erasing Flash Memory................................................................................ 113
7.6.1 Program/Program-Verify ...................................................................................... 114
7.6.2 Erase/Erase-Verify................................................................................................ 117
7.6.3 Interrupts during Flash Memory Programming/Erasing....................................... 117
7.7 Protection............................................................................................................................ 119
7.7.1 Hardware Protection.............................................................................................. 119
7.7.2 Software Protection............................................................................................... 120
7.7.3 Error Protection..................................................................................................... 120
7.8 Interrupt Handling when Programming/Erasing Flash Memory........................................ 121
7.9 Flash Memory and Power-Down States............................................................................. 122
7.10 Flash Memory Programmer Mode ..................................................................................... 122
7.10.1 Socket Adapter Pin Correspondence Diagram...................................................... 123
7.10.2 Programmer Mode Operation................................................................................ 125
7.10.3 Memory Read Mode.............................................................................................. 126
7.10.4 Auto-Program Mode ............................................................................................. 129
7.10.5 Auto-Erase Mode.................................................................................................. 131
7.10.6 Status Read Mode.................................................................................................. 133
7.10.7 Status Polling ........................................................................................................ 134
7.10.8 Programmer Mode Transition Time...................................................................... 134
7.10.9 Notes on Memory Programming........................................................................... 135
Section 8 RAM.................................................................................................................... 137
8.1 Overview............................................................................................................................ 137
8.1.1 Block Diagram...................................................................................................... 137
Section 9 I/O Ports ............................................................................................................. 139
9.1 Overview............................................................................................................................ 139
9.2 Port 1 .................................................................................................................................. 140
9.2.1 Overview............................................................................................................... 140
9.2.2 Register Configuration and Description................................................................ 140
9.2.3 Port Data Register 1 (PDR1)................................................................................. 141
9.2.4 Port Control Register 1 (PCR1) ............................................................................ 141
9.2.5 Port Pull-Up Control Register 1 (PUCR1)............................................................ 141
9.2.6 Port Mode Register 1 (PMR1) .............................................................................. 142
9.2.7 Pin Functions......................................................................................................... 144
9.2.8 MOS Input Pull-Up............................................................................................... 145
9.3 Port 2 .................................................................................................................................. 146
9.3.1 Overview............................................................................................................... 146
9.3.2 Register Configuration and Description................................................................ 146
9.3.3 Port Data Register 2 (PDR2)................................................................................. 146
9.3.4 Port Control Register 2 (PCR2) ............................................................................ 147
iv
9.3.5 Pin Functions......................................................................................................... 148
9.4 Port 5 .................................................................................................................................. 149
9.4.1 Overview............................................................................................................... 149
9.4.2 Register Configuration and Description................................................................ 149
9.4.3 Port Data Register 5 (PDR5)................................................................................. 150
9.4.4 Port Control Register 5 (PCR5) ............................................................................ 150
9.4.5 Port Pull-Up Control Register 5 (PUCR5)............................................................ 151
9.4.6 Port Mode Register 5 (PMR5) .............................................................................. 151
9.4.7 Pin Functions......................................................................................................... 152
9.4.8 MOS Input Pull-Up............................................................................................... 153
9.5 Port 7 .................................................................................................................................. 154
9.5.1 Overview............................................................................................................... 154
9.5.2 Register Configuration and Description................................................................ 154
9.5.3 Port Data Register 7 (PDR7)................................................................................. 154
9.5.4 Port Control Register 7 (PCR7) ............................................................................ 155
9.5.5 Pin Functions......................................................................................................... 155
9.6 Port 8 .................................................................................................................................. 156
9.6.1 Overview............................................................................................................... 156
9.6.2 Register Configuration and Description................................................................ 156
9.6.3 Port Data Register 8 (PDR8)................................................................................. 157
9.6.4 Port Control Register 8 (PCR8) ............................................................................ 157
9.6.5 Pin Functions......................................................................................................... 158
9.7 Port B.................................................................................................................................. 161
9.7.1 Overview............................................................................................................... 161
9.7.2 Register Configuration and Description................................................................ 161
9.7.3 Port Data Register B (PDRB)................................................................................ 161
9.7.4 Pin Functions......................................................................................................... 162
Section 10 Timer A .............................................................................................................. 163
10.1 Overview............................................................................................................................ 163
10.1.1 Features ................................................................................................................. 163
10.1.2 Block Diagram...................................................................................................... 164
10.1.3 Pin Configuration.................................................................................................. 164
10.1.4 Register Configuration.......................................................................................... 165
10.2 Register Descriptions.......................................................................................................... 165
10.2.1 Timer Mode Register A (TMA)............................................................................ 165
10.2.2 Timer Counter A (TCA)........................................................................................ 166
10.3 Timer Operation ................................................................................................................. 167
10.3.1 Interval Timer Operation ...................................................................................... 167
10.3.2 Clock Time Base Operation.................................................................................. 167
10.3.3 Clock Output ......................................................................................................... 167
10.4 Timer A Operation States................................................................................................... 168
v
Section 11 Timer V .............................................................................................................. 169
11.1 Overview............................................................................................................................ 169
11.1.1 Features ................................................................................................................. 169
11.1.2 Block Diagram...................................................................................................... 170
11.1.3 Pin Configuration.................................................................................................. 171
11.1.4 Register Configuration.......................................................................................... 171
11.2 Register Descriptions.......................................................................................................... 172
11.2.1 Timer Counter V (TCNTV).................................................................................. 172
11.2.2 Time Constant Registers A and B (TCORA, TCORB)........................................ 172
11.2.3 Timer Control Register V0 (TCRV0)................................................................... 173
11.2.4 Timer Control/Status Register V (TCSRV).......................................................... 175
11.2.5 Timer Control Register V1 (TCRV1)................................................................... 177
11.3 Timer Operation ................................................................................................................. 178
11.3.1 Timer V Operation Modes.................................................................................... 182
11.3.2 Interrupt Sources ................................................................................................... 182
11.3.3 Application Examples ........................................................................................... 183
11.3.4 Application Notes.................................................................................................. 185
Section 12 Timer W ............................................................................................................. 191
12.1 Overview............................................................................................................................ 191
12.1.1 Features ................................................................................................................. 191
12.1.2 Block Diagrams..................................................................................................... 193
12.1.3 Input/Output Pins.................................................................................................. 194
12.1.4 Register Configuration.......................................................................................... 195
12.2 Register Description........................................................................................................... 196
12.2.1 Timer Mode Register W (TMRW) ....................................................................... 196
12.2.2 Timer Control Register W (TCRW)...................................................................... 197
12.2.3 Timer Interrupt Enable Register W (TIERW)...................................................... 199
12.2.4 Timer Status Register W (TSRW)........................................................................ 201
12.2.5 Timer I/O Control Register 0 (TIOR0)................................................................. 203
12.2.6 Timer I/O Control Register 1 (TIOR1)................................................................. 204
12.2.7 Timer Counter (TCNT)......................................................................................... 206
12.2.8 General Registers A to D (GRA to GRD)............................................................. 206
12.3 CPU Interface..................................................................................................................... 207
12.3.1 16-Bit Registers..................................................................................................... 207
12.3.2 8-Bit Registers....................................................................................................... 207
12.4 Operation............................................................................................................................ 208
12.4.1 Overview............................................................................................................... 208
12.4.2 Operation Timing.................................................................................................. 223
12.5 Usage Notes........................................................................................................................ 228
vi
Section 13 Watchdog Timer.............................................................................................. 237
13.1 Overview............................................................................................................................ 237
13.1.1 Features ................................................................................................................. 237
13.1.2 Block Diagram...................................................................................................... 237
13.1.3 Register Configuration.......................................................................................... 238
13.2 Register Descriptions.......................................................................................................... 238
13.2.1 Timer Control/Status Register WD (TCSRWD) .................................................. 238
13.2.2 Timer Counter WD (TCWD)................................................................................ 240
13.2.3 Timer Mode Register WD (TMWD).................................................................... 241
13.3 Operation............................................................................................................................ 242
13.3.1 Watchdog Timer Operating Modes....................................................................... 243
Section 14 Serial Communication Interface 3.............................................................. 245
14.1 Overview............................................................................................................................ 245
14.1.1 Features ................................................................................................................. 245
14.1.2 Block Diagram...................................................................................................... 247
14.1.3 Pin Configuration.................................................................................................. 248
14.1.4 Register Configuration.......................................................................................... 248
14.2 Register Descriptions.......................................................................................................... 249
14.2.1 Receive Shift Register (RSR)................................................................................ 249
14.2.2 Receive Data Register (RDR)............................................................................... 249
14.2.3 Transmit Shift Register (TSR).............................................................................. 250
14.2.4 Transmit Data Register (TDR).............................................................................. 250
14.2.5 Serial Mode Register (SMR)................................................................................. 251
14.2.6 Serial Control Register 3 (SCR3).......................................................................... 253
14.2.7 Serial Status Register (SSR).................................................................................. 256
14.2.8 Bit Rate Register (BRR)........................................................................................ 260
14.3 Operation............................................................................................................................ 267
14.3.1 Asynchronous Mode ............................................................................................. 267
14.3.2 Synchronous Mode................................................................................................ 267
14.3.3 Interrupts and Continuous Transmission/Reception............................................. 269
14.4 Operation in Asynchronous Mode...................................................................................... 271
14.4.1 Data Transfer Format............................................................................................ 271
14.4.2 Clock ..................................................................................................................... 273
14.4.3 Data Transfer Operations...................................................................................... 273
14.5 Operation in Synchronous Mode........................................................................................ 280
14.5.1 Data Transfer Format............................................................................................ 281
14.5.2 Clock ..................................................................................................................... 281
14.5.3 Data Transfer Operations...................................................................................... 282
14.6 Multiprocessor Communication Function.......................................................................... 287
14.7 Interrupts ............................................................................................................................ 294
14.8 Usage Notes........................................................................................................................ 295
14.8.1 Relation between Writes to TDR and Bit TDRE.................................................. 295
vii
14.8.2 Operation when a Number of Receive Errors Occur Simultaneously.................. 295
14.8.3 Break Detection and Processing............................................................................ 296
14.8.4 Mark State and Break Detection........................................................................... 296
14.8.5 Receive Error Flags and Transmit Operation (Synchronous Mode Only)............ 296
14.8.6 Receive Data Sampling Timing and Receive Margin in Asynchronous Mode.... 296
14.8.7 Relation between RDR Reads and Bit RDRF....................................................... 298
Section 15 I2C Bus Interface (IIC)................................................................................... 299
15.1 Overview............................................................................................................................ 299
15.1.1 Features ................................................................................................................. 299
15.1.2 Block Diagram...................................................................................................... 300
15.1.3 Pin Configuration.................................................................................................. 301
15.1.4 Register Configuration.......................................................................................... 302
15.2 Register Descriptions.......................................................................................................... 303
15.2.1 I2C Bus Data Register (ICDR).............................................................................. 303
15.2.2 Slave Address Register (SAR).............................................................................. 306
15.2.3 Second Slave Address Register (SARX).............................................................. 307
15.2.4 I2C Bus Mode Register (ICMR)............................................................................ 307
15.2.5 I
15.2.6 I
2
C Bus Control Register (ICCR).......................................................................... 310
2
C Bus Status Register (ICSR)............................................................................. 316
15.2.7 Timer Serial Control Register (TSCR).................................................................. 320
15.3 Operation............................................................................................................................ 321
15.3.1 I2C Bus Data Format.............................................................................................. 321
15.3.2 Master Transmit Operation................................................................................... 322
15.3.3 Master Receive Operation..................................................................................... 324
15.3.4 Slave Receive Operation....................................................................................... 326
15.3.5 Slave Transmit Operation...................................................................................... 328
15.3.6 IRIC Setting Timing and SCL Control ................................................................. 330
15.3.7 Noise Canceler...................................................................................................... 331
15.3.8 Sample Flowcharts................................................................................................ 331
15.4 Usage Notes........................................................................................................................ 336
Section 16 A/D Converter.................................................................................................. 341
16.1 Overview............................................................................................................................ 341
16.1.1 Features ................................................................................................................. 341
16.1.2 Block Diagram...................................................................................................... 342
16.1.3 Input Pins .............................................................................................................. 343
16.1.4 Register Configuration.......................................................................................... 344
16.2 Register Descriptions.......................................................................................................... 344
16.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 344
16.2.2 A/D Control/Status Register (ADCSR)................................................................ 345
16.2.3 A/D Control Register (ADCR).............................................................................. 347
16.3 CPU Interface..................................................................................................................... 348
viii
16.4 Operation............................................................................................................................ 350
16.4.1 Single Mode (SCAN = 0)...................................................................................... 350
16.4.2 Scan Mode (SCAN = 1)........................................................................................ 352
16.4.3 Input Sampling and A/D Conversion Time.......................................................... 354
16.4.4 External Trigger Input Timing.............................................................................. 355
16.5 Interrupts ............................................................................................................................ 356
16.6 Usage Notes........................................................................................................................ 356
Section 17 Power Supply Circuit..................................................................................... 359
17.1 Overview............................................................................................................................ 359
17.2 When Using the Internal Power Supply Step-Down Circuit.............................................. 359
17.3 When Not Using the Internal Power Supply Step-Down Circuit....................................... 360
Section 18 Electrical Characteristics............................................................................... 361
18.1 Absolute Maximum Ratings............................................................................................... 361
18.2 Electrical Characteristics (F-ZTAT™ Version)................................................................. 361
18.2.1 Power Supply Voltage and Operating Ranges...................................................... 361
18.2.2 DC Characteristics ................................................................................................ 363
18.2.3 AC Characteristics ................................................................................................ 368
18.2.4 A/D Converter Characteristics.............................................................................. 372
18.2.5 Watchdog Timer.................................................................................................... 373
18.2.6 Flash Memory Characteristics (Preliminary)........................................................ 374
18.3 Electrical Characteristics (Mask ROM Version)................................................................ 376
18.3.1 Power Supply Voltage and Operating Ranges...................................................... 376
18.3.2 DC Characteristics ................................................................................................ 378
18.3.3 AC Characteristics ................................................................................................ 383
18.3.4 A/D Converter Characteristics.............................................................................. 387
18.3.5 Watchdog Timer.................................................................................................... 388
18.4 Operation Timing ............................................................................................................... 389
18.5 Output Load Circuit............................................................................................................ 392
Appendix A Instruction Set................................................................................................ 393
A.1 Instruction List.................................................................................................................... 393
A.2 Operation Code Map .......................................................................................................... 408
A.3 Number of Execution States............................................................................................... 411
A.4 Combinations of Instructions and Addressing Modes........................................................ 418
Appendix B Internal I/O Registers.................................................................................. 419
B.1 Register Addresses ............................................................................................................. 419
B.2 Register Bits ....................................................................................................................... 422
Appendix C I/O Port Block Diagrams............................................................................ 425
ix
Appendix D Port States in the Different Processing States...................................... 442
Appendix E Model Names................................................................................................. 443
Appendix F Package Dimensions.................................................................................... 444
x
Section 1 Overview
1.1 Features
Table 1.1 Features
Item Description
CPU H8/300H CPU (upward compatibility with H8/300 CPU at object level)
• General-register machine
Sixteen 16-bit registers (also usable as eight 16-bit registers plus
sixteen 8-bit registers or eight 32-bit registers)
• High-speed operation
Max. operation speed: 16 MHz
Add/subtract: 0.125 µs
Multiply/divide: 0.875 µs
• Address space: 64 kbytes
Interrupts
Clock pulse
generators
Power-down
modes
• Instruction features
8/16/32-bit data transfer, arithmetic, and logic instructions
Signed and unsigned multiply instructions
(8 bits × 8 bits, 16 bits × 16 bits)
Signed and unsigned divide instructions
(16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
Bit accumulator function
Bit manipulation instructions with register-indirect specification of bit
positions
• 11 external interrupt sources (NMI, IRQ3 to IRQ0, WKP5 to WKP0)
• 20 internal interrupt sources
• System clock pulse generator: 1 to 16 MHz
• Sub-system clock pulse generator: 32.768 kHz (for watch)
Transition possible between five modes
• Active mode
• Sleep mode
• Standby mode
• Subsleep mode
• Subactive mode
Gear function
• Module standby function
1
Item Description
Memory
Type No. ROM RAM
HD64F3664 (Flash memory version) 32 kbytes 2,048 bytes
HD6433664 (Mask ROM version) 32 kbytes 1,024 bytes
HD6433663 (Mask ROM version) 24 kbytes 1,024 bytes
HD6433662 (Mask ROM version) 16 kbytes 512 bytes
HD6433661 (Mask ROM version) 12 kbytes 512 bytes
HD6433660 (Mask ROM version) 8 kbytes 512 bytes
I/O ports
Timers
• 29 I/O pins, including 8 large current ports (I
= 20 mA, @ VOL = 1.5 V
OL
• 8 input pins (also used for analog input)
• Timer A: 8-bit timer
Count-up timer with selection of eight internal clock signals divided from the
system clock and four clock signals divided from the watch sub-clock
• Timer V: 8-bit timer
Count-up timer with selection of six internal clock signals or event input
from external pin
Compare-match waveform output
Externally triggerable
• Timer W: 16-bit timer
Counts any of four internal clock signals or external events
Maximum of four types of pulses can be input or output and processed
Output compare/input capture (4 output pins)
Output compare/input capture operation can be buffered
PWM mode can be set (maximum of three synchronous outputs)
• Watchdog timer: 8-bit timer
Reset signal generated by counter overflow
Operates independent from system clock by internal oscillation circuit
Serial
communication
interface
• Selectable between asynchronous mode or 8-bit clock synchronous mode
• Incorporate baud rate generator
• Multi-processor communication function (asynchronous)
2
Item Description
2
C bus
I
interface
• Conforms to I
• Selectable between single master mode and slave mode
• Supports two slave addresses
2
C bus interface proposed by Philips Electronics
A/D converter
Package
• 10-bit resolution
• 8-channel analog input pins (selectable between single mode and scan mode)
• Conversion time: 7 µs
• Sample and hold function
Code Body Size Pin Pitch
QFP-64 (FP-64E) 10.0 × 10.0 mm 0.5 mm
QFP-64 (FP-64A) 14.0 × 14.0 mm 0.8 mm
SDIP-42 (DP-42S) 14.0 × 37.3 mm 1.78 mm
3
1.2 Internal Block Diagram
VCLVSSVCCRES
P10/TMOW
P11
P12
P14/IRQ0
P15/IRQ1
P16/IRQ2
P17/IRQ3/TRGV
P20/SCK3
P21/RXD
P22/TXD
P57/SCL
P56/SDA
P55/WKP5/ADTRG
P54/WKP4
P53/WKP3
P52/WKP2
P51/WKP1
P50/WKP0
TEST
NMI
X1
Subclock
generator
Port 1
Port 2Port 5
X2
OSC1
OSC2
System
clock
generator
CPU
H8/300H
Data bus (lower)
ROM
Timer W
Timer A
Timer V
A/D converter
RAM
2
I
C bus
interface
SCI3
Watchdog
timer
Address bus
Data bus (upper)
Port 7Port 8
P76/TMOV
P75/TMCIV
P74/TMRIV
P87
P86
P85
P84/FTIOD
P83/FTIOC
P82/FTIOB
P81/FTIOA
P80/FTCI
= 1.5 V
OL
= 20 mA @ V
OL
CMOS large current port
I
4
Port B
CC
AV
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
Figure 1.1 Block Diagram
1.3 Pin Arrangement
NC
NC
P14/IRQ0
P15/IRQ1
P16/IRQ2
P17/IRQ3/TRGV
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
PB3/AN3
PB2/AN2
PB1/AN1
PB0/AN0
NC
NC
NCNCP22/TXD
P21/RXD
P20/SCK3
P87
P86
P85
P84/FTIOD
P83/FTIOC
P82/FTIOB
P81/FTIOA
P80/FTCI
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
50
51
52
53
54
55
56
57
H8/3664 Series
Top view
58
59
60
61
62
63
64
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
NMI
NC
NC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
NC
P76/TMOV
P75/TMCIV
P74/TMRIV
P57/SCL
P56/SDA
P12
P11
P10/TMOW
P55/WKP5/ADTRG
P54/WKP4
P53/WKP3
P52/WKP2
NC
NC
NC
Note: Do not connect NC pins.
Figure 1.2 Pin Arrangement (FP-64E, FP-64A)
NC
CC
AV
X2
X1
CL
V
RES
V
TEST
SS
OSC2
OSC1
CC
V
P50/WKP0
P51/WKP1
NC
NC
5
PB3/AN3
1
42
P17/IRQ3/TRGV
PB2/AN2
PB1/AN1
PB0/AN0
AV
CC
X2
X1
V
CL
RES
TEST
V
SS
OSC2
OSC1
V
CC
P50/WKP0
P51/WKP1
P52/WKP2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
H8/3664 Series
Top view
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P16/IRQ2
P15/IRQ1
P14/IRQ0
P22/TXD
P21/RXD
P20/SCK3
P87
P86
P85
P84/FTI0D
P83/FTI0C
P82/FTI0B
P81/FTI0A
P80/FTCI
NMI
P76/TMOV
P53/WKP3
P54/WKP4
P55/WKP5/ADTRG
P10/TMOW
18
19
20
21
25
24
23
22
P75/TMCIV
P74/TMRIV
P57/SCL
P56/SDA
Note: DP-42S has no P11, P12, PB4/AN4, PB5/AN5, PB6/AN6, and PB7/AN7 pins.
Figure 1.3 Pin Arrangement (DP-42S)
6
1.4 Pin Functions
Table 1.2 Pin Functions
Type Symbol
Pin No.
FP-64E
FP-64A DP-42S I/O Name and Functions
Power
source pins
V
CC
12 14 Input Power supply: All VCC pins should
be connected to the user system
V
.
CC
V
SS
9 11 Input Ground: All VSS pins should be
connected to the user system GND
(0 V).
AV
CC
3 5 Input Analog power supply: This is the
power supply pin for the A/D
converter. When the A/D converter
is not used, connect this pin to the
user system V
V
CL
6 8 Input Internal step-down power supply:
CC
.
Connect a capacitor of around
0.1 µF between this pin and the V
SS
pin for stabilization.
Clock pins OSC1 11 13 Input System clock: These pins connect
to a crystal or ceramic oscillator, or
can be used to input an external
clock.
OSC2 10 12 Output
See section 5, Clock Pulse
Generators, for a typical connection
diagram.
X1 5 7 Input Subclock: These pins connect to a
X2 4 6 Output
System
RES 7 9 Input Reset: When this pin is driven low,
control
TEST 8 10 Input Test: This is a test pin, not for use
32.768-kHz crystal oscillator.
See section 5, Clock Pulse
Generators, for a typical connection
diagram.
the chip is reset.
in application systems. It should be
connected to V
SS
.
7
Type Symbol
Pin No.
FP-64E
FP-64A DP-42S I/O Name and Functions
Interrupt
pins
NMI 35 27 Input Non-maskable interrupt request
input pin
IRQ0 to
IRQ3
51 to 54 39 to 42 Input IRQ interrupt request 0 to 3:
These are input pins for edgesensitive external interrupts, with a
selection of rising or falling edge.
WKP0 to
WKP5
13, 14,
19 to 22
15 to 20 Input WKP interrupt request 0 to 5:
These are input pins for edgesensitive external interrupts, with a
selection of rising or falling edge.
Timer A TMOW 23 21 Output Clock output: This is an output pin
for waveforms generated by the
timer A output circuit.
Timer V TMOV 30 26 Output Timer V output: This is an output
pin for waveforms generated by the
timer V output compare function.
TMCIV 29 25 Input Timer V event input: This is an
event input pin for input to the timer
V counter.
TMRIV 28 24 Input Timer V counter reset: This is a
counter reset input pin for timer V.
TRGV 54 42 Input Timer V counter trigger input:
This is a trigger input pin for the
timer V counter.
Timer W FTCI 36 28 Input Timer W clock input: This is an
external clock input pin for input to
the timer X counter.
I2C bus
inerface
FTIOA to
FTIOD
SDA 26 22 I/O I2C data I/O: Can directly drive a
37 to 40 29 to 32 I/O Timer W output compare A/input
capture/PWM output pin
bus by NMOS open-drain output.
SCL 27 23 I/O I2C clock I/O: Can directly drive a
bus by NMOS open-drain output.
8
Type Symbol
Pin No.
FP-64E
FP-64A DP-42S I/O Name and Functions
Serial communication
interface
(SCI)
TXD 46 38 Output SCI3 transmit data output: This is
the data output pin.
RXD 45 37 Input SCI3 receive data input: This is
the data input pin.
SCK3 44 36 Output SCI3 clock I/O: This is the clock
I/O pin.
A/D
converter
AN7 to AN0 55 to 62 1 to 4 Input Analog input channels 7 to 0:
These are analog data input
channels to the A/D converter.
ADTRG 22 20 Input A/D converter trigger input: This
is the external trigger input pin to
the A/D converter.
I/O ports PB7 to PB0 55 to 62 1 to 4 Input Port B: This is an 8-bit input port.
P17 to P14,
P12 to P10
51 to 54,
23 to 25
39 to 42,21I/O Port 1: This is a 7-bit I/O port.
P22 to P20 44 to 46 36 to 38 I/O Port 2: This is a 3-bit I/O port.
P57 to P50 13, 14,
19 to 22,
15 to 20,
22, 23
I/O Port 5: This is an 8-bit I/O port.
26, 27
P76 to P74 28 to 30 24 to 26 I/O Port 7: This is a 3-bit I/O port.
P87 to P80 36 to 43 28 to 35 I/O Port 8: This is an 8-bit I/O port.
Other NC Non-connected pins: These pins
must be left unconnected.
9
10
Section 2 CPU
2.1 Features
The H8/3664 Series has an H8/300H CPU with an internal 32-bit architecture that is upwardcompatible with the H8/300 CPU, and supports only normal mode, which has a 64-kbyte address
space.
The H8/300H CPU has the following features.
• Upward compatibility with H8/300 CPU
Can execute H8/300 Series object programs
Additional eight 16-bit extended registers
32-bit transfer and arithmetic and logic instructions are added
Signed multiply and divide instructions are added
• General registers
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers and eight 16-bit
registers or eight 32-bit registers)
• Sixty-two basic instructions
8/16/32-bit data transfer and arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
• Eight addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, or @aa:24]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8, PC) or @(d:16, PC)]
Memory indirect [@@aa:8]
• 64-kbyte address space
• High-speed operation
All frequently-used instructions execute in two to four states
Maximum clock frequency: 16 MHz
8/16/32-bit register-register add/subtract: 2 states
8 × 8-bit register-register multiply: 14 states
16 ÷ 8-bit register-register divide: 14 states
11
16 × 16-bit register-register multiply: 22 states
32 ÷ 16-bit register-register divide: 22 states
• Low-power mode
Transition to low-power state by SLEEP instruction
2.2 Address Space and Memory Map
The address space of the H8/3664 Series CPU is 64 kbytes, which includes the program area and
the data area.
Figures 2.1 and 2.2 show the memory map.
12
H'0000
H'0033
H'0034
HD64F3664
(Flash memory version)
Interrupt vector
On-chip ROM
(32 kbytes)
H'0000
H'0033
H'0034
H'1FFF
HD6433660
(Mask ROM version)
Interrupt vector
On-chip ROM
(8 kbytes)
H'0000
H'0033
H'0034
H'2FFF
HD6433661
(Mask ROM version)
Interrupt vector
On-chip ROM
(12 kbytes)
H'7FFF
H'F780
H'FB7F
H'FB80
H'FF7F
H'FF80
H'FFFF
Not used
(1-kbyte work area
for flash memory
programming)
On-chip RAM
(2 kbytes)
(1-kbyte user area)
Internal I/O register
H'FD80
H'FF7F
H'FF80
H'FFFF
Not used
On-chip RAM
(512 bytes)
Internal I/O register
Not used
H'FD80
On-chip RAM
(512 bytes)
H'FF7F
H'FF80
Internal I/O register
H'FFFF
Figure 2.1 Memory Map (1)
13
H'0000
H'0033
H'0034
HD6433662
(Mask ROM version)
Interrupt vector
On-chip ROM
(16 kbytes)
H'0000
H'0033
H'0034
HD6433663
(Mask ROM version)
Interrupt vector
On-chip ROM
(24 kbytes)
H'0000
H'0033
H'0034
HD6433664
(Mask ROM version)
Interrupt vector
H'3FFF
Not used
On-chip ROM
(32 kbytes)
H'5FFF
H'7FFF
Not used
Not used
H'FD80
On-chip RAM
(512 bytes)
H'FF7F
H'FF80
Internal I/O register
H'FFFF
14
H'FB80
On-chip RAM
(1 kbyte)
H'FF7F
H'FF80
Internal I/O register
H'FFFF
Figure 2.2 Memory Map (2)
H'FB80
On-chip RAM
(1 kbyte)
H'FF7F
H'FF80
Internal I/O register
H'FFFF
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