Hitachi H8/3062, HD6433062, HD6433060, H8/3062F-ZTAT, HD64F3062 Hardware Manual

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Hitachi Single-Chip Microcomputer

H8/3062 Series

H8/3062

HD6433062

H8/3061

HD6433061

H8/3060

HD6433060

H8/3062F-ZTAT™

ADE-602-136B Rev. 3.0 3/20/00 Hitachi, Ltd.

HD64F3062, HD64F3062R, HD64F3062A

H8/3064F-ZTAT™

HD64F3064

Hardware Manual

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

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7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.

Preface

The H8/3062 Series is a series of high-performance single-chip microcontrollers that integrate system supporting functions together with an H8/300H CPU core.

The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space.

The on-chip supporting functions include ROM, RAM, 16-bit timers, 8-bit timers, a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, a D/A converter, I/O ports, and other facilities. The twochannel SCI supports a smart card interface handling ISO/IEC7816-3 character transmission as an expansion function. Functions have also been added to reduce power consumption in batterypowered applications: individual modules can be placed in standby mode, and the frequency of the system clock supplied to the chip can be divided under program control.

The address space is divided into eight areas. The data bus width and access cycle length can be selected independently for each area, simplifying the connection of different types of memory. Seven MCU operating modes (modes 1 to 7) are provided, offering a choice of initial data bus width and address space size.

With these features, the H8/3062 Series enables easy implementation of compact, highperformance systems.

In addition to its mask ROM versions, the H8/3062 Series has F-ZTAT™* versions with on-chip flash memory that allows programs to be rewritten after the chip is mounted on a board. This version offers flexibility in the development of new products to meet fast-changing market needs.

This manual describes the H8/3062 Series hardware. For details of the instruction set, refer to the H8/300H Series Programming Manual.

Note: * F-ZTAT™ is a trademark of Hitachi, Ltd.

List of Items Revised or Added for This Version

Page Item Description

All — H8/3064F-ZTAT and

H8/3062F-ZTAT A-Mask Version descriptions added

Product code descriptions

amended 2 Table 1.1 Features CPU Description amended 6 Figure 1.1 Block Diagram Notes amended 7 Table 1.2 Comparison of H8/3062 Series Pin

Arrangements

10 Figure 1.4 Pin Arrangement of H8/3064F-ZTAT and

H8/3062F-ZTAT A-Mask Version(FP-100B or TFP100B Package, Top View)

11 Figure 1.5 Pin Arrangement of H8/3064F-ZTAT and

H8/3062F-ZTAT A-Mask Version(FP-100A Package, Top View)

12 to 15

19 Table 1.4 Pin Assignments in Each Mode Notes amended 20 1.4.1 Pin Arrangement Description added 22 Table 1.6 Differences between H8/3062F-ZTAT,

22 1.5 Notes on H8/3064F-ZTAT and H8/3062F-ZTAT

1.3.2 Pin Functions Table 1.3 Pin Functions

H8/3062F-ZTAT R-Mask Version, and On-Chip Mask ROM Versions

A-Mask Version

Added

Description added and

revised

Description added

Added

22 1.5.1 Pin Arrangement Description revised 24, 25 1.5.3 VCL Pin Description added 24 Figure 1.6 H8/3062F-ZTAT A-Mask Version and

H8/3064F-ZTAT

25 Figure 1.7 Difference between 5 V and 3 V Operation

Models 26 1.6 Setting Oscillation Settling Wait Time Added 26 1.7 Caution on Crystal Resonator Connection Description added 27, 28 2.1.1 Features Description added 37 2.6.1 Instruction Set Overview Total number of instructions

Description amended

Description added

amended

Page Item Description

44, 45 Table 2.7 Bit Manipulation Instructions Function descriptions added 49, 50 2.6.5 Notes on Use of Bit Manipulation Instructions Description added 54 Table 2.13 Effective Address Calculation No. 1 Addressing Mode and

Instruction Format amended 65 Table 3.1 Operating Mode Selection Table amended 66 3.1.1 Operating Mode Selection Description added 70 3.4.5 Mode 5 Description added 72 3.6.1 Comparison of H8/3062 Series Memory Maps Added 80 Figure 3.4 H8/3064F-ZTAT Memory Map in Each

Added

Operating Mode

80, 81 Figure 3.4 H8/3064F-ZTAT Memory Map in Each

Addresses revised

Operating Mode

132 6.2.5 Bus Control Register(BCR) Bit 1

Note added 136,

Figure 6.3 Memory Map in 16-Mbyte Mode Description added

137 153 Figure 6.17 Example of Wait State Insertion Timing Amended 205 to

Table 7.21 Port A Pin Functions (Modes 1 to 7) Description added

207 212,

Table 7.23 Port B Pin Functions (Modes 1 to 5) Description added

213 214,

Table 7.24 Port B Pin Functions (Modes 6 and 7) Description amended

215 217 to

Section 8 16-Bit Timer Register names amended

279 242 8.2.11 Timer Output Level Setting Register C (TOLR) Description added 281 to

Section 9 8-Bit Timers Register names amended

318 285 Table 9.2 8-Bit Timer Registers Initial value amended

288 9.2.3 Time Constant Registers B (TCORB) Note added 290,

9.2.4 Timer Control Register (8TCR) Descriptions of bits 4 to 0

291 292 to

9.2.5 Timer control/status register Description added and

296 298 Figures 9.5 and 9.7 8TCNT Access Operations Amended

(8TCSR2)

amended

Page Item Description

302 to 306

9.4.4 Timing of Status Flag Setting

9.4.5 Operation with Cascaded Connection

Description amended

9.4.6 Input Capture Setting 307 9.5.1 Interrupt Sources Description amended 308 9.6 8-Bit Timer Application Example Amended 315 9.7.7 Contention between 8TCNT Byte Write and

Description amended Increment in 16-Bit Count Mode (Cascaded Connection)

Figure 9.24 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode

379 Table 12.3 Examples of Bit Rates and BRR Settings in

25 MHz added Asynchronous Mode

380 Table 12.4 Examples of Bit Rates and BRR Settings in

25 MHz added Synchronous Mode

382 Table 12.5 Maximum Bit Rates for Various

25 MHz added Frequencies (Asynchronous Mode)

383 Table 12.6 Maximum Bit Rates with External Clock

25 MHz added Input (Asynchronous Mode)

384 Table 12.7 Maximum Bit Rates with External Clock

25 MHz added Input (Synchronous Mode)

391 Figure 12.5 Sample Flowchart for Transmitting Serial

Description added Data

417 13.1 Overview Description amended 430 Table 13.5 Bit Rates (bits/s) for Various BRR Settings

(When n=0)

431 Table 13.6 BRR Settings for Typical Bit Rates

25 MHz added

Note amended

25 MHz added (bits/s)(When n=0)

Table 13.7 Maximum Bit Rates for Various

20 MHz and 25 MHz added Frequencies (Smart Card Interface Mode)

438 Figure 13.10 Procedure for Stopping and Restarting

Amended the Clock

441 13.4 Usage Notes Description added 443 14.1 Overview Description added

14.1.1 Features High-speed conversion

471 Table 16.1 H8/3062 Series On-Chip RAM

Specifications

25 MHz added

Added

Page Item Description

486 Table 17.6 On-Board Programming Mode Setting Note amended 509 Table 17.10 H8/3062F-ZTAT and H8/3062F-ZTAT R-

Added

Mask Version Socket Adapter Product Codes

513 to 515

513 17.9 Flash Memory Programming and Erasing

17.9 Flash Memory Programming and Erasing Precautions

9 added

Note added

Precautions

516 Figure 17.19 ROM Block Diagram (H8/3062 Mask

Amended

ROM Version) 517 17.11 Notes on Ordering Mask ROM Version Chips 4 added 518 17.12 Notes when Converting the F-ZTAT Application

Description added

Software to the Mask-ROM Versions 519 to

Section 18 Flash Memory [H8/3064F-ZTAT] Added 567

569 to

Section 19 Flash Memory [H8/3062F-ZTAT] Added 618

620 20.2.1 Connecting a Crystal Resonator

Table 20.1(1) Damping Resistance Value

Description added and revised

Table 20.1(2) External Capacitance Values 621 Table 20.2 Crystal Resonator Parameters 25 MHz added 623 Table 20.3 (1) Clock Timing for On-Chip Flash

Table amended

Memory Versions

Table 20.3 (2) Clock Timing for On-Chip Mask ROM

Table added

Versions 626 Table 20.5 Comparison of H8/3062 Series Operating

Revised

Frequency Ranges 635 21.4.3 Selection of Waiting Time for Exit from

Software Standby Mode

When Using External Clock Amendment and addition of 1 and 2

636 Table 21.3 Clock Frequency and Waiting Time for

25 MHz added

Clock to Settle 638 21.4.6 Cautions on Clearing the software Standby

Mode of F-ZTAT Version 643 Table 22.1 Electrical Characteristics of H8/3062

Addition of (3) Comparison of products in H8/3062 Series

Added

Series Products 650 Table 22.3 DC Characteristics (2) Current dissipation typ value

amended

Page Item Description

653 Table 22.3 DC Characteristics (3) Current dissipation typ value

amended 658 Table 22.6 Control Signal Timing Description added 669 Table 22.12 DC Characteristics (1) Note 4 added 672 Table 22.12 DC Characteristics (2) Note 4 added 676 Table 22.15 Control Signal Timing Description added 688 to

22.3 Electrical Characteristics of H8/3064F-ZTAT Added

709 710 to

731 738 Figure 22.19 Basic Bus Cycle: Three-State Access

22.4 Electrical Characteristics of H8/3062F-ZTAT AMask Version

Added

Amended

with One Wait State

768 Table B.1 Comparison of H8/3062 Series Internal I/O

Table added

779 to

B.2 Address List (H8/3064F-ZTAT) Table added

788 789 to

B.3 Address List (H8/3062F-ZTAT A-Mask Version) Table added

798 799 to

873

B.4 Functions Amendments and additions

Note added 912 Table F.1 H8/3062 Series H8/3064F-ZTAT and

H8/3062F-ZTAT A-mask

version added 919 H.1 Differences between H8/3067 and H8/3062

Series, H8/3048 Series, H8/3007 and H8/3006, and

A/D converter conversion

states added

H8/3002

923 Table H.1 Pin Arrangement of Each Product Note amended

Comparison of H8/3062 Series Product Specifications

There are seven members of the H8/3062 Series: the H8/3062F-ZTAT, H8/3062F-ZTAT R-mask version, H8/3062F-ZTAT A-mask version, and H8/3064F-ZTAT (all with on-chip flash memory), and the H8/3062 mask ROM version, H8/3061 mask ROM version, and H8/3060 mask ROM version.

The specifications of these products are compared below.

H8/3062 Mask ROM Version, H8/3061 Mask ROM Version,

H8/3062F-ZTAT

H8/3062F-ZTAT R-Mask Version

H8/3060 Mask ROM Version H8/3064F-ZTAT

H8/3062F-ZTAT A-Mask Version

Product specifications

Product code

Pin arrangement

RAM size 4 kbytes 4 kbytes H8/3062:

On-chip singlepower-supply flash memory

HD64F3062 HD64F3062R HD6433062

See figures 1.2 and 1.3, Pin Arrangement, in section 1

H8/3062F-ZTAT version with address output functions added

See figures 1.2 and 1.3, Pin Arrangement, in section 1

Mask ROM version

HD6433061 HD6433060

See figures 1.2 and 1.3, Pin Arrangement, in section 1

4 kbytes

On-chip largecapacity singlepower-supply flash memory

Internal step-down circuit

HD64F3064 HD64F3062A

5 V operation model has VCL pin, and requires connection of external capacitor

See figures 1.4 and 1.5, Pin Arrangement, in section 1

8 kbytes 4 kbytes

H8/3062 F-ZTAT high-speed operation version

5 V operation model has VCL pin, and requires connection of external capacitor

See figures 1.4 and 1.5, Pin Arrangement, in section 1

ROM size 128 kbytes 128 kbytes H8/3062:

H8/3061: 4 kbytes

H8/3060: 2 kbytes

256 kbytes 128 kbytes

128 kbytes H8/3061:

96 kbytes H8/3060:

64 kbytes

H8/3062F-ZTAT

H8/3062F-ZTAT R-Mask Version

H8/3062 Mask ROM Version, H8/3061 Mask ROM Version, H8/3060 Mask ROM Version H8/3064F-ZTAT

H8/3062F-ZTAT A-Mask Version

Address output functions

Flash memory

Electrical characteristics (operating frequency)

Compatible with previous H8/300H Series

See section 17, ROM

See table 22.1, Comparison of H8/3062 Series Electrical Characteristics, in section 22

Address update mode 1 or 2 selectable

See 6.3.5, Address Output Method, in section 6

See section 17, ROM

See table 22.1, Comparison of H8/3062 Series Electrical Characteristics, in section 22

Address update mode 1 or 2 selectable

See 6.3.5, Address Output Method, in section 6

Address update mode 1 or 2 selectable

See 6.3.5, Address Output Method, in section 6

— See 18.1.1,

Differences between H8/3062F-ZTAT and H8/3062FZTAT R-Mask Version, in section 18

See table 22.1, Comparison of H8/3062 Series Electrical Characteristics, in section 22

Address update mode 1 or 2 selectable

See 6.3.5, Address Output Method, in section 6

See 19.1.1, Differences between H8/3062F-ZTAT and H8/3062FZTAT R-Mask Version, in section 19

See table 22.1, Comparison of H8/3062 Series Electrical Characteristics, in section 22

1 to 20 MHz 1 to 20 MHz 1 to 20 MHz 2 to 25 MHz 2 to 25 MHz

Registers See table B.1,

Comparison of H8/3062 Series Internal I/O Register Specifications, in appendix B

See appendix B.1, Address List

Usage notes

See 1.4, H8/3062F-ZTAT R-Mask Version Usage Note, in section 1

See table B.1, Comparison of H8/3062 Series Internal I/O Register Specifications, in appendix B

See appendix B.1, Address List

See 1.4, H8/3062F-ZTAT R-Mask Version Usage Note, in section 1

See table B.1, Comparison of H8/3062 Series Internal I/O Register Specifications, in appendix B

See appendix B.1, Address List

See 1.4, H8/3062F-ZTAT R-Mask Version Usage Note, in section 1

See table B.1, Comparison of H8/3062 Series Internal I/O Register Specifications, in appendix B

See appendix B.2, Address List

See 1.5, H8/3064F-ZTAT and H8/3062FZTAT A-Mask Version Usage Note, in section 1

See table B.1, Comparison of H8/3062 Series Internal I/O Register Specifications, in appendix B

See appendix B.3, Address List

See 1.5, H8/3064F-ZTAT and H8/3062FZTAT A-Mask Version Usage Note, in section 1

Contents

Section 1 Overview............................................................................................................ 1

1.1 Overview............................................................................................................................ 1

1.2 Block Diagram.................................................................................................................... 6

1.3 Pin Description................................................................................................................... 7

1.3.1 Pin Arrangement ................................................................................................... 7

1.3.2 Pin Functions......................................................................................................... 12

1.3.3 Pin Assignments in Each Mode............................................................................ 16

1.4 Notes on H8/3062F-ZTAT R-Mask Version ..................................................................... 20

1.4.1 Pin Arrangement ................................................................................................... 20

1.4.2 Product Type Names and Markings...................................................................... 21

1.4.3 Differences between H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version.. 21

1.5 Notes on H8/3064F-ZTAT and H8/3062F-ZTAT A-Mask Version.................................. 22

1.5.1 Pin Arrangement ................................................................................................... 22

1.5.2 Product Type Names and Markings...................................................................... 23

1.5.3 VCL Pin .................................................................................................................. 24

1.5.4 Note on Changeover to Mask ROM Version........................................................ 25

1.6 Setting Oscillation Settling Wait Time .............................................................................. 26

1.7 Caution on Crystal Resonator Connection......................................................................... 26

Section 2 CPU...................................................................................................................... 27

2.1 Overview............................................................................................................................ 27

2.1.1 Features ................................................................................................................. 27

2.1.2 Differences from H8/300 CPU.............................................................................. 28

2.2 CPU Operating Modes ....................................................................................................... 28

2.3 Address Space .................................................................................................................... 29

2.4 Register Configuration ....................................................................................................... 30

2.4.1 Overview............................................................................................................... 30

2.4.2 General Registers.................................................................................................. 31

2.4.3 Control Registers................................................................................................... 32

2.4.4 Initial CPU Register Values.................................................................................. 33

2.5 Data Formats ...................................................................................................................... 34

2.5.1 General Register Data Formats............................................................................. 34

2.5.2 Memory Data Formats.......................................................................................... 35

2.6 Instruction Set .................................................................................................................... 37

2.6.1 Instruction Set Overview ...................................................................................... 37

2.6.2 Instructions and Addressing Modes...................................................................... 38

2.6.3 Tables of Instructions Classified by Function....................................................... 39

2.6.4 Basic Instruction Formats...................................................................................... 48

2.6.5 Notes on Use of Bit Manipulation Instructions .................................................... 49

2.7 Addressing Modes and Effective Address Calculation...................................................... 51

2.7.1 Addressing Modes................................................................................................. 51

2.7.2 Effective Address Calculation............................................................................... 53

2.8 Processing States................................................................................................................ 57

2.8.1 Overview............................................................................................................... 57

2.8.2 Program Execution State....................................................................................... 57

2.8.3 Exception-Handling State ..................................................................................... 58

2.8.4 Exception Handling Operation.............................................................................. 59

2.8.5 Bus-Released State................................................................................................ 60

2.8.6 Reset State............................................................................................................. 60

2.8.7 Power-Down State ................................................................................................ 61

2.9 Basic Operational Timing .................................................................................................. 61

2.9.1 Overview............................................................................................................... 61

2.9.2 On-Chip Memory Access Timing......................................................................... 61

2.9.3 On-Chip Supporting Module Access Timing........................................................ 62

2.9.4 Access to External Address Space........................................................................ 63

Section 3 MCU Operating Modes................................................................................. 65

3.1 Overview............................................................................................................................ 65

3.1.1 Operating Mode Selection .................................................................................... 65

3.1.2 Register Configuration.......................................................................................... 66

3.2 Mode Control Register (MDCR)........................................................................................ 66

3.3 System Control Register (SYSCR) .................................................................................... 67

3.4 Operating Mode Descriptions ............................................................................................ 69

3.4.1 Mode 1 .................................................................................................................. 69

3.4.2 Mode 2 .................................................................................................................. 69

3.4.3 Mode 3 .................................................................................................................. 70

3.4.4 Mode 4 .................................................................................................................. 70

3.4.5 Mode 5 .................................................................................................................. 70

3.4.6 Mode 6 .................................................................................................................. 70

3.4.7 Mode 7 .................................................................................................................. 70

3.5 Pin Functions in Each Operating Mode.............................................................................. 71

3.6 Memory Map in Each Operating Mode.............................................................................. 72

3.6.1 Comparison of H8/3062 Series Memory Maps.................................................... 72

3.6.2 Reserved Areas...................................................................................................... 73

Section 4 Exception Handling........................................................................................ 83

4.1 Overview............................................................................................................................ 83

4.1.1 Exception Handling Types and Priority................................................................ 83

4.1.2 Exception Handling Operation.............................................................................. 83

4.1.3 Exception Vector Table ........................................................................................ 84

4.2 Reset................................................................................................................................... 86

4.2.1 Overview............................................................................................................... 86

4.2.2 Reset Sequence...................................................................................................... 86

4.2.3 Interrupts after Reset............................................................................................. 89

4.3 Interrupts ............................................................................................................................ 90

4.4 Trap Instruction.................................................................................................................. 90

4.5 Stack Status after Exception Handling............................................................................... 91

4.6 Notes on Stack Usage......................................................................................................... 92

Section 5 Interrupt Controller......................................................................................... 95

5.1 Overview............................................................................................................................ 95

5.1.1 Features ................................................................................................................. 95

5.1.2 Block Diagram...................................................................................................... 96

5.1.3 Pin Configuration.................................................................................................. 97

5.1.4 Register Configuration.......................................................................................... 97

5.2 Register Descriptions.......................................................................................................... 97

5.2.1 System Control Register (SYSCR)....................................................................... 97

5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB).............................................. 98

5.2.3 IRQ Status Register (ISR)..................................................................................... 103

5.2.4 IRQ Enable Register (IER) ................................................................................... 104

5.2.5 IRQ Sense Control Register (ISCR)...................................................................... 105

5.3 Interrupt Sources ................................................................................................................ 106

5.3.1 External Interrupts................................................................................................. 106

5.3.2 Internal Interrupts.................................................................................................. 107

5.3.3 Interrupt Exception Handling Vector Table.......................................................... 107

5.4 Interrupt Operation............................................................................................................. 111

5.4.1 Interrupt Handling Process.................................................................................... 111

5.4.2 Interrupt Exception Handling Sequence ............................................................... 116

5.4.3 Interrupt Response Time....................................................................................... 117

5.5 Usage Notes........................................................................................................................ 118

5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction....................... 118

5.5.2 Instructions that Inhibit Interrupts......................................................................... 119

5.5.3 Interrupts during EEPMOV Instruction Execution............................................... 119

Section 6 Bus Controller.................................................................................................. 121

6.1 Overview............................................................................................................................ 121

6.1.1 Features ................................................................................................................. 121

6.1.2 Block Diagram...................................................................................................... 122

6.1.3 Pin Configuration.................................................................................................. 123

6.1.4 Register Configuration.......................................................................................... 124

6.2 Register Descriptions.......................................................................................................... 124

6.2.1 Bus Width Control Register (ABWCR)................................................................ 124

6.2.2 Access State Control Register (ASTCR).............................................................. 125

6.2.3 Wait Control Registers H and L (WCRH, WCRL) .............................................. 126

6.2.4 Bus Release Control Register (BRCR)................................................................. 130

iii

6.2.5 Bus Control Register (BCR) ................................................................................. 131

6.2.6 Chip Select Control Register (CSCR)................................................................... 133

6.2.7 Address Control Register (ADRCR)..................................................................... 134

6.3 Operation............................................................................................................................ 135

6.3.1 Area Division........................................................................................................ 135

6.3.2 Bus Specifications................................................................................................. 138

6.3.3 Memory Interfaces................................................................................................ 139

6.3.4 Chip Select Signals................................................................................................ 139

6.3.5 Address Output Method........................................................................................ 140

6.4 Basic Bus Interface............................................................................................................. 142

6.4.1 Overview............................................................................................................... 142

6.4.2 Data Size and Data Alignment.............................................................................. 142

6.4.3 Valid Strobes......................................................................................................... 143

6.4.4 Memory Areas....................................................................................................... 144

6.4.5 Basic Bus Control Signal Timing.......................................................................... 145

6.4.6 Wait Control.......................................................................................................... 152

6.5 Idle Cycle............................................................................................................................ 154

6.5.1 Operation............................................................................................................... 154

6.5.2 Pin States in Idle Cycle......................................................................................... 156

6.6 Bus Arbiter ......................................................................................................................... 156

6.6.1 Operation............................................................................................................... 157

6.7 Register and Pin Input Timing ........................................................................................... 159

6.7.1 Register Write Timing .......................................................................................... 159

6.7.2 BREQ Pin Input Timing........................................................................................ 160

Section 7 I/O Ports ............................................................................................................. 161

7.1 Overview............................................................................................................................ 161

7.2 Port 1 .................................................................................................................................. 165

7.2.1 Overview............................................................................................................... 165

7.2.2 Register Descriptions............................................................................................ 165

7.3 Port 2 .................................................................................................................................. 168

7.3.1 Overview............................................................................................................... 168

7.3.2 Register Descriptions............................................................................................ 169

7.4 Port 3 .................................................................................................................................. 172

7.4.1 Overview............................................................................................................... 172

7.4.2 Register Descriptions............................................................................................ 172

7.5 Port 4 .................................................................................................................................. 174

7.5.1 Overview............................................................................................................... 174

7.5.2 Register Descriptions............................................................................................ 175

7.6 Port 5 .................................................................................................................................. 177

7.6.1 Overview............................................................................................................... 177

7.6.2 Register Descriptions............................................................................................ 178

7.7 Port 6 .................................................................................................................................. 180

7.7.1 Overview............................................................................................................... 180

7.7.2 Register Descriptions............................................................................................ 181

7.8 Port 7 .................................................................................................................................. 184

7.8.1 Overview............................................................................................................... 184

7.8.2 Register Description.............................................................................................. 185

7.9 Port 8 .................................................................................................................................. 186

7.9.1 Overview............................................................................................................... 186

7.9.2 Register Descriptions............................................................................................ 187

7.10 Port 9 .................................................................................................................................. 191

7.10.1 Overview............................................................................................................... 191

7.10.2 Register Descriptions............................................................................................ 192

7.11 Port A.................................................................................................................................. 196

7.11.1 Overview............................................................................................................... 196

7.11.2 Register Descriptions............................................................................................ 198

7.12 Port B.................................................................................................................................. 208

7.12.1 Overview............................................................................................................... 208

7.12.2 Register Descriptions............................................................................................ 210

Section 8 16-Bit Timer...................................................................................................... 217

8.1 Overview............................................................................................................................ 217

8.1.1 Features ................................................................................................................. 217

8.1.2 Block Diagrams..................................................................................................... 219

8.1.3 Pin Configuration.................................................................................................. 222

8.1.4 Register Configuration.......................................................................................... 223

8.2 Register Descriptions.......................................................................................................... 224

8.2.1 Timer Start Register (TSTR)................................................................................. 224

8.2.2 Timer Synchro Register (TSNC).......................................................................... 225

8.2.3 Timer Mode Register (TMDR)............................................................................. 226

8.2.4 Timer Interrupt Status Register A (TISRA).......................................................... 229

8.2.5 Timer Interrupt Status Register B (TISRB).......................................................... 231

8.2.6 Timer Interrupt Status Register C (TISRC).......................................................... 234

8.2.7 Timer Counters (16TCNT).................................................................................... 236

8.2.8 General Registers (GRA, GRB)............................................................................ 237

8.2.9 Timer Control Registers (16TCR)........................................................................ 238

8.2.10 Timer I/O Control Register (TIOR)...................................................................... 240

8.2.11 Timer Output Level Setting Register C (TOLR) .................................................. 242

8.3 CPU Interface..................................................................................................................... 244

8.3.1 16-Bit Accessible Registers.................................................................................. 244

8.3.2 8-Bit Accessible Registers.................................................................................... 246

8.4 Operation............................................................................................................................ 247

8.4.1 Overview............................................................................................................... 247

8.4.2 Basic Functions ..................................................................................................... 247

8.4.3 Synchronization .................................................................................................... 255

8.4.4 PWM Mode........................................................................................................... 257

8.4.5 Phase Counting Mode........................................................................................... 261

8.4.6 16-Bit Timer Output Timing................................................................................. 263

8.5 Interrupts ............................................................................................................................ 264

8.5.1 Setting of Status Flags........................................................................................... 264

8.5.2 Timing of Clearing of Status Flags....................................................................... 266

8.5.3 Interrupt Sources ................................................................................................... 267

8.6 Usage Notes........................................................................................................................ 268

Section 9 8-Bit Timers...................................................................................................... 281

9.1 Overview............................................................................................................................ 281

9.1.1 Features ................................................................................................................. 281

9.1.2 Block Diagram...................................................................................................... 283

9.1.3 Pin Configuration.................................................................................................. 284

9.1.4 Register Configuration.......................................................................................... 285

9.2 Register Descriptions.......................................................................................................... 286

9.2.1 Timer Counters (8TCNT)...................................................................................... 286

9.2.2 Time Constant Registers A (TCORA).................................................................. 287

9.2.3 Time Constant Registers B (TCORB) .................................................................. 288

9.2.4 Timer Control Register (8TCR)............................................................................ 289

9.2.5 Timer Control/Status Registers (8TCSR) ............................................................. 292

9.3 CPU Interface..................................................................................................................... 297

9.3.1 8-Bit Registers....................................................................................................... 297

9.4 Operation............................................................................................................................ 299

9.4.1 8TCNT Count Timing........................................................................................... 299

9.4.2 Compare Match Timing........................................................................................ 300

9.4.3 Input Capture Signal Timing................................................................................. 301

9.4.4 Timing of Status Flag Setting................................................................................ 302

9.4.5 Operation with Cascaded Connection................................................................... 303

9.4.6 Input Capture Setting............................................................................................ 306

9.5 Interrupt.............................................................................................................................. 307

9.5.1 Interrupt Sources ................................................................................................... 307

9.5.2 A/D Converter Activation..................................................................................... 308

9.6 8-Bit Timer Application Example...................................................................................... 308

9.7 Usage Notes........................................................................................................................ 309

9.7.1 Contention between 8TCNT Write and Clear....................................................... 309

9.7.2 Contention between 8TCNT Write and Increment............................................... 310

9.7.3 Contention between TCOR Write and Compare Match....................................... 311

9.7.4 Contention between TCOR Read and Input Capture............................................ 312

9.7.5 Contention between Counter Clearing by Input Capture and Counter Increment 313

9.7.6 Contention between TCOR Write and Input Capture........................................... 314

9.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode

(Cascaded Connection) ......................................................................................... 315

9.7.8 Contention between Compare Matches A and B.................................................. 316

9.7.9 8TCNT Operation and Internal Clock Source Switchover................................... 316

Section 10 Programmable Timing Pattern Controller (TPC).................................. 319

10.1 Overview............................................................................................................................ 319

10.1.1 Features ................................................................................................................. 319

10.1.2 Block Diagram...................................................................................................... 320

10.1.3 Pin Configuration.................................................................................................. 321

10.1.4 Register Configuration.......................................................................................... 322

10.2 Register Descriptions.......................................................................................................... 323

10.2.1 Port A Data Direction Register (PADDR)............................................................ 323

10.2.2 Port A Data Register (PADR)............................................................................... 323

10.2.3 Port B Data Direction Register (PBDDR) ............................................................ 324

10.2.4 Port B Data Register (PBDR)................................................................................ 324

10.2.5 Next Data Register A (NDRA) ............................................................................. 325

10.2.6 Next Data Register B (NDRB).............................................................................. 327

10.2.7 Next Data Enable Register A (NDERA)............................................................... 329

10.2.8 Next Data Enable Register B (NDERB) ............................................................... 330

10.2.9 TPC Output Control Register (TPCR).................................................................. 331

10.2.10 TPC Output Mode Register (TPMR) .................................................................... 333

10.3 Operation............................................................................................................................ 335

10.3.1 Overview............................................................................................................... 335

10.3.2 Output Timing....................................................................................................... 336

10.3.3 Normal TPC Output.............................................................................................. 337

10.3.4 Non-Overlapping TPC Output.............................................................................. 339

10.3.5 TPC Output Triggering by Input Capture ............................................................. 341

10.4 Usage Notes........................................................................................................................ 342

10.4.1 Operation of TPC Output Pins.............................................................................. 342

10.4.2 Note on Non-Overlapping Output......................................................................... 342

Section 11 Watchdog Timer.............................................................................................. 345

11.1 Overview............................................................................................................................ 345

11.1.1 Features ................................................................................................................. 345

11.1.2 Block Diagram...................................................................................................... 346

11.1.3 Pin Configuration.................................................................................................. 346

11.1.4 Register Configuration.......................................................................................... 347

11.2 Register Descriptions.......................................................................................................... 347

11.2.1 Timer Counter (TCNT)......................................................................................... 347

11.2.2 Timer Control/Status Register (TCSR)................................................................. 348

11.2.3 Reset Control/Status Register (RSTCSR)............................................................. 350

11.2.4 Notes on Register Access...................................................................................... 351

11.3 Operation............................................................................................................................ 353

11.3.1 Watchdog Timer Operation .................................................................................. 353

vii

11.3.2 Interval Timer Operation ...................................................................................... 354

11.3.3 Timing of Setting of Overflow Flag (OVF).......................................................... 354

11.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) ................................... 355

11.4 Interrupts ............................................................................................................................ 356

11.5 Usage Notes........................................................................................................................ 356

Section 12 Serial Communication Interface ................................................................. 357

12.1 Overview............................................................................................................................ 357

12.1.1 Features ................................................................................................................. 357

12.1.2 Block Diagram...................................................................................................... 359

12.1.3 Pin Configuration.................................................................................................. 360

12.1.4 Register Configuration.......................................................................................... 361

12.2 Register Descriptions.......................................................................................................... 362

12.2.1 Receive Shift Register (RSR)................................................................................ 362

12.2.2 Receive Data Register (RDR) ............................................................................... 362

12.2.3 Transmit Shift Register (TSR).............................................................................. 363

12.2.4 Transmit Data Register (TDR).............................................................................. 363

12.2.5 Serial Mode Register (SMR)................................................................................. 364

12.2.6 Serial Control Register (SCR)............................................................................... 367

12.2.7 Serial Status Register (SSR).................................................................................. 371

12.2.8 Bit Rate Register (BRR)........................................................................................ 376

12.3 Operation............................................................................................................................ 384

12.3.1 Overview............................................................................................................... 384

12.3.2 Operation in Asynchronous Mode........................................................................ 387

12.3.3 Multiprocessor Communication............................................................................ 396

12.3.4 Synchronous Operation......................................................................................... 403

12.4 SCI Interrupts ..................................................................................................................... 411

12.5 Usage Notes........................................................................................................................ 412

12.5.1 Notes on Use of SCI.............................................................................................. 412

Section 13 Smart Card Interface ...................................................................................... 417

13.1 Overview............................................................................................................................ 417

13.1.1 Features ................................................................................................................. 417

13.1.2 Block Diagram...................................................................................................... 418

13.1.3 Pin Configuration.................................................................................................. 418

13.1.4 Register Configuration.......................................................................................... 419

13.2 Register Descriptions.......................................................................................................... 420

13.2.1 Smart Card Mode Register (SCMR)..................................................................... 420

13.2.2 Serial Status Register (SSR).................................................................................. 422

13.2.3 Serial Mode Register (SMR)................................................................................. 423

13.2.4 Serial Control Register (SCR)............................................................................... 424

13.3 Operation............................................................................................................................ 425

13.3.1 Overview............................................................................................................... 425

viii

13.3.2 Pin Connections.................................................................................................... 425

13.3.3 Data Format........................................................................................................... 426

13.3.4 Register Settings.................................................................................................... 428

13.3.5 Clock ..................................................................................................................... 430

13.3.6 Transmitting and Receiving Data.......................................................................... 432

13.4 Usage Notes........................................................................................................................ 439

Section 14 A/D Converter.................................................................................................. 443

14.1 Overview............................................................................................................................ 443

14.1.1 Features ................................................................................................................. 443

14.1.2 Block Diagram...................................................................................................... 444

14.1.3 Pin Configuration.................................................................................................. 445

14.1.4 Register Configuration.......................................................................................... 446

14.2 Register Descriptions.......................................................................................................... 446

14.2.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 446

14.2.2 A/D Control/Status Register (ADCSR) ................................................................ 447

14.2.3 A/D Control Register (ADCR).............................................................................. 449

14.3 CPU Interface ..................................................................................................................... 450

14.4 Operation............................................................................................................................ 452

14.4.1 Single Mode (SCAN = 0)...................................................................................... 452

14.4.2 Scan Mode (SCAN = 1)........................................................................................ 454

14.4.3 Input Sampling and A/D Conversion Time .......................................................... 456

14.4.4 External Trigger Input Timing.............................................................................. 457

14.5 Interrupts ............................................................................................................................ 458

14.6 Usage Notes........................................................................................................................ 458

Section 15 D/A Converter.................................................................................................. 463

15.1 Overview............................................................................................................................ 463

15.1.1 Features ................................................................................................................. 463

15.1.2 Block Diagram...................................................................................................... 464

15.1.3 Pin Configuration.................................................................................................. 465

15.1.4 Register Configuration.......................................................................................... 465

15.2 Register Descriptions.......................................................................................................... 466

15.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) .................................................. 466

15.2.2 D/A Control Register (DACR).............................................................................. 466

15.2.3 D/A Standby Control Register (DASTCR)........................................................... 468

15.3 Operation............................................................................................................................ 468

15.4 D/A Output Control............................................................................................................ 470

Section 16 RAM.................................................................................................................... 471

16.1 Overview............................................................................................................................ 471

16.1.1 Block Diagram...................................................................................................... 472

16.1.2 Register Configuration.......................................................................................... 472

16.2 System Control Register (SYSCR) .................................................................................... 473

16.3 Operation............................................................................................................................ 474

Section 17 ROM [H8/3062F-ZTAT, H8/3062F-ZTAT ROM Version,

On-Chip Mask ROM Models]

17.1 Overview............................................................................................................................ 475

17.2 Overview of Flash Memory (H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version)....... 476

17.2.1 Features ................................................................................................................. 476

17.2.2 Block Diagram...................................................................................................... 477

17.2.3 Pin Configuration.................................................................................................. 478

17.2.4 Register Configuration.......................................................................................... 478

17.3 Flash Memory Register Descriptions ................................................................................. 479

17.3.1 Flash Memory Control Register (FLMCR) .......................................................... 479

17.3.2 Erase Block Register (EBR).................................................................................. 482

17.3.3 RAM Control Register (RAMCR)........................................................................ 483

17.3.4 Flash Memory Status Register (FLMSR).............................................................. 485

17.4 On-Board Programming Mode........................................................................................... 486

17.4.1 Boot Mode............................................................................................................. 489

17.4.2 User Program Mode.............................................................................................. 494

17.5 Flash Memory Programming/Erasing ................................................................................ 496

17.5.1 Program Mode....................................................................................................... 497

17.5.2 Program-Verify Mode........................................................................................... 498

..................................................................... 475

17.5.3 Erase Mode............................................................................................................ 500

17.5.4 Erase-Verify Mode................................................................................................ 500

17.6 Flash Memory Protection ................................................................................................... 502

17.6.1 Hardware Protection.............................................................................................. 502

17.6.2 Software Protection............................................................................................... 504

17.6.3 Error Protection..................................................................................................... 504

17.6.4 NMI Input Disabling Conditions .......................................................................... 506

17.7 Flash Memory Emulation in RAM..................................................................................... 507

17.8 Flash Memory PROM Mode.............................................................................................. 509

17.8.1 Socket Adapters and Memory Map ...................................................................... 509

17.8.2 Notes on Use of PROM Mode.............................................................................. 510

17.9 Flash Memory Programming and Erasing Precautions...................................................... 511

17.10 Mask ROM (H8/3062 Mask ROM Version, H8/3061 Mask ROM Version,

H8/3060 Mask ROM Version) Overview.......................................................................... 516

17.10.1 Block Diagram...................................................................................................... 516

17.11 Notes on Ordering Mask ROM Version Chips .................................................................. 517

17.12 Notes when Converting the F-ZTAT Application Software to the Mask-ROM Versions. 518

Section 18 Flash Memory [H8/3064F-ZTAT]............................................................. 519

18.1 Overview............................................................................................................................ 519

18.1.1 Differences from H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version........ 520

18.2 Features .............................................................................................................................. 521

18.2.1 Block Diagram...................................................................................................... 522

18.2.2 Pin Configuration.................................................................................................. 523

18.2.3 Register Configuration.......................................................................................... 523

18.3 Register Descriptions.......................................................................................................... 524

18.3.1 Flash Memory Control Register 1 (FLMCR1)...................................................... 524

18.3.2 Flash Memory Control Register 2 (FLMCR2)...................................................... 527

18.3.3 Erase Block Register 1 (EBR1) ............................................................................ 528

18.3.4 Erase Block Register 2 (EBR2) ............................................................................ 528

18.3.5 RAM Control Register (RAMCR)........................................................................ 529

18.4 Overview of Operation....................................................................................................... 531

18.4.1 Mode Transitions.................................................................................................. 531

18.4.2 On-Board Programming Modes............................................................................ 533

18.4.3 Flash Memory Emulation in RAM........................................................................ 535

18.4.4 Block Configuration.............................................................................................. 536

18.5 On-Board Programming Mode........................................................................................... 537

18.5.1 Boot Mode............................................................................................................. 538

18.5.2 User Program Mode.............................................................................................. 543

18.6 Flash Memory Programming/Erasing ................................................................................ 545

18.6.1 Program Mode....................................................................................................... 547

18.6.2 Program-Verify Mode........................................................................................... 548

18.6.3 Erase Mode............................................................................................................ 552

18.6.4 Erase-Verify Mode................................................................................................ 552

18.7 Flash Memory Protection ................................................................................................... 554

18.7.1 Hardware Protection.............................................................................................. 554

18.7.2 Software Protection............................................................................................... 555

18.7.3 Error Protection..................................................................................................... 555

18.8 Flash Memory Emulation in RAM..................................................................................... 558

18.9 NMI Input Disabling Conditions........................................................................................ 560

18.10 Flash Memory PROM Mode.............................................................................................. 561

18.10.1 Socket Adapters and Memory Map ...................................................................... 561

18.10.2 Notes on Use of PROM Mode .............................................................................. 562

18.11 Flash Memory Programming and Erasing Precautions...................................................... 562

Section 19 Flash Memory [H8/3062F-ZTAT A-Mask Version]............................ 569

19.1 Overview............................................................................................................................ 569

19.1.1 Differences from H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version........ 570

19.2 Features............................................................................................................................... 571

19.2.1 Block Diagram...................................................................................................... 572

19.2.2 Pin Configuration.................................................................................................. 573

19.2.3 Register Configuration.......................................................................................... 573

19.3 Register Descriptions.......................................................................................................... 574

19.3.1 Flash Memory Control Register 1 (FLMCR1)...................................................... 574

19.3.2 Flash Memory Control Register 2 (FLMCR2)...................................................... 577

19.3.3 Erase Block Register (EBR).................................................................................. 578

19.3.4 RAM Control Register (RAMCR)........................................................................ 579

19.4 Overview of Operation....................................................................................................... 581

19.4.1 Mode Transitions.................................................................................................. 581

19.4.2 On-Board Programming Modes............................................................................ 583

19.4.3 Flash Memory Emulation in RAM........................................................................ 585

19.4.4 Block Configuration.............................................................................................. 586

19.5 On-Board Programming Mode........................................................................................... 587

19.5.1 Boot Mode............................................................................................................. 588

19.5.2 User Program Mode.............................................................................................. 593

19.6 Flash Memory Programming/Erasing ................................................................................ 595

19.6.1 Program Mode....................................................................................................... 597

19.6.2 Program-Verify Mode........................................................................................... 598

19.6.3 Erase Mode............................................................................................................ 602

19.6.4 Erase-Verify Mode................................................................................................ 602

19.7 Flash Memory Protection ................................................................................................... 604

19.7.1 Hardware Protection.............................................................................................. 604

19.7.2 Software Protection............................................................................................... 605

19.7.3 Error Protection..................................................................................................... 605

19.8 Flash Memory Emulation in RAM..................................................................................... 608

19.9 NMI Input Disabling Conditions........................................................................................ 609

19.10 Flash Memory PROM Mode.............................................................................................. 610

19.10.1 Socket Adapters and Memory Map....................................................................... 610

19.10.2 Notes on Use of PROM Mode .............................................................................. 611

19.11 Flash Memory Programming and Erasing Precautions...................................................... 612

19.12 Notes when Converting the F-ZTAT Application Software to the Mask-ROM Versions 618

Section 20 Clock Pulse Generator ................................................................................... 619

20.1 Overview............................................................................................................................ 619

20.1.1 Block Diagram...................................................................................................... 619

20.2 Oscillator Circuit................................................................................................................ 620

20.2.1 Connecting a Crystal Resonator............................................................................ 620

20.2.2 External Clock Input ............................................................................................. 622

20.3 Duty Adjustment Circuit .................................................................................................... 624

20.4 Prescalers............................................................................................................................ 624

20.5 Frequency Divider.............................................................................................................. 624

20.5.1 Register Configuration.......................................................................................... 625

20.5.2 Division Control Register (DIVCR) ..................................................................... 625

20.5.3 Usage Notes.......................................................................................................... 626

Section 21 Power-Down State .......................................................................................... 627

21.1 Overview............................................................................................................................ 627

xii

21.2 Register Configuration ....................................................................................................... 629

21.2.1 System Control Register (SYSCR) ....................................................................... 629

21.2.2 Module Standby Control Register H (MSTCRH)................................................. 631

21.2.3 Module Standby Control Register L (MSTCRL).................................................. 632

21.3 Sleep Mode......................................................................................................................... 634

21.3.1 Transition to Sleep Mode...................................................................................... 634

21.3.2 Exit from Sleep Mode ........................................................................................... 634

21.4 Software Standby Mode ..................................................................................................... 634

21.4.1 Transition to Software Standby Mode .................................................................. 634

21.4.2 Exit from Software Standby Mode........................................................................ 635

21.4.3 Selection of Waiting Time for Exit from Software Standby Mode...................... 635

21.4.4 Sample Application of Software Standby Mode................................................... 637

21.4.5 Note....................................................................................................................... 637

21.4.6 Cautions on Clearing the software Standby Mode of F-ZTAT Version............... 638

21.5 Hardware Standby Mode.................................................................................................... 639

21.5.1 Transition to Hardware Standby Mode................................................................. 639

21.5.2 Exit from Hardware Standby Mode...................................................................... 639

21.5.3 Timing for Hardware Standby Mode.................................................................... 639

21.6 Module Standby Function .................................................................................................. 640

21.6.1 Module Standby Timing........................................................................................ 640

21.6.2 Read/Write in Module Standby............................................................................. 640

21.6.3 Usage Notes.......................................................................................................... 640

21.7 System Clock Output Disabling Function.......................................................................... 641

Section 22 Electrical Characteristics............................................................................... 643

22.1 Electrical Characteristics of H8/3062 Mask ROM Version,

H8/3061 Mask ROM Version, and H8/3060 Mask ROM Version.................................... 645

22.1.1 Absolute Maximum Ratings.................................................................................. 645

22.1.2 DC Characteristics................................................................................................ 646

22.1.3 AC Characteristics................................................................................................ 657

22.1.4 A/D Conversion Characteristics............................................................................ 663

22.1.5 D/A Conversion Characteristics............................................................................ 665

22.2 Electrical Characteristics of H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version.... 666

22.2.1 Absolute Maximum Ratings.................................................................................. 666

22.2.2 DC Characteristics................................................................................................ 667

22.2.3 AC Characteristics................................................................................................ 675

22.2.4 A/D Conversion Characteristics............................................................................ 681

22.2.5 D/A Conversion Characteristics............................................................................ 683

22.2.6 Flash Memory Characteristics .............................................................................. 684

22.3 Electrical Characteristics of H8/3064F-ZTAT................................................................... 688

22.3.1 Absolute Maximum Ratings.................................................................................. 688

22.3.2 DC Characteristics................................................................................................ 689

22.3.3 AC Characteristics................................................................................................ 697

xiii

22.3.4 A/D Conversion Characteristics............................................................................ 703

22.3.5 D/A Conversion Characteristics............................................................................ 705

22.3.6 Flash Memory Characteristics .............................................................................. 706

22.4 Electrical Characteristics of H8/3062F-ZTAT A-Mask Version ....................................... 710

22.4.1 Absolute Maximum Ratings.................................................................................. 710

22.4.2 DC Characteristics................................................................................................ 711

22.4.3 AC Characteristics................................................................................................ 719

22.4.4 A/D Conversion Characteristics............................................................................ 725

22.4.5 D/A Conversion Characteristics............................................................................ 727

22.4.6 Flash Memory Characteristics .............................................................................. 728

22.5 Operational Timing ............................................................................................................ 732

22.5.1 Clock Timing........................................................................................................ 732

22.5.2 Control Signal Timing .......................................................................................... 733

22.5.3 Bus Timing............................................................................................................ 735

22.5.4 TPC and I/O Port Timing...................................................................................... 739

22.5.5 Timer Input/Output Timing .................................................................................. 739

22.5.6 SCI Input/Output Timing...................................................................................... 740

Appendix A Instruction Set............................................................................................... 741

A.1 Instruction List.................................................................................................................... 741

A.2 Operation Code Maps......................................................................................................... 756

A.3 Number of States Required for Execution.......................................................................... 759

Appendix B Internal I/O Registers................................................................................. 768

B.1 Address List (H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version,

H8/3062 Mask ROM Version, H8/3061 Mask ROM Version,

H8/3060 Mask ROM Version)........................................................................................... 769

B.2 Address List (H8/3064F-ZTAT) ........................................................................................ 779

B.3 Address List (H8/3062F-ZTAT A-Mask Version) ............................................................ 789

B.4 Functions............................................................................................................................ 799

Appendix C I/O Port Block Diagrams........................................................................... 874

C.1 Port 1 Block Diagram......................................................................................................... 874

C.2 Port 2 Block Diagram......................................................................................................... 875

C.3 Port 3 Block Diagram......................................................................................................... 876

C.4 Port 4 Block Diagram......................................................................................................... 877

C.5 Port 5 Block Diagram......................................................................................................... 878

C.6 Port 6 Block Diagrams ....................................................................................................... 879

C.7 Port 7 Block Diagrams ....................................................................................................... 884

C.8 Port 8 Block Diagrams ....................................................................................................... 885

C.9 Port 9 Block Diagrams ....................................................................................................... 889

C.10 Port A Block Diagrams...................................................................................................... 895

C.11 Port B Block Diagrams ...................................................................................................... 898

xiv

Appendix D Pin States........................................................................................................ 904

D.1 Port States in Each Mode ................................................................................................... 904

D.2 Pin States at Reset.............................................................................................................. 908

Appendix E Timing of Transition to and Recovery from Hardware

Standby Mode

............................................................................................... 911

Appendix F Product Code Lineup.................................................................................. 912

Appendix G Package Dimensions................................................................................... 914

Appendix H Comparison of H8/300H Series Product Specifications.................. 917

H.1 Differences between H8/3067 and H8/3062 Series, H8/3048 Series,

H8/3007 and H8/3006, and H8/3002.................................................................................. 917

H.2 Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B)......... 920

Section 1 Overview

1.1 Overview

The H8/3062 Series is a series of microcontrollers (MCUs) that integrate system supporting functions together with an H8/300H CPU core having an original Hitachi architecture.

The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU, enabling easy porting of software from the H8/300 Series.

The on-chip system supporting functions include ROM, RAM, a 16-bit timer, an 8-bit timer, a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, a D/A converter, I/O ports, and other facilities.

The seven members of the H8/3062 Series are the H8/3062F-ZTAT, H8/3062F-ZTAT R-mask version, H8/3062 (mask ROM version), H8/3061 (mask ROM version), H8/3060 (mask ROM version), H8/3064F-ZTAT, and H8/3062F-ZTAT A-mask version.

Seven MCU operating modes offer a choice of bus width and address space size. The modes (modes 1 to 7) include two single-chip modes and five expanded modes.

In addition to its mask ROM versions, the H8/3062 Series has F-ZTAT™* versions with on-chip flash memory that allows programs to be freely rewritten by the user. This version enables users to respond quickly and flexibly to changing application specifications, growing production volumes, and other conditions.

Table 1.1 summarizes the features of the H8/3062 Series.

Note: * F-ZTATTM (Flexible ZTAT) is a trademark of Hitachi, Ltd.

Table 1.1 Features

Feature Description

CPU Upward-compatible with the H8/300 CPU at the object-code level

General-register machine

• Sixteen 16-bit general registers (also usable as sixteen 8-bit registers plus eight 16-bit registers, or as eight 32-bit registers)

High-speed operation

H8/3062F-ZTZT

Maximum clock rate

20 MHz 100 ns 700 ns

Add /subtract

Multiply /divide

H8/3062F-ZTAT R-Mask version H8/3062 (mask ROM version) H8/3061 (mask ROM version) H8/3060 (mask ROM version)

H8/3064F-ZTAT

25 MHz 80 ns 560 ns

H8/3062F-ZTAT A-Mask version 16-Mbyte address space

Instruction features

• 8/16/32-bit data transfer, arithmetic, and logic instructions

• Signed and unsigned multiply instructions (8 bits x 8 bits, 16 bits x 16 bits)

• Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)

• Bit accumulator function

Bit manipulation instructions with register-indirect specification of bit positions

Memory ROM RAM

H8/3062F-ZTAT

128 kbytes 4 kbytes H8/3062F-ZTAT R-mask version H8/3062F-ZTAT A-mask version H8/3062 (mask ROM version)

H8/3061 (mask ROM version) 96 kbytes 4 kbytes H8/3060 (mask ROM version) 64 kbytes 2 kbytes H8/3064F-ZTAT 256 kbytes 8 kbytes

Interrupt controller

• Seven external interrupt pins: NMI, IRQ

• 27 internal interrupts

to IRQ

• Three selectable interrupt priority levels

Feature Description

Bus controller

16-bit timer, 3 channels

• Address space can be partitioned into eight areas, with independent bus specifications in each area

• Chip select output available for areas 0 to 7

• 8-bit access or 16-bit access selectable for each area

• Two-state or three-state access selectable for each area

• Selection of two wait modes

• Number of program wait states selectable for each area

• Bus arbitration function

• Two address update modes (not available in the H8/3062F-ZTAT)

• Three 16-bit timer channels, capable of processing up to six pulse outputs or

six pulse inputs

• 16-bit timer counter (channels 0 to 2)

• Two multiplexed output compare/input capture pins (channels 0 to 2)

• Operation can be synchronized (channels 0 to 2)

• PWM mode available (channels 0 to 2)

8-bit timer, 4 channels

Programmable timing pattern controller (TPC)

Watchdog timer (WDT), 1 channel

Serial communication interface (SCI), 2 channels

• Phase counting mode available (channel 2)

• 8-bit up-counter (external event count capability)

• Two time constant registers

• Two channels can be connected

• Maximum 16-bit pulse output, using 16-bit timer as time base

• Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups)

• Non-overlap mode available

• Internal reset signal can be generated by overflow

• Reset signal can be output externally (not available in on-chip flash memory

versions)

• Usable as an interval timer

• Selection of asynchronous or synchronous mode

• Full duplex: can transmit and receive simultaneously

• On-chip baud-rate generator

• Smart card interface functions added

Feature Description

A/D converter

• Resolution: 10 bits

• Eight channels, with selection of single or scan mode

• Variable analog conversion voltage range

• Sample-and-hold function

• A/D conversion can be started by an external trigger or 8-bit timer compare-

match

D/A converter

• Resolution: 8 bits

• Two channels

• D/A outputs can be sustained in software standby mode

I/O ports

• 70 input/output pins

• 9 input-only pins

Operating modes Seven MCU operating modes

Address

Mode

Space

Mode 1 1 Mbyte A

Address Pins

to A

Initial Bus Width

8 bits 16 bits

Max. Bus Width

Power-down state

Other features

Mode 2 1 Mbyte A19 to A Mode 3 16 Mbytes A23 to A Mode 4 16 Mbytes A23 to A Mode 5 16 Mbytes A23 to A

16 bits 16 bits 8 bits 16 bits 16 bits 16 bits

8 bits 16 bits Mode 6 64 kbytes — — — Mode 7 1 Mbyte — — —

• On-chip ROM is disabled in modes 1 to 4

• In the versions with on-chip flash memory, an on-board programming mode is

supported that allows flash memory to be programmed in modes 5 and 7.

• Sleep mode

• Software standby mode

• Hardware standby mode

• Module standby function

• Programmable system clock frequency division

• On-chip clock pulse generator

Feature Description

Product lineup

Package

Product Type Model

H8/3062F-ZTAT 5 V operation HD64F3062F 100-pin QFP (FP-100B)

HD64F3062TE 100-pin TQFP (TFP-100B) HD64F3062FP 100-pin QFP (FP-100A)

H8/3062F-ZTAT 5 V operation HD64F3062RF 100-pin QFP (FP-100B) R-mask version

3 V operation HD64F3062RVF 100-pin QFP (FP-100B)

H8/3062 mask 5 V operation HD6433062F 100-pin QFP (FP-100B) ROM version

Low-voltage HD6433062VF 100-pin QFP (FP-100B) operation

H8/3061 mask 5 V operation HD6433061F 100-pin QFP (FP-100B) ROM version

HD64F3062RTE 100-pin TQFP (TFP-100B) HD64F3062RFP 100-pin QFP (FP-100A)

HD64F3062RVTE 100-pin TQFP (TFP-100B) HD64F3062RVFP 100-pin QFP (FP-100A)

HD6433062TE 100-pin TQFP (TFP-100B) HD6433062FP 100-pin QFP (FP-100A)

HD6433062VTE 100-pin TQFP (TFP-100B) HD6433062VFP 100-pin QFP (FP-100A)

HD6433061TE 100-pin TQFP (TFP-100B)

(Hitachi Package Code)

HD6433061FP 100-pin QFP (FP-100A)

Low-voltage HD6433061VF 100-pin QFP (FP-100B) operation

H8/3060 mask 5 V operation HD6433060F 100-pin QFP (FP-100B) ROM version

Low-voltage HD6433060VF 100-pin QFP (FP-100B) operation

H8/3064F-ZTAT 5 V operation HD64F3064F 100-pin QFP (FP-100B)

3 V operation HD64F3064VF 100-pin QFP (FP-100B)

H8/3062F-ZTAT 5 V operation HD64F3062AF 100-pin QFP (FP-100B) A-mask version

HD6433061VTE 100-pin TQFP (TFP-100B) HD6433061VFP 100-pin QFP (FP-100A)

HD6433060TE 100-pin TQFP (TFP-100B) HD6433060FP 100-pin QFP (FP-100A)

HD6433060VTE 100-pin TQFP (TFP-100B) HD6433060VFP 100-pin QFP (FP-100A)

HD64F3064TE 100-pin TQFP (TFP-100B) HD64F3064FP 100-pin QFP (FP-100A)

HD64F3064VTE 100-pin TQFP (TFP-100B) HD64F3064VFP 100-pin QFP (FP-100A)

HD64F3062ATE 100-pin TQFP (TFP-100B)

HD64F3062AFP 100-pin QFP (FP-100A)

3 V operation HD64F3062AVF 100-pin QFP (FP-100B)

HD64F3062AVTE 100-pin TQFP (TFP-100B) HD64F3062AVFP 100-pin QFP (FP-100A)

+ 909 hidden pages

Hitachi H8/3062, HD6433062, HD6433060, H8/3062F-ZTAT, HD64F3062 Hardware Manual

Specifications and Main Features

Frequently Asked Questions

User Manual