Hitachi HD6433060, HD6433064B, HD6433062B, HD6433061B, HD6433060B Hardware Manual

...

To all our customers

Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp.

The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself.

Renesas Technology Home Page: http://www.renesas.com

Renesas Technology Corp. Customer Support Dept. April 1, 2003

Cautions

Keep safety first in your circuit designs!

1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliabl e, but there is always the possibility that trouble may occur with them. Trouble with semicondu ctors may lead to personal injury , fire or propert y da mage. Remember to give due consideration to safety when making your circuit designs, with appropriate measu res such as (i) placement of substitutive, auxiliar y circuits, (ii) use of nonflammable material or (iii) preve n tion ag ain st any malf u nc tio n or mishap.

Notes regar ding these ma terials

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Hitachi Single-Chip Microcomputer

The revision list can be viewed directly by  clicking the title page.  The revision list summarizes the locations of  revisions and additions. Details should always  be checked by referring to the relevant text.

H8/3062 Series

H8/3062 HD6433062 H8/3061 HD6433061 H8/3060 HD6433060

H8/3062B Series

H8/3064B HD6433064B H8/3062B HD6433062B H8/3061B HD6433061B H8/3060B HD6433060B

H8/3062F-ZTAT™

HD64F3062, HD64F3062R, HD64F3062B

H8/3064F-ZTAT™

HD64F3064B

Hardware Manual

ADE-602-136D Rev. 5.0 3/18/03 Hitachi, Ltd.

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.

Preface

The H8/3062 Series is a high-performance single-chip microcomputer that integrates peripheral functions necessary for system configuration with an H8/300H CPU featuring a 32-bit internal architecture as its core.

The on-chip peripheral functions include ROM, RAM, 16-bit timers, 8-bit timers, a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), a D/A converter, an A/D converter, and I/O ports, providing an ideal configuration as a microcomputer for embedding in sophisticated control systems. Flash memory (F-ZTAT™*) and mask ROM are available as on-chip ROM, enabling users to respond quickly and flexibly to changing application specifications and the demands of the transition from initial to full-fledged volume production.

Note: * F-ZTAT is a trademark of Hitachi, Ltd.

Intended Readership: This manual is intended for users undertaking the design of an application

system using the H8/3062 Series. Readers using this manual require a basic knowledge of electrical circuits, logic circuits, and microcomputers.

Purpose: The purpose of this manual is to give users an understanding of the hardware

functions and electrical characteristics of the H8/3062 Series. Details of execution instructions can be found in the H8/300H Series Programming Manual, which should be read in conjunction with the present manual.

Using this Manual:

• For an overall understanding of the H8/3062 Series's functions

Follow the Table of Contents. This manual is broadly divided into sections on the CPU, system control functions, peripheral functions, and electrical characteristics.

• For a detailed understanding of CPU functions

Refer to the separate publication H8/300H Series Programming Manual.

Note on bit notation: Bits are shown in high-to-low order from left to right.

Related Material: The latest information is available at our Web Site. Please make sure that

you have the most up-to-date information available. (http://www.hitachisemiconductor.com/)

User's Manuals on the H8/3062:

Manual Title ADE No.

H8/3062 Hardware Manual This manual H8/300H Series Programming Manual ADE-602-053

Users manuals for development tools:

Manual Title ADE No.

C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual ADE-702-247 H8S, H8/300 Series Simulator/Debugger User’s Manual ADE-702-037 Hitachi Embedded Workshop User’s Manual ADE-702-201 H8S, H8/300 Series Hitachi Embedded Workshop, Hitachi Debugging

Interface User’s Manual

ADE-702-231

Application Note:

Manual Title ADE No.

H8/300H for CPU Application Note ADE-502-033 H8/300H On-Chip Supporting Modules Application Note ADE-502-035 H8/300H Technical Q&A ADE-502-038

Comparison of H8/3062 Series Product Specifications

There are 11 members of the H8/3062 Series: the H8/3062F-ZTAT, H8/3062F-ZTAT R-mask version, H8/3062F-ZTAT B-mask version, and H8/3064F-ZTAT B-mask version (all with on-chip flash memory), and the H8/3062 mask ROM version, H8/3061 mask ROM version, H8/3060 mask ROM version, H8/3064 mask ROM B-mask version, H8/3062 mask ROM B-mask version, H8/3061 mask ROM B-mask version, and H8/3060 mask ROM B-mask version.

The specifications of these products are compared below.

H8/3064 Mask ROM

H8/3062 Mask

H8/3062F-ZTAT H8/3062F-ZTAT

Product specifications

Product code

Pin arrangement

RAM size 4 kbytes H8/3062:

On-chip singlepower-supply flash memory

HD64F3062 HD64F3062R HD6433062

See figures 1.2 and 1.3, Pin Arrangement, in section 1 H8/3064F-ZTAT

R-Mask Version

H8/3062F-ZTAT version with address output functions added

ROM Version, H8/3061 Mask ROM Version, H8/3060 Mask ROM Version

Mask ROM version

HD6433061 HD6433060

4 kbytes H8/3061:

4 kbytes H8/3060:

2 kbytes

H8/3064F-ZTAT B-Mask Version

On-chip largecapacity singlepower-supply flash memory

Internal stepdown circuit

HD64F3064B HD64F3062B HD6433064B

B-mask version has V

pin, and

requires connection of external capacitor

See figures 1.4 and 1.5, Pin Arrangement, in section 1

8 kbytes 4 kbytes H8/3064B:

H8/3062F-ZTAT B-Mask Version

H8/3062F-ZTAT high-speed operation version

H8/3062F-ZTAT B-mask version has V

pin, and

requires connection of external capacitor

See figures 1.4 and 1.5, Pin Arrangement, in section 1

B-Mask Version, H8/3062 Mask ROM B-Mask Version, H8/3061 Mask ROM B-Mask Version, H8/3060 Mask ROM B-Mask Version

Mask ROM version

HD6433062B HD6433061B HD6433060B

H8/3064 mask ROM B-mask version, H8/3062 mask ROM B-mask version, H8/3061 mask ROM B-mask version, and H8/3060 mask ROM B-mask version have V

pin, and require

connection of external capacitor

See figures 1.4 and 1.5, Pin Arrangement, in section 1

8 kbytes H8/3062B:

4 kbytes H8/3061B:

4 kbytes H8/3060B:

2 kbytes

H8/3062F-ZTAT H8/3062F-ZTAT

ROM size 128 kbytes H8/3062:

Address output functions

Flash memory

Mask ROM — — See section 17,

Electrical characteristics (operating frequency)

Compatible with previous H8/300H Series

See section 17, ROM — See 18.1.1,

See table 22.1, Comparison of H8/3062 Series Electrical Characteristics, in section 22

R-Mask Version

Address update mode 1 or 2 selectable

See 6.3.5, Address Output Method, in section 6

1 to 20 MHz 2 to 25 MHz

H8/3062 Mask ROM Version, H8/3061 Mask ROM Version, H8/3060 Mask ROM Version

128 kbytes H8/3061:

96 kbytes H8/3060:

64 kbytes

ROM

H8/3064 Mask ROM B-Mask Version,

H8/3062 Mask ROM H8/3064F-ZTAT B-Mask Version

256 kbytes 128 kbytes H8/3064B:

Differences between H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version, in section 18

— — Mask ROM B-mask

H8/3062F-ZTAT B-Mask Version

See 19.1.1, Differences between H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version, in section 19

B-Mask Version,

H8/3061 Mask ROM

B-Mask Version,

H8/3060 Mask ROM

B-Mask Version

256 kbytes

H8/3062B:

128 kbytes

H8/3061B:

96 kbytes

H8/3060B:

64 kbytes

—

version of H8/3064:

see section 18.

Mask ROM B-mask

versions of H8/3062,

H8/3061, and

H8/3060: see section

19.

H8/3062 Mask

H8/3062F-ZTAT H8/3062F-ZTAT

Registers See table B.1, Comparison of H8/3062 Series Internal I/O Register Specifications,

Usage notes

in appendix B See appendix

B.1, Address List

See 1.4, H8/3062F-ZTAT R-Mask Version Usage Note, in section 1

R-Mask Version

See appendix B.1, Address List

ROM Version, H8/3061 Mask ROM Version, H8/3060 Mask ROM Version

See appendix B.1, Address List

H8/3064F-ZTAT B-Mask Version

See appendix B.2, Address List

See 1.5, H8/3064F-ZTAT B-Mask Version, and H8/3062F-ZTAT B-Mask Version Usage Note, in section 1

H8/3062F-ZTAT B-Mask Version

See appendix B.3, Address List

H8/3064 Mask ROM B-Mask Version, H8/3062 Mask ROM B-Mask Version, H8/3061 Mask ROM B-Mask Version, H8/3060 Mask ROM B-Mask Version

Mask ROM B-mask version of H8/3064: see appendix B.2, Address List.

Mask ROM B-mask versions of H8/3062, H8/3061, and H8/3060: see appendix B.3, Address List.

List of Items Revised or Added for This Version

Description

Section Page Item

All — All The H8/3064 mask ROM

1. Overview 18 1.3.3 Pin Assignments in Each Mode

25 1.5.2 Product Type

Names and Markings

27 1.5.4 Notes on

Changeover to Mask ROM Version or Mask ROM B-Mask Version

6. Bus Controller 139 6.3.1 Area Division

(See Manual for Details)

B-mask version, H8/3062 mask ROM B-mask version, H8/3061 mask ROM B-mask version, and H8/3060 mask ROM Bmask version are added to the product line-up.

Table 1.4 Pin Assignments in Each Mode (FP-100B or TFP-100B, FP-100A)

• (V

)*4 is added to modes 2

to 7 in the first row.

Table 1.7 Differences in H8/3062F-ZTAT R-Mask Version, H8/3062F-ZTAT B-Mask Version, H8/3064FZTAT, and H8/3064F-ZTAT B-Mask Version Markings

• The marking examples of H8/3062F-ZTAT B-mask version and H8/3064FZTAT B-mask version are amended.

• Title is amended.

• Note (2) is added.

• Figure 6.3 Memory Map in

16-Mbyte Mode (H8/3060 Mask ROM Version, H8/3060 Mask ROM B-Mask Version) (2) is added.

• The Memory Map in 16Mbyte Mode (H8/3064FZTAT B-Mask Version, H8/3064 Mask ROM B-Mask Version) is moved from figure 6.3 (2) to figure

6.3 (3).

Description

Section Page Item

12. Serial Communication Interface

14. A/D Converter 447 14.1.1 Features The high-speed conversion

17. ROM [H8/3062FZTAT, H8/3062F-ZTAT R-Mask Version, On-Chip Mask ROM Models]

18. H8/3064 Internal Voltage Step-Down Version ROM [H8/3064F-ZTAT B-Mask Version, H8/3064 Mask ROM B-Mask Version]

19. H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version, Mask ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]

394 12.3.2 Operation in

Asynchronous Mode

482 17.2.4 Register

Configuration

523 to 574 All The title of the section is

572 18.12 Mask ROM

(H8/3064 Mask ROM B-Mask Version) Overview

573 18.13 Notes on Ordering

Mask ROM Version Chips

574 18.14 Notes on

Converting the F-ZTAT Application Software to the Mask ROM Versions

575 to 626 All

594 19.5.1 Boot Mode The start address of the

(See Manual for Details)

Figure 12.4 Sample Flowchart for SCI Initialization

• Note is added.

time is amended. Note 3 is deleted.

changed from Flash Memory [H8/3064F-ZTAT B-Mask Version].

Newly added.

• The title of the section is changed from Flash Memory.

• Descriptions on the mask ROM B-mask versions of H8/3062, H8/3061, and H8/3060 are added.

programming control program is amended to H'FFF520.

Section Page Item

19. H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version, Mask ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]

20. Clock Pulse Generator

21. Power-Down State 644 21.4.3 Selection of

22. Electrical Characteristics

624 19.12 Mask ROM

(H8/3062 Mask ROM BMask Version, H8/3061 Mask ROM B-Mask Version, H8/3060 Mask ROM B-Mask Version) Overview

625 19.13 Notes on Ordering

Mask ROM Version Chips

626 19.14 Notes on

Converting the F-ZTAT Application Software to the Mask ROM Versions

628 20.2.1 Connecting a

Crystal Resonator

634 20.5.3 Usage Notes Table 20.7 Comparison of

Waiting Time for Exit from Software Standby Mode

695 22.3 Electrical

Characteristics of H8/3064F-ZTAT B-Mask Version

22.3.1 Absolute Maximum Ratings

696, 699 22.3.2 DC

Characteristics

Description (See Manual for Details)

Newly added.

• Moved from 19.12.

• Table is amended.

Table 20.1 (1) Damping Resistance Value

• Note is amended.

H8/3062 Series Operating Frequency Ranges is amended.

Table 21.3 Clock Frequency and Waiting Time for Clock to Settle

• The value 13.1 is specified for the recommended setting for DIV = 1, DIV0 = 1, and 32468 states

Table 22.21 Absolute Maximum Ratings

The operating temperature rating is amended

Table22.22 DC Characteristics, and Table

22.23 Permissible Output

Currents

• A new condition is added.

Section Page Item

22. Electrical Characteristics

701, 702, 703, 705

707 22.3.4 A/D Conversion

708 22.3.5 D/A Conversion

709 22.3.6 Flash Memory

711 to 723 22.4 Electrical

724 to 739 22.5 Electrical

724 22.5.1 Absolute

725 22.5.2 DC

730, 731, 732, 734

22.3.3 AC Characteristics

Characteristics

Characteristics of H8/3064 Mask ROM BMask Version

Characteristics of H8/3062F-ZTAT B-Mask Version

Maximum Ratings

Characteristics

22.5.3 AC Characteristics

Description (See Manual for Details)

Table 22.24 Clock Timing, Table 22.25 Control Signal Timing, Table 22.26 Bus Timing, and Table 22.27 Timing of On-Chip Supporting Modules

• A new condition is added. Table 22.28 A/D Conversion

Characteristics

• A new condition is added. Table 22.29 D/A conversion

Characteristics

• A new condition is added. Table 22.30 Flash Memory

Characteristics

• A new condition is added. Newly added

The section is moved from

22.4.

Table 22.40 Absolute Maximum Ratings

The operating temperature rating is amended

Table22.41 DC Characteristics, and Table

22.42 Permissible Output Currents

• A new condition is added. Table 22.43 Clock Timing,

Table 22.44 Control Signal Timing, Table 22.45 Bus Timing, and Table 22.46 Timing of On-Chip Supporting Modules

• A new condition is added.

Section Page Item

22. Electrical Characteristics

736 22.5.4 A/D Conversion

Characteristics

737 22.5.5 D/A Conversion

Characteristics

738 22.5.6 Flash Memory

Characteristics

740 to 752 22.6 Electrical

Characteristics of H8/3062 Mask ROM B-Mask Version, H8/3061 Mask ROM B-Mask Version, and H8/3060 Mask ROM B-Mask Version

753 to 761 22.7 Operational Timing The section is moved from

Appendix 906 C.7 Port 7 Block

Diagram

Description (See Manual for Details)

Table 22.47 A/D Conversion Characteristics

• A new condition is added.

Table 22.48 D/A conversion Characteristics

• A new condition is added.

Table 22.49 Flash Memory Characteristics

• A new condition is added.

Newly added

22.5.

• Figure C.7(a) Port 7 Block Diagram (Pins P7

to P75) is

amended.

• Figure C.7(b) Port 7 Block Diagram (Pins P7

to P77) is

amended.

Section 1 Overview........................................................................................................... 1

1.1 Overview............................................................................................................................ 1

1.2 Block Diagram................................................................................................................... 7

1.3 Pin Description.................................................................................................................. 8

1.3.1 Pin Arrangement .................................................................................................. 8

1.3.2 Pin Functions........................................................................................................ 13

1.3.3 Pin Assignments in Each Mode............................................................................ 18

1.4 Notes on H8/3062F-ZTAT R-Mask Version .................................................................... 22

1.4.1 Pin Arrangement .................................................................................................. 22

1.4.2 Product Type Names and Markings ..................................................................... 23

1.4.3 Differences between H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version. 23

1.5 Notes on H8/3064F-ZTAT B-Mask Version, H8/3062F-ZTAT B-Mask Version, H8/3064 Mask ROM B-Mask Version, H8/3062 Mask ROM B-Mask Version,

H8/3061 Mask ROM B-Mask Version, and H8/3060 Mask ROM B-Mask Version ....... 24

1.5.1 Pin Arrangement.................................................................................................. 25

1.5.2 Product Type Names and Markings ..................................................................... 25

1.5.3 VCL Pin.................................................................................................................. 26

1.5.4 Notes on Changeover to On-Chip Mask ROM Versions and

On-Chip Mask ROM B-Mask Versions............................................................... 27

1.6 Setting Oscillation Settling Wait Time.............................................................................. 28

1.7 Caution on Crystal Resonator Connection........................................................................ 28

Section 2 CPU..................................................................................................................... 29

2.1 Overview............................................................................................................................ 29

2.1.1 Features ................................................................................................................ 29

2.1.2 Differences from H8/300 CPU............................................................................. 30

2.2 CPU Operating Modes ...................................................................................................... 31

2.3 Address Space.................................................................................................................... 31

2.4 Register Configuration ......................................................................................................32

2.4.1 Overview.............................................................................................................. 32

2.4.2 General Registers.................................................................................................. 33

2.4.3 Control Registers.................................................................................................. 34

2.4.4 Initial CPU Register Values...................................................................................... 35

2.5 Data Formats...................................................................................................................... 36

2.5.1 General Register Data Formats ............................................................................ 36

2.5.2 Memory Data Formats.......................................................................................... 37

2.6 Instruction Set.................................................................................................................... 39

2.6.1 Instruction Set Overview...................................................................................... 39

2.6.2 Instructions and Addressing Modes ..................................................................... 40

2.6.3 Tables of Instructions Classified by Function...................................................... 41

2.6.4 Basic Instruction Formats..................................................................................... 50

2.6.5 Notes on Use of Bit Manipulation Instructions.................................................... 51

2.7 Addressing Modes and Effective Address Calculation..................................................... 53

2.7.1 Addressing Modes................................................................................................ 53

2.7.2 Effective Address Calculation.............................................................................. 55

2.8 Processing States ............................................................................................................... 59

2.8.1 Overview.............................................................................................................. 59

2.8.2 Program Execution State...................................................................................... 59

2.8.3 Exception-Handling State .................................................................................... 60

2.8.4 Exception Handling Operation ............................................................................. 61

2.8.5 Bus-Released State............................................................................................... 62

2.8.6 Reset State............................................................................................................ 62

2.8.7 Power-Down State................................................................................................ 63

2.9 Basic Operational Timing.................................................................................................. 63

2.9.1 Overview.............................................................................................................. 63

2.9.2 On-Chip Memory Access Timing ........................................................................ 63

2.9.3 On-Chip Supporting Module Access Timing....................................................... 64

2.9.4 Access to External Address Space ....................................................................... 65

Section 3 MCU Operating Modes ................................................................................ 67

3.1 Overview............................................................................................................................ 67

3.1.1 Operating Mode Selection.................................................................................... 67

3.1.2 Register Configuration ......................................................................................... 68

3.2 Mode Control Register (MDCR)....................................................................................... 68

3.3 System Control Register (SYSCR).................................................................................... 69

3.4 Operating Mode Descriptions............................................................................................ 72

3.4.1 Mode 1.................................................................................................................. 72

3.4.2 Mode 2.................................................................................................................. 72

3.4.3 Mode 3.................................................................................................................. 72

3.4.4 Mode 4.................................................................................................................. 72

3.4.5 Mode 5.................................................................................................................. 72

3.4.6 Mode 6.................................................................................................................. 73

3.4.7 Mode 7.................................................................................................................. 73

3.5 Pin Functions in Each Operating Mode............................................................................. 73

3.6 Memory Map in Each Operating Mode............................................................................. 74

3.6.1 Comparison of H8/3062 Series Memory Maps.................................................... 74

3.6.2 Reserved Areas..................................................................................................... 75

Section 4 Exception Handling........................................................................................ 85

4.1 Overview............................................................................................................................ 85

4.1.1 Exception Handling Types and Priority ............................................................... 85

4.1.2 Exception Handling Operation ............................................................................. 85

4.1.3 Exception Vector Table........................................................................................ 86

4.2 Reset.................................................................................................................................. 88

4.2.1 Overview.............................................................................................................. 88

4.2.2 Reset Sequence..................................................................................................... 88

4.2.3 Interrupts after Reset ............................................................................................ 91

4.3 Interrupts............................................................................................................................ 92

4.4 Trap Instruction ................................................................................................................. 92

4.5 Stack Status after Exception Handling.............................................................................. 93

4.6 Notes on Stack Usage........................................................................................................94

Section 5 Interrupt Controller........................................................................................ 97

5.1 Overview............................................................................................................................ 97

5.1.1 Features ................................................................................................................ 97

5.1.2 Block Diagram...................................................................................................... 98

5.1.3 Pin Configuration ................................................................................................. 99

5.1.4 Register Configuration ......................................................................................... 99

5.2 Register Descriptions......................................................................................................... 99

5.2.1 System Control Register (SYSCR) ...................................................................... 99

5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ............................................. 100

5.2.3 IRQ Status Register (ISR) .................................................................................... 105

5.2.4 IRQ Enable Register (IER) .................................................................................. 106

5.2.5 IRQ Sense Control Register (ISCR)..................................................................... 107

5.3 Interrupt Sources................................................................................................................ 108

5.3.1 External Interrupts................................................................................................ 108

5.3.2 Internal Interrupts................................................................................................. 109

5.3.3 Interrupt Exception Handling Vector Table ......................................................... 109

5.4 Interrupt Operation............................................................................................................ 113

5.4.1 Interrupt Handling Process ................................................................................... 113

5.4.2 Interrupt Exception Handling Sequence .............................................................. 118

5.4.3 Interrupt Response Time ...................................................................................... 119

5.5 Usage Notes....................................................................................................................... 120

5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction...................... 120

5.5.2 Instructions that Inhibit Interrupts........................................................................ 121

5.5.3 Interrupts during EEPMOV Instruction Execution.............................................. 121

Section 6 Bus Controller.................................................................................................. 123

6.1 Overview............................................................................................................................ 123

6.1.1 Features ................................................................................................................ 123

6.1.2 Block Diagram...................................................................................................... 124

6.1.3 Pin Configuration ................................................................................................. 125

6.1.4 Register Configuration ......................................................................................... 126

6.2 Register Descriptions......................................................................................................... 126

6.2.1 Bus Width Control Register (ABWCR) ............................................................... 126

iii

6.2.2 Access State Control Register (ASTCR).............................................................. 127

6.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 128

6.2.4 Bus Release Control Register (BRCR) ................................................................ 132

6.2.5 Bus Control Register (BCR) ................................................................................ 133

6.2.6 Chip Select Control Register (CSCR).................................................................. 135

6.2.7 Address Control Register (ADRCR).................................................................... 136

6.3 Operation ........................................................................................................................... 137

6.3.1 Area Division........................................................................................................ 137

6.3.2 Bus Specifications................................................................................................ 141

6.3.3 Memory Interfaces................................................................................................ 142

6.3.4 Chip Select Signals............................................................................................... 142

6.3.5 Address Output Method ....................................................................................... 143

6.4 Basic Bus Interface............................................................................................................ 145

6.4.1 Overview.............................................................................................................. 145

6.4.2 Data Size and Data Alignment ............................................................................. 145

6.4.3 Valid Strobes........................................................................................................ 146

6.4.4 Memory Areas...................................................................................................... 147

6.4.5 Basic Bus Control Signal Timing......................................................................... 148

6.4.6 Wait Control......................................................................................................... 155

6.5 Idle Cycle........................................................................................................................... 157

6.5.1 Operation.............................................................................................................. 157

6.5.2 Pin States in Idle Cycle ........................................................................................ 159

6.6 Bus Arbiter ........................................................................................................................ 159

6.6.1 Operation.............................................................................................................. 160

6.7 Register and Pin Input Timing .......................................................................................... 162

6.7.1 Register Write Timing.......................................................................................... 162

6.7.2 BREQ Pin Input Timing....................................................................................... 163

Section 7 I/O Ports ............................................................................................................ 165

7.1 Overview............................................................................................................................ 165

7.2 Port 1.................................................................................................................................. 169

7.2.1 Overview.............................................................................................................. 169

7.2.2 Register Descriptions............................................................................................ 169

7.3 Port 2.................................................................................................................................. 172

7.3.1 Overview.............................................................................................................. 172

7.3.2 Register Descriptions............................................................................................ 173

7.4 Port 3.................................................................................................................................. 176

7.4.1 Overview.............................................................................................................. 176

7.4.2 Register Descriptions............................................................................................ 176

7.5 Port 4.................................................................................................................................. 178

7.5.1 Overview.............................................................................................................. 178

7.5.2 Register Descriptions............................................................................................ 179

7.6 Port 5.................................................................................................................................. 181

7.6.1 Overview.............................................................................................................. 181

7.6.2 Register Descriptions............................................................................................ 182

7.7 Port 6.................................................................................................................................. 184

7.7.1 Overview.............................................................................................................. 184

7.7.2 Register Descriptions............................................................................................ 185

7.8 Port 7.................................................................................................................................. 188

7.8.1 Overview.............................................................................................................. 188

7.8.2 Register Description............................................................................................. 189

7.9 Port 8.................................................................................................................................. 190

7.9.1 Overview.............................................................................................................. 190

7.9.2 Register Descriptions............................................................................................ 191

7.10 Port 9.................................................................................................................................. 195

7.10.1 Overview.............................................................................................................. 195

7.10.2 Register Descriptions............................................................................................ 196

7.11 Port A................................................................................................................................. 200

7.11.1 Overview.............................................................................................................. 200

7.11.2 Register Descriptions............................................................................................ 202

7.12 Port B................................................................................................................................. 212

7.12.1 Overview.............................................................................................................. 212

7.12.2 Register Descriptions............................................................................................ 214

Section 8 16-Bit Timer..................................................................................................... 221

8.1 Overview............................................................................................................................ 221

8.1.1 Features ................................................................................................................ 221

8.1.2 Block Diagrams.................................................................................................... 223

8.1.3 Pin Configuration ................................................................................................. 226

8.1.4 Register Configuration ......................................................................................... 227

8.2 Register Descriptions......................................................................................................... 228

8.2.1 Timer Start Register (TSTR)................................................................................ 228

8.2.2 Timer Synchro Register (TSNC).......................................................................... 229

8.2.3 Timer Mode Register (TMDR) ............................................................................ 230

8.2.4 Timer Interrupt Status Register A (TISRA) ......................................................... 233

8.2.5 Timer Interrupt Status Register B (TISRB).......................................................... 235

8.2.6 Timer Interrupt Status Register C (TISRC).......................................................... 238

8.2.7 Timer Counters (16TCNT)................................................................................... 240

8.2.8 General Registers (GRA, GRB) ........................................................................... 241

8.2.9 Timer Control Registers (16TCR)........................................................................ 242

8.2.10 Timer I/O Control Register (TIOR) ..................................................................... 244

8.2.11 Timer Output Level Setting Register C (TOLR).................................................. 246

8.3 CPU Interface.................................................................................................................... 248

8.3.1 16-Bit Accessible Registers.................................................................................. 248

8.3.2 8-Bit Accessible Registers.................................................................................... 250

8.4 Operation ........................................................................................................................... 251

8.4.1 Overview.............................................................................................................. 251

8.4.2 Basic Functions .................................................................................................... 251

8.4.3 Synchronization.................................................................................................... 259

8.4.4 PWM Mode.......................................................................................................... 261

8.4.5 Phase Counting Mode .......................................................................................... 265

8.4.6 16-Bit Timer Output Timing ................................................................................ 267

8.5 Interrupts............................................................................................................................ 268

8.5.1 Setting of Status Flags.......................................................................................... 268

8.5.2 Timing of Clearing of Status Flags ...................................................................... 270

8.5.3 Interrupt Sources .................................................................................................. 271

8.6 Usage Notes....................................................................................................................... 272

Section 9 8-Bit Timers ..................................................................................................... 285

9.1 Overview............................................................................................................................ 285

9.1.1 Features ................................................................................................................ 285

9.1.2 Block Diagram...................................................................................................... 287

9.1.3 Pin Configuration ................................................................................................. 288

9.1.4 Register Configuration ......................................................................................... 289

9.2 Register Descriptions......................................................................................................... 290

9.2.1 Timer Counters (8TCNT)..................................................................................... 290

9.2.2 Time Constant Registers A (TCORA) ................................................................. 291

9.2.3 Time Constant Registers B (TCORB).................................................................. 292

9.2.4 Timer Control Register (8TCR) ........................................................................... 293

9.2.5 Timer Control/Status Registers (8TCSR) ............................................................ 296

9.3 CPU Interface.................................................................................................................... 301

9.3.1 8-Bit Registers...................................................................................................... 301

9.4 Operation ........................................................................................................................... 303

9.4.1 8TCNT Count Timing.......................................................................................... 303

9.4.2 Compare Match Timing ....................................................................................... 304

9.4.3 Input Capture Signal Timing................................................................................ 305

9.4.4 Timing of Status Flag Setting............................................................................... 306

9.4.5 Operation with Cascaded Connection .................................................................. 307

9.4.6 Input Capture Setting............................................................................................ 310

9.5 Interrupt ............................................................................................................................. 311

9.5.1 Interrupt Sources .................................................................................................. 311

9.5.2 A/D Converter Activation .................................................................................... 312

9.6 8-Bit Timer Application Example..................................................................................... 312

9.7 Usage Notes....................................................................................................................... 313

9.7.1 Contention between 8TCNT Write and Clear...................................................... 313

9.7.2 Contention between 8TCNT Write and Increment .............................................. 314

9.7.3 Contention between TCOR Write and Compare Match ...................................... 315

9.7.4 Contention between TCOR Read and Input Capture ........................................... 316

9.7.5 Contention between Counter Clearing by Input Capture and Counter Increment 317

9.7.6 Contention between TCOR Write and Input Capture .......................................... 318

9.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode

(Cascaded Connection) ........................................................................................ 319

9.7.8 Contention between Compare Matches A and B ................................................. 320

9.7.9 8TCNT Operation and Internal Clock Source Switchover .................................. 320

Section 10 Programmable Timing Pattern Controller (TPC).................................. 323

10.1 Overview............................................................................................................................ 323

10.1.1 Features ................................................................................................................ 323

10.1.2 Block Diagram...................................................................................................... 324

10.1.3 Pin Configuration ................................................................................................. 325

10.1.4 Register Configuration ......................................................................................... 326

10.2 Register Descriptions......................................................................................................... 327

10.2.1 Port A Data Direction Register (PADDR) ........................................................... 327

10.2.2 Port A Data Register (PADR) .............................................................................. 327

10.2.3 Port B Data Direction Register (PBDDR)............................................................ 328

10.2.4 Port B Data Register (PBDR)............................................................................... 328

10.2.5 Next Data Register A (NDRA) ............................................................................ 329

10.2.6 Next Data Register B (NDRB)............................................................................. 331

10.2.7 Next Data Enable Register A (NDERA).............................................................. 333

10.2.8 Next Data Enable Register B (NDERB) .............................................................. 334

10.2.9 TPC Output Control Register (TPCR) ................................................................. 335

10.2.10 TPC Output Mode Register (TPMR) ................................................................... 337

10.3 Operation ........................................................................................................................... 339

10.3.1 Overview.............................................................................................................. 339

10.3.2 Output Timing...................................................................................................... 340

10.3.3 Normal TPC Output ............................................................................................. 341

10.3.4 Non-Overlapping TPC Output ............................................................................. 343

10.3.5 TPC Output Triggering by Input Capture ............................................................ 345

10.4 Usage Notes....................................................................................................................... 346

10.4.1 Operation of TPC Output Pins ............................................................................. 346

10.4.2 Note on Non-Overlapping Output........................................................................ 346

Section 11 Watchdog Timer ............................................................................................. 349

11.1 Overview............................................................................................................................ 349

11.1.1 Features ................................................................................................................ 349

11.1.2 Block Diagram...................................................................................................... 350

11.1.3 Pin Configuration ................................................................................................. 350

11.1.4 Register Configuration ......................................................................................... 351

11.2 Register Descriptions......................................................................................................... 351

11.2.1 Timer Counter (TCNT) ........................................................................................ 351

11.2.2 Timer Control/Status Register (TCSR)................................................................ 352

11.2.3 Reset Control/Status Register (RSTCSR)............................................................ 354

vii

11.2.4 Notes on Register Rewriting ................................................................................ 355

11.3 Operation ........................................................................................................................... 357

11.3.1 Watchdog Timer Operation.................................................................................. 357

11.3.2 Interval Timer Operation...................................................................................... 358

11.3.3 Timing of Setting of Overflow Flag (OVF) ......................................................... 358

11.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) .................................. 359

11.4 Interrupts............................................................................................................................ 360

11.5 Usage Notes....................................................................................................................... 360

Section 12 Serial Communication Interface................................................................ 361

12.1 Overview............................................................................................................................ 361

12.1.1 Features ................................................................................................................ 361

12.1.2 Block Diagram...................................................................................................... 363

12.1.3 Pin Configuration ................................................................................................. 364

12.1.4 Register Configuration ......................................................................................... 365

12.2 Register Descriptions......................................................................................................... 366

12.2.1 Receive Shift Register (RSR)............................................................................... 366

12.2.2 Receive Data Register (RDR) .............................................................................. 366

12.2.3 Transmit Shift Register (TSR).............................................................................. 367

12.2.4 Transmit Data Register (TDR)............................................................................. 367

12.2.5 Serial Mode Register (SMR)................................................................................ 368

12.2.6 Serial Control Register (SCR).............................................................................. 371

12.2.7 Serial Status Register (SSR)................................................................................. 375

12.2.8 Bit Rate Register (BRR)....................................................................................... 380

12.3 Operation ........................................................................................................................... 388

12.3.1 Overview.............................................................................................................. 388

12.3.2 Operation in Asynchronous Mode........................................................................ 391

12.3.3 Multiprocessor Communication........................................................................... 400

12.3.4 Synchronous Operation........................................................................................ 407

12.4 SCI Interrupts .................................................................................................................... 415

12.5 Usage Notes....................................................................................................................... 416

12.5.1 Notes on Use of SCI............................................................................................. 416

Section 13 Smart Card Interface...................................................................................... 421

13.1 Overview............................................................................................................................ 421

13.1.1 Features ................................................................................................................ 421

13.1.2 Block Diagram...................................................................................................... 422

13.1.3 Pin Configuration ................................................................................................. 422

13.1.4 Register Configuration ......................................................................................... 423

13.2 Register Descriptions......................................................................................................... 424

13.2.1 Smart Card Mode Register (SCMR) .................................................................... 424

13.2.2 Serial Status Register (SSR)................................................................................. 426

13.2.3 Serial Mode Register (SMR)................................................................................ 427

viii

13.2.4 Serial Control Register (SCR).............................................................................. 428

13.3 Operation ........................................................................................................................... 429

13.3.1 Overview.............................................................................................................. 429

13.3.2 Pin Connections.................................................................................................... 429

13.3.3 Data Format.......................................................................................................... 430

13.3.4 Register Settings................................................................................................... 432

13.3.5 Clock .................................................................................................................... 434

13.3.6 Transmitting and Receiving Data......................................................................... 436

13.4 Usage Notes....................................................................................................................... 443

Section 14 A/D Converter ................................................................................................. 447

14.1 Overview............................................................................................................................ 447

14.1.1 Features ................................................................................................................ 447

14.1.2 Block Diagram...................................................................................................... 448

14.1.3 Pin Configuration ................................................................................................. 449

14.1.4 Register Configuration ......................................................................................... 450

14.2 Register Descriptions......................................................................................................... 450

14.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 450

14.2.2 A/D Control/Status Register (ADCSR)................................................................ 451

14.2.3 A/D Control Register (ADCR)............................................................................. 453

14.3 CPU Interface.................................................................................................................... 454

14.4 Operation ........................................................................................................................... 456

14.4.1 Single Mode (SCAN = 0)..................................................................................... 456

14.4.2 Scan Mode (SCAN = 1) ....................................................................................... 458

14.4.3 Input Sampling and A/D Conversion Time.......................................................... 460

14.4.4 External Trigger Input Timing ............................................................................. 461

14.5 Interrupts............................................................................................................................ 462

14.6 Usage Notes....................................................................................................................... 462

Section 15 D/A Converter ................................................................................................. 467

15.1 Overview............................................................................................................................ 467

15.1.1 Features ................................................................................................................ 467

15.1.2 Block Diagram...................................................................................................... 468

15.1.3 Pin Configuration ................................................................................................. 469

15.1.4 Register Configuration ......................................................................................... 469

15.2 Register Descriptions......................................................................................................... 470

15.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1).................................................. 470

15.2.2 D/A Control Register (DACR)............................................................................. 470

15.2.3 D/A Standby Control Register (DASTCR).......................................................... 472

15.3 Operation ........................................................................................................................... 472

15.4 D/A Output Control ........................................................................................................... 474

Section 16 RAM................................................................................................................... 475

16.1 Overview............................................................................................................................ 475

16.1.1 Block Diagram...................................................................................................... 476

16.1.2 Register Configuration ......................................................................................... 476

16.2 System Control Register (SYSCR).................................................................................... 477

16.3 Operation ........................................................................................................................... 478

Section 17 ROM [H8/3062F-ZTAT, H8/3062F-ZTAT ROM Version,

On-Chip Mask ROM Models]

17.1 Overview............................................................................................................................ 479

17.2 Overview of Flash Memory (H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version)...... 480

17.2.1 Features ................................................................................................................ 480

17.2.2 Block Diagram...................................................................................................... 481

17.2.3 Pin Configuration ................................................................................................. 482

17.2.4 Register Configuration ......................................................................................... 482

17.3 Flash Memory Register Descriptions ................................................................................ 483

17.3.1 Flash Memory Control Register (FLMCR).......................................................... 483

17.3.2 Erase Block Register (EBR)................................................................................. 486

17.3.3 RAM Control Register (RAMCR) ....................................................................... 487

17.3.4 Flash Memory Status Register (FLMSR)............................................................. 489

17.4 On-Board Programming Mode.......................................................................................... 490

17.4.1 Boot Mode............................................................................................................ 493

17.4.2 User Program Mode ............................................................................................. 498

17.5 Flash Memory Programming/Erasing................................................................................ 500

17.5.1 Program Mode...................................................................................................... 501

17.5.2 Program-Verify Mode.......................................................................................... 502

17.5.3 Erase Mode........................................................................................................... 504

17.5.4 Erase-Verify Mode............................................................................................... 504

17.6 Flash Memory Protection.................................................................................................. 506

17.6.1 Hardware Protection............................................................................................. 506

17.6.2 Software Protection.............................................................................................. 508

17.6.3 Error Protection.................................................................................................... 508

17.6.4 NMI Input Disabling Conditions............................................................................ 510

17.7 Flash Memory Emulation in RAM.................................................................................... 511

17.8 Flash Memory PROM Mode ............................................................................................. 513

17.8.1 Socket Adapters and Memory Map...................................................................... 513

17.8.2 Notes on Use of PROM Mode.............................................................................. 514

17.9 Flash Memory Programming and Erasing Precautions ..................................................... 515

17.10 Mask ROM (H8/3062 Mask ROM Version, H8/3061 Mask ROM Version,

H8/3060 Mask ROM Version) Overview.......................................................................... 520

17.10.1 Block Diagram ..................................................................................................... 520

17.11 Notes on Ordering Mask ROM Version Chips.................................................................. 521

17.12 Notes when Converting the F-ZTAT Application Software to the Mask-ROM Versions 522

.................................................................... 479

Section 18 H8/3064 Internal Voltage Step-Down Version ROM

[H8/3064F-ZTAT B-Mask Version, H8/3064 Mask ROM B-Mask Version]

18.1 Overview............................................................................................................................ 523

18.1.1 Differences from H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version....... 524

18.2 Features.............................................................................................................................. 525

18.2.1 Block Diagram...................................................................................................... 526

18.2.2 Pin Configuration ................................................................................................. 527

18.2.3 Register Configuration ......................................................................................... 527

18.3 Register Descriptions......................................................................................................... 528

18.3.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 528

18.3.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 531

18.3.3 Erase Block Register 1 (EBR1)............................................................................ 532

18.3.4 Erase Block Register 2 (EBR2)............................................................................ 532

18.3.5 RAM Control Register (RAMCR) ....................................................................... 533

18.4 Overview of Operation...................................................................................................... 535

18.4.1 Mode Transitions.................................................................................................. 535

18.4.2 On-Board Programming Modes ........................................................................... 537

18.4.3 Flash Memory Emulation in RAM....................................................................... 539

18.4.4 Block Configuration............................................................................................. 540

18.5 On-Board Programming Mode.......................................................................................... 541

18.5.1 Boot Mode............................................................................................................ 542

18.5.2 User Program Mode.............................................................................................. 547

18.6 Flash Memory Programming/Erasing................................................................................ 549

18.6.1 Program Mode...................................................................................................... 551

18.6.2 Program-Verify Mode.......................................................................................... 552

18.6.3 Erase Mode........................................................................................................... 556

18.6.4 Erase-Verify Mode............................................................................................... 556

18.7 Flash Memory Protection .................................................................................................. 558

18.7.1 Hardware Protection............................................................................................. 558

18.7.2 Software Protection.............................................................................................. 559

18.7.3 Error Protection.................................................................................................... 559

18.8 Flash Memory Emulation in RAM.................................................................................... 562

18.9 NMI Input Disabling Conditions....................................................................................... 564

18.10 Flash Memory PROM Mode............................................................................................. 565

18.10.1 Socket Adapters and Memory Map...................................................................... 565

18.10.2 Notes on Use of PROM Mode.............................................................................. 566

18.11 Flash Memory Programming and Erasing Precautions..................................................... 566

18.12 Mask ROM (H8/3064 Mask ROM B-Mask Version) Overview...................................... 572

18.12.1 Block Diagram...................................................................................................... 572

18.13 Notes on Ordering Mask ROM Version Chips.................................................................. 573

18.14 Notes when Converting the F-ZTAT Application Software to the Mask-ROM Version. 574

.................................................. 523

Section 19 H8/3062 Internal Voltage Step-Down Version ROM

[H8/3062F-ZTAT B-Mask Version, Mask ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]

19.1 Overview............................................................................................................................ 575

19.1.1 Differences from H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version......... 576

19.2 Features.............................................................................................................................. 577

19.2.1 Block Diagram...................................................................................................... 578

19.2.2 Pin Configuration ................................................................................................. 579

19.2.3 Register Configuration ......................................................................................... 579

19.3 Register Descriptions......................................................................................................... 580

19.3.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 580

19.3.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 583

19.3.3 Erase Block Register (EBR)................................................................................. 584

19.3.4 RAM Control Register (RAMCR) ....................................................................... 585

19.4 Overview of Operation...................................................................................................... 587

19.4.1 Mode Transitions.................................................................................................. 587

19.4.2 On-Board Programming Modes ........................................................................... 589

19.4.3 Flash Memory Emulation in RAM....................................................................... 591

19.4.4 Block Configuration............................................................................................. 592

19.5 On-Board Programming Mode.......................................................................................... 593

19.5.1 Boot Mode............................................................................................................ 594

19.5.2 User Program Mode ............................................................................................. 599

19.6 Flash Memory Programming/Erasing................................................................................ 601

19.6.1 Program Mode...................................................................................................... 603

19.6.2 Program-Verify Mode.......................................................................................... 604

19.6.3 Erase Mode........................................................................................................... 608

19.6.4 Erase-Verify Mode............................................................................................... 608

19.7 Flash Memory Protection .................................................................................................. 610

19.7.1 Hardware Protection............................................................................................. 610

19.7.2 Software Protection.............................................................................................. 611

19.7.3 Error Protection.................................................................................................... 611

19.8 Flash Memory Emulation in RAM.................................................................................... 614

19.9 NMI Input Disabling Conditions....................................................................................... 615

19.10 Flash Memory PROM Mode............................................................................................. 616

19.10.1 Socket Adapters and Memory Map...................................................................... 616

19.10.2 Notes on Use of PROM Mode.............................................................................. 617

19.11 Flash Memory Programming and Erasing Precautions..................................................... 618

19.12 Mask ROM (H8/3062 Mask ROM B-Mask Version, H8/3061 Mask ROM B-Mask

Version, H8/3060 Mask ROM B-Mask Version) Overview............................................. 624

19.12.1 Block Diagram...................................................................................................... 624

19.13 Notes on Ordering Mask ROM Version Chips.................................................................. 625

19.14 Notes when Converting the F-ZTAT Application Software to the Mask-ROM Versions 626

........................................................ 575

xii

Section 20 Clock Pulse Generator .................................................................................. 627

20.1 Overview............................................................................................................................ 627

20.1.1 Block Diagram...................................................................................................... 627

20.2 Oscillator Circuit ............................................................................................................... 628

20.2.1 Connecting a Crystal Resonator........................................................................... 628

20.2.2 External Clock Input ............................................................................................ 630

20.3 Duty Adjustment Circuit.................................................................................................... 632

20.4 Prescalers........................................................................................................................... 632

20.5 Frequency Divider............................................................................................................. 632

20.5.1 Register Configuration ......................................................................................... 633

20.5.2 Division Control Register (DIVCR) .................................................................... 633

20.5.3 Usage Notes.......................................................................................................... 634

Section 21 Power-Down State.......................................................................................... 635

21.1 Overview............................................................................................................................ 635

21.2 Register Configuration ...................................................................................................... 637

21.2.1 System Control Register (SYSCR) ...................................................................... 637

21.2.2 Module Standby Control Register H (MSTCRH)................................................ 639

21.2.3 Module Standby Control Register L (MSTCRL)................................................. 640

21.3 Sleep Mode........................................................................................................................ 642

21.3.1 Transition to Sleep Mode ..................................................................................... 642

21.3.2 Exit from Sleep Mode .......................................................................................... 642

21.4 Software Standby Mode .................................................................................................... 642

21.4.1 Transition to Software Standby Mode.................................................................. 642

21.4.2 Exit from Software Standby Mode....................................................................... 643

21.4.3 Selection of Waiting Time for Exit from Software Standby Mode...................... 643

21.4.4 Sample Application of Software Standby Mode.................................................. 645

21.4.5 Usage Note ........................................................................................................... 645

21.4.6 Cautions on Clearing the software Standby Mode of F-ZTAT Version.............. 646

21.5 Hardware Standby Mode ................................................................................................... 647

21.5.1 Transition to Hardware Standby Mode ................................................................ 647

21.5.2 Exit from Hardware Standby Mode ..................................................................... 647

21.5.3 Timing for Hardware Standby Mode ................................................................... 647

21.6 Module Standby Function.................................................................................................. 648

21.6.1 Module Standby Timing....................................................................................... 648

21.6.2 Read/Write in Module Standby............................................................................ 648

21.6.3 Usage Notes.......................................................................................................... 648

21.7 System Clock Output Disabling Function ......................................................................... 649

Section 22 Electrical Characteristics.............................................................................. 651

22.1 Electrical Characteristics of H8/3062 Mask ROM Version, H8/3061 Mask ROM Version,

and H8/3060 Mask ROM Version..................................................................................... 652

22.1.1 Absolute Maximum Ratings................................................................................. 652

xiii

22.1.2 DC Characteristics................................................................................................ 653

22.1.3 AC Characteristics................................................................................................ 664

22.1.4 A/D Conversion Characteristics........................................................................... 670

22.1.5 D/A Conversion Characteristics........................................................................... 672

22.2 Electrical Characteristics of H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version... 673

22.2.1 Absolute Maximum Ratings................................................................................. 673

22.2.2 DC Characteristics................................................................................................ 674

22.2.3 AC Characteristics................................................................................................ 682

22.2.4 A/D Conversion Characteristics........................................................................... 688

22.2.5 D/A Conversion Characteristics........................................................................... 690

22.2.6 Flash Memory Characteristics.............................................................................. 691

22.3 Electrical Characteristics of H8/3064F-ZTAT B-Mask Version ...................................... 695

22.3.1 Absolute Maximum Ratings................................................................................. 695

22.3.2 DC Characteristics................................................................................................ 696

22.3.3 AC Characteristics................................................................................................ 701

22.3.4 A/D Conversion Characteristics........................................................................... 707

22.3.5 D/A Conversion Characteristics........................................................................... 708

22.3.6 Flash Memory Characteristics.............................................................................. 709

22.4 Electrical Characteristics of H8/3064 Mask ROM B-Mask Version ................................ 711

22.4.1 Absolute Maximum Ratings................................................................................. 711

22.4.2 DC Characteristics................................................................................................ 712

22.4.3 AC Characteristics................................................................................................ 716

22.4.4 A/D Conversion Characteristics........................................................................... 722

22.4.5 D/A Conversion Characteristics........................................................................... 723

22.5 Electrical Characteristics of H8/3062F-ZTAT B-Mask Version ...................................... 724

22.5.1 Absolute Maximum Ratings................................................................................. 724

22.5.2 DC Characteristics................................................................................................ 725

22.5.3 AC Characteristics................................................................................................ 730

22.5.4 A/D Conversion Characteristics........................................................................... 736

22.5.5 D/A Conversion Characteristics........................................................................... 737

22.5.6 Flash Memory Characteristics.............................................................................. 738

22.6 Electrical Characteristics of H8/3062 Mask ROM B-Mask Version,

H8/3061 Mask ROM B-Mask Version, and H8/3060 Mask ROM B-Mask Version........ 740

22.6.1 Absolute Maximum Ratings................................................................................. 740

22.6.2 DC Characteristics................................................................................................ 741

22.6.3 AC Characteristics................................................................................................ 745

22.6.4 A/D Conversion Characteristics........................................................................... 751

22.6.5 D/A Conversion Characteristics........................................................................... 752

22.7 Operational Timing............................................................................................................ 753

22.7.1 Clock Timing........................................................................................................ 753

22.7.2 Control Signal Timing.......................................................................................... 754

22.7.3 Bus Timing........................................................................................................... 756

22.7.4 TPC and I/O Port Timing ..................................................................................... 760

xiv

+ 965 hidden pages

Hitachi HD6433060, HD6433064B, HD6433062B, HD6433061B, HD6433060B Hardware Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Cautions

Preface

Comparison of H8/3062 Series Product Specifications

List of Items Revised or Added for This Version

Contents