harman kardon HD 74 LVC 1 G 57 Service Manual

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HD74LVC1G57

Configurable Multiple–Function Gate

REJ03D0011–0300Z

Rev.3.00

Jun. 29, 2004

Description

The HD74LVC1G57 has configurable multiple–function gate in a 6-pin package. The Output state is determined by
eight patterns of 3–bit input. The user can choose the logic functions AND, NAND, NOR, EX–NOR. Low voltage and
high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power
consumption extends the battery life.

Features

• The basic gate function is lined up as renesas uni logic series.

• Supply voltage range: 1.65 to 5.5 V

Operating temperature range: –40 to +85°C

• All inputs V

All outputs V

• Output current: ±4 mA (@V

• All the logical input has hysteresis voltage for the slow transition.

• Ordering Information

Part Name Package Type Package Code

HD74LVC1G57CPE TBS-6V CP
HD74LVC1G57CLE

(Max.) = 5.5 V (@VCC = 0 V to 5.5 V)

IH

(Max.) = 5.5 V (@VCC = 0 V)

O

= 1.65 V)

CC

±8 mA (@V
±24 mA (@V
±32 mA (@V

WCSP-6 pin

= 2.3 V)

CC

= 3.0 V)

CC

= 4.5 V)

CC

TBS-6AV CL

Package

Abbreviation

Taping Abbreviation

(Quantity)

E (3,000 pcs/reel)

Article Indication

Rev.3.00 Jun. 29, 2004 page 1 of 1

Marking

Year code

Month code

K R Y M

HD74LVC1G57

Function Table

Inputs Output

IN2 IN1 IN0 Y

LLLH
LLHL
LHLH
LHHL
HLLL
HLHL
HHLH
HHHH
H: High level
L: Low level

Pin Arrangement

0.9 mm

Height 0.5 mm

0.5 mm pitch

0.17 mm 6–Ball (CP)

0.23 mm 6–Ball (CL)

Logic Diagram

34IN0

GND V

IN1

(Bottom view) (Top view)

IN0

IN1

5

2

16

Y

CC

IN2

1.4 mm

Pin#1 INDEX

Y

IN2

Rev.3.00 Jun. 29, 2004 page 2 of 9

HD74LVC1G57

Function Selection Table

Logic Function Figure No.

2–input AND 1
2–input AND with both inputs inverted 4
2–input NAND with one input inverted 2, 3
2–input OR with one input inverted 2, 3
2–input NOR 4
2–input NOR with both inputs inverted 1
2–input EX–NOR 5

Logic Configurations

V

CC

1 (IN1) (IN2) 6

A
B

A
B

Y

Y

A

) 5

2 (GND)

3 (IN0) (Y) 4

(V

CC

B

Y

V

CC

1 (IN1) (IN2) 6

A
B

A
B

Y

Y

A

) 5

2 (GND)

3 (IN0) (Y) 4

(V

CC

B

Y

Figure 1. 2–inputs AND Gate

Figure 2. 2–inputs NAND Gate
with A input inverted

V

CC

A

1 (IN1) (IN2) 6

) 5

2 (GND)

3 (IN0) (Y) 4

(V

CC

A
B

A
B

Y

Y

B

Y

A
B

A
B

Y

Y

A

1 (IN1) (IN2) 6

) 5

2 (GND)

3 (IN0) (Y) 4

(V

CC

V

CC

B

Y

Figure 4. 2–inputs NOR GateFigure 3. 2–inputs NAND Gate

with B input inverted

V

CC

1 (IN1) (IN2) 6

A
A
B

Y

2 (GND)

3 (IN0) (Y) 4

(V

) 5

CC

B

Y

Figure 5. 2–inputs EX–NOR Gate

Rev.3.00 Jun. 29, 2004 page 3 of 9