How it Works
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HD 642350
Service Manual
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harman kardon H 8 S 2350, HD 642350 Service Manual

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H8S/2350 Series
H8S/2351, HD6432351, H8S/2350, HD6412350
Hardware Manual
ADE-602-111A Rev. 2.0 3/10/03 Hitachi, Ltd. MC-Setsu
Notice
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.

Preface

The H8S/2350 Series is a series of high-performance microcontrollers with a 32-bit H8S/2000 CPU core, and a set of on-chip supporting functions required for system configuration.
The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit general registers with a 32-bit internal configuration, and a concise and optimized instruction set. The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based on the high-level language C can also be run efficiently.
The address space is divided into eight areas. The data bus width and access states can be selected for each of these areas, and various kinds of memory can be connected fast and easily.
On-chip memory consists of large-capacity ROM (H8S/2351 only) and RAM.
On-chip supporting functions include a 16-bit timer pulse unit (TPU), programmable pulse generator (PPG), watchdog timer (WDT), serial communication interface (SCI), A/D converter, D/A converter, and I/O ports.
In addition, an on-chip DMA controller (DMAC) and data transfer controller (DTC) are provided, enabling high-speed data transfer without CPU intervention.
Use of the H8S/2350 Series enables easy implementation of compact, high-performance systems capable of processing large volumes of data.
This manual describes the hardware of the H8S/2350 Series. Refer to the H8S/2600 Series and H8S/2000 Series Programming Manual for a detailed description of the instruction set.

Contents

Section 1 Overview............................................................................................................ 1
1.1 Overview............................................................................................................................ 1
1.2 Block Diagram................................................................................................................... 5
1.3 Pin Description................................................................................................................... 6
1.3.1 Pin Arrangement................................................................................................... 6
1.3.2 Pin Functions in Each Operating Mode................................................................ 8
1.3.3 Pin Functions........................................................................................................ 13
Section 2 CPU..................................................................................................................... 21
2.1 Overview............................................................................................................................ 21
2.1.1 Features................................................................................................................. 21
2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 22
2.1.3 Differences from H8/300 CPU ............................................................................. 23
2.1.4 Differences from H8/300H CPU.......................................................................... 23
2.2 CPU Operating Modes....................................................................................................... 24
2.3 Address Space.................................................................................................................... 29
2.4 Register Configuration....................................................................................................... 30
2.4.1 Overview............................................................................................................... 30
2.4.2 General Registers.................................................................................................. 31
2.4.3 Control Registers.................................................................................................. 32
2.4.4 Initial Register Values .......................................................................................... 34
2.5 Data Formats...................................................................................................................... 35
2.5.1 General Register Data Formats............................................................................. 35
2.5.2 Memory Data Formats.......................................................................................... 37
2.6 Instruction Set.................................................................................................................... 38
2.6.1 Overview............................................................................................................... 38
2.6.2 Instructions and Addressing Modes...................................................................... 39
2.6.3 Table of Instructions Classified by Function........................................................ 41
2.6.4 Basic Instruction Formats..................................................................................... 51
2.7 Addressing Modes and Effective Address Calculation...................................................... 52
2.7.1 Addressing Mode.................................................................................................. 52
2.7.2 Effective Address Calculation.............................................................................. 55
2.8 Processing States................................................................................................................ 59
2.8.1 Overview............................................................................................................... 59
2.8.2 Reset State ............................................................................................................ 60
2.8.3 Exception-Handling State..................................................................................... 61
2.8.4 Program Execution State ...................................................................................... 64
2.8.5 Bus-Released State................................................................................................ 64
2.8.6 Power-Down State................................................................................................ 64
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2.9 Basic Timing...................................................................................................................... 65
2.9.1 Overview............................................................................................................... 65
2.9.2 On-Chip Memory (ROM, RAM).......................................................................... 65
2.9.3 On-Chip Supporting Module Access Timing....................................................... 67
2.9.4 External Address Space Access Timing............................................................... 68
Section 3 MCU Operating Modes................................................................................. 69
3.1 Overview............................................................................................................................ 69
3.1.1 H8S/2350 Operating Mode Selection................................................................... 69
3.1.2 H8S/2351 Operating Mode Selection................................................................... 70
3.1.3 Register Configuration.......................................................................................... 71
3.2 Register Descriptions......................................................................................................... 71
3.2.1 Mode Control Register (MDCR).......................................................................... 71
3.2.2 System Control Register (SYSCR)....................................................................... 72
3.3 Operating Mode Descriptions............................................................................................ 73
3.3.1 Mode 1.................................................................................................................. 73
3.3.2 Mode 2 (H8S/2351 Only) ..................................................................................... 73
3.3.3 Mode 3 (H8S/2351 Only) ..................................................................................... 73
3.3.4 Mode 4.................................................................................................................. 73
3.3.5 Mode 5.................................................................................................................. 74
3.3.6 Mode 6 (H8S/2351 Only) ..................................................................................... 74
3.3.7 Mode 7 (H8S/2351 Only) ..................................................................................... 74
3.4 Pin Functions in Each Operating Mode............................................................................. 75
3.5 Memory Map in Each Operating Mode............................................................................. 75
Section 4 Exception Handling........................................................................................ 79
4.1 Overview............................................................................................................................ 79
4.1.1 Exception Handling Types and Priority................................................................ 79
4.1.2 Exception Handling Operation ............................................................................. 80
4.1.3 Exception Vector Table........................................................................................ 80
4.2 Reset................................................................................................................................... 82
4.2.1 Overview............................................................................................................... 82
4.2.2 Reset Types........................................................................................................... 82
4.2.3 Reset Sequence ..................................................................................................... 83
4.2.4 Interrupts after Reset............................................................................................. 84
4.2.5 State of On-Chip Supporting Modules after Reset Release.................................. 84
4.3 Traces................................................................................................................................. 85
4.4 Interrupts............................................................................................................................ 86
4.5 Trap Instruction.................................................................................................................. 87
4.6 Stack Status after Exception Handling .............................................................................. 88
4.7 Notes on Use of the Stack.................................................................................................. 89
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Section 5 Interrupt Controller......................................................................................... 91
5.1 Overview............................................................................................................................ 91
5.1.1 Features................................................................................................................. 91
5.1.2 Block Diagram...................................................................................................... 92
5.1.3 Pin Configuration.................................................................................................. 93
5.1.4 Register Configuration.......................................................................................... 93
5.2 Register Descriptions......................................................................................................... 94
5.2.1 System Control Register (SYSCR)....................................................................... 94
5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK) ............................................ 95
5.2.3 IRQ Enable Register (IER)................................................................................... 96
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ..................................... 97
5.2.5 IRQ Status Register (ISR) .................................................................................... 98
5.3 Interrupt Sources................................................................................................................ 99
5.3.1 External Interrupts................................................................................................ 99
5.3.2 Internal Interrupts.................................................................................................. 100
5.3.3 Interrupt Exception Handling Vector Table ......................................................... 100
5.4 Interrupt Operation............................................................................................................. 104
5.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 104
5.4.2 Interrupt Control Mode 0...................................................................................... 107
5.4.3 Interrupt Control Mode 2...................................................................................... 109
5.4.4 Interrupt Exception Handling Sequence............................................................... 111
5.4.5 Interrupt Response Times..................................................................................... 113
5.5 Usage Notes ....................................................................................................................... 114
5.5.1 Contention between Interrupt Generation and Disabling ..................................... 114
5.5.2 Instructions that Disable Interrupts....................................................................... 115
5.5.3 Times when Interrupts are Disabled..................................................................... 115
5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... 115
5.6 DTC and DMAC Activation by Interrupt.......................................................................... 116
5.6.1 Overview............................................................................................................... 116
5.6.2 Block Diagram...................................................................................................... 116
5.6.3 Operation .............................................................................................................. 117
Section 6 Bus Controller.................................................................................................. 119
6.1 Overview............................................................................................................................ 119
6.1.1 Features................................................................................................................. 119
6.1.2 Block Diagram...................................................................................................... 121
6.1.3 Pin Configuration.................................................................................................. 122
6.1.4 Register Configuration.......................................................................................... 123
6.2 Register Descriptions......................................................................................................... 124
6.2.1 Bus Width Control Register (ABWCR) ............................................................... 124
6.2.2 Access State Control Register (ASTCR).............................................................. 125
6.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 126
6.2.4 Bus Control Register H (BCRH).......................................................................... 130
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6.2.5 Bus Control Register L (BCRL)........................................................................... 132
6.2.6 Memory Control Register (MCR) ........................................................................ 134
6.2.7 DRAM Control Register (DRAMCR).................................................................. 137
6.2.8 Refresh Timer/Counter (RTCNT) ........................................................................ 140
6.2.9 Refresh Time Constant Register (RTCOR).......................................................... 140
6.3 Overview of Bus Control................................................................................................... 141
6.3.1 Area Partitioning................................................................................................... 141
6.3.2 Bus Specifications ................................................................................................ 142
6.3.3 Memory Interfaces................................................................................................ 143
6.3.4 Advanced Mode.................................................................................................... 144
6.3.5 Areas in Normal Mode.......................................................................................... 145
6.3.6 Chip Select Signals............................................................................................... 146
6.4 Basic Bus Interface............................................................................................................ 147
6.4.1 Overview............................................................................................................... 147
6.4.2 Data Size and Data Alignment.............................................................................. 147
6.4.3 Valid Strobes........................................................................................................ 149
6.4.4 Basic Timing......................................................................................................... 150
6.4.5 Wait Control.......................................................................................................... 158
6.5 DRAM Interface ................................................................................................................ 160
6.5.1 Overview............................................................................................................... 160
6.5.2 Setting DRAM Space............................................................................................ 160
6.5.3 Address Multiplexing............................................................................................ 160
6.5.4 Data Bus................................................................................................................ 161
6.5.5 Pins Used for DRAM Interface ............................................................................ 161
6.5.6 Basic Timing......................................................................................................... 162
6.5.7 Precharge State Control........................................................................................ 163
6.5.8 Wait Control ......................................................................................................... 164
6.5.9 Byte Access Control ............................................................................................. 166
6.5.10 Burst Operation..................................................................................................... 168
6.5.11 Refresh Control..................................................................................................... 171
6.6 DMAC Single Address Mode and DRAM Interface......................................................... 174
6.6.1 When DDS = 1...................................................................................................... 174
6.6.2 When DDS = 0...................................................................................................... 175
6.7 Burst ROM Interface.......................................................................................................... 176
6.7.1 Overview............................................................................................................... 176
6.7.2 Basic Timing......................................................................................................... 176
6.7.3 Wait Control.......................................................................................................... 178
6.8 Idle Cycle........................................................................................................................... 179
6.8.1 Operation .............................................................................................................. 179
6.8.2 Pin States in Idle Cycle......................................................................................... 183
6.9 Write Data Buffer Function ............................................................................................... 184
6.10 Bus Release........................................................................................................................ 185
6.10.1 Overview............................................................................................................... 185
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6.10.2 Operation .............................................................................................................. 185
6.10.3 Pin States in External Bus Released State............................................................ 186
6.10.4 Transition Timing ................................................................................................. 187
6.10.5 Usage Note............................................................................................................ 188
6.11 Bus Arbitration................................................................................................................... 188
6.11.1 Overview............................................................................................................... 188
6.11.2 Operation .............................................................................................................. 188
6.11.3 Bus Transfer Timing............................................................................................. 189
6.11.4 External Bus Release Usage Note ........................................................................ 189
6.12 Resets and the Bus Controller............................................................................................ 190
Section 7 DMA Controller.............................................................................................. 191
7.1 Overview............................................................................................................................ 191
7.1.1 Features................................................................................................................. 191
7.1.2 Block Diagram...................................................................................................... 192
7.1.3 Overview of Functions.......................................................................................... 193
7.1.4 Pin Configuration.................................................................................................. 195
7.1.5 Register Configuration.......................................................................................... 196
7.2 Register Descriptions (1) (Short Address Mode) .............................................................. 197
7.2.1 Memory Address Registers (MAR)...................................................................... 198
7.2.2 I/O Address Register (IOAR) ............................................................................... 199
7.2.3 Execute Transfer Count Register (ETCR)............................................................ 199
7.2.4 DMA Control Register (DMACR) ....................................................................... 200
7.2.5 DMA Band Control Register (DMABCR)........................................................... 205
7.3 Register Descriptions (2) (Full Address Mode)................................................................. 211
7.3.1 Memory Address Register (MAR)........................................................................ 211
7.3.2 I/O Address Register (IOAR) ............................................................................... 211
7.3.3 Execute Transfer Count Register (ETCR)............................................................ 212
7.3.4 DMA Control Register (DMACR) ....................................................................... 213
7.3.5 DMA Band Control Register (DMABCR)........................................................... 217
7.4 Register Descriptions (3) ................................................................................................... 222
7.4.1 DMA Write Enable Register (DMAWER)........................................................... 222
7.4.2 DMA Terminal Control Register (DMATCR)..................................................... 225
7.4.3 Module Stop Control Register (MSTPCR)........................................................... 226
7.5 Operation............................................................................................................................ 227
7.5.1 Transfer Modes..................................................................................................... 227
7.5.2 Sequential Mode ................................................................................................... 230
7.5.3 Idle Mode.............................................................................................................. 233
7.5.4 Repeat Mode......................................................................................................... 236
7.5.5 Single Address Mode............................................................................................ 240
7.5.6 Normal Mode........................................................................................................ 243
7.5.7 Block Transfer Mode............................................................................................ 246
7.5.8 DMAC Activation Sources................................................................................... 252
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7.5.9 Basic DMAC Bus Cycles...................................................................................... 255
7.5.10 DMAC Bus Cycles (Dual Address Mode) ........................................................... 256
7.5.11 DMAC Bus Cycles (Single Address Mode)......................................................... 264
7.5.12 Write Data Buffer Function.................................................................................. 270
7.5.13 DMAC Multi-Channel Operation......................................................................... 271
7.5.14 Relation Between External Bus Requests, Refresh Cycles, the DTC,
and the DMAC...................................................................................................... 273
7.5.15 NMI Interrupts and DMAC.................................................................................. 274
7.5.16 Forced Termination of DMAC Operation............................................................ 275
7.5.17 Clearing Full Address Mode................................................................................. 276
7.6 Interrupts............................................................................................................................ 277
7.7 Usage Notes ....................................................................................................................... 278
Section 8 Data Transfer Controller............................................................................... 283
8.1 Overview............................................................................................................................ 283
8.1.1 Features................................................................................................................. 283
8.1.2 Block Diagram...................................................................................................... 284
8.1.3 Register Configuration.......................................................................................... 285
8.2 Register Descriptions......................................................................................................... 286
8.2.1 DTC Mode Register A (MRA)............................................................................. 286
8.2.2 DTC Mode Register B (MRB).............................................................................. 288
8.2.3 DTC Source Address Register (SAR) .................................................................. 289
8.2.4 DTC Destination Address Register (DAR) .......................................................... 289
8.2.5 DTC Transfer Count Register A (CRA)............................................................... 289
8.2.6 DTC Transfer Count Register B (CRB)................................................................ 290
8.2.7 DTC Enable Registers (DTCER).......................................................................... 290
8.2.8 DTC Vector Register (DTVECR) ........................................................................ 291
8.2.9 Module Stop Control Register (MSTPCR)........................................................... 292
8.3 Operation............................................................................................................................ 293
8.3.1 Overview............................................................................................................... 293
8.3.2 Activation Sources................................................................................................ 295
8.3.3 DTC Vector Table ................................................................................................ 296
8.3.4 Location of Register Information in Address Space............................................. 299
8.3.5 Normal Mode........................................................................................................ 300
8.3.6 Repeat Mode......................................................................................................... 301
8.3.7 Block Transfer Mode............................................................................................ 302
8.3.8 Chain Transfer...................................................................................................... 304
8.3.9 Operation Timing.................................................................................................. 305
8.3.10 Number of DTC Execution States........................................................................ 306
8.3.11 Procedures for Using DTC.................................................................................... 308
8.3.12 Examples of Use of the DTC................................................................................ 309
8.4 Interrupts............................................................................................................................ 311
8.5 Usage Notes ....................................................................................................................... 312
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Section 9 I/O Ports............................................................................................................. 313
9.1 Overview............................................................................................................................ 313
9.2 Port 1.................................................................................................................................. 319
9.2.1 Overview............................................................................................................... 319
9.2.2 Register Configuration.......................................................................................... 320
9.2.3 Pin Functions........................................................................................................ 322
9.3 Port 2.................................................................................................................................. 330
9.3.1 Overview............................................................................................................... 330
9.3.2 Register Configuration.......................................................................................... 331
9.3.3 Pin Functions........................................................................................................ 333
9.4 Port 3.................................................................................................................................. 341
9.4.1 Overview............................................................................................................... 341
9.4.2 Register Configuration.......................................................................................... 341
9.4.3 Pin Functions........................................................................................................ 344
9.5 Port 4.................................................................................................................................. 346
9.5.1 Overview............................................................................................................... 346
9.5.2 Register Configuration.......................................................................................... 347
9.5.3 Pin Functions........................................................................................................ 347
9.6 Port 5.................................................................................................................................. 348
9.6.1 Overview............................................................................................................... 348
9.6.2 Register Configuration.......................................................................................... 348
9.6.3 Pin Functions........................................................................................................ 350
9.7 Port 6.................................................................................................................................. 351
9.7.1 Overview............................................................................................................... 351
9.7.2 Register Configuration.......................................................................................... 352
9.7.3 Pin Functions........................................................................................................ 354
9.8 Port A................................................................................................................................. 356
9.8.1 Overview............................................................................................................... 356
9.8.2 Register Configuration.......................................................................................... 357
9.8.3 Pin Functions........................................................................................................ 360
9.8.4 MOS Input Pull-Up Function [H8S/2351 Only] .................................................. 362
9.9 Port B ................................................................................................................................. 363
9.9.1 Overview............................................................................................................... 363
9.9.2 Register Configuration [H8S/2351 Only]............................................................. 364
9.9.3 Pin Functions........................................................................................................ 366
9.9.4 MOS Input Pull-Up Function [H8S/2351 Only] .................................................. 368
9.10 Port C ................................................................................................................................. 369
9.10.1 Overview............................................................................................................... 369
9.10.2 Register Configuration [H8S/2351 Only]............................................................. 370
9.10.3 Pin Functions........................................................................................................ 372
9.10.4 MOS Input Pull-Up Function [H8S/2351 Only] .................................................. 374
9.11 Port D................................................................................................................................. 375
9.11.1 Overview............................................................................................................... 375
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9.11.2 Register Configuration [H8S/2351 Only]............................................................. 376
9.11.3 Pin Functions........................................................................................................ 378
9.11.4 MOS Input Pull-Up Function [H8S/2351]............................................................ 379
9.12 Port E.................................................................................................................................. 380
9.12.1 Overview............................................................................................................... 380
9.12.2 Register Configuration.......................................................................................... 381
9.12.3 Pin Functions........................................................................................................ 383
9.12.4 MOS Input Pull-Up Function [H8S/2351 Only] .................................................. 384
9.13 Port F.................................................................................................................................. 385
9.13.1 Overview............................................................................................................... 385
9.13.2 Register Configuration.......................................................................................... 386
9.13.3 Pin Functions........................................................................................................ 388
9.14 Port G................................................................................................................................. 391
9.14.1 Overview............................................................................................................... 391
9.14.2 Register Configuration.......................................................................................... 392
9.14.3 Pin Functions........................................................................................................ 394
Section 10 16-Bit Timer Pulse Unit (TPU).................................................................. 397
10.1 Overview............................................................................................................................ 397
10.1.1 Features................................................................................................................. 397
10.1.2 Block Diagram...................................................................................................... 401
10.1.3 Pin Configuration.................................................................................................. 402
10.1.4 Register Configuration.......................................................................................... 404
10.2 Register Descriptions......................................................................................................... 406
10.2.1 Timer Control Register (TCR).............................................................................. 406
10.2.2 Timer Mode Register (TMDR)............................................................................. 411
10.2.3 Timer I/O Control Register (TIOR)...................................................................... 413
10.2.4 Timer Interrupt Enable Register (TIER)............................................................... 426
10.2.5 Timer Status Register (TSR) ................................................................................ 429
10.2.6 Timer Counter (TCNT)......................................................................................... 433
10.2.7 Timer General Register (TGR)............................................................................. 434
10.2.8 Timer Start Register (TSTR)................................................................................ 435
10.2.9 Timer Synchro Register (TSYR).......................................................................... 436
10.2.10 Module Stop Control Register (MSTPCR)........................................................... 437
10.3 Interface to Bus Master...................................................................................................... 438
10.3.1 16-Bit Registers.................................................................................................... 438
10.3.2 8-Bit Registers...................................................................................................... 438
10.4 Operation............................................................................................................................ 440
10.4.1 Overview............................................................................................................... 440
10.4.2 Basic Functions..................................................................................................... 441
10.4.3 Synchronous Operation ........................................................................................ 447
10.4.4 Buffer Operation................................................................................................... 449
10.4.5 Cascaded Operation.............................................................................................. 453
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10.4.6 PWM Modes......................................................................................................... 455
10.4.7 Phase Counting Mode........................................................................................... 460
10.5 Interrupts............................................................................................................................ 467
10.5.1 Interrupt Sources and Priorities............................................................................ 467
10.5.2 DTC/DMAC Activation........................................................................................ 469
10.5.3 A/D Converter Activation..................................................................................... 469
10.6 Operation Timing............................................................................................................... 470
10.6.1 Input/Output Timing............................................................................................. 470
10.6.2 Interrupt Signal Timing ........................................................................................ 474
10.7 Usage Notes ....................................................................................................................... 478
Section 11 Programmable Pulse Generator (PPG)..................................................... 489
11.1 Overview............................................................................................................................ 489
11.1.1 Features................................................................................................................. 489
11.1.2 Block Diagram...................................................................................................... 490
11.1.3 Pin Configuration.................................................................................................. 491
11.1.4 Registers................................................................................................................ 492
11.2 Register Descriptions......................................................................................................... 493
11.2.1 Next Data Enable Registers H and L (NDERH, NDERL) ................................... 493
11.2.2 Output Data Registers H and L (PODRH, PODRL) ............................................ 494
11.2.3 Next Data Registers H and L (NDRH, NDRL).................................................... 495
11.2.4 Notes on NDR Access.......................................................................................... 495
11.2.5 PPG Output Control Register (PCR).................................................................... 497
11.2.6 PPG Output Mode Register (PMR)...................................................................... 499
11.2.7 Port 1 Data Direction Register (P1DDR).............................................................. 502
11.2.8 Port 2 Data Direction Register (P2DDR).............................................................. 502
11.2.9 Module Stop Control Register (MSTPCR)........................................................... 503
11.3 Operation............................................................................................................................ 504
11.3.1 Overview............................................................................................................... 504
11.3.2 Output Timing ...................................................................................................... 505
11.3.3 Normal Pulse Output ............................................................................................ 506
11.3.4 Non-Overlapping Pulse Output ............................................................................ 508
11.3.5 Inverted Pulse Output ........................................................................................... 511
11.3.6 Pulse Output Triggered by Input Capture............................................................. 512
11.4 Usage Notes ....................................................................................................................... 513
Section 12 Watchdog Timer.............................................................................................. 515
12.1 Overview............................................................................................................................ 515
12.1.1 Features................................................................................................................. 515
12.1.2 Block Diagram...................................................................................................... 516
12.1.3 Pin Configuration.................................................................................................. 517
12.1.4 Register Configuration.......................................................................................... 517
12.2 Register Descriptions......................................................................................................... 518
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12.2.1 Timer Counter (TCNT)......................................................................................... 518
12.2.2 Timer Control/Status Register (TCSR) ................................................................ 518
12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 520
12.2.4 Notes on Register Access...................................................................................... 522
12.3 Operation............................................................................................................................ 524
12.3.1 Watchdog Timer Operation.................................................................................. 524
12.3.2 Interval Timer Operation...................................................................................... 525
12.3.3 Timing of Setting Overflow Flag (OVF).............................................................. 525
12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF).......................... 526
12.4 Interrupts............................................................................................................................ 527
12.5 Usage Notes ....................................................................................................................... 527
12.5.1 Contention between Timer Counter (TCNT) Write and Increment...................... 527
12.5.2 Changing Value of CKS2 to CKS0...................................................................... 527
12.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 528
12.5.4 System Reset by WDTOVF Signal ...................................................................... 528
12.5.5 Internal Reset in Watchdog Timer Mode ............................................................. 528
Section 13 Serial Communication Interface (SCI)..................................................... 529
13.1 Overview............................................................................................................................ 529
13.1.1 Features................................................................................................................. 529
13.1.2 Block Diagram...................................................................................................... 531
13.1.3 Pin Configuration.................................................................................................. 532
13.1.4 Register Configuration.......................................................................................... 533
13.2 Register Descriptions......................................................................................................... 534
13.2.1 Receive Shift Register (RSR) ............................................................................... 534
13.2.2 Receive Data Register (RDR)............................................................................... 534
13.2.3 Transmit Shift Register (TSR).............................................................................. 535
13.2.4 Transmit Data Register (TDR).............................................................................. 535
13.2.5 Serial Mode Register (SMR)................................................................................ 536
13.2.6 Serial Control Register (SCR).............................................................................. 539
13.2.7 Serial Status Register (SSR) ................................................................................. 543
13.2.8 Bit Rate Register (BRR) ....................................................................................... 546
13.2.9 Smart Card Mode Register (SCMR)..................................................................... 555
13.2.10 Module Stop Control Register (MSTPCR)........................................................... 556
13.3 Operation............................................................................................................................ 557
13.3.1 Overview............................................................................................................... 557
13.3.2 Operation in Asynchronous Mode........................................................................ 559
13.3.3 Multiprocessor Communication Function............................................................ 570
13.3.4 Operation in Clocked Synchronous Mode............................................................ 578
13.4 SCI Interrupts..................................................................................................................... 586
13.5 Usage Notes ....................................................................................................................... 588
x
Section 14 Smart Card Interface...................................................................................... 593
14.1 Overview............................................................................................................................ 593
14.1.1 Features................................................................................................................. 593
14.1.2 Block Diagram...................................................................................................... 594
14.1.3 Pin Configuration.................................................................................................. 595
14.1.4 Register Configuration.......................................................................................... 596
14.2 Register Descriptions......................................................................................................... 597
14.2.1 Smart Card Mode Register (SCMR)..................................................................... 597
14.2.2 Serial Status Register (SSR) ................................................................................. 598
14.2.3 Serial Mode Register (SMR)................................................................................ 599
14.2.4 Serial Control Register (SCR).............................................................................. 600
14.3 Operation............................................................................................................................ 601
14.3.1 Overview............................................................................................................... 601
14.3.2 Pin Connections.................................................................................................... 602
14.3.3 Data Format.......................................................................................................... 603
14.3.4 Register Settings ................................................................................................... 605
14.3.5 Clock..................................................................................................................... 607
14.3.6 Data Transfer Operations...................................................................................... 609
14.3.7 Operation in GSM Mode...................................................................................... 616
14.4 Usage Notes ....................................................................................................................... 617
Section 15 A/D Converter.................................................................................................. 621
15.1 Overview............................................................................................................................ 621
15.1.1 Features................................................................................................................. 621
15.1.2 Block Diagram...................................................................................................... 622
15.1.3 Pin Configuration.................................................................................................. 623
15.1.4 Register Configuration.......................................................................................... 624
15.2 Register Descriptions......................................................................................................... 625
15.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 625
15.2.2 A/D Control/Status Register (ADCSR)................................................................ 626
15.2.3 A/D Control Register (ADCR) ............................................................................. 628
15.2.4 Module Stop Control Register (MSTPCR)........................................................... 629
15.3 Interface to Bus Master...................................................................................................... 630
15.4 Operation............................................................................................................................ 631
15.4.1 Single Mode (SCAN = 0) ..................................................................................... 631
15.4.2 Scan Mode (SCAN = 1)........................................................................................ 633
15.4.3 Input Sampling and A/D Conversion Time.......................................................... 635
15.4.4 External Trigger Input Timing.............................................................................. 636
15.5 Interrupts............................................................................................................................ 637
15.6 Usage Notes ....................................................................................................................... 637
Section 16 D/A Converter.................................................................................................. 643
16.1 Overview............................................................................................................................ 643
xi
16.1.1 Features................................................................................................................. 643
16.1.2 Block Diagram...................................................................................................... 644
16.1.3 Pin Configuration.................................................................................................. 645
16.1.4 Register Configuration.......................................................................................... 645
16.2 Register Descriptions......................................................................................................... 646
16.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1).................................................. 646
16.2.2 D/A Control Register (DACR) ............................................................................. 646
16.2.3 Module Stop Control Register (MSTPCR)........................................................... 648
16.3 Operation............................................................................................................................ 649
Section 17 RAM.................................................................................................................... 651
17.1 Overview............................................................................................................................ 651
17.1.1 Block Diagram...................................................................................................... 651
17.1.2 Register Configuration.......................................................................................... 652
17.2 Register Descriptions......................................................................................................... 652
17.2.1 System Control Register (SYSCR)....................................................................... 652
17.3 Operation............................................................................................................................ 653
17.4 Usage Note......................................................................................................................... 653
Section 18 ROM (H8S/2351 Only)................................................................................. 655
18.1 Overview............................................................................................................................ 655
18.1.1 Block Diagram...................................................................................................... 655
18.2 Operation............................................................................................................................ 656
Section 19 Clock Pulse Generator................................................................................... 657
19.1 Overview............................................................................................................................ 657
19.1.1 Block Diagram...................................................................................................... 657
19.1.2 Register Configuration.......................................................................................... 658
19.2 Register Descriptions......................................................................................................... 659
19.2.1 System Clock Control Register (SCKCR)............................................................ 659
19.3 Oscillator............................................................................................................................ 660
19.3.1 Connecting a Crystal Resonator............................................................................ 660
19.3.2 External Clock Input............................................................................................. 662
19.4 Duty Adjustment Circuit.................................................................................................... 664
19.5 Medium-Speed Clock Divider ........................................................................................... 664
19.6 Bus Master Clock Selection Circuit................................................................................... 664
Section 20 Power-Down Modes ...................................................................................... 665
20.1 Overview............................................................................................................................ 665
20.1.1 Register Configuration.......................................................................................... 666
20.2 Register Descriptions......................................................................................................... 667
20.2.1 Standby Control Register (SBYCR)..................................................................... 667
20.2.2 System Clock Control Register (SCKCR)............................................................ 668
xii
20.2.3 Module Stop Control Register (MSTPCR)........................................................... 669
20.3 Medium-Speed Mode......................................................................................................... 670
20.4 Sleep Mode ........................................................................................................................ 671
20.5 Module Stop Mode ............................................................................................................ 671
20.5.1 Module Stop Mode ............................................................................................... 671
20.5.2 Usage Notes.......................................................................................................... 672
20.6 Software Standby Mode..................................................................................................... 673
20.6.1 Software Standby Mode........................................................................................ 673
20.6.2 Clearing Software Standby Mode......................................................................... 673
20.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode... 674
20.6.4 Software Standby Mode Application Example .................................................... 674
20.6.5 Usage Notes.......................................................................................................... 675
20.7 Hardware Standby Mode ................................................................................................... 676
20.7.1 Hardware Standby Mode...................................................................................... 676
20.7.2 Hardware Standby Mode Timing ......................................................................... 676
20.8 ø Clock Output Disabling Function ................................................................................... 677
Section 21 Electrical Characteristics.............................................................................. 679
21.1 Absolute Maximum Ratings.............................................................................................. 679
21.2 DC Characteristics ............................................................................................................. 680
21.3 AC Characteristics ............................................................................................................. 685
21.3.1 Clock Timing........................................................................................................ 686
21.3.2 Control Signal Timing.......................................................................................... 688
21.3.3 Bus Timing ........................................................................................................... 690
21.3.4 DMAC Timing...................................................................................................... 700
21.3.5 Timing of On-Chip Supporting Modules.............................................................. 704
21.4 A/D Conversion Characteristics ........................................................................................ 709
21.5 D/A Convervion Characteristics........................................................................................ 710
21.6 Usage Note......................................................................................................................... 710
Appendix A Instruction Set............................................................................................... 711
A.1 Instruction List................................................................................................................... 711
A.2 Instruction Codes ............................................................................................................... 735
A.3 Operation Code Map.......................................................................................................... 750
A.4 Number of States Required for Instruction Execution....................................................... 754
A.5 Bus States During Instruction Execution........................................................................... 765
A.6 Condition Code Modification ............................................................................................ 779
Appendix B Internal I/O Register................................................................................... 785
B.1 Addresses ........................................................................................................................... 785
B.2 Functions............................................................................................................................ 794
xiii
Appendix C I/O Port Block Diagrams........................................................................... 913
C.1 Port 1 Block Diagram........................................................................................................ 913
C.2 Port 2 Block Diagram........................................................................................................ 916
C.3 Port 3 Block Diagram........................................................................................................ 917
C.4 Port 4 Block Diagram........................................................................................................ 920
C.5 Port 5 Block Diagram........................................................................................................ 921
C.6 Port 6 Block Diagram........................................................................................................ 923
C.7 Port A Block Diagram........................................................................................................ 929
C.8 Port B Block Diagram........................................................................................................ 935
C.9 Port C Block Diagram........................................................................................................ 937
C.10 Port D Block Diagram........................................................................................................ 939
C.11 Port E Block Diagram........................................................................................................ 941
C.12 Port F Block Diagram........................................................................................................ 943
C.13 Port G Block Diagram........................................................................................................ 951
Appendix D Pin States........................................................................................................ 955
D.1 Port States in Each Mode [H8S/2351] ............................................................................... 955
D.2 Port States in Each Mode [H8S/2350] ............................................................................... 959
Appendix E Pin States at Power-On.............................................................................. 962
E.1 When Pins Settle from an Indeterminate State at Power-On............................................. 962
E.2 When Pins Settle from the High-Impedance State at Power-On....................................... 963
Appendix F Timing of Transition to and Recovery from Hardware
Standby Mode
............................................................................................... 964
Appendix G Product Code Lineup.................................................................................. 965
Appendix H Package Dimensions................................................................................... 966
xiv

Section 1 Overview

1.1 Overview

The H8S/2350 Series is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2000 CPU, employing Hitachi's proprietary architecture, and equipped with peripheral functions on-chip.
The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series.
On-chip peripheral functions required for system configuration include DMA controller (DMAC) and data transfer controller (DTC) bus masters, ROM (H8S/2351 only) and RAM memory, a16-bit timer-pulse unit (TPU), programmable pulse generator (PPG), watchdog timer (WDT), serial communication interface (SCI), A/D converter, D/A converter, and I/O ports.
The H8S/2351 has on-chip mask ROM.
The H8S/2351 supports seven operating modes (modes 1 to 7), while the H8S/2350 supports three operating modes (modes 1, 4, and 5). There is a choice of address space and single-chip mode or expansion mode.
The features of the H8S/2350 Series are shown in Table 1-1.
1
Table 1-1 Overview
Item Specification
CPU • General-register machine
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers
or eight 32-bit registers)
• High-speed operation suitable for realtime controlMaximum clock rate: 20 MHzHigh-speed arithmetic operations
8/16/32-bit register-register add/subtract : 50 ns 16 × 16-bit register-register multiply : 1000 ns 32 ÷ 16-bit register-register divide : 1000 ns
• Instruction set suitable for high-speed operationSixty-five basic instructions8/16/32-bit move/arithmetic and logic instructionsUnsigned/signed multiply and divide instructionsPowerful bit-manipulation instructions
• Two CPU operating modesNormal mode : 64-kbyte address spaceAdvanced mode : 16-Mbyte address space
Bus controller • Address space divided into 8 areas, with bus specifications settable
independently for each area
• Chip select output possible for each area
• Choice of 8-bit or 16-bit access space for each area
• 2-state or 3-state access space can be designated for each area
• Number of program wait states can be set for each area
• Burst ROM directly connectable
• Maximum 8-Mbyte DRAM directly connectable (or use of interval timer
possible)
• External bus release function
DMA controller (DMAC)
• Choice of short address mode or full address mode
• 4 channels in short address mode
• 2 channels in full address mode
• Transfer possible in repeat mode, block transfer mode, etc.
• Single address mode transfer possible
• Can be activated by internal interrupt
2
Table 1-1 Overview (cont)
Item Specification
Data transfer controller (DTC)
16-bit timer-pulse unit (TPU)
Programmable pulse generator (PPG)
Watchdog timer • Watchdog timer or interval timer selectable Serial communica-
tion interface (SCI) 2 channels
A/D converter • Resolution: 10 bits
D/A converter • Resolution: 8 bits
I/O ports • 87 I/O pins, 8 input-only pins Memory • Mask ROM
• Can be activated by internal interrupt or software
• Multiple transfers or multiple types of transfer possible for one activation
source
• Transfer possible in repeat mode, block transfer mode, etc.
• Request can be sent to CPU for interrupt that activated DTC
• 6-channel 16-bit timer on-chip
• Pulse I/O processing capability for up to 16 pins'
• Automatic 2-phase encoder count capability
• Maximum 16-bit pulse output possible with TPU as time base
• Output trigger selectable in 4-bit groups
• Non-overlap margin can be set
• Direct output or inverse output setting possible
• Asynchronous mode or synchronous mode selectable
• Multiprocessor communication function
• Smart card interface function
• Input: 8 channels
• High-speed conversion : 6.7 µs minimum conversion time
(at 20 MHz operation)
• Single or scan mode selectable
• Sample and hold circuit
• A/D conversion can be activated by external trigger or timer trigger
• Output: 2 channels
• High-speed static RAM
Product Name ROM RAM
H8S/2350 — 2 kbytes H8S/2351 64 kbytes 2 kbytes
Interrupt controller • Nine external interrupt pins (NMI, IRQ0 to IRQ7)
• 42 internal interrupt sources
• Eight priority levels settable
3
Table 1-1 Overview (cont)
Item Specification
Power-down state • Medium-speed mode
• Sleep mode
• Module stop mode
• Software standby mode
• Hardware standby mode
Operating modes Seven MCU operating modes
CPU Operating
Mode
Mode
1 Normal On-chip ROM disabled Disabled
2* On-chip ROM enabled Enabled
3* Single-chip mode Enabled — 4 Advanced On-chip ROM disabled Disabled
5 On-chip ROM disabled Disabled
6* On-chip ROM enabled Enabled
7* Single-chip mode Enabled — Note: *Only applies to the H8S/2351.
Clock pulse generator
Packages • 120-pin plastic TQFP (TFP-120)
Product lineup Model Name
• Built-in duty correction circuit
• 128-pin plastic QFP (FP-128)
ROMless Version
— HD6432351 64 k/2 k TFP-120
HD6412350 — —/2 k TFP-120
Description ROM
expansion mode
expansion mode
expansion mode
expansion mode
expansion mode
Mask ROM Version
External Data Bus
On-Chip
ROM/RAM (Bytes) Packages
Initial Maximum Value Value
8 bits 16 bits
8 bits 16 bits
16 bits 16 bits
8 bits 16 bits
8 bits 16 bits
FP-128
FP-128
4

1.2 Block Diagram

y
Figure 1-1 shows an internal block diagram of the H8S/2350 Series.
15
14
13
12
11
10
9
/D PD
8
/D
/D
/D
3
2
1
0
PD
PD
PD
VCCVCCVCCVCCVCCVSSVSSVSSVSSVSSVSSVSSV
/D
/D
/D
/D
7
6
5
PD
PD
PD
4
PD
SS
7
6
5
4
3
2
1
/D
/D
/D
/D
7
6
5
PE
PE
PE
PE
0
/D
/D
/D
/D
4
3
2
1
0
PE
PE
PE
PE
PF
/WAIT /LCAS/BREQO
2
P67/CS7/IRQ3 P6
6
P6
P6
/TEND0/CS5
P6
1
/DREQ0/CS4
P6
0
MD MD MD
EXTAL
XTAL
STBY
RES
WDTOVF
NMI
PF7/ø
/AS
PF
6
/RD
PF
5
/HWR
PF
4
/LWR
PF
3
/BACK
PF
1
/BREQ
PF
0
PG
/CS0
4
/CS1
PG
3
/CS2
PG
2
PG
/CS3
1
/CAS
PG
0
/CS6/IRQ2
/IRQ1
P6
5
/IRQ0
P6
4
/TEND1
3
/DREQ1
2
WDT
SCI
Port E
Internal data bus
Internal address bus
Bus controller
Peripheral data bus
Peripheral address bus
Port
Port
Port
Port
Port
A
B
C
3
5
PA
/IRQ7
7/A23
PA
/IRQ6
6/A22
/IRQ5
PA
5/A21
/IRQ4
PA
4/A20
PA
3/A19
PA2/A
18
PA1/A
17
PA0/A
16
PB7/A
15
PB6/A
14
PB5/A
13
PB4/A
12
PB3/A
11
PB2/A
10
PB1/A
9
PB0/A
8
PC7/A
7
PC6/A
6
PC5/A
5
PC4/A
4
PC3/A
3
PC2/A
2
PC1/A
1
PC0/A
0
P35/SCK1
/SCK0
P3
4
P3
/RxD1
3
/RxD0
P3
2
/TxD1
P3
1
/TxD0
P3
0
P5
0
P5
1
P5
2
P53/ADTRG
Port D
2 1 0
H8S/2000 CPU
generator
Clock pulse
Port
Interrupt controller
*
ROM
F
DTC
DMAC
RAM
Port
G
Port
TPU
6
PPG
D/A converter
A/D converter
Note: * Onl
applies to the H8S/2351.
/PO0/TIOCA3
/PO1/TIOCB3
/PO2/TIOCC3
0
/PO14/TIOCA2
6
P1
/PO15/TIOCB2/TCLKD
7
P1
1
2
P2
P2
P2
/PO8/TIOCA0/DACK0
/PO9/TIOCB0/DACK1
0
1
P1
P1
/PO10/TIOCC0/TCLKA
/PO11/TIOCD0/TCLKB
2
3
P1
P1
/PO12/TIOCA1
4
P1
/PO13/TIOCB1/TCLKC
5
P1
Figure 1-1 Block Diagram
/PO4/TIOCA4
/PO3/TIOCD3
4
3
P2
P2
/PO5/TIOCB4
/PO6/TIOCA5
5
6
P2
P2
V
/PO7/TIOCB5
7
P2
Port 4Port 2Port 1
ref
SS
CC
AV
/AN5
/AN4
/AN3
/AN2
/AN1
AV
5
P4
P4
/AN7/DA1
/AN6/DA0
7
6
P4
P4
/AN0
4
3
2
1
0
P4
P4
P4
P4
5

1.3 Pin Description

1.3.1 Pin Arrangement

Figures 1-2 and 1-3 show the pin arrangement of the H8S/2350 Series.
/BREQ
/BACK
/LCAS/WAIT /BREQO
/LWR
/HWR
/RD
/AS
P5
P53/ADTRG
AV
V
P40/AN0
/AN1
P4
1
P4
/AN2
2
/AN3
P4
3
/AN4
P4
4
P4
/AN5
5
/AN6/DA0
P4
6
/AN7/DA1
P4
7
AV
V
P17/PO15/TIOCB2/TCLKD
P1
/PO14/TIOCA2
6
/PO13/TIOCB1/TCLKC
P1
5
/PO12/TIOCA1
P1 P1 P1
4
/PO11/TIOCD0/TCLKB
3
/PO10/TIOCC0/TCLKA
2
/PO9/TIOCB0/DACK1
P1
1
P1
/PO8/TIOCA0/DACK0
0
MD MD MD
PG0/CAS 
/CS3
PG
1
PG
/CS2
2
/CS1
PG
3
/CS0
PG
4
0
1
2
3
4
P51P50PF
9089888786858483828180797877767574737271706968676665646362
91
2
92 93
CC
94
ref
95
PF
PF
PF
PF
/ø
5
6
7
CC
SS
PF
EXTAL
XTAL
PF
PF
V
VCCSTBY
V
96 97 98 99 100 101 102 103
SS
104
SS
105 106 107 108 109 110 111 112 113
0
114
1
115
2
116 117 118 119 120
1234567891011121314151617181920212223242526272829
0
1
2
3
4
5
6
7
8
9
10
11
/A PC
SS
/A
/A
/A
/A
/A
/A
/A
V
1
2
3
4
PC
PC
PC
PC
/A
5
6
7
0
1
PB
PB
PC
PC
CC
/A
V
0
PC
12
SS
V
/A
/A
/A
2
3
4
PB
PB
PB
NMI
13
/A
5
PB
RES
WDTOVF
14
/A
/A
6
PB
PB
/PO0/TIOCA3
0
P2
15
16
/A
7
0
PA
/PO1/TIOCB3
/PO2/TIOCC3
1
2
P2
P2
17
18
/A
/A
2
1
PA
PA
/PO3/TIOCD3 P2
/A PA
/PO4/TIOCA4
3
P2
19
V
3
/PO5/TIOCB4
4
P2
SS
/IRQ4 /A
PA
/PO6/TIOCA5
5
P2
/IRQ5
20
/A
4
PA
/PO7/TIOCB5
6
P2
/IRQ6
21
/A
5
PA
7
22 6
/TEND1
/DREQ1
3
2
P6
P6
/IRQ7
23
/A
/CS7/IRQ3
7
7
PA
P6
/TEND0/CS5
1
P6
61
60
P60/DREQ0/CS4
59
V
SS
58
P35/SCK1
57
P3 P3
56
P3
55
P3
54
P3
53
V
52
CC
PD7/D
51
PD6/D
50
PD5/D
49
PD4/D
48
V
47
SS
PD3/D
46
PD2/D
45
PD1/D
44
PD0/D
43
PE7/D
42
PE6/D
41
PE5/D
40
PE4/D
39
V
38
SS
PE3/D
37
PE2/D
36
PE1/D
35
PE0/D
34
V
33
CC
P64/IRQ0
32
P6
31
30
/CS6/IRQ2
6
P6
/SCK0
4
/RxD1
3
/RxD0
2
/TxD1
1
/TxD0
0
/IRQ1
5
15 14 13 12
11 10 9 8 7 6 5 4
3 2 1 0
Figure 1-2 Pin Arrangement (TFP-120: Top View)
6
AV
V P40/AN0 P4
/AN1
1
P4
/AN2
2
P4
/AN3
3
P4
/AN4
4
P4
/AN5
5
P4
/AN6/DA0
6
P4
/AN7/DA1
7
AV
P17/PO15/TIOCB2/TCLKD
P1
6
P1
/PO13/TIOCB1/TCLKC
5
P1
4
P1
/PO11/TIOCD0/TCLKB
3
P1
/PO10/TIOCC0/TCLKA
2
P1
/PO9/TIOCB0/DACK1
1
P1
/PO8/TIOCA0/DACK0
0
V /PO14/TIOCA2 /PO12/TIOCA1
MD MD
MD PG0/CAS  PG
/CS3
1
PG
/CS2
2
/BREQ
/BACK
/LCAS/WAIT /BREQO
/LWR
/HWR
/RD
/AS
/ø
4
5
6
7
CC
PF
4
/A
4
PC
SS
PF
PF
V
V
PF
EXTAL
XTAL
VCCSTBY
NMI
RES
5
6
7
8
9
10
11
12
13
14
/A
/A
/A
5
6
7
PC
PC
PC
SS
/A
/A
V
/A
/A
/A
/A
0
1
2
PB
PB
PB
/A
3
4
5
6
PB
PB
PB
PB
103
CC
104
ref
105 106 107 108 109 110 111 112 113
SS
114
SS
115 116 117 118 119 120 121 122 123
0
124
1
125
2
126 127 128
/ADTRG
3
2
P5
P5
102
101
123456789
/CS1
/CS0
3
4
PG
PG
0
1
2
3
PF
PF
VSSVSSP51P50PF
9998979695949392919089888786858483828180797877767574737271706968676665
100
PF
1011121314151617181920212223242526272829303132333435363738
0
1
2
SS
NC
V
3
CC
V
SS
/A
/A
/A
/A
V
0
1
2
3
PC
PC
PC
PC
Figure 1-3 Pin Arrangement (FP-128: Top View)
/PO0/TIOCA3
/PO1/TIOCB3
0
1
P2
WDTOVF
P2
15
16
17
/A
/A
/A
7
0
1
PB
PA
PA
/PO2/TIOCC3
/PO3/TIOCD3
2
3
P2
P2
18
19
/A
/A
2
3
PA
PA
/PO4/TIOCA4
/PO5/TIOCB4
4
5
P2
P2
SS
V
/IRQ4
20
/A
4
PA
/PO6/TIOCA5
/PO7/TIOCB5
6
7
P2
P2
/IRQ5
/IRQ6
21
22
/A
/A
5
6
PA
PA
/TEND1
/DREQ1
3
2
P6
P6
/IRQ7
23
/A
/CS7/IRQ3
7
7
PA
P6
/TEND0/CS5
1
P6
/CS6/IRQ2
6
P6
SSVSS
V
SSVSS
V
/DREQ0/CS4
0
P6
/IRQ1
5
P6
SS
V
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
/IRQ0
4
P6
P35/SCK1 P3
/SCK0
4
P3
/RxD1
3
P3
/RxD0
2
P3
/TxD1
1
P3
/TxD0
0
V
CC
PD7/D
15
PD6/D
14
PD5/D
13
PD4/D
12
V
SS
PD3/D
11
PD2/D
10
PD1/D
9
PD0/D
8
PE7/D
7
PE6/D
6
PE5/D
5
PE4/D
4
V
SS
PE3/D
3
PE2/D
2
PE1/D
1
PE0/D
0
V
CC
7

1.3.2 Pin Functions in Each Operating Mode

Table 1-2 shows the pin functions of the H8S/2350 Series in each of the operating modes.
Table 1-2 Pin Functions in Each Operating Mode
Pin No. Pin Name
TFP-120 FP-128 Mode 1 Mode 2* Mode 3* Mode 4 Mode 5 Mode 6* Mode 7*
15 VCCV
CC
26 A0PC0/A 37 A1PC1/A 48 A2PC2/A 59 A3PC3/A 610VSSV
SS
711A4PC4/A 812A5PC5/A 913A6PC6/A 10 14 A 11 15 A 12 16 A 13 17 A 14 18 A 15 19 V 16 20 A 17 21 A 18 22 A 19 23 A 20 24 PA 21 25 PA 22 26 PA 23 27 PA 24 28 V
7
8
9
10
11
SS
12
13
14
15
0
1
2
3
SS
PC7/A PB0/A PB1/A PB2/A PB3/A V
SS
PB4/A PB5/A PB6/A PB7/A PA
0
PA
1
PA
2
PA
3
V
SS
25 29 PA4/IRQ4 PA4/IRQ4 PA4/IRQ4 A
26 30 PA5/IRQ5 PA5/IRQ5 PA5/IRQ5 PA5/A21/
27 31 PA6/IRQ6 PA6/IRQ6 PA6/IRQ6 PA6/A22/
V
CC
PC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PC PC PC V PC PC PC PC PB PB PB PB V PB PB PB PB PA PA PA PA V
0
1
2
3
SS
4
5
6
7
0
1
2
3
SS
4
5
6
7
0
1
2
3
SS
V
CC
A
0
A
1
A
2
A
3
V
SS
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
V
SS
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
V
SS
20
V
CC
A
0
A
1
A
2
A
3
V
SS
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
V
SS
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
V
SS
A
20
V
CC
PC0/A
0
PC1/A
1
PC2/A
2
PC3/A
3
V
SS
PC4/A
4
PC5/A
5
PC6/A
6
PC7/A
7
PB0/A
8
PB1/A
9
PB2/A
10
PB3/A
11
V
SS
PB4/A
12
PB5/A
13
PB6/A
14
PB7/A
15
PA0/A
16
PA1/A
17
PA2/A
18
PA3/A
19
V
SS
PA4/A20/
V
CC
PC
0
PC
1
PC
2
PC
3
V
SS
PC
4
PC
5
PC
6
PC
7
PB
0
PB
1
PB
2
PB
3
V
SS
PB
4
PB
5
PB
6
PB
7
PA
0
PA
1
PA
2
PA
3
V
SS
PA4/IRQ4
IRQ4
IRQ5
IRQ6
PA5/A21/
IRQ5
PA6/A22/
IRQ6
PA5/A21/
IRQ5
PA6/A22/
IRQ6
PA5/IRQ5
PA6/IRQ6
8
Table 1-2 Pin Functions in Each Operating Mode (cont)
Pin No. Pin Name
TFP-120 FP-128 Mode 1 Mode 2* Mode 3* Mode 4 Mode 5 Mode 6* Mode 7*
28 32 PA7/IRQ7 PA7/IRQ7 PA7/IRQ7 PA7/A23/
IRQ7
29 33 P67/IRQ3 P67/IRQ3 P67/IRQ3 P67/IRQ3/
CS7
30 34 P66/IRQ2 P66/IRQ2 P66/IRQ2 P66/IRQ2/
CS6
—35 VSSV —36 VSSV
SS
SS
V
SS
V
SS
V
SS
V
SS
31 37 P65/IRQ1 P65/IRQ1 P65/IRQ1 P65/IRQ1 P65/IRQ1 P65/IRQ1 P65/IRQ1 32 38 P64/IRQ0 P64/IRQ0 P64/IRQ0 P64/IRQ0 P64/IRQ0 P64/IRQ0 P64/IRQ0 33 39 V
CC
34 40 PE0/D 35 41 PE1/D 36 42 PE2/D 37 43 PE3/D 38 44 V
SS
39 45 PE4/D 40 46 PE5/D 41 47 PE6/D 42 48 PE7/D 43 49 D 44 50 D 45 51 D 46 52 D 47 53 V 48 54 D 49 55 D 50 56 D 51 57 D 52 58 V
8
9
10
11
SS
12
13
14
15
CC
V
CC
PE0/D
0
PE1/D
1
PE2/D
2
PE3/D
3
V
SS
PE4/D
4
PE5/D
5
PE6/D
6
PE7/D
7
D
8
D
9
D
10
D
11
V
SS
D
12
D
13
D
14
D
15
V
CC
V
CC
PE
0
1
2
3
4
5
6
7
PE PE PE V PE PE PE PE PD PD PD PD V PD PD PD PD V
0
1
2
3
SS
4
5
6
7
0
1
2
3
SS
4
5
6
7
CC
V
CC
PE0/D PE1/D PE2/D PE3/D V
SS
PE4/D PE5/D PE6/D PE7/D D
8
D
9
D
10
D
11
V
SS
D
12
D
13
D
14
D
15
V
CC
53 59 P30/TxD0 P30/TxD0 P30/TxD0 P30/TxD0 P30/TxD0 P30/TxD0 P30/TxD0 54 60 P31/TxD1 P31/TxD1 P31/TxD1 P31/TxD1 P31/TxD1 P31/TxD1 P31/TxD1 55 61 P32/RxD0 P32/RxD0 P32/RxD0 P32/RxD0 P32/RxD0 P32/RxD0 P32/RxD0
0
1
2
3
4
5
6
7
PA7/A23/
IRQ7 P67/IRQ3/
CS7 P66/IRQ2/
CS6
V
SS
V
SS
V
CC
PE0/D
0
PE1/D
1
PE2/D
2
PE3/D
3
V
SS
PE4/D
4
PE5/D
5
PE6/D
6
PE7/D
7
D
8
D
9
D
10
D
11
V
SS
D
12
D
13
D
14
D
15
V
CC
PA7/A23/
IRQ7 P67/IRQ3/
CS7 P66/IRQ2/
CS6
V
SS
V
SS
V
CC
PE0/D
0
PE1/D
1
PE2/D
2
PE3/D
3
V
SS
PE4/D
4
PE5/D
5
PE6/D
6
PE7/D
7
D
8
D
9
D
10
D
11
V
SS
D
12
D
13
D
14
D
15
V
CC
PA7/IRQ7
P67/IRQ3
P66/IRQ2
V
SS
V
SS
V
CC
PE
0
PE
1
PE
2
PE
3
V
SS
PE
4
PE
5
PE
6
PE
7
PD
0
PD
1
PD
2
PD
3
V
SS
PD
4
PD
5
PD
6
PD
7
V
CC
9
Table 1-2 Pin Functions in Each Operating Mode (cont)
Pin No. Pin Name
TFP-120 FP-128 Mode 1 Mode 2* Mode 3* Mode 4 Mode 5 Mode 6* Mode 7*
56 62 P33/RxD1 P33/RxD1 P33/RxD1 P33/RxD1 P33/RxD1 P33/RxD1 P33/RxD1 57 63 P34/SCK0 P34/SCK0 P34/SCK0 P34/SCK0 P34/SCK0 P34/SCK0 P34/SCK0 58 64 P35/SCK1 P35/SCK1 P35/SCK1 P35/SCK1 P35/SCK1 P35/SCK1 P35/SCK1 59 65 V
SS
60 66 P60/
DREQ0
—67 VSSV —68 VSSV 61 69 P61/
TEND0
62 70 P62/
DREQ1
63 71 P63/
TEND1
64 72 P27/PO7/
TIOCB5
65 73 P26/PO6/
TIOCA5
66 74 P25/PO5/
TIOCB4
67 75 P24/PO4/
TIOCA4
68 76 P23/PO3/
TIOCD3
69 77 P22/PO2/
TIOCC3
70 78 P21/PO1/
TIOCB3
71 79 P20/PO0/
TIOCA3 72 80 WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF 73 81 RES RES RES RES RES RES RES
74 82 NMI NMI NMI NMI NMI NMI NMI
V
SS
P60/
DREQ0
SS
SS
P61/
TEND0
P62/
DREQ1
P63/ TEND1
P27/PO7/ TIOCB5
P26/PO6/ TIOCA5
P25/PO5/ TIOCB4
P24/PO4/ TIOCA4
P23/PO3/ TIOCD3
P22/PO2/ TIOCC3
P21/PO1/ TIOCB3
P20/PO0/ TIOCA3
V
SS
P60/
DREQ0
V
SS
V
SS
P61/
TEND0
P62/
DREQ1
P63/
TEND1
P27/PO7/ TIOCB5
P26/PO6/ TIOCA5
P25/PO5/ TIOCB4
P24/PO4/ TIOCA4
P23/PO3/ TIOCD3
P22/PO2/ TIOCC3
P21/PO1/ TIOCB3
P20/PO0/ TIOCA3
V
SS
P60/
DREQ0/ CS4
V
SS
V
SS
P61/
TEND0/ CS5
P62/
DREQ1
P63/
TEND1
P27/PO7/ TIOCB5
P26/PO6/ TIOCA5
P25/PO5/ TIOCB4
P24/PO4/ TIOCA4
P23/PO3/ TIOCD3
P22/PO2/ TIOCC3
P21/PO1/ TIOCB3
P20/PO0/ TIOCA3
V
SS
P60/
DREQ0/ CS4
V
SS
V
SS
P61/
TEND0/ CS5
P62/
DREQ1
P63/
TEND1
P27/PO7/ TIOCB5
P26/PO6/ TIOCA5
P25/PO5/ TIOCB4
P24/PO4/ TIOCA4
P23/PO3/ TIOCD3
P22/PO2/ TIOCC3
P21/PO1/ TIOCB3
P20/PO0/ TIOCA3
V
SS
P60/
DREQ0/ CS4
V
SS
V
SS
P61/
TEND0/ CS5
P62/
DREQ1
P63/ TEND1
P27/PO7/ TIOCB5
P26/PO6/ TIOCA5
P25/PO5/ TIOCB4
P24/PO4/ TIOCA4
P23/PO3/ TIOCD3
P22/PO2/ TIOCC3
P21/PO1/ TIOCB3
P20/PO0/ TIOCA3
V
SS
P60/
DREQ0
V
SS
V
SS
P61/
TEND0
P62/
DREQ1
P63/
TEND1
P27/PO7/ TIOCB5
P26/PO6/ TIOCA5
P25/PO5/ TIOCB4
P24/PO4/ TIOCA4
P23/PO3/ TIOCD3
P22/PO2/ TIOCC3
P21/PO1/ TIOCB3
P20/PO0/ TIOCA3
10
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