Goldstar FFH-565AX, ffh-363ax Service Manual

INTERNAL BLOCK DIAGRAM OF ICs

■ LA1837

■ BA3126N

1 2 3 4 5 6 7 8 9

REC SW GND P/B SW CONT GND VCC P/B SW GND REC SW

■ KIA6289N

Pre Out

Ch2

Pre IN
Ch2/B
(Play Rec)	1kΩ
Pre IN
Ch2/A	1kΩ
(Play only)
Pre IN
Ch1/A	1kΩ
Pre IN
Ch1/B
(Play Rec)	1kΩ

Pre Out

Ch1

		3.3 F
10kΩ			100	R . R
		0.018 F	F		3.3 F
				Vcc
	Gvc	47 F
100Ω			9.1kΩ
		GV		A
1000			6.8kΩ		180kΩ
				1.2 F
F		180kΩ
				B

	22	21	20	19	18	17	16
Ch1/B NF							Ch2
23				A/B
Ch2/A		Ch2		Vref2	Vref	Vref1
24
Ch1/A
1		Ch1
Ch1/B							Ch1
2						M/N
	3	4	5	6	7	8	9
	NF	Metal		Pre	Mix	GND1 M/N	REC
		Out		Out	Out		Out
	180kΩ				10kΩ
							180kΩ
	Gv				Vcc
Gvo		9.1kΩ		6.8kΩ			Gv
						N
		47 F					47 F
						M
1000 F
	100Ω 0.018 F						3.3 F
							150kΩ
10Ω	3.3 F

		Rec Out
10kΩ		Ch2
300kΩ	Gvo	Gv
1000 F		47 F
15		150kΩ
	Rec	2.2kΩ
14	IN		Rec IN
		3.3 F	Ch2
1000pF
13 ALC
ALC		1MΩ	47 F
12	GND
		IN
11	Rec	2.2kΩ	Rec IN
			Ch1
		3.3 F
1000pF
10
NF

100kΩ

Gvo

1000 F

Rec Out Ch1

10kΩ

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■ KIA7805 P/PI ~ KIA7824P/PI
								1	INPUT
			8		9	13
			R		R	R
			Q8			Q9
4	18						Q16
R	R					R21		Q17
					Q14
							R12
						Q15
	Q12					17	11
			Q10			R	R	2
	5								OUTPUT
	R				Q6
		Q13	Q5				20
					16		R
				R	R
Z1	6					Q11
	R
		1		2
		R		R	C1
			Q7
							19
					Q4
							R
		Q1			Q2	Q3
	7
	R
			10		14
			R		R
								3	GND
■ LC72723M
+5V		VREF		FLOUT		CIN			+5V
Vdda								CLOCK	Vddd
							PLL
								RECOVERY
REFERENCE						(57kHz)
								(1187.5Hz)
VOLTAGE
									Vssd
Vssa					VREF
		57kHz
MPXIN	ANTIALIASING	BPF			SMOOTHING			DATA	RDDA
		(SCF)						DECODER
	FILTER				FILTER

RDCL

				RAM	MODE
				(128bit)
			CLK(4.332MHz)		RST
	TEST	TEST		RDS-ID	RDS-ID
			OSC	DETECT	READY
		XIN	XOUT

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■ BU2090F

Block diagram

Vss	1	Control circuit	16	VDD
DATA	2	12-bit shift register	15	Q11
CLOCK	3	Latch	14	Q10
Q0	4	Output buffer	13	Q9
Q1	5	(open drain)	12	Q8
Q2	6		11	Q7
Q3	7		10	Q6
Q4	8		9	Q5

PIN DESCRIPTION

		Pin No.		Pin name			Function
	BU2090/F/FS	BU2092/F	BU2092/FV
	1	1	1	Vss			GND
	2	2	2	DATA			Serial data input
	3	3	3	CLOCK			Data shift clock input
	-	4	4	LCK			Data latch clock input
	4	5	5	Q0			parallel data output
	5	6	6	Q1			parallel data output
	6	7	7	Q2			parallel data output
	7	8	8	Q3			parallel data output
	8	9	9	Q4			parallel data output
	9	10	10	Q5			parallel data output
	10	11	11	Q6			parallel data output
	-	-	12	N.C.			Not connected
	-	-	13	N.C.			Not connected
	11	12	14	Q7			parallel data output
	12	13	15	Q8			parallel data output
	13	14	16	Q9			parallel data output
	14	15	17	Q10			parallel data output
	15	16	18	Q11			parallel data output
	-	17	19				Output Enable
					OE
	16	18	20	VDD			Power supply

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