Page 1
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INTERNAL BLOCK DIAGRAM OF ICs
■ BU1923/BU1923F
RDS/RBDS decoder
Page 2
- 2-38 -
• Internal circuit configuration
■ BA3126N
2-channel head switch for radio cassette recoreders
■ BU2090F
-12 -bit, Serial IN, parallel OUT driver
Control circuit
12-bit shift register
Latch
VSS
2
1
3
4
5
6
7
8
DATA
CLOCK
Q0
Q1
Q2
Q3
Q4
16
15
14
13
12
11
10
9
VDD
Q11
Q10
Q9
Q8
Q7
Q6
Q5
Output buffer
(open drain)
Page 3
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+5V
18K15K
IN (L)
1µF
15K 1µF
MUTE/
ST-BY
GND
IN (R)
1µF
4.7Ω
4.7Ω
100nF
100nF
OUT (L)
OUT (R)
1000µF
1000µF
+V
S
3
5
7
9
6
11
2
4+
+
-
-
D94AU085
RL (L)
RL (R)
-V
S
µP
560Ω
18K
IN- (L)8
10 IN- (R)
1
560Ω
18K
■ TDA7265
■ BA3308
Dual preamplifier with ALC
Page 4
- 2-40 -
■ KA78R33
Low Dropout Voltage Regulator
■ KIA 78R12 PI
4 TERMINAL LOW DROP VOLTAGE REGULATOR
Page 5
- 2-41 -
■ LA1837
Single-Chip Home Stereo IC with Electronic Tuning Support
■ LC72131, 72131M
AM/FM PLL Frequency Synthesizer
B01 B02 B03 B04 I01 I02
XIN
PD
AIN
AOUT
IFIN
XOUT
FMIN
AMIN
CE
DI
CL
D0
VDD
VSS
REFERENCE
DIVIDER
PHASE DETECTOR
CHARGE PUMP
UNLOCK
DETECTOR
UNIVERSAL
COUNTER
DATA SHIFT REGISTER
LATCH
12bits PROGRAMMABLE
DIVIDER
SWALLOW COUNTER
1/16. 1/17 4bits
POWER
ON
RESET
CCB
I/F
1
2
Page 6
- 2-42 -
■ TDA7442D
DIGITALLY CONTROLLED AUDIO PROCESSOR
L-IN1
100K
100K
100K
100K
100K
100K
100K
100K
48918
27
21
22
20
26
24
25
LOUT
SCL
SDA
DIG_GND
ROUT
V
S
AGND
RB
RB
14 15
10 11 19 12 13 23
5
G
G
6
7
3
2
INPUT MULTIPLEXER
+GAIN
MUXOUTR INR TREBLE(R) BIN(R) BOUT(R) CREF D98AU883
0/30dB
2dB STEP
MUXOUTL
VOLUME TREBLE
I CBUS DECODER + LATCHES
BASS
SPKR ATT
LEFT
VOLUME TREBLE BASS
SUPPLY
V
REF
SPKR ATT
RIGHT
INLTREBLE(L) BOUT(L)BIN(L)
1
28
L-IN2
L-IN3
L-IN4
R-IN1
R-IN2
R-IN3
R-IN4
2
L_IN3
L_IN4
MUXOUTL
IN(L)
MUXOUT(R)
BIN(R)
IN(R)
BOUT(R)
BIN(L)
1
3
2
4
5
6
7
8
9
BOUT(L)
N.C.
N.C.
TREBLE(R)
TREBLE(L)
SCL
SDA
DIG-GND
CREF23
22
21
20
19
17
18
16
15
D98AU884
10
11
12
13
14
28
27
26
25
24
R_IN3
R_IN2
R_IN1
L_IN1
L_IN2 V
S
AGND
ROUT
LOUT
R_IN4
• PIN CONNECTION(TOP VIEW)
Page 7
- 2-43 -
■ FAN8039BD3
5-CH Motor Driver
NO Symbol Description NO Symbol Description
1DO1-CH1 Drive Output (-) 15 GND2 Power Ground1 (CH 2,3,5)
2DO1+CH1 Drive Output (+) 16 DO5+ CH5 Drive Output (+)
3IN1 CH1 Drive Input 17 DO5- CH5 Drive Output(-)
4REGVCC Regulator Supply Voltage 18 DO3- CH3 Drive Output(-)
5REB Regulator Output 19 DO3+ CH3 Drive Output (+)
6REO Regulator Feedback Input 20 IN3 CH3 Drive Input
7RESX Regulator Reset 21 VCC1 Supply Voltage1(CH2,CH3,CH5)
8GND1 Signal Ground 22 PS Power Save
9CTL CH5 Motor Speed Control 23 VREF Bias Voltage
10 FWD CH5 Forward Input 24 VCC Supply Voltage(CH1,CH4)
11 REV CH5 Reverse Input 25 IN4 CH4 Drive Input
12 IN2 CH2 Drive Input 26 DO4+ CH4 Drive Output (+)
13 DO2+ CH2 Drive Output (+) 27 DO4- CH4 Drive Output (-)
14 DO2- CH2 Drive Output (-) 28 GND3 Power Ground2 (CH 1,4)
• PIN Definitions
Page 8
- 2-44 -
■ KIA6225P/S
BIPOLAR LINEAR INTEGRATED CIRCUIT
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