Fujitsu SPARC JPS1 Implementation Supplement Manual

SPARC JPS1
Implementation Supplement:
Fujitsu SPARC64 V

Fujitsu Limited
Release 1.0, 1 July 2002

Fujitsu Limited
4-1-1 Kamikodan ak a
Nahahara-ku, Kawasaki, 211-858 8
Japan

Part No. 806-6755-1.0

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http://www.sun.com http://www.fujitsu.com/

Release 1.0, 1 July 2002 F. Chapter 2

3 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

F.CHAPTER

Contents

1. Ove r view 1

Navigating the SPARC64 V Implementation Supplement 1
Fonts and Notational Conventions 1
The SPARC64 V processor 2

Component Overview 4
Instruction Control Unit (IU) 6
Execution Unit (EU) 6
Storage Unit (SU) 7
Secondary Cache and External Access Unit (SXU) 8

2. Def i n itio n s 9

3. Architectu ra l Ove rv iew 13

4. Data Formats 15

5. Registers 17

Nonprivileged Registers 17

Floating-Point State Register (FSR) 18
Ti ck (TICK) Register 19

Privileged Registers 19

Trap State (TSTATE) Register 19
Ver sion (VER) Re g i s t e r 20
Ancillary State Registers (ASRs) 20
Registers Referenced Through ASIs 22

i

Floating-Point Deferred-Trap Queue (FQ) 24
IU Deferred-Trap Queue 24

6. Instructions 25

Instruction Execution 25

Data Prefetch 25
Instruction Prefetch 26

Syncing Instructions 27
Instruction Formats and Fields 28
Instruct ion Categories 29

Control-Transfer Instructions (CT Is) 29

Floating-Point Operate (FPop ) Instructions 30

Implementation-Dependent Instructions 30
Processor Pipeline 31

Instruction Fetch Stages 31

Issue Stages 33

Execution Stages 33

Completion Stages 34

7. Traps 35

Processor States, Norma l and Spe cial Traps 35

RED_state 36

error_state 36
Trap Categories 37

Deferred Traps 37

Reset Traps 37

Uses of the Trap Categories 37
Trap Control 38

PIL Control 38
Trap-Table Entry Ad dresses 38

Trap Type (TT) 38

Details of Supported Traps 39
Trap Processing 39
Exception and Interrupt Descriptions 39

SPARC V9 Implementation-Dependent, Optional Traps That Are

Mandatory in SPARC JPS1 39

ii SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

SPARC JPS1 Implementation-Dependent Traps 39

8. Memory Models 4 1

Overview 42

SPARC V 9 Mem o ry Mo de l 42

Mode Control 42
Synchronizing Instruction and Data Me mory 42

A. Instruction Definitions: SPARC64 V Extensions 45

Block Load and Store Instructions (VIS I) 47

Call and Link 49

Implementation-Dependent Instructions 49

Floating-Point Multiply-Add/Subtract 50
Jump and Link 53
Load Quadword, Atomic [Physical] 54
Memory Barrier 55
Partial Store (VIS I) 57
Prefetch Data 57
Read State Register 58
SHUTDOWN (VIS I) 58
Writ e Sta te Re gi s ter 59
Deprecated In st ruc t io n s 59

Store Barrier 59

B. IEEE Std 754 -198 5 R e qui rem e nts for SPARC V9 61

Traps Inhibiting Results 61
Floating-Point Nonstandard Mode 61

fp_exception_other Exception (ftt=unfinished_FPop) 62

Operation Under FSR.NS = 1 65

C. Implementation Dependencies 69

Definition of an Implementation Depe nde ncy 69
Hardware Characteristics 70
Implementation Dependency Categories 70
List of Implementation Dependencies 70

Release 1.0, 1 July 2002 F. Chapter Contents iii

D. Form a l Spe c ific at io n of t he Mem ory Mod e ls 81

E. Op co de Map s 83

F. Memory Management Unit 85

Virtual Address Translation 85
Translation Table Entry (TTE) 86

TSB Organization 88
TSB Pointer Formation 88

Faults and Traps 89
Reset, Disable, and RED_state Behavior 91
Internal Regist ers an d A SI op era tion s 92

Accessing MMU Registers 92
I/D TLB Data In, Data Access, and Tag Read Regis ters 93
I/D TSB Extension Registers 97
I/D Synchronous Fault Status Registers (I-SF SR, D-SF SR ) 97

MMU Bypass 104

TLB Replacement Policy 105

G. Assembly Language Syntax 107

H. Software Considerations 109

I. Extending the SPARC V9 Architecture 111

J. Changes from SPARC V8 to SPARC V9 113

K. Programming with the Memory Models 115

L. Addr e ss Spa c e Iden ti fier s 117

SPARC64 V ASI Assignments 117

Special Memor y Acc e ss ASI s 119

Barrier Assist for Parallel Processing 121

Interface Definition 121
ASI Registers 122

M. Cache Orga n izatio n 125

Cache Types 125

Level-1 Instruction Cache (L1I Cache) 126

iv SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

Level-1 Data Ca c he (L 1D C ach e) 12 7

Level-2 Unified Cache (L2 Cache) 127
Cache Coherency Protocols 128
Cache Control/Status Instructions 128

Flush Level-1 Instruction Cache (ASI_FLUSH _L1I) 129

Level-2 Cache Control Register (ASI_L2_CTRL) 130

L2 Diagnostics Tag Re ad (AS I_L 2_DI AG_ TAG_READ) 130

L2 Diagnostics Tag Re ad R egist ers ( AS I_L 2_DI AG_TAG_READ_REG) 131

N. Interrupt Handling 133

Interrupt D isp a tc h 13 3
Interrupt Re c ei ve 1 3 5
Interrupt Global Registers 136
Interrupt-Rela ted AS R Re gis ter s 136

Interrupt Vector Dispatch Register 136

Interrupt Vector Dispatch Status Register 136

Interrupt Vector Receive Register 136

O. Rese t, RED_ sta te, a nd err or_s t ate 13 7

Reset Types 137

Power-on Reset (POR) 137

Watchdog Reset (W DR) 138

Externally Initiated Reset (XIR) 138

Software-Initi ate d R eset (S IR) 13 8
RED_state and e rror_stat e 13 9

RED_state 140

error_state 140

CPU Fatal Error state 141
Processor State after Reset and in RED_state 141

Operating Status Register (OPSR) 146

Hard w are Po wer- O n Reset S e quence 1 4 7

Firmware Initialization Sequence 147

P. Error Handling 149

Error Classification 149

Fatal Error 149

Release 1.0, 1 July 2002 F. Chapter Contents v

error_state Transition Error 150
Urgent Error 150
Restrainable Error 152

Action a n d E rror Cont ro l 153

Registers Related to Error Handling 153
Summary of Actions Upon Error Detection 154
Extent of Automatic Source Data Correction for Correctable Error 157
Error Marking for Cacheable Data Error 157
ASI_EIDR 161
Control o f E r ro r Actio n ( ASI_ERROR_CONTROL) 161

Fatal Error a n d erro r_state Transi t ion Error 1 63

ASI_STCHG_ERROR_INFO 163

Fatal Error Types 164
Types of error_state Transition Errors 164

Urgent Error 165

URGENT ERRO R STATUS (ASI_UGESR) 165
Action of

async_data_error

(ADE) Trap 168
Instruction End-Method at ADE Trap 170
Expected So ftw are Hand li ng of AD E Trap 171

Instruction Access Errors 173
Data Access Errors 173
Restrainable Errors 174

ASI_ASYNC_FAULT_STATUS (ASI_AFSR) 174
ASI_ASYNC_FAULT_ADDR_D1 177
ASI_ASYNC_FAULT_ADDR _U 2 178
Expected Software Handling of Restrainable Errors 179

Handling of Internal Register Errors 181

Register Error Handling (Excluding ASRs and ASI Registers) 181
ASR Error Handling 182
ASI Register Error Handling 183

Cache Error Handling 188

Handling of a Cache Tag Error 188
Handling of an I1 Cache Data Error 190
Handling of a D1 Cache Data Error 190
Handling of a U2 Cache Data Error 192
Automatic Way Reduction of I1 Cache, D1 Cache, and U2 Cache 193

vi SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

TLB Error Handling 195

Handling of TLB Entry Errors 195
Automatic Way Reduction of sTLB 196

Handling of Extended UPA Bus Interface Error 197

Handling of Extended UPA Address Bus Error 197
Handling of Extended UPA Data Bus Erro r 197

Q. Perfo rman ce In strum e ntat io n 201

Performance Monitor Overview 201

Sample Pseudo co d es 2 01

Performance Monitor Description 203

Instruction Statistics 204
Trap-R el ate d St atisti cs 2 06
MMU Event Counters 207
Cache Event Counters 208
UPA Event Counters 210
Miscellaneous Counters 211

R. UPA Programmer’s Model 213

Mapping of the CPU’s UPA Port Slave Area 213
UPA PortI D Reg iste r 214
UPA Config Regi ster 215

S. Summary of Differences between SPARC64 V and UltraSPARC-III 219

Bibliography 223

General References 223

Index 225

Release 1.0, 1 July 2002 F. Chapter Contents vii

viii SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Relea se 1. 0, 1 July 20 02

F.CHAPTER

1

Overview

1.1 Navigating the SPARC64 V
Implementation Supplement

We sugges t that you approach this Imple mentation Supple ment SPARC Joint
Programming Specification as follows.

1. Familiarize yourself with the SPARC64 V processor and its components by
reading these sections:

■

The SPARC64 V processor on page 2

■

Component Overview on page 4

■

Processor Pipel ine on page 31

2. Study the terminology in Chapter 2, Definitions:

3. For details of a rchitectural changes, see the remaining chapters i n this
Implementation Supplement as your interests direct.

For this revision, we added new appendixes: Appendix R,
and Appendix S, Summary of Differences between SPARC64 V and UltraSPARC-III.

UPA Programmer’s Model

1.2 Fonts and Notational Conventions

Please refer to Section 1.2 of Commonality for font and notational conventions.

,

1

1.3 The SPARC64 V processor

The SPARC64 V processor is a high-performance, high-reliability, and high-integrity
processor that fully implements the instruction set architecture that conforms to
SPARC V9, as described in JPS1 Commonality. In addition, the SPARC64 V processor
implements the following features:

64-bit virtual a ddress space and 4 3-bit physic al address space

■

Advanced RAS features that enable high-integrity error handling

■

Microarchitecture for High Performance

The SPARC64 V i s an out-of-order execution supersc alar processor that issues up to
four instructions per cycle. Instructions in the predicted path are issued in program
order and are stored temporarily in
of program order to appropriate execution units. Instructions commit in program
order when no exceptional conditions occur during execution and all prior
instructions commit (that is, the result of the instruction execution becomes visible).
Out-of-order execution in SPARC64 V contributes to high performance.

SPARC64 V implements a large branch history buffer to predict its instruction path.
The history buffer is large enough to sustain a good prediction rate for large-scale
programs such as DBMS and to support the advanced instruction fetch mechanism
of SPARC64 V. This instruction fetch scheme predicts the execution path beyond the
multiple conditional branches in accordance with the branch history. It then tries to
prefetch instructions on the predicted path as much as possible to reduce the effect
of the performance penalty caused by instruction cache misses.

reservation stations

until they are dispatched out

High Integration

SPARC64 V integrates an on-board, associative, level-2 cache. The level-2 cache is
unified for instruction and data. It is the lowest layer in the cache hierarchy.

This integration contributes to both performance and reliability of SPARC64 V. It
enables shorter access time and more associativity and thus contributes to higher
performance. It contributes to higher reliability by eliminating the external
connections for level-2 cache.

High Reliability and High Integri ty

SPARC64 V implements the following advanced RAS features for reliability and
integrity beyond that of ordinary microprocessors.

2 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

1. Advanced RAS features for caches

■

Strong cache error protection:

ECC protection for D1 (Data level 1) cache data, U2 (unified level 2) cache data,

■

and the U2 cache tag.
Parity protection for I1 (Instruction level 1) cache data.

■

Parity protection and duplication for the I1 cache tag and the D1 cache tag.

■

■

Automatic correction of all types of single-bit error:

Automatic single-bit error correction for the ECC protected data.

■

Invalidation and refilling of I1 cache data for the I1 cache data parity error.

■

Copying from duplicated tag for I1 cache tag and D1 cache tag parity errors.

■

■

Dynamic way reduction while cache consistency is maintained.

■

Error marking for cacheable data uncorrectable errors:

Special error-marking pattern for cacheable data with uncorrectable errors. The

■

identification of the module that first detects the error is embedded in the
special pattern.
Error-source isolation with faulty module identification in the special error-

■

marking. The identification information enables the processor to avoid
repetitive error logging for the same error cause.

2. Advanced RAS featur es for the core

■

Strong error protection:

Parity protection for all data paths.

■

Parity protection for most of software-visible regist ers and internal temporary

■

registers.
Parity predic tion or residue ch ecking for t he accumula tor outpu t.

■

■

Hardware instruction retry

■

Support for software instruction retry (after failure of hardware instruction retry)

■

Error isolation for software recovery:

Error indication for each programmable register group.

■

Indication of retryability of the trapped instruction.

■

Use of different error traps to differentiate degrees of adverse effects on the

■

CPU and the system.

3. Extended RAS inte rface to software

■

Error classification according to the severity of the effect on program execution:

Urgent error (nonmaskable): Unable to continue execution without OS

■

intervention; reported through a trap.
Restrainable error (maskable): OS controls whether the error is report ed

■

through a trap, so error does not directly affect program execution.

■

Isolated error indication to determine the effect on software

Release 1.0, 1 July 2002 F. Chapter 1 Overview 3

■

Asynchronous data error (

Relaxed instruc tion en d metho d (precise , retryab le, not retryable ) for th e

■

async_data_error

exception to indicate how the instruction should end; depends

ADE

) trap for additional errors:

on the executing instruction and the detected error.

ADE

Some

■

Simultaneous reporting of all detected

■

traps that are deferred but retryable.

handling of retryability.

1.3.1 Component Overview

The SPARC64 V processor contains these components.

Instruction control Unit (IU)

■

Execution Unit (EU)

■

Storage Unit (SU)

■

Secondary cache and eXternal access Unit (SXU)

■

ADE

errors at the error barrier for correct

FIGURE 1-1

illustrates the major units; the following subsections describe them.

4 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

Extended UPA Bus

SX-Unit

UPA interface logic

MoveIn buffer

S-Unit interface

S-Unit

SX interface

I-TLB tag data

MoveOut buffer

U2$ U2$ data

tag 2M 4-way

SX order queue Store queue

D-TLB tag data

E-Unit

ALU
Input
Registers

and
Output
Registers

GUB FUB

ALUs
EXA

EXB
FLA
FLB

EAGA
EAGB

2048
+ 32

entry

Level-1 I cache

128 KB, 2-way

2048
+ 32

entry

Level-1 D cache

128 KB, 2-way

GPR FPR

I-Unit

Instruction Instruction
fetch buffer
pipeline

Commit stack entry
Reservation stations

PC
nPC

CCR

E-unit
control

logic

FSR

Branch
history

FIGURE 1-1

Release 1.0, 1 July 2002 F. Chapter 1 Overview 5

SPARC64 V Major Units

1.3.2 Instruction Contro l Unit (IU)

The IU predicts the instruction execution path, fetches instructions on the predicted
path, distributes the fetched instructions to appropriate reservation stations, and
dispatches the instructions to the execution pipeline. The instructions are executed
out of order, and the IU commits the instructions in order. Major blocks are defined

TABLE 1-1

in

.

TABLE 1-1

Name Description

Instruction fetch pipeline Five stages: fetch address generation, iTLB access, iTLB match,

Branch history 16K entries, 4-way set associative.
Instruction buffer Six entries, 32 bytes/entry.
Reservation station Six reservation stations to h old instruct ions until th ey can

Commit stac k entries Sixty-four en tries; bas ically one ins truction/en try, to h old

PC, nPC, CCR , FSR Program-vi sible regi sters for instructio n execu tion con trol.

Instruction Control Unit Major Blocks

I-Cache fetch, and a write to I-buffer.

execute: RSBR for branch and the other control-transfer
instructions; RSA fo r load/st ore instruct ions; RSEA and RSEB for
integer arithmetic instructions; RSFA and RSFB for floating-point
arithmetic and VIS instruct ions.

information about instructions issued but not yet committed.

1.3.3 Execution Unit (EU)

The EU carries out execution of all integer arithmetic, logical, shift instructions, all
floating-point instructions, and all VIS graphic instructions.
EU major blocks.

TABLE 1-2

describes the

TABLE 1-2

Name Description

General register (gr) renaming
regi ste r fi le (GUB: gr update
buffer)

Gr a rch ite ctu re re gi ste r fi le ( GPR) 160 entries, 1 read port, 2 write ports
Floating-point (fr) renaming

regi ste r fi le (FUB: fr update
buffer)

Fr a rchi te ctu re re gis ter fi le ( FPR)Thirty-two entries,

EU control logic Controls the i nstruction e xecution s tages: instru ction

6 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

Execution Un it Major B locks

Thirty-two entries, 8 read ports, 2 write ports

Thirty-two entries, 8 read ports, 2 write ports

6 read ports, 2 write ports

selection, register read, and execution.

TABLE 1-2

Name Description

Execution Un it Major B locks (Continued)

Interface registers Input/output registers to other units.
Two i nteger execu tion pipeline s

(EXA, EXB)
Two floating-point and graphics

execution pipelines (FLA, FLB)

Two virtual address adders for
memory access pipeline (EAGA,
EAGB)

1.3.4 Storage Unit (SU)

The SU handles all sourcing and sinking of data fo r load and store instructions.

TABLE 1-3

describes the SU major blocks.

64-bit ALU and shifters.

Each floating-point execution pipeline can execute floating
point multipl y, floatin g point add/ sub, floatin g-point
multiply and add, floating point div/sqrt, and floating­point graph ics instruct ion.

Two 64-bit virtual addresses for load/store.

TABLE 1-3

Name Description

Storage Unit Major Blocks

Instruction level-1 cache 128-Kbyte, 2-way associative, 64-byte line; provides low latency

instruction source

Data level-1 cache 128-Kbyte, 2-way associative, 64-byte line, writeback; provides

the low latency data source for loads and stores.

Instruction Translation
Buffer

1024 entries, 2-way associative TLB for 8-Kbyte pages,
1024 entries, 2-way associative TLB for 4-Mbyte pages

1

,

32 entries, fully associative TLB for unlocked 64-Kbyte, 512-

1

Kbyte, 4-Mbyte

pages and locked pages in all sizes.

Data Translation Buffer 1024 entries, 2-way associative TLB for 8-Kbyte pages,

1024 entries, 2-way associative TLB for 4-Mbyte pages

1

,

32 entries, fully associative TLB for unlocked 64-Kbyte, 512-

1

Kbyte, 4-Mbyte

pages and locked pages in all sizes.

Store queue Decouples the pipeline from the latency of store operations.

Allows the pipeline to cont inue flowin g while the st ore waits for
data, and eventually writes into the data level 1 cache.

1. Unloced 4-Mbyte page entry is stored either in 2-way associative TLB or fully associative
TLB exclusively, depending on the setting.

Release 1.0, 1 July 2002 F. Chapter 1 Overview 7

1.3.5 Secondary Cache and External Access Unit (SXU)

The SXU controls the operation of unified level-2 caches and the external data access
interface (extended UPA interface).

TABLE 1-4

describes the major block s of the SXU.

TABLE 1-4

Name Description

Unified level-2 ca che 2-Mbyte, 4-way associative, 64-byte line, writeback; provides low

Movein buffer Sixteen entries, 64-bytes/entry; catches returning data from

Moveout buffer Eight entries, 64-bytes/entry; holds writeback data. A maximum

Extended UPA interface
control logic

Secondary Cache and External Access Unit Major Blocks

latency data source for bo th instruction level-1 c ache and data
level-1 cache.

memory system in response to the cache line read request. A
maximum of 16 outstanding cache read operations can be issued.

of 8 outstanding writeback requests can be issued.
Send/receive transaction packets to/from Extended UPA

interface connected to the system.

8 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

F.CHAPTER

2

Definitions

This chapter defines concepts unique to the SPARC64 V, the Fujitsu implementation
of SPARC JPS1. For definition of terms that are common to all implementations,
please refer to Chapter 2 of Commonality.

committed Term applied to an instruction whe n it has co mpleted with out error and all

prior instructions have completed without error and have been committed. When
an instruction is committ ed, the state of the machin e is permanently chang ed
to reflect the result of the i nstruction; th e previously existi ng state i s no longe r
needed and can be disca rded.

completed Term applied to an instruction after it has finished, has sent a none rror status to

the issue unit, and all of its source operands are nonspeculative. Note:
Although the state of the machine has been temporarily altered by completion
of an instruction, th e state has no t yet been permane ntly changed and the old
state can be recovered until the instruction has been committed.

executed Term applied to an instruct ion that ha s been proces sed by an ex ecution un it

such as a load unit. An instruction is in execution as long as it is still being
processed by an execution unit.

fetched Term applied to an instruction that is obtained from the I2 instruction cache or

from the on-chip internal cache and sent to the issue unit.

finished Term applied to an instruction when it has completed execution in a functional

unit and has forwarded its result onto a result bus. Results on the result bus are
transferred to the register file, as are the waiting instructions in the instruction
queues.

initiated Term applied to an i nst ructi on wh en i t h as all of t he resources that it ne e ds ( for

example, source operands) and has been selected for execution.

instruction dispatch Synonym: instruction initiation.

instruction issued Term applied to an in struction when it has been d ispatched to a reservation

station.

9

instruction retired Term applied to an instructi on when all machine resources (seri al numbers,

renamed registers) have been reclaimed and are available for use b y other
instructions. An instru ction can only be retired after it has been c ommitted.

instruction stall Term applied to an instructi on that is not allowed to be issued . Not every

instruction can be issued in a given cycle. The SPARC64 V implementation
imposes certain issue constrain ts based on resource availability and program
requirements.

issue-stalling

instruction An instruction that prevents ne w instructio ns from being is sued until it has

committed.

machine sync The state of a machine when all previously executing instructions have

committed; that is, when no issued but uncommitt ed instructions are in the
machine.

Memory Manag ement

Unit (MMU) Refers to the address translation h ardware in SPARC64 V that tr anslates 64-bit

virtual address into physica l address. T he MMU is c omposed of the mITLB,
mDTLB, uITLB, uDTLB, and the ASI registers used to manage address
translation.

mTLB Main TLB. Split i nto I and D, c alled mITL B and m DTLB, respectiv ely. Contai ns

address translations for the uITLB and uDT LB. When the uITL B or uDTLB do
not contain a transl ation, they ask the mTLB for th e translation. If the mTLB
contains the translatio n, it sends the translation to th e respective uTLB. If the
mTLB does not contain the translation , it generates a fast access excep tion to a
software translation trap handler, which will load the translation information
(TTE) into the mTLB and retry the access. See also TLB.

uDTLB Micro Data TLB. A small, fully associative buffer that contains address

translations for data accesses. Misses in the uDTLB are handled by the mTLB.

uITLB Micro Instruction TLB. A s mall, fully asso ciative buffer that co ntains address

translations fo r instructio n accesses . Misses i n the uTLB are handled by th e
mTLB.

nonspeculative A distribution syst em whereby a result i s guaranteed known correct or an

operand stat e is known to be vali d. SPAR C64 V employ s speculati ve
distribution, meaning that results can be distributed from functional units
before the point at which guaranteed validity of the result is known.

reclaimed The status when all instruction-related resources that were held until commit

have been released and are available for subse quent instructions. Ins truction
resources are usually reclaimed a few cycles after they are committed.

rename registers A large set of hardware registers implemented by SPARC64 V that are invisible

to the programmer. Before instructions are issued, source and destination
registers are mapped onto this s et of renam e register s. This al lows ins tructions
that normally would be blocked, waiting for an architected register, to proceed

10 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

in parallel . When i nstructi ons are committed, results in renamed registers are
posted to the architected registers in the proper sequence to produce the correct
program results.

scan A method used to initialize all of the machine state within a chip. In a chip that

has been desi gned t o be scann able, all of t he mac hine stat e is co nnected i n one
or several loops called “scan rings.” Initialization data can be scanne d into the
chip through the scan rings. The sta te of the machine also can be scanned out
through the scan rings.

reservation station A holding location that b uffers disp atch ed in structi on s unt il all i np ut o pera nds

are available. SPARC64 V implements dataflow execution based on operand
availability. When operands are available, the instruc tions in the reservation
station are scheduled for ex ecution. Reserv ation stations also con tain special
tag-matching logic that captures the appropriate operand data. Reservation
stations are sometimes referred to as queues (for example, the integer queue).

speculative A distribution syst em whereby a result is no t guaranteed as kn own to be

correct or an operan d state is not known to be valid. SPARC64 V employs
speculative distribution, meaning results can be distributed from functional
units before the point at which guaranteed validity of the result is known.

superscalar An implementation that allows several instructions to be issued, executed, and

committed in one clock cycle. SPARC64 V issues up to 4 instructions per clock
cycle.

sync Synonym: machine sync.

syncing instruction An instruction that causes a machine sync. Thus, before a syncing instruction is

issued, all previous instructions (in program order) must have been committed.
At that point, the syncing instruction is issued, executed, completed, and
committed by itself.

TLB Translation lo okaside buffer.

Release 1.0, 1 July 2002 F. Chapter 2 Definitions 11

12 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

F.CHAPTER

3

Architectural Overview

Please refer to Chapter 3 in the Commonality section of SPARC Joint Programming
Specification.

13

14 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

F.CHAPTER

4

Data Formats

Please refer to Chapter 4, Data Formats in Commonality.

15

16 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

F.CHAPTER

5

Registers

The SPARC64 V processor includes two types of registers: general-purpose—that is,
working, data, control/status—and ASI registers.

The SPARC V9 architecture also defines two implementation-dependent registers:
the IU Deferred-Trap Queue and the Floating-Point Deferred-Trap Queue (FQ);
SPARC64 V does not need or contain either queue. All processor traps caused by
instructio n executi on are precise, and there are severa l disrupti ng traps caus ed by
asynchronous events, such as interrupts, asynchronous error conditions, and
RED_state entry traps.

For general information, please see parallel subsections of Chapter 5 in
Commonality. For easier referencing, this chapter follows the organization of
Chapter 5 in Commonality.

For information on MMU registers, please refer to Section F.10, Internal Registers a nd
ASI operations, on page 92.

The chapter contains these sections:

■

Nonprivileged Re gisters on page 17

■

Privileged Registers on page 19

5.1 Nonprivile ged Register s

Most of the definitions for the registers are as described in the corresponding
sections of Commonality. Only SPARC64 V-specific features are described in this
section.

17

5.1.7 Floating-Point State Register (FSR)

Please refer to Section 5.1.7 of Commonality for the description of FSR.
The sections below describe SPARC64 V-specific features of the FSR regis ter.

FSR_nonstandard_fp (NS)

SPARC V9 defines the FSR.NS bit which, when set to 1, causes the FPU to produce
implementation-dependent results that may not conform to IEEE Std 754-1985.
SPARC64 V im plements thi s bit.

When FSR.NS = 1, denormal input operands and denormal results that would
otherwise trap are flushed to 0 of the same sign and an inexact exception is signalled
(that may be masked by FSR.TEM.NXM). See Section B.6, Floating-Point Nonstandard
Mode, on page 61 for details.

When FSR.NS = 0, the normal IEEE Std 754-1985 behavior is implemented.

FSR_version (

For each SPARC V9 IU implementation (as identified by its VER.impl field), there
may be one or more FPU implementations or none. This field identifies the
particular FPU implementation present. For the first SPARC64 V, FSR.ver =0 (impl.
dep. #19); however, future versions of the architecture may set FSR.ver to other
values. Consult the SPARC64 V Data Sheet for the setting of F SR.v er for your
chipset.

FSR_floating-point_trap_type (

The complete conditions under which SPARC64 V triggers
trap type
on page 61 (impl. dep. #248).

unfinished_FPop

)

ver

)

ftt

fp_exception_other

is described in Section B.6, Floating-Point Nonstandard Mode,

with

FSR_current_exception (cexc)

Bits 4 through 0 indicate that one or more IEEE_754 floating-point exceptions were
generated b y the most rece ntly execu ted FPop in struction. T he absence of an
exception causes the corresponding bit to be cleared.

In SPARC64 V , the cexc bits are set according to the following pseudocode:

if (<LDFSR or LDXFSR commits>)

<update using data from LDFSR or LDXFSR>;

else if (<FPop commits with ftt = 0>)

<update using value from FPU>

18 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

else if (<FPop commits with IEEE_754_exception>)

<set one bit in the CEXC field as supplied by FPU>;

else if (<FPop commits with unfinished_FPop error>)

<no change>;

else if (<FPop commits with unimplemented_FPop error>)

<no change>;

else

<no change>;

FSR Conformance

SPARC V9 a llows the TEM, cexc, and aexc fields to be implemented in hardware in
either of two ways (both of whi ch comply with IEEE Std 754-19 85). SPARC 64 V
follows case (1); that is, it implements al l three fields in conformance with IEEE Std
754-1985. See FSR Con formance in Section 5.1. 7 of Commonality for more
information about other implementation methods.

5.1.9 Tick (TICK) Register

SPARC64 V implements TICK.counter register as a 63-bit register (impl. dep.
#105).

Implementation Note –

when the TICK register is read is the value of TICK.counter when the RDTICK
instruction is executed. The difference between the counter values read from the
TICK register on two reads reflects the number of processor cycles executed between
the executi ons of the RDTICK instructions, not their commits. In longer code
sequences, the difference between this value and the value that would have been
obtained when the instructions are committed would have been small.

On SPARC64 V, the counter part of the value returned

5.2 Privileged Registers

Please refer to Section 5.2 of Commonality for the description of privileged registers.

5.2.6 Trap State (TSTATE) Register

SPARC64 V i mpleme nts only bits 2:0 of t he TSTATE.CWP field. Writes to bits 4 and 3
are ignored, and reads of these bits always return zeroes.

Release 1.0, 1 July 2002 F. Chapter 5 Registers 19