Fujitsu SPARC64 V User Manual

Fujitsu Limited 4-1-1 Kamikodanak a Nahahara-ku, Ka w as ak i, 211 -858 8 Japan

SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V

Fujitsu Limited Release 1.0, 1 July 2002

Part No. 806-6755-1.0

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Release 1.0, 1 July 2002 F. Chapter 2

3 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

F.CHAPTER

1. Ove r v iew 1

Navigating the SPARC64 V Implementation Supplement 1 Fonts and Notational Conventions 1 The SPARC64 V processor 2

Component Overview 4 Instruction Control Unit (IU) 6 Execution Unit (EU) 6 Storage Unit (SU) 7 Secondary Cache and External Access Unit (SXU) 8

2. Def i n i t ions 9

3. Architectura l Ov e rvi ew 13

4. Data Formats 15

5. Registers 17

Nonprivileged Registers 17

Floating-Point State Register (FSR) 18 Ti ck (TICK) Reg ister 19

Privileged Registers 19

Trap State (TSTATE) Register 19 Ver sion (VER) Re g i ster 20 Ancillary State Registers (ASRs) 20 Registers Referenced Through ASIs 22

Floating-Point Deferred-Trap Queue (FQ) 24 IU Deferred-Trap Queue 24

6. Instructions 25

Instruction Execution 25

Data Prefetch 25 Instruction Prefetch 26

Syncing Instructions 27 Instruction Formats and Fields 28 Instructi o n Categories 29

Control-Transfer Instructio ns (CTI s) 29

Floating-Point Operate (FPop) Instructio ns 30

Implementation-Dependent Instructions 30 Processor Pipeline 31

Instruction Fetch Stages 31

Issue Stages 33

Execution Stages 33

Completion Stages 34

7. Traps 35

Processor States, Normal and Sp ec ial Traps 35

RED_state 36

error_state 36 Trap Categories 37

Deferred Trap s 37

Reset Traps 37

Uses of the Trap Categories 37 Trap Control 38

PIL Control 38 Trap-Table Entry Addresses 38

Trap Type (TT) 38

Details of Supported Tr aps 39 Trap Processing 39 Exception and Interrupt Descriptions 39

SPARC V9 Implementation-Dependent, Optional Traps That Are

Mandatory in SPARC JPS1 39

ii SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

SPARC JPS1 Implementation-Dependent Traps 39

8. Mem ory Models 41

Overview 42

SPARC V9 M em or y Mo de l 42

Mode Control 42 Synchronizing Instruction and Data Memo ry 42

A. Instruction Definitions: SPARC64 V Extensions 45

Block Load and Store Instructions (VIS I) 47

Call and Link 49

Implementation-Dependent Instructions 49

Floating-Point Multiply-Add/Subtract 50 Jump and Link 53 Load Quadword, Atomic [Physical] 54 Memory Barrier 55 Partial Store (VIS I) 57 Prefetch Data 57 Read State Register 58 SHUTDOWN (VIS I) 58 Wr ite St at e Re gis t er 59 Deprecated I ns tru c ti on s 59

Store Barrier 59

B. IEEE S td 754 - 198 5 Re qu ir eme nt s fo r SPARC V9 61

Traps Inhibiting Results 61 Floating-Point Nonstandard Mode 6 1

fp_exception_other Exception (ftt=unfinished_FPop) 62

Operation Under FSR.NS = 1 65

C. Implementation Dependencies 69

Definition of an Implementation Depend ency 69 Hardware Characteristics 70 Implementation Dependency Categories 70 List of Implementation Dependencies 70

Release 1.0, 1 July 2002 F. Chapter Contents iii

D. Forma l S pe cifi c atio n o f t he M emo ry M od els 81

E. Opc ode M ap s 8 3

F. Memory Management Unit 85

Virtual Address Translation 85 Translation Table Entry (TTE) 86

TSB Organization 88 TSB Pointer Formation 88

Faults and Traps 89 Reset, Disable, and RED_state Behavior 91 Internal Register s an d ASI ope rat ion s 92

Accessing MMU Registers 92 I/D TLB Data In, Data Access, and Tag Rea d Regis ters 93 I/D TSB Extension Registers 97 I/D Synchronous Fault Status Registers (I-SFSR , D-SF SR) 97

MMU Bypass 104

TLB Replacement Policy 105

G. Assembly Language Syntax 107

H. Software Considerations 109

I. Extending the SPARC V9 Architecture 111

J. Changes from SPARC V8 to SPARC V9 113

K. Programming with the Memory Models 115

L. Addre ss S pa ce Id enti fi er s 117

SPARC64 V ASI Assignments 117

Special Memory Ac ce ss AS Is 119

Barrier Assist for Parallel Processing 121

Interface Definition 121 ASI Registers 122

M. Cache Orga nizat io n 125

Cache Types 125

Level-1 Instruction Cache (L1I Cache) 126

iv SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

Level-1 Data Cac he (L1D C a ch e) 127

Level-2 Unified Cache (L2 Cache) 127 Cache Coherency Pro tocols 128 Cache Control/Status Instructions 128

Flush Level-1 Instruction Cache (ASI_FLUSH_L1I) 129

Level-2 Cache Control Register (ASI_L2_CTRL) 130

L2 Diagnostics Tag Read (ASI_L2_DIAG_ TAG_READ) 130

L2 Diagnostics Tag Read Registers (AS I_L 2_DI AG_TAG_READ_REG) 131

N. Interrupt Handling 133

Interrupt Dis p at c h 13 3 Interrupt Re ce iv e 1 35 Interrupt Global Registers 136 Interrupt-Related AS R Regis ter s 13 6

Interrupt Vector Dispatch Register 136

Interrupt Vector Dispatch Status Register 136

Interrupt Vector Receive Register 136

O. Rese t, RED_ s tate , and err or_st at e 137

Reset Types 137

Power-on Reset (POR) 137

Watchdog R eset (W DR) 138

Externally Initiated Reset (XIR) 138

Software-Initiat ed R ese t (S I R) 13 8 RED_state and error_st ate 139

RED_state 140

error_state 140

CPU Fatal Error state 141 Processor State after Reset and in RED_state 141

Operating Status Register (OPSR) 146

Hardw are Power-On Rese t Sequ ence 147

Firmware Initialization Sequence 147

P. Error Handling 14 9

Error Classification 149

Fatal Error 149

Release 1.0, 1 July 2002 F. Chapter Contents v

error_state Transition Error 150 Urgent Error 150 Restrainable Error 152

Acti on an d Erro r Cont ro l 153

Registers Related to Error Handling 153 Summary of Actions Upon E rror Detection 154 Extent of Automatic Source Data Correction for Correctable Error 157 Error Marking for Cacheable Data Error 157 ASI_EIDR 161 Cont rol of E rror A c tion (ASI_ERROR_CONTROL) 161

Fatal Er ro r and e r ro r_s t a t e Tran s i tion Erro r 1 63

ASI_STCHG_ERROR_INFO 163

Fatal Error Types 164 Types of error_state Tra nsition Errors 164

Urgent Error 165

URGENT ERROR STATUS (ASI_UGESR) 165 Action of

async_data_error

(ADE) Trap 168 Instruction End-Method at ADE Trap 170 Expected Soft w are Hand ling of ADE Trap 171

Instruction Access Errors 173 Data Access Errors 173 Restrainable Errors 174

ASI_ASYNC_FAULT_STATUS (ASI_AFSR) 174 ASI_ASYNC_FAULT_ADDR_D1 177 ASI_ASYNC_FAULT_A DDR_U 2 17 8 Expected Software Handling of Restrainable Errors 179

Handling of Internal Register Errors 181

Cache Error Handling 188

Handling of a Cache Tag Error 188 Handling of an I1 Cache Data Error 190 Handling of a D1 Cache Data Error 190 Handling of a U2 Cache Data Error 192 Automatic Way Reduction of I1 Cache, D1 Cache, and U2 Cache 193

vi SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

TLB Error Handling 195

Handling of TLB Entry Errors 195 Automatic Way Reduction of sTLB 196

Handling of Extended UPA Bus Interface Error 197

Handling of Extended UPA Address Bus Error 197 Handling of Extended UPA Data Bus Error 197

Q. Perform anc e Ins trume nt atio n 20 1

Performance Monitor Overview 201

Sample Pseudo co des 2 01

Performance Monitor Description 203

Instruction Statistics 204 Trap-R el at ed S tat istic s 2 06 MMU Event Counters 207 Cache Event Counters 208 UPA Event Counters 210 Miscellaneous Counters 211

R. UPA Programmer’s Model 213

Mapping of the CPU’s UPA Port Slave Area 213 UPA Por tID Re gist er 214 UPA Conf ig Re giste r 215

S. Summary of Differences between SPARC64 V and UltraSPARC-III 219

Bibliography 223

General References 223

Index 225

Release 1.0, 1 July 2002 F. Chapter Contents vii

viii SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Rele a se 1. 0, 1 July 20 02

F.CHAPTER

Overview

1.1 Navigating the SPARC64 V Implementation Supplement

We sugg est that you approach this Impl ementation Suppl ement SPARC Joint Programming Specification as follows.

1. Familiarize yourself with the SPARC64 V processor and its components by reading these sections:

■

The SPARC64 V processor on page 2

■

Component Overview on page 4

■

Processor Pipel ine on page 31

2. Study the terminology in Chapter 2, Definitions:

3. For details of architectural changes, se e the remaining cha pters in this Implementation Supplement as your interests direct.

For this revision, we added new appendixes: Appendix R, and Appendix S, Summary of Differences between SPARC64 V and UltraSPARC-III.

UPA Programmer’s Model

1.2 Fonts and Notational Conventions

Please refer to Section 1.2 of Commonality for font a nd notational conventions.

1.3 The SPARC64 V processor

The SPARC64 V processor is a high-performance, high-reliability, and high-integrity processor that fully implements the instruction set architecture that conforms to SPARC V9, as described in JPS1 Commonality. In addition, the SPARC64 V processor implements the following features:

64-bit virtual a ddress space and 4 3-bit physical address space

■

Advanced RAS features that enable high-integrity error handling

■

Microarchitecture for High Performance

The SPARC6 4 V is an out-of-order execution superscala r processor that issues up to four instructions per cycle. Instructions in the predicted path are issued in program order and are stored temporarily in of program order to appropriate execution units. Instructions commit in program order when no exceptional conditions occur during execution and all prior instructions commit (that is, the result of the instruction execution becomes visible). Out-of-order execution in SPARC64 V contributes to high performance.

SPARC64 V implements a large branch history buffer to predict its instruction path. The history buffer is large enough to sustain a good prediction rate for large-scale programs such as DBMS and to support the advanced instruction fetch mechanism of SPARC64 V. This instruction fetch scheme predicts the execution path beyond the multiple conditional branches in accordance with the branch history. It then tries to prefetch instructions on the predicted path as much as possible to reduce the effect of the performance penalty caused by instruction cache misses.

reservation st ations

until they are dispatched out

High Integration

SPARC64 V integrates an on-board, associative, level-2 cache. The level-2 cache is unified for instruction and data. It is the lowest layer in the cache hierarchy.

This integration contributes to both performance and reliability of SPARC64 V. It enables shorter access time and more associativity and thus contributes to higher performance. It contributes to higher reliability by eliminating the external connections for level-2 cache.

High Reliability and High Integrity

SPARC64 V implements the following advanced RAS features for reliability and integrity beyond that of ordinary microprocessors.

2 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

1. Advanced RAS features for caches

■

Strong cache error protection:

ECC protection for D1 (Data level 1) cache data, U2 (unified level 2) cache data,

■

and the U2 cache tag. Parity protection for I1 (Instruction level 1) cache data.

■

Parity protection and duplication for the I1 cache tag and the D1 cache tag.

■

Automatic correction of all types of single-bit error:

Automatic single-bit error correction for the ECC protected data.

■

Invalidation and refilling of I1 cache data for the I1 cache data parity error.

■

Copying from duplicated tag for I1 cache tag and D1 cache tag parity errors.

■

Dynamic way reduction while cache consistency is maintained.

■

Error marking for cacheable data uncorrectable errors:

Special error-marking pattern for cacheable data with uncorrectable errors. The

■

identification of the module that first detects the error is embedded in the special pattern. Error-source isolation with faulty module identification in the special error-

■

marking. The identification information enables the processor to avoid repetitive error logging for the same error cause.

2. Advanced RAS features for the core

■

Strong error protection:

Parity protection for all data paths.

■

Parity protection for most of software-visible registers and internal temporary

■

registers. Parity predicti on or residue che cking for t he accumula tor output.

■

Hardware instruction retry

■

Support for software instruction retry (after failure of hardware instruction retry)

■

Error isolation for software recovery:

Error indication for each programmable register group.

■

Indication of retryability of the trapped instruction.

■

Use of different error traps to differentiate degrees of adverse effects on the

■

CPU and the system.

3. Extended RAS interface to software

■

Error classification according to the severity of the effect on program execution:

Urgent error (nonmaskable): Unable to continue execution without OS

■

intervention; reported through a trap. Restrainable error (maskable): OS controls whether the error is reported

■

through a trap, so error does not directly affect program execution.

■

Isolated error indication to determine the effect on software

Release 1.0, 1 July 2002 F. Chapter 1 Overview 3

■

Asynchronous data error (

Relaxed i nstruct ion en d method (precise , retryab le, not ret ryable ) for the

■

async_data_error

exception to indicate how the instruction should end; depends

ADE

) trap for additional errors:

on the executing instruction and the detected error.

ADE

Some

■

Simultaneous reporting of all detected

■

traps that are deferred but retryable.

handling of retryability.

1.3.1 Component Overview

The SPARC64 V processor contains these components.

Instruction control Unit (IU)

■

Execution Unit (EU)

■

Storage Unit (SU)

■

Secondary cache and eXternal access Unit (SXU)

■

ADE

errors at the error barrier for correct

FIGURE 1-1

illustrates the major units; the following subsections describe them.

4 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

Extended UPA Bus

SX-Unit

UPA interface logic

MoveIn buffer

S-Unit interface

S-Unit

SX interface

I-TLB tag data 2048

+ 32

entry

Level-1 I cache

128 KB, 2-way

MoveOut buffer

U2$ U2$ data tag 2M 4-way

SX order queue Store queue

D-TLB tag data 2048

+ 32 entry

Level-1 D cache

128 KB, 2-way

E-Unit

ALU Input Registers

and Output Registers

GUB FUB

GPR FPR

ALUs EXA

EXB FLA FLB EAGA EAGB

I-Unit

Instruction Instruction fetch buffer pipeline

Commit stack entry Reservation stations

PC nPC

CCR

E-unit control

logic

FSR

Branch history

FIGURE 1-1

Release 1.0, 1 July 2002 F. Chapter 1 Overview 5

SPARC64 V Major Units

1.3.2 Instruction Control Unit (IU)

The IU predicts the instruction execution path, fetches instructions on the predicted path, distributes the fetched instructions to appropriate reservation stations, and dispatches the instructions to the execution pipeline. The instructions are executed out of order, and the IU commits the instructions in order. Major blocks are defined

TABLE 1-1

Name Description

Instruction fetch pipeline Five stages: fetch address generation, iTLB access, iTLB match,

Branch history 16K entries, 4-way set associative. Instruction buffer Six entries, 32 bytes/entry. Reservation s tation Six reservation s tations to ho ld instructio ns until the y can

Commit stack entries Sixty-four ent ries; basica lly one inst ruction/ent ry, to hold

PC, nPC, CCR, FSR Program-vi sible regist ers for in structio n execu tion con trol.

Instruction Control Unit Major Blocks

I-Cache fetch, and a write to I-buffer.

execute: RSBR for branch and the other control-transfer instructions; RSA for l oad/sto re instruction s; RSEA and RSEB for integer arithmetic instructions; RSFA and RSFB for floating-point arithmetic and V IS instructio ns.

information about instructions issued but not yet committed.

1.3.3 Execution Unit (EU)

The EU carries out execution of all integer arithmetic, logical, shift instructions, all floating-point instructions, and all VIS graphic instructions. EU major blocks.

TABLE 1-2

Execution Un it Major B locks

TABLE 1-2

describes the

Name Description

General register (gr) renaming regis te r fi le (GUB: gr update buffer)

Gr a rch ite ctu re re gis te r fi le ( GPR) 160 entries, 1 read port, 2 write ports Floating-point (fr) renaming

regis te r fi le (FUB: fr update buffer)

Fr arc hi tec ture reg is ter fil e (FPR )Thirty-two entries,

EU control logic Controls the in struction exe cution sta ges: instru ction

6 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

Thirty-two entries, 8 read ports, 2 write ports

6 read ports, 2 write ports

selection, register read, and execution.

TABLE 1-2

Name Description

Execution Un it Major B locks (C o n tinued)

Interface registers Input/output registers to other units. Tw o integer ex ecution pipelin es

(EXA, EXB) Two floating-point and graphics

execution pipelines (FLA, FLB)

Two virtual address adders for memory access pipeline (EAGA, EAGB)

1.3.4 Storage Unit (SU)

The SU handles all sourcing and sinking of data for load and store instructions.

TABLE 1-3

describes the SU major blocks.

64-bit ALU and shifters.

Each floating-point execution pipeline can execute floating point multiply, floating point add/sub, floa ting-point multiply and add, floating point div/sqrt, and floatingpoint graphi cs instruction .

Two 64- bit virtual addresses for load/store.

TABLE 1-3

Name Description

Storage Unit Major Blocks

Instruction level-1 cache 128-Kbyte, 2-way associative, 64-byte line; provides low latency

instruction source

Data level-1 cache 128-Kbyte, 2-way associative, 64-byte line, writeback; provides

the low latency data source for loads and stores.

Instruction Translation Buffer

1024 entries, 2-way associative TLB for 8-Kbyte pages,

1024 entries, 2-way associative TLB for 4-Mbyte pages 32 entries, fully associative TLB for unlocked 64-Kbyte, 512-

Kbyte, 4-Mbyte

pages and locked pages in all sizes.

Data Translation Buffer 1024 entries, 2-way associative TLB for 8- Kbyte pages,

1024 entries, 2-way associative TLB for 4-Mbyte pages 32 entries, fully associative TLB for unlocked 64-Kbyte, 512-

Kbyte, 4-Mbyte

pages and locked pages in all sizes.

Store queue Decouples the pipeline from the latency of store operations.

Allows the pipeline t o contin ue flowing while the store w aits for data, and eventually writes into the data level 1 cache.

1. Unloced 4-Mbyte page entry is stored either in 2-way associative TLB or fully associative TLB exclusively, depending on the setting.

Release 1.0, 1 July 2002 F. Chapter 1 Overview 7

1.3.5 Secondary Cache and External Access Unit (SXU)

The SXU controls the operation of unified level-2 caches and the external data access interface (extended UPA interface).

TABLE 1-4

describes the major blocks of the SXU.

TABLE 1-4

Name Description

Unified level-2 cache 2-Mbyte, 4-way associative, 64-byte line, writeback; provides low

Movein buffer Sixteen entries, 64-bytes/entry; catches returning data from

Moveout buffer Eight entries, 64-bytes/entry; holds writeback data. A maximum

Extended UPA interface control logic

Secondary Cache and External Access Unit Major Blocks

latency data s ource for both instruction l evel-1 c ache and data level-1 cache.

memory system in response to the cache line read request. A maximum of 16 outstanding cache read operations can be issued.

of 8 outstanding writeback requests can be issued. Send/receive transaction packets to/from Extended UPA

interface connected to the system.

8 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

F.CHAPTER

Definitions

This chapter defines concepts unique to the SPARC64 V, the Fujitsu implementation of SPARC JPS1. For definition of terms that are common to all implementations, please refer to Chapter 2 of Commonality.

committed Term applied to an instruction when it has completed w ithout error and all

prior instructions have completed without error and have been committed. When an instruction is committ ed, the state of the machine is permanently change d to reflect the result of the ins truction; the previously existing state is no longer needed and can be disca rded.

completed Term applied to an instruction after it has finished, has sent a no nerror stat us to

the issue unit, and all of its source operands are nonspeculative. Note: Although the state of the machine has been temporarily altered by completion of an instruction, th e state has not y et been permanentl y changed and the old state can be recovered until the instruction has been committed.

executed Te rm applied to an instru ction that ha s been proces sed by an execution u nit

such as a load unit. An instruction is in execution as long as it is still being processed by an execution unit.

fetched Term applied to an instruction that is obtained from the I2 instruction cache or

from the on-chip internal cache an d sent to the i ssue unit.

finished Term applied to an instruction when it has completed execution in a functional

unit and has forwarded its result onto a result bus. Results on the result bus are transferred to the register file, as are the waiting instructions in the instruction queues.

initiated Term applied to an inst ruct ion wh en it ha s al l of t he resources that it nee ds (fo r

example, source operands) and has been selected for execution.

instruction dispatch Synonym: instruction initiation.

instruction issued Term applied to an instruction whe n it has bee n dispatched to a reservation

station.

instruction retired Term applied to an instruct ion when all machine resources (s erial numbers,

renamed registers) have been reclaimed and are avai lable for use by o ther instructions. An instruc tion can only be retired after it has been committed.

instruction stall Term applied to an instruc tion that is not allowed to be issu ed. Not every

instruction can be issued in a given cycle. The SPARC64 V implementation imposes certain issue constraints bas ed on resource availability and program requirements.

issue-stalling

instruction An instruction that prevents ne w instructions from being is sued until it has

committed.

machine sync The state of a machine when all previously executing instructions have

committed; that is, when no i ssued but uncommitted instructions are in the machine.

Memory Manageme nt

Unit (MMU) Refers to the address translation h ardware in SPARC6 4 V that translates 64-bit

virtual address in to physica l address. The MMU is co mposed of the mITLB, mDTLB, uITLB, uDTLB, and the ASI registers used to manage address translation.

mTLB Main TLB. Sp lit into I and D, cal led m ITLB and mD TLB, respe ctive ly. Contains

address translations for the uITLB and uDTLB . When the uITLB o r uDTLB do not contain a translatio n, they ask the mTLB for the translation. If the mTLB contains the translation, it sends the tran slation to the respective uTLB. If the mTLB does not contain the translation, it ge nerates a fast access exceptio n to a software translation trap handler, which will load the translation information (TTE) into the mTLB and retry the access. See also TLB.

uDTLB Micro Data TLB. A small, fully associative buffer that contains address

translations for data accesses. Misses in the uDTLB are handled by the mTLB.

uITLB Micro Instruction TLB. A small , fully associ ative buffer that contai ns address

translations for instruction accesses. Misses in the uTLB are han dled by th e mTLB.

nonspeculative A distri bution syst em whereby a result i s guaranteed known cor rect or an

operand stat e is known to be valid . SPARC64 V employs sp eculative distribution, meaning that results can be distributed from functional units before the point at which guaranteed validity of the result is known.

reclaimed The status when all instruction-related resources that were held until commit

have been released and are availabl e for subsequent instructions. Instruct ion resources are usually reclaimed a few cycles after they are committed.

rename registers A large set of hardware registers implemented by SPARC64 V that are invisible

to the programmer. Before instructions are issued, source and destination registers are mapped on to this s et of rename registers. This al lows inst ructions that normally would be blocked, waiting for an architected register, to proceed

10 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

in parallel . When i nstruction s are committed, results in renamed registers are posted to the architected registers in the proper sequence to produce the correct program results.

scan A method used to initialize all of the machine state within a chip. In a chip that

has been desi gned to be scann able, a ll of t he machin e state is conne cted i n one or several loops c alled “scan ri ngs.” Initi alization data can be sca nned into the chip through the scan rings. The state of the machine also can be s canned out through the scan rings.

reservation station A holding location that b uffers di spatc h ed in struc ti ons u nt il al l i nput o pera nds

are available. SPARC64 V implements dataflow execution based on operand availability. When opera nds are availabl e, the in structions in the reservation station are scheduled for ex ecution. Reservati on stations also contai n special tag-matching logic that captures the appropriate operand data. Reservation stations are sometimes referred to as queues (for example, the integer queue).

speculative A distribution syst em whereby a result is not g uaranteed as kn own to be

correct or an operan d state is not known to be valid. SPARC64 V employs speculative distribution, meaning results can be distributed from functional units before the point at which guaranteed validity of the result is known.

superscalar An implementation that allows several instructions to be issued, executed, and

committed in one clock cycle. SPARC64 V issues up to 4 instructions per clock cycle.

sync Synonym: machine sync.

syncing instruction An instruction that causes a machine sync. Thus, before a syncing instruction is

issued, all previo us instructions (in program order) must hav e been committed. At that point, the syncing instruction is issued, executed, completed, and committed by itself.

TLB Translation l ookaside b uffer.

Release 1.0, 1 July 2002 F. Chapter 2 Definitions 11

12 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

F.CHAPTER

Architectural Overview

Please refer to Chapter 3 in the Commonality section of SPARC Joint Programming Specification.

14 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

F.CHAPTER

Data Formats

Please refer to Chapter 4, Data Formats in Commonality.

16 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

F.CHAPTER

Registers

The SPARC64 V processor includes two types of registers: general-purpose—that is, working, data, control/status—and ASI registers.

The SPARC V9 architecture also defines two implementation-dependent registers: the IU Deferred-Trap Queue and the Floating-Point Deferred-Trap Queue (FQ); SPARC64 V does not need or contain either queue. All processor traps caused by instruction executio n are precise, and there are severa l disruptin g traps cause d by asynchronous events, such as interrupts, asynchronous error conditions, and RED_state entry traps.

For general information, please see parallel subsections of Chapter 5 in Commonality. For easier referencing, this chapter follows the organization of Chapter 5 in Commonality.

For information on MMU registers, please refer to Section F.10, Inte rnal Regist ers and ASI operations, on page 9 2.

The chapter contains these sections:

■

Nonprivileged Regi sters on page 17

■

Privileged Registers on page 19

5.1 Nonprivileged Register s

Most of the definitions for the registers are as described in the corresponding sections of Commonality. Only SPARC64 V-specific features are described in this section.

5.1.7 Floating-Point State Register (FSR)

Please refer to Section 5.1.7 of Commonality for the description of FSR. The sections below describe SPARC64 V-specific features of the FSR regi st er.

FSR_nonstandard_fp (NS)

SPARC V 9 defines th e FSR.NS bit which, when set to 1, causes the FPU to produce implementation-dependent results that may not conform to IEEE Std 754-1985. SPARC 64 V implements th is bit.

When FSR.NS = 1, denormal input operands and denormal results that would otherwise trap are flushed to 0 of the same sign and an inexact exception is signalled (that may be masked by FSR.TEM.NXM). See Section B.6, Floating-Point Nonstandard Mode, on page 61 for details.

When FSR.NS = 0, the normal IEEE Std 754-1985 behavi or is implemented.

FSR_version (

For each SPARC V9 IU implementation (as identified by its VER.impl field), there may be one or more FPU implementations or none. This field identifies the particular FPU implementation present. For the first SPARC64 V, FSR.ver =0 (impl. dep. #19); however, future versions of the architecture may set FSR.ver to other values. Consult the SPARC64 V Data Sheet for the setting of FSR.ver for your chipset.

FSR_floating-point_trap_type (

The complete conditions under which SPARC64 V triggers trap type on page 61 (impl. de p. #248).

unfinished_FPop

)

ver

)

ftt

fp_exception_other

is described in Section B.6, Floating-Point Nonstandard Mode,

with

FSR_current_exception (cexc)

Bits 4 through 0 indicate that one or more IEEE_754 f loating-point exceptions were generated b y the most recent ly execute d FPop inst ruction. Th e absence of an exception causes the corresponding bit to be cleared.

In SPAR C64 V, the cexc bits are set according to the following pseudocode:

if (<LDFSR or LDXFSR commits>)

<update using data from LDFSR or LDXFSR>;

else if (<FPop commits with ftt = 0>)

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else if (<FPop commits with IEEE_754_exception>)

<set one bit in the CEXC field as supplied by FPU>;

else if (<FPop commits with unfinished_FPop error>)

<no change>;

else if (<FPop commits with unimplemented_FPop error>)

<no change>;

else

<no change>;

FSR Conformance

SPARC V 9 allow s th e TEM, cexc, and aexc fields to be implemented in hardware in either of two ways (both of which co mply with IEEE Std 754-1985) . SPAR C64 V follows case (1); that is, it implements all t hree fields in conformance with IEEE Std 754-1985. See FSR Conform ance in Section 5.1.7 of Commonality for more information about other implementation methods.

5.1.9 Tick (TICK) Register

SPARC64 V impl ements TICK.counter register as a 63-bit register (impl. dep. #105).

Implementation Note –

when the TICK register is read is the value of TICK.counter when the RDTICK instruction is executed. The difference between the counter values read from the TICK register on two reads reflects the number of processor cycles executed between the executions of the RDTICK instructions, not their commits. In longer code sequences, the difference between this value and the value that would have been obtained when the instructions are committed would have been small.

On SPARC64 V, the counter part of the value returned

5.2 Privileged Registers

Please refer to Section 5.2 of Commonality for the description of privileged registers.

5.2.6 Trap State (TSTATE) Register

SPARC64 V implem ents onl y bits 2: 0 of the TS TATE.CWP field. Writes to bits 4 and 3 are ignored, and reads of these bits always return zeroes.

Release 1.0, 1 July 2002 F. Chapter 5 Registers 19

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